WO2004027823A3 - Semiconductor multi-package module having wire bond interconnection between stacked packages - Google Patents

Semiconductor multi-package module having wire bond interconnection between stacked packages Download PDF

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Publication number
WO2004027823A3
WO2004027823A3 PCT/US2003/028919 US0328919W WO2004027823A3 WO 2004027823 A3 WO2004027823 A3 WO 2004027823A3 US 0328919 W US0328919 W US 0328919W WO 2004027823 A3 WO2004027823 A3 WO 2004027823A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor multi
package module
wire bond
stacked packages
package
Prior art date
Application number
PCT/US2003/028919
Other languages
French (fr)
Other versions
WO2004027823A2 (en
Inventor
Marcos Karnezos
Original Assignee
Chippac Inc
Marcos Karnezos
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/632,550 external-priority patent/US6972481B2/en
Priority claimed from US10/632,549 external-priority patent/US7064426B2/en
Priority claimed from US10/632,568 external-priority patent/US7205647B2/en
Priority claimed from US10/632,551 external-priority patent/US6838761B2/en
Priority claimed from US10/632,552 external-priority patent/US20040061213A1/en
Priority claimed from US10/632,553 external-priority patent/US7053476B2/en
Priority to KR1020057004551A priority Critical patent/KR101166575B1/en
Priority to EP03754585A priority patent/EP1547141A4/en
Application filed by Chippac Inc, Marcos Karnezos filed Critical Chippac Inc
Priority to JP2004568930A priority patent/JP4800625B2/en
Priority to AU2003272405A priority patent/AU2003272405A1/en
Publication of WO2004027823A2 publication Critical patent/WO2004027823A2/en
Publication of WO2004027823A3 publication Critical patent/WO2004027823A3/en

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
PCT/US2003/028919 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages WO2004027823A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2003272405A AU2003272405A1 (en) 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages
JP2004568930A JP4800625B2 (en) 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages and method of forming the same
KR1020057004551A KR101166575B1 (en) 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages
EP03754585A EP1547141A4 (en) 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages

Applications Claiming Priority (14)

Application Number Priority Date Filing Date Title
US41159002P 2002-09-17 2002-09-17
US60/411,590 2002-09-17
US10/632,550 US6972481B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US10/632,552 2003-08-02
US10/632,553 US7053476B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US10/632,551 2003-08-02
US10/632,553 2003-08-02
US10/632,552 US20040061213A1 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US10/632,568 2003-08-02
US10/632,549 2003-08-02
US10/632,551 US6838761B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US10/632,568 US7205647B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US10/632,550 2003-08-02
US10/632,549 US7064426B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having wire bond interconnect between stacked packages

Publications (2)

Publication Number Publication Date
WO2004027823A2 WO2004027823A2 (en) 2004-04-01
WO2004027823A3 true WO2004027823A3 (en) 2004-05-21

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PCT/US2003/028919 WO2004027823A2 (en) 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages

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EP (1) EP1547141A4 (en)
JP (3) JP4800625B2 (en)
KR (1) KR101166575B1 (en)
AU (1) AU2003272405A1 (en)
TW (3) TWI378548B (en)
WO (1) WO2004027823A2 (en)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3858854B2 (en) * 2003-06-24 2006-12-20 富士通株式会社 Multilayer semiconductor device
TWI442520B (en) * 2005-03-31 2014-06-21 Stats Chippac Ltd Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7394148B2 (en) 2005-06-20 2008-07-01 Stats Chippac Ltd. Module having stacked chip scale semiconductor packages
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP5522561B2 (en) * 2005-08-31 2014-06-18 マイクロン テクノロジー， インク． Microelectronic device package, stacked microelectronic device package, and method of manufacturing microelectronic device
US8198735B2 (en) 2006-12-31 2012-06-12 Stats Chippac Ltd. Integrated circuit package with molded cavity
US8124451B2 (en) 2007-09-21 2012-02-28 Stats Chippac Ltd. Integrated circuit packaging system with interposer
KR20110124065A (en) 2010-05-10 2011-11-16 하나 마이크론(주) Stack type semiconductor package
KR20110124063A (en) * 2010-05-10 2011-11-16 하나 마이크론(주) Stack type semiconductor package
KR101688005B1 (en) * 2010-05-10 2016-12-20 삼성전자주식회사 Semiconductor package having dual land and related device
TWI406377B (en) * 2010-12-27 2013-08-21 Powertech Technology Inc Ball grid array package with three-dimensional pin 1 mark and its manufacturing method
US9165906B2 (en) 2012-12-10 2015-10-20 Invensas Corporation High performance package on package
JP6128993B2 (en) 2013-06-28 2017-05-17 キヤノン株式会社 Multilayer semiconductor device, printed circuit board, electronic device, and method of manufacturing multilayer semiconductor device
KR101563910B1 (en) * 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 EMI shielding device for semiconductor package and method for manufacturing the same
US9995641B2 (en) * 2013-10-30 2018-06-12 Honeywell International Inc. Force sensor with gap-controlled over-force protection
JP6357371B2 (en) * 2014-07-09 2018-07-11 新光電気工業株式会社 Lead frame, semiconductor device, and lead frame manufacturing method
US9666730B2 (en) 2014-08-18 2017-05-30 Optiz, Inc. Wire bond sensor package
KR101961377B1 (en) * 2015-07-31 2019-03-22 송영희 Land Grid Array semiconductor package
KR101799668B1 (en) * 2016-04-07 2017-11-20 앰코 테크놀로지 코리아 주식회사 Semiconductor package and manufacturing method thereof
CN110062956B (en) * 2016-12-30 2023-10-10 英特尔公司 Microelectronic device for high frequency communication using three-dimensional stacked ultra-thin package module design
KR102283390B1 (en) 2019-10-07 2021-07-29 제엠제코(주) Semiconductor package for multi chip and method of fabricating the same
KR102325217B1 (en) 2020-05-18 2021-11-11 제엠제코(주) Multi die stack semiconductor package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5373189A (en) * 1992-08-13 1994-12-13 Commissariate A L'energie Atomique Three-dimensional multichip module
US6075289A (en) * 1996-10-24 2000-06-13 Tessera, Inc. Thermally enhanced packaged semiconductor assemblies

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5222014A (en) * 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
JPH05283608A (en) * 1992-03-31 1993-10-29 Toshiba Corp Resin-sealed semiconductor device and manufacture thereof
US5247423A (en) * 1992-05-26 1993-09-21 Motorola, Inc. Stacking three dimensional leadless multi-chip module and method for making the same
US5436203A (en) * 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
US5652185A (en) * 1995-04-07 1997-07-29 National Semiconductor Corporation Maximized substrate design for grid array based assemblies
JP3644662B2 (en) * 1997-10-29 2005-05-11 株式会社ルネサステクノロジ Semiconductor module
JPH11243175A (en) * 1998-02-25 1999-09-07 Rohm Co Ltd Composite semiconductor device
JPH11265975A (en) * 1998-03-17 1999-09-28 Mitsubishi Electric Corp Multi-layer integrated circuit device
JP2000058691A (en) * 1998-08-07 2000-02-25 Sharp Corp Millimeter wave semiconductor device
US6201302B1 (en) * 1998-12-31 2001-03-13 Sampo Semiconductor Corporation Semiconductor package having multi-dies
JP2000269411A (en) * 1999-03-17 2000-09-29 Shinko Electric Ind Co Ltd Semiconductor device and manufacture thereof
JP4075204B2 (en) * 1999-04-09 2008-04-16 松下電器産業株式会社 Multilayer semiconductor device
JP4284744B2 (en) * 1999-04-13 2009-06-24 ソニー株式会社 High frequency integrated circuit device
JP2000340736A (en) * 1999-05-26 2000-12-08 Sony Corp Semiconductor device, packaging structure thereof and manufacturing method of them
JP2001127246A (en) * 1999-10-29 2001-05-11 Fujitsu Ltd Semiconductor device
JP2001223326A (en) * 2000-02-09 2001-08-17 Hitachi Ltd Semiconductor device
JP2001358280A (en) * 2000-04-12 2001-12-26 Sony Corp Lead frame, its manufacturing method, semiconductor integrated circuit device, and its manufacturing method
JP3916854B2 (en) * 2000-06-28 2007-05-23 シャープ株式会社 Wiring board, semiconductor device, and package stack semiconductor device
JP2002040095A (en) * 2000-07-26 2002-02-06 Nec Corp Semiconductor device and mounting method thereof
JP4570809B2 (en) 2000-09-04 2010-10-27 富士通セミコンダクター株式会社 Multilayer semiconductor device and manufacturing method thereof
JP2002158326A (en) * 2000-11-08 2002-05-31 Apack Technologies Inc Semiconductor device and manufacturing method thereof
JP3798620B2 (en) * 2000-12-04 2006-07-19 富士通株式会社 Manufacturing method of semiconductor device
US6340846B1 (en) * 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
JP2002184936A (en) * 2000-12-11 2002-06-28 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2002217354A (en) * 2001-01-15 2002-08-02 Shinko Electric Ind Co Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5373189A (en) * 1992-08-13 1994-12-13 Commissariate A L'energie Atomique Three-dimensional multichip module
US6075289A (en) * 1996-10-24 2000-06-13 Tessera, Inc. Thermally enhanced packaged semiconductor assemblies

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1547141A4 *

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WO2004027823A2 (en) 2004-04-01
EP1547141A4 (en) 2010-02-24
JP4800625B2 (en) 2011-10-26
JP2013211589A (en) 2013-10-10
AU2003272405A8 (en) 2004-04-08
JP2005539403A (en) 2005-12-22
AU2003272405A1 (en) 2004-04-08
TW201131731A (en) 2011-09-16
JP5856103B2 (en) 2016-02-09
EP1547141A2 (en) 2005-06-29
KR20050044925A (en) 2005-05-13
TW200419765A (en) 2004-10-01
JP5602685B2 (en) 2014-10-08
TWI469301B (en) 2015-01-11
KR101166575B1 (en) 2012-07-18
TW201017853A (en) 2010-05-01
JP2011181971A (en) 2011-09-15
TWI329918B (en) 2010-09-01
TWI378548B (en) 2012-12-01

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