JP2000294723A - Stacked semiconductor device and its manufacture - Google Patents
Stacked semiconductor device and its manufactureInfo
- Publication number
- JP2000294723A JP2000294723A JP10227999A JP10227999A JP2000294723A JP 2000294723 A JP2000294723 A JP 2000294723A JP 10227999 A JP10227999 A JP 10227999A JP 10227999 A JP10227999 A JP 10227999A JP 2000294723 A JP2000294723 A JP 2000294723A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor device
- carrier substrate
- stacked
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、フリップチップ実
装工法で実装した半導体装置どうしまたは、フリップチ
ップ実装工法の半導体装置と、もう一つ別の半導体装置
（外周部に電気的接続が取れる電極端子部を有している
半導体装置）とが放熱性接着剤を介して、接着させた積
層型の半導体装置に関するもので、特に、積層化した半
導体装置の放熱性の向上化を図り、半導体装置の大容量
化・高機能化・高信頼性化を実現することができること
を目的とした積層型半導体装置に関するものである。ま
た、従来のフリップチップ実装構造の半導体装置を個々
に実装することよりも、更に、高密度実装化を実現する
ことができることを特徴とした積層型半導体装置とその
製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted by a flip-chip mounting method, a semiconductor device manufactured by a flip-chip mounting method, and another semiconductor device (electrode terminal which can be electrically connected to an outer peripheral portion). Semiconductor device having a portion) is related to a stacked semiconductor device bonded via a heat-radiating adhesive, and in particular, to improve heat dissipation of the stacked semiconductor device, The present invention relates to a stacked semiconductor device for achieving high capacity, high functionality, and high reliability. Also, the present invention relates to a stacked semiconductor device characterized in that it is possible to realize a higher density mounting than to individually mount a conventional semiconductor device having a flip chip mounting structure, and to a method of manufacturing the same.
【０００２】[0002]
【従来の技術】一般的に積層型半導体装置は、複数の半
導体装置を積層化するため、技術的に放熱特性が重要課
題となっている。従来の積層型半導体装置は、リードフ
レーム上下に、２種類の半導体素子を搭載し、ワイヤー
ボンディングにより電気的に接続し、半導体素子全体を
モールド封止しているなどの構造であり、筐体を通じ
て、電子機器のシステム本体への熱放散させる機構が十
分でない構造であった。2. Description of the Related Art Generally, in a stacked semiconductor device, since a plurality of semiconductor devices are stacked, the heat radiation characteristic is technically an important issue. A conventional stacked semiconductor device has a structure in which two types of semiconductor elements are mounted above and below a lead frame, electrically connected by wire bonding, and the entire semiconductor element is molded and sealed. However, the mechanism for dissipating heat to the system body of the electronic device is not sufficient.
【０００３】以下、図面を参照して従来の積層型半導体
装置の構造例について説明する。図５および図６は、従
来の積層型半導体装置を示す断面図である。Hereinafter, an example of the structure of a conventional stacked semiconductor device will be described with reference to the drawings. 5 and 6 are cross-sectional views showing a conventional stacked semiconductor device.
【０００４】まず図５に示すような積層型半導体装置
は、第１の半導体素子１の電極（図示せず）に金などの
バンプ２を形成し、このバンプ２に銅材よりなるリード
３をインナーボンディングし、続いて、そのリード３を
リードフレーム４にアウターボンディングを施して接続
する。さらに、リードフレーム４を裏返しにして、第２
の半導体素子５に、再び前記の処理を施すことにより、
第２の半導体素子５のバンプ２とリードフレーム４との
間を銅材のリ−ド３で接続する。その後、封止樹脂６に
より樹脂モールドを施こし、リードフレーム４を必要な
形状に成形加工し、樹脂封止型の積層型半導体装置を構
成している。First, in a stacked semiconductor device as shown in FIG. 5, a bump 2 made of gold or the like is formed on an electrode (not shown) of a first semiconductor element 1, and a lead 3 made of a copper material is formed on the bump 2. Then, the leads 3 are connected to the lead frame 4 by outer bonding. Further, the lead frame 4 is turned over and the second
By performing the above-described processing again on the semiconductor element 5 of
The bumps 2 of the second semiconductor element 5 and the lead frames 4 are connected by copper leads 3. After that, a resin mold is applied with the sealing resin 6 and the lead frame 4 is formed into a required shape to form a resin-sealed stacked semiconductor device.
【０００５】次に、従来の積層型半導体装置として別の
例を図６に示している。図６は従来の積層型半導体装置
を示す断面図である。Next, another example of a conventional stacked semiconductor device is shown in FIG. FIG. 6 is a sectional view showing a conventional stacked semiconductor device.
【０００６】図６に示すように、従来のフリップチップ
実装型の積層型半導体装置は、その主面の電極パッド７
にバンプ２が形成された第１の半導体素子１が、その主
面を下にして（フリップチップ）、支持体であるセラミ
ックを絶縁基体とした多層回路基板よりなる半導体キャ
リア基板８上の複数の電極９とが半田あるいは導電性接
着剤等により接合されている。そして、接合された第１
の半導体素子１と半導体キャリア基板８との隙間には、
エポキシ系の封止樹脂６が充填封止されている。なお、
半導体キャリア基板８は、その裏面に外部端子１０を有
し、電極９と外部端子１０とは半導体キャリア基板８内
に形成されたビア(図示せず）により、内部接続されて
いる。そしてもう一つ別の第２の半導体素子５が、半田
または導電性接着剤１１等を介して、第１の半導体素子
１の裏面と接合されており、この第２の半導体素子５の
表面の電極パッド７から、半導体キャリア基板８の表面
外周部にあるボンディングパッド１２に金属細線１３で
ボンディングされている。そして第１の半導体素子１、
第２の半導体素子５および金属細線１３を含む半導体キ
ャリア基板８の上面側を封止樹脂６で樹脂モールドして
積層型半導体装置を構成している。As shown in FIG. 6, a conventional flip-chip mounting type laminated semiconductor device has an electrode pad 7 on its main surface.
The first semiconductor element 1 on which the bumps 2 are formed is formed on a semiconductor carrier substrate 8 composed of a multilayer circuit board having a ceramic support as an insulating base with its main surface facing down (flip chip). The electrode 9 is joined with solder or a conductive adhesive or the like. And the joined first
In the gap between the semiconductor element 1 and the semiconductor carrier substrate 8,
An epoxy-based sealing resin 6 is filled and sealed. In addition,
The semiconductor carrier substrate 8 has external terminals 10 on its back surface, and the electrodes 9 and the external terminals 10 are internally connected by vias (not shown) formed in the semiconductor carrier substrate 8. Further, another second semiconductor element 5 is joined to the back surface of the first semiconductor element 1 via a solder or a conductive adhesive 11 or the like. The metal pads 13 are bonded from the electrode pads 7 to the bonding pads 12 on the outer periphery of the surface of the semiconductor carrier substrate 8. And the first semiconductor element 1,
The upper surface side of the semiconductor carrier substrate 8 including the second semiconductor element 5 and the fine metal wires 13 is resin-molded with the sealing resin 6 to form a stacked semiconductor device.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら前記従来
の積層型半導体装置の構造では、発熱体である半導体素
子からの発熱を、電子機器システム内の筐体を通じて効
率良く、且つ十分に放散させるための高放熱システム機
能が組み込まれておらず、消費電力が高い仕様の半導体
素子を積層化した半導体装置に組み込んだ場合、急激な
半導体素子の温度上昇により半導体素子が破壊し、その
積層型半導体装置が動作しなくなるといった不具合が発
生する。そのため、高放熱仕様の積層型半導体装置の実
現を図ることが重要であり、且つ大容量化し、高機能化
した積層型半導体装置の実現が必要不可欠であった。However, in the structure of the conventional stacked semiconductor device, the heat generated from the semiconductor element as the heating element is efficiently and sufficiently dissipated through the housing in the electronic equipment system. If a high-heat dissipation system function is not built in and a semiconductor device with high power consumption is incorporated into a stacked semiconductor device, the semiconductor device will be destroyed due to a rapid rise in temperature of the semiconductor device, and the stacked semiconductor device A malfunction such as not operating occurs. Therefore, it is important to realize a stacked semiconductor device having a high heat dissipation specification, and it is essential to realize a stacked semiconductor device having a large capacity and a high function.
【０００８】本発明は、前記従来の課題を解決するもの
で、複数の半導体素子より発生する熱の放熱特性を向上
させ、積層型半導体装置の信頼性の向上化を図ることは
もちろん、従来の２つの半導体素子を個々に実装する場
合に比べ信号遅延が小さく、且つ実装面積を縮小化する
こともできる半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. The present invention improves the heat radiation characteristics of heat generated from a plurality of semiconductor elements and improves the reliability of a stacked semiconductor device. It is an object of the present invention to provide a semiconductor device in which a signal delay is small and a mounting area can be reduced as compared with a case where two semiconductor elements are individually mounted.
【０００９】[0009]
【課題を解決するための手段】前記課題を解決するため
に本発明の積層型半導体装置は、以下のような構成を有
している。すなわち、概念的には、少なくとも第１の半
導体装置と第２の半導体装置とよりなり、互いの半導体
装置どうしを放熱性接着剤を介して積層化して接合した
積層型半導体装置であって、前記第１の半導体装置上に
第２の半導体装置が積層され、前記第１の半導体装置と
第２の半導体装置とが電気的に接続され、前記第２の半
導体装置上に放熱用の金属製プレート板が設けられ、前
記金属製プレート板が露出するように、前記第１の半導
体装置と前記第２の半導体装置との外囲を封止樹脂で封
止した積層型半導体装置である。In order to solve the above-mentioned problems, a stacked semiconductor device according to the present invention has the following configuration. That is, conceptually, a stacked semiconductor device comprising at least a first semiconductor device and a second semiconductor device, wherein the semiconductor devices are stacked and bonded together via a heat-radiating adhesive, A second semiconductor device is stacked on the first semiconductor device, the first semiconductor device and the second semiconductor device are electrically connected, and a metal plate for heat dissipation is provided on the second semiconductor device. A stacked semiconductor device in which a plate is provided and an outer periphery of the first semiconductor device and the second semiconductor device is sealed with a sealing resin so that the metal plate plate is exposed.
【００１０】また、本発明の積層型半導体装置は、底面
に外部端子を有し、上面に前記外部端子と基板内接続し
た電極を有した絶縁性回路基板よりなる第１の半導体キ
ャリア基板と、前記電極に対応してその主面の電極パッ
ドがバンプを介して接合された第１の半導体素子とより
なる第１の半導体装置と、底面に外部端子を有し、上面
に前記外部端子と基板内接続した電極を有した絶縁性回
路基板よりなる第２の半導体キャリア基板と、前記電極
に対応してその主面の電極パッドがバンプを介して接合
された第２の半導体素子とよりなる第２の半導体装置と
が放熱性接着剤を介して積層化して接合した積層型半導
体装置であって、前記第１の半導体素子の裏面と第２の
半導体素子の裏面とが接合され、前記第２の半導体キャ
リア基板の底面の外部端子と前記第１の半導体キャリア
基板の上面の電極とが金属細線で電気的に接続され、前
記第２の半導体キャリア基板の底面上に放熱用の金属製
プレート板が設けられ、前記金属製プレート板が露出す
るように、前記第１の半導体キャリア基板の上面領域の
前記第２の半導体装置を含む領域を封止樹脂で封止した
積層型半導体装置である。[0010] The stacked semiconductor device of the present invention further comprises a first semiconductor carrier substrate comprising an insulating circuit substrate having external terminals on a bottom surface and electrodes connected to the external terminals and the substrate on the upper surface; A first semiconductor device comprising a first semiconductor element in which an electrode pad on a main surface corresponding to the electrode is bonded via a bump; an external terminal on a bottom surface; A second semiconductor carrier substrate comprising an insulated circuit board having internally connected electrodes; and a second semiconductor element comprising a second semiconductor element having an electrode pad on the main surface thereof bonded to the corresponding electrode via a bump. A second semiconductor device, wherein the back surface of the first semiconductor element and the back surface of the second semiconductor element are bonded to each other, Of the bottom of the semiconductor carrier substrate The terminal and the electrode on the upper surface of the first semiconductor carrier substrate are electrically connected by thin metal wires, and a metal plate plate for heat radiation is provided on the bottom surface of the second semiconductor carrier substrate. A stacked semiconductor device in which a region including an upper surface region of the first semiconductor carrier substrate and including the second semiconductor device is sealed with a sealing resin so that a plate plate is exposed.
【００１１】また、底面に外部端子を有し、上面に前記
外部端子と基板内接続した電極を有した絶縁性回路基板
よりなる第１の半導体キャリア基板と、前記電極に対応
してその主面の電極パッドがバンプを介して接合された
第１の半導体素子とよりなる第１の半導体装置と、底面
に外部端子を有し、上面に前記外部端子と基板内接続し
た電極を有した絶縁性回路基板よりなる第２の半導体キ
ャリア基板と、前記電極に対応してその主面の電極パッ
ドがバンプを介して接合された第２の半導体素子とより
なる第２の半導体装置とが放熱性接着剤を介して積層化
して接合した積層型半導体装置であって、前記第１の半
導体素子の裏面と第２の半導体キャリア基板の底面とが
金属製プレート板を介して前記放熱性接着剤により接合
され、前記第２の半導体キャリア基板の上面の電極と前
記第１の半導体キャリア基板の上面の電極とが金属細線
で電気的に接続され、前記第１の半導体キャリア基板の
上面領域の前記第２の半導体装置を含む領域を封止樹脂
で封止した積層型半導体装置である。Also, a first semiconductor carrier substrate comprising an insulating circuit board having an external terminal on a bottom surface and an electrode connected to the external terminal and the substrate on an upper surface, and a main surface corresponding to the electrode A first semiconductor device comprising a first semiconductor element in which electrode pads are bonded via bumps, an insulating device having an external terminal on a bottom surface, and an electrode connected to the external terminal in the substrate on an upper surface. A second semiconductor device comprising a second semiconductor carrier substrate comprising a circuit substrate and a second semiconductor device comprising a second semiconductor element having an electrode pad on the main surface corresponding to the electrode and joined via a bump is bonded to the second semiconductor carrier substrate. A laminated semiconductor device laminated and bonded via an agent, wherein a back surface of the first semiconductor element and a bottom surface of a second semiconductor carrier substrate are bonded by the heat-radiating adhesive via a metal plate plate. And the second An electrode on the upper surface of the conductor carrier substrate and an electrode on the upper surface of the first semiconductor carrier substrate are electrically connected by a thin metal wire, and a region of the upper surface region of the first semiconductor carrier substrate including the second semiconductor device. Is a stacked semiconductor device in which is sealed with a sealing resin.
【００１２】さらに具体的には、第１の半導体素子と第
１の半導体キャリア基板との間隙、および第２の半導体
素子と第２の半導体キャリア基板との間隙には、それぞ
れ樹脂が充填封止されている積層型半導体装置である。More specifically, resin is filled and sealed in the gap between the first semiconductor element and the first semiconductor carrier substrate and in the gap between the second semiconductor element and the second semiconductor carrier substrate, respectively. Is a stacked semiconductor device.
【００１３】本発明の積層型半導体装置の製造方法にお
いては、第１の半導体素子の主面の電極パッドにバンプ
を形成し、そのバンプの先端部に導電性接着剤を形成
し、第２の半導体素子の電極パッドにバンプを形成し、
その先端部に導電性接着剤を形成する工程と、前記第１
の半導体チップをその主面側を下にして第１の半導体キ
ャリア基板の上面の電極に対応させ、バンプ上の導電性
接着剤を介して接合し、第２の半導体チップをその主面
側を下にして第２の半導体キャリア基板の上面の電極に
対応させ、バンプ上の導電性接着剤を介して接合する工
程と、前記第１の半導体素子と第１の半導体キャリア基
板との間隙に封止樹脂を注入して充填封止し、前記第２
の半導体素子と第２の半導体キャリア基板との間隙に封
止樹脂を注入して充填封止する工程と、前記第２の半導
体素子側の第２の半導体キャリアの裏面の略中央部に対
して、放熱性接着剤を用いて、放熱用の金属製プレート
板を接合する工程と、前記第１の半導体キャリアに接合
された第１の半導体素子の裏面と、第２の半導体キャリ
ア基板が接合された第２の半導体素子の裏面とを放熱性
接着剤により接合して積層構造を構成する工程と、前記
第２の半導体素子が接合された第２の半導体キャリアの
電極端子と前記第１の半導体キャリアの上面のボンディ
ングパッド部とを金属細線により電気的に接続する工程
と、前記金属製プレート板が被らないように、前記第１
の半導体キャリア基板の上面領域をポッティング封止樹
脂で封止し、前記第１の半導体素子、第２の半導体素子
および金属細線による接続領域を封止する工程とよりな
る積層型半導体装置の製造方法である。In the method of manufacturing a stacked semiconductor device according to the present invention, a bump is formed on an electrode pad on a main surface of a first semiconductor element, and a conductive adhesive is formed on a tip of the bump. Form bumps on the electrode pads of the semiconductor element,
Forming a conductive adhesive at the tip thereof;
The semiconductor chip of the above is made to correspond to the electrode on the upper surface of the first semiconductor carrier substrate with its main surface side down, joined via a conductive adhesive on the bumps, and the second semiconductor chip is connected with its main surface side A step of lowering the electrode so as to correspond to an electrode on the upper surface of the second semiconductor carrier substrate and bonding it via a conductive adhesive on the bump; and sealing the gap between the first semiconductor element and the first semiconductor carrier substrate. The sealing resin is injected and filled and sealed.
Injecting a sealing resin into a gap between the semiconductor element and the second semiconductor carrier substrate to fill and seal the gap, and applying a sealing resin to a substantially central portion of the back surface of the second semiconductor carrier on the second semiconductor element side. Bonding a metal plate plate for heat radiation using a heat-radiating adhesive, and bonding the second semiconductor carrier substrate to the back surface of the first semiconductor element bonded to the first semiconductor carrier. Forming a laminated structure by bonding the back surface of the second semiconductor element to the back surface of the second semiconductor element with a heat dissipating adhesive, and connecting the electrode terminal of the second semiconductor carrier to which the second semiconductor element is bonded and the first semiconductor Electrically connecting the bonding pad portion on the upper surface of the carrier with a thin metal wire, and the first metal plate so as not to cover the metal plate.
Sealing the upper surface region of the semiconductor carrier substrate with a potting sealing resin, and sealing the connection region by the first semiconductor element, the second semiconductor element, and the thin metal wire. It is.
【００１４】前記構成の通り、放熱用の金属製プレート
板、放熱性接着剤を用いているので、発熱体である２種
の半導体素子からの熱エネルギ−を、電子機器内の筐体
を通じて効率良く熱放散することにより、積層化した半
導体装置の高放熱化が図れるものである。これにより、
急激な半導体装置の温度上昇による半導体装置の破壊を
防止し、半導体装置の大容量化・高速化及び更なる高密
度実装化等が実現できるものである。As described above, since the metal plate plate for heat dissipation and the heat dissipation adhesive are used, the heat energy from the two types of semiconductor elements, which are the heating elements, can be efficiently transmitted through the housing in the electronic equipment. By dissipating heat well, high heat dissipation of the stacked semiconductor devices can be achieved. This allows
The semiconductor device can be prevented from being destroyed due to a rapid rise in the temperature of the semiconductor device, and the capacity and speed of the semiconductor device can be increased, and further high-density mounting can be realized.
【００１５】[0015]
【発明の実施の形態】本発明の積層型半導体装置は、放
熱性接着剤により２つの半導体装置を接合し、上側の半
導体装置に放熱用の部材、例えば金属製プレート板を設
けたものであり、少なくとも第１の半導体装置と第２の
半導体装置とよりなり、互いの半導体装置どうしを放熱
性接着剤を介して積層化して接合した積層型半導体装置
であって、第１の半導体装置上に第２の半導体装置が積
層され、その第１の半導体装置と第２の半導体装置とが
電気的に接続され、また第２の半導体装置上に放熱用の
金属製プレート板が設けられ、その金属製プレート板が
露出するように、第１の半導体装置と第２の半導体装置
との外囲を封止樹脂で封止した構成を有するものであ
る。BEST MODE FOR CARRYING OUT THE INVENTION A stacked semiconductor device according to the present invention is a device in which two semiconductor devices are joined by a heat-radiating adhesive, and a heat-dissipating member, for example, a metal plate is provided on the upper semiconductor device. A stacked semiconductor device comprising at least a first semiconductor device and a second semiconductor device, wherein the semiconductor devices are stacked and bonded together via a heat-radiating adhesive, and A second semiconductor device is stacked, the first semiconductor device is electrically connected to the second semiconductor device, and a metal plate for heat dissipation is provided on the second semiconductor device. The semiconductor device has a configuration in which the outer periphery of the first semiconductor device and the second semiconductor device is sealed with a sealing resin so that the plate plate is exposed.
【００１６】以下、本発明の積層型半導体装置およびそ
の製造方法の一実施形態について図面を参照しながら説
明する。Hereinafter, an embodiment of a stacked semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings.
【００１７】まず第１の実施形態にかかる積層型半導体
装置について説明する。図１は本実施形態の積層型半導
体装置を示す断面図である。なお図１において、図１
（ａ）は断面図であって、図１（ｂ）は図１（ａ）の破
線円の部分を拡大した図である。First, a stacked semiconductor device according to the first embodiment will be described. FIG. 1 is a cross-sectional view showing the stacked semiconductor device of the present embodiment. In FIG. 1, FIG.
1A is a cross-sectional view, and FIG. 1B is an enlarged view of a portion indicated by a broken circle in FIG. 1A.
【００１８】図１に示すように本実施形態の積層型半導
体装置は、その主面の電極パッド７にバンプ２の形成さ
れた第１の半導体素子１がその主面側を下にして、支持
体であるセラミックを絶縁基体とした多層回路基板より
成る半導体キャリア基板８ａに接合されている。ここで
第１の半導体素子１上に形成されたバンプ２と半導体キ
ャリア基板８ａ上の複数の電極９ａとが半田あるいは導
電性接着剤１４等により接合されている。そして接合さ
れた第１の半導体素子１と半導体キャリア基板８ａとの
隙間には、エポキシ系の封止樹脂６が充填封止されてい
る。なお、半導体キャリア基板８ａはその裏面に外部端
子１０を有し、電極９ａと外部端子１０とは、半導体キ
ャリア基板８ａ内に形成されたビア（図示せず）により
内部接続されているものである。そして第１の半導体素
子１の裏面側に放熱性接着剤１５を介して第２の半導体
素子５がその裏面側で接合されており、この第２の半導
体素子５もまた第１の半導体素子の実装構造と同様に、
その主面の電極パッド７にバンプ２の形成された第２の
半導体素子５がその主面側を下にして、支持体であるセ
ラミックを絶縁基体とした多層回路基板より成る半導体
キャリア基板８ｂに接合されている。そして同様に、第
２の半導体素子５上に形成されたバンプ２と半導体キャ
リア基板８ｂ上の複数の電極９ｂとが半田あるいは導電
性接着剤等１４により接合されている。そして接合され
た第２の半導体素子５と半導体キャリア基板８ｂとの隙
間には、エポキシ系の封止樹脂６が充填封止されてい
る。なお、半導体キャリア基板８ｂはその裏面に外部端
子１０を有し、電極９ｂと外部端子１０とは、半導体キ
ャリア基板８ｂ内に形成されたビア（図示せず）により
内部接続されているものである。As shown in FIG. 1, in the stacked semiconductor device of this embodiment, the first semiconductor element 1 having the bumps 2 formed on the electrode pads 7 on the main surface thereof is supported with its main surface side down. It is joined to a semiconductor carrier substrate 8a composed of a multilayer circuit board having a ceramic body as an insulating base. Here, the bumps 2 formed on the first semiconductor element 1 and the plurality of electrodes 9a on the semiconductor carrier substrate 8a are joined by solder, a conductive adhesive 14, or the like. The gap between the joined first semiconductor element 1 and the semiconductor carrier substrate 8a is filled and sealed with an epoxy-based sealing resin 6. The semiconductor carrier substrate 8a has external terminals 10 on the back surface, and the electrodes 9a and the external terminals 10 are internally connected by vias (not shown) formed in the semiconductor carrier substrate 8a. . The second semiconductor element 5 is joined to the back side of the first semiconductor element 1 via a heat-radiating adhesive 15 on the back side, and this second semiconductor element 5 is also a part of the first semiconductor element. Like the mounting structure,
The second semiconductor element 5 in which the bumps 2 are formed on the electrode pads 7 on the main surface is placed on the semiconductor carrier substrate 8b composed of a multilayer circuit board using ceramic as an insulating base as a supporting body with the main surface side down. Are joined. Similarly, the bumps 2 formed on the second semiconductor element 5 and the plurality of electrodes 9b on the semiconductor carrier substrate 8b are joined by solder or a conductive adhesive 14 or the like. The gap between the bonded second semiconductor element 5 and the semiconductor carrier substrate 8b is filled and sealed with an epoxy-based sealing resin 6. The semiconductor carrier substrate 8b has external terminals 10 on its back surface, and the electrodes 9b and the external terminals 10 are internally connected by vias (not shown) formed in the semiconductor carrier substrate 8b. .
【００１９】また、積層化した２種の半導体素子のう
ち、第２の半導体素子５からの電気的信号を電気的にユ
ーザ基板へ導くため、第２の半導体素子５の半導体キャ
リア基板８ｂ裏面の外周部にある電極端子１６から、積
層化した下側にある第１の半導体素子１の半導体キャリ
ア基板８ａの表層面外周部に設けたボンディングパッド
部１７へ金線等の金属細線１３でボンディングしている
ものである。そして第２の半導体素子５側の半導体キャ
リア基板８ｂの裏面の略中央部には、放熱用の金属メッ
キ層または金属製プレート板１８が設けられているもの
である。In order to electrically guide the electric signal from the second semiconductor element 5 to the user substrate among the two kinds of stacked semiconductor elements, the back surface of the semiconductor carrier substrate 8b of the second semiconductor element 5 is formed. Bonding is performed from the electrode terminal 16 on the outer peripheral portion to the bonding pad portion 17 provided on the outer peripheral portion of the surface layer surface of the semiconductor carrier substrate 8a of the first semiconductor element 1 on the lower side by the thin metal wire 13 such as a gold wire. Is what it is. A metal plate layer 18 for heat dissipation or a metal plate 18 is provided substantially at the center of the back surface of the semiconductor carrier substrate 8b on the second semiconductor element 5 side.
【００２０】そして金属製プレート板1８が被さらない
ように、半導体キャリア基板８ａの上面領域をポッティ
ング封止樹脂１９で封止しているものである。The upper surface area of the semiconductor carrier substrate 8a is sealed with a potting sealing resin 19 so as not to cover the metal plate plate 18.
【００２１】なお、半導体キャリア８ｂの略中央部に設
けた放熱用の金属製プレート板１８の上面には、マーク
インク２０で積層化した半導体装置の製品品番や密番等
をマーキング捺印しているものである。また、半導体キ
ャリア基板８ａはポッティング封止樹脂１９がはみ出さ
ないように、基板の周囲には上方に突出した枠部が形成
されているものである。The product number, dense number, etc. of the stacked semiconductor devices are marked and stamped with the mark ink 20 on the upper surface of the metal plate plate 18 for heat radiation provided substantially at the center of the semiconductor carrier 8b. Things. The semiconductor carrier substrate 8a has a frame portion protruding upward around the substrate so that the potting sealing resin 19 does not protrude.
【００２２】以上のように、フリップチップ実装構造の
２つの半導体装置をその互いの半導体素子１，５の裏面
どうしを合わせて、放熱性接着剤１５を介して積層化
し、接合されているものである。この構造により、実装
面積を低減し、かつ放熱特性を向上させた積層型半導体
装置が得られるものである。As described above, the two semiconductor devices having the flip-chip mounting structure are laminated and joined together with the back surfaces of the semiconductor elements 1 and 5 interposed therebetween through the heat-radiating adhesive 15. is there. With this structure, a stacked semiconductor device having a reduced mounting area and improved heat radiation characteristics can be obtained.
【００２３】次に本実施形態の積層型半導体装置の製造
方法について、同図をもとに説明する。Next, a method of manufacturing the stacked semiconductor device according to the present embodiment will be described with reference to FIG.
【００２４】まず、個々に、第１の半導体素子１の主面
の電極パッド７にバンプ２を形成し、そのバンプ２の先
端部に導電性接着剤１４を転写法により形成する。同様
に第２の半導体素子５の電極パッド７にもバンプ２を形
成し、その先端部に導電性接着剤１４を転写法により形
成する。First, the bumps 2 are individually formed on the electrode pads 7 on the main surface of the first semiconductor element 1, and a conductive adhesive 14 is formed on the tip of the bump 2 by a transfer method. Similarly, the bump 2 is also formed on the electrode pad 7 of the second semiconductor element 5, and a conductive adhesive 14 is formed on the tip of the bump 2 by a transfer method.
【００２５】次に、個々に第１の半導体チップ１をその
主面側を下にして半導体キャリア基板８ａの電極９ａに
対応させ、バンプ２上の導電性接着剤１４を介して接合
する。同様に第２の半導体チップ５をその主面側を下に
して半導体キャリア基板８ｂの電極９ｂに対応させ、バ
ンプ２上の導電性接着剤１４を介して接合する。なお、
半導体素子と半導体キャリアとの接合においては、導電
性接着剤１４の硬化のために所定条件で加熱処理を行
う。Next, the first semiconductor chips 1 are individually bonded with the main surface side down to correspond to the electrodes 9a of the semiconductor carrier substrate 8a via the conductive adhesive 14 on the bumps 2. Similarly, the second semiconductor chip 5 is joined with the main surface side down to the electrode 9b of the semiconductor carrier substrate 8b via the conductive adhesive 14 on the bump 2. In addition,
In joining the semiconductor element and the semiconductor carrier, heat treatment is performed under predetermined conditions to cure the conductive adhesive 14.
【００２６】次に、個々に第１の半導体素子１と半導体
キャリア基板８ａとの間隙に封止樹脂６を注入して充填
封止する。同様に第２の半導体素子５と半導体キャリア
基板８ｂとの間隙に封止樹脂６を注入して充填封止す
る。通常、封止樹脂６に用いる樹脂は熱硬化型であるた
め、樹脂注入して加熱し、樹脂を熱硬化させて封止す
る。Next, a sealing resin 6 is individually injected into the gap between the first semiconductor element 1 and the semiconductor carrier substrate 8a and filled and sealed. Similarly, a sealing resin 6 is injected into the gap between the second semiconductor element 5 and the semiconductor carrier substrate 8b to fill and seal. Usually, since the resin used for the sealing resin 6 is a thermosetting resin, the resin is injected and heated, and the resin is thermoset and sealed.
【００２７】次に、第２の半導体素子５側の半導体キャ
リア８ｂの裏面の略中央部に対して、放熱性接着剤を用
いて、放熱用の金属製プレート板１８を接合する。また
は金属製プレート板１８の代わりに、金属メッキ層を形
成してもよい。なお、ここで、放熱用の金属製プレート
板１８を半導体キャリア基板８ｂ裏面の中央部付近に接
合するのは、放熱特性を向上させるために熱伝導を均一
にするためである。Next, a metal plate 18 for heat dissipation is joined to a substantially central portion of the back surface of the semiconductor carrier 8b on the second semiconductor element 5 side using a heat dissipation adhesive. Alternatively, a metal plating layer may be formed instead of the metal plate 18. Here, the reason why the metal plate 18 for heat dissipation is joined to the vicinity of the center of the back surface of the semiconductor carrier substrate 8b is to make heat conduction uniform in order to improve heat dissipation characteristics.
【００２８】次に、半導体キャリア８ａに接合された第
１の半導体素子１の裏面と、半導体キャリア基板８ｂが
接合された第２の半導体素子５の裏面とを放熱性接着剤
１５により接合して積層構造を構成する。なお、この工
程の後に前記工程で形成した放熱用の金属製プレート板
１８を半導体キャリア８ｂの裏面に接合してもよい。Next, the back surface of the first semiconductor element 1 joined to the semiconductor carrier 8a and the back surface of the second semiconductor element 5 joined to the semiconductor carrier substrate 8b are joined by a heat-radiating adhesive 15. Configure a laminated structure. After this step, the metal plate 18 for heat dissipation formed in the above step may be joined to the back surface of the semiconductor carrier 8b.
【００２９】そして、第２の半導体素子５が接合された
半導体キャリア８ｂの電極端子１６と半導体キャリア８
ａのボンディングパッド部１７とを金属細線１３により
電気的に接続する。Then, the electrode terminal 16 of the semiconductor carrier 8b to which the second semiconductor element 5 is joined and the semiconductor carrier 8
a is electrically connected to the bonding pad portion 17 of FIG.
【００３０】最後に金属製プレート板1８が被さらない
ように、半導体キャリア基板８ａの上面領域をポッティ
ング封止樹脂１９で封止し、第１の半導体素子１、第２
の半導体素子５および金属細線１３による接続領域を封
止し、積層型半導体装置を得る。Finally, the upper surface area of the semiconductor carrier substrate 8a is sealed with a potting sealing resin 19 so as not to cover the metal plate plate 18, so that the first semiconductor element 1 and the second
The connection region of the semiconductor element 5 and the thin metal wire 13 is sealed to obtain a stacked semiconductor device.
【００３１】また通常の製品製造工程では、積層型半導
体装置の半導体キャリア８ｂの略中央部に設けた放熱用
の金属製プレート板１８の上面に、マークインク２０で
積層化した半導体装置の製品品番や密番等をマーキング
捺印する。In a normal product manufacturing process, the product number of the semiconductor device laminated with the mark ink 20 is formed on the upper surface of a metal plate plate 18 for heat radiation provided substantially at the center of the semiconductor carrier 8b of the stacked semiconductor device. And a secret number.
【００３２】次に本実施形態の積層型半導体装置を応用
した実施形態について説明する。図２は本実施形態の積
層型半導体装置を示す断面図である。Next, an embodiment to which the stacked semiconductor device of this embodiment is applied will be described. FIG. 2 is a cross-sectional view showing the stacked semiconductor device of the present embodiment.
【００３３】図２に示す積層型半導体装置は、図１に示
した積層型半導体装置を基板に対して２つ並列に配置
し、ＭＣＭ（Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌｅ）化
した構成である。図２に示した構造は、図１に示した積
層型半導体装置として、第１の積層型半導体装置２１と
第２の積層型半導体装置２２とを１つの基板２３上に形
成し、それら２つの積層型半導体装置を一体でポッティ
ング封止樹脂１９で封止したものである。そして各積層
型半導体装置から発生する熱を電子機器内の筐体２４を
通じて放熱することが可能となり、更なる高密度実装化
が図れるものである。これにより、例えば４種の半導体
素子を積層化し、１つの基板に実装でき、高密度実装化
を実現できる。なお、他の構成は図１に示した構成と同
じである。The stacked semiconductor device shown in FIG. 2 has a configuration in which two stacked semiconductor devices shown in FIG. 1 are arranged in parallel with respect to a substrate to form an MCM (Multi Chip Module). In the structure shown in FIG. 2, a first stacked semiconductor device 21 and a second stacked semiconductor device 22 are formed on one substrate 23 as the stacked semiconductor device shown in FIG. The stacked semiconductor device is integrally sealed with a potting sealing resin 19. Then, the heat generated from each stacked semiconductor device can be radiated through the housing 24 in the electronic device, so that further high-density mounting can be achieved. Thus, for example, four types of semiconductor elements can be stacked and mounted on one substrate, and high-density mounting can be realized. The other configuration is the same as the configuration shown in FIG.
【００３４】次に本実施形態の積層型半導体装置を応用
した別の実施形態について説明する。図３は本実施形態
の積層型半導体装置を示す断面図である。Next, another embodiment to which the stacked semiconductor device of this embodiment is applied will be described. FIG. 3 is a sectional view showing the stacked semiconductor device of the present embodiment.
【００３５】図３に示す積層型半導体装置は、図１に示
した積層型半導体装置における上側の半導体装置とし
て、図１のようにフリップチップ実装した半導体装置で
はなく、パッケージ底面に外部電極２５が配列したモー
ルド封止型の半導体装置２６を第１の半導体素子１の裏
面に対して、放熱性接着剤１５により接合した構成であ
る。なお、他の構成は図１に示した構成と同じである。
図３の構成のように、フリップチップ実装した半導体装
置どうしでなくとも積層型を構成し、半導体装置２６の
裏面中央部に放熱用の金属製プレート板１８を設けるこ
とにより、電子機器の筐体へ放熱させることができるも
のであり、高密度実装を実現するとともに、放熱性を向
上させることができる。The stacked semiconductor device shown in FIG. 3 is different from the stacked semiconductor device shown in FIG. 1 in that the upper semiconductor device is not a flip-chip mounted semiconductor device as shown in FIG. The arrangement is such that the arranged mold-sealed type semiconductor devices 26 are joined to the back surface of the first semiconductor element 1 with a heat-radiating adhesive 15. The other configuration is the same as the configuration shown in FIG.
As in the configuration shown in FIG. 3, a semiconductor device mounted on a flip-chip type is formed as a stacked type, and a metal plate 18 for heat dissipation is provided at the center of the back surface of the semiconductor device 26 to thereby provide a housing for electronic equipment. Heat can be dissipated to the substrate, and high-density mounting can be realized, and heat radiation can be improved.
【００３６】次に本実施形態の積層型半導体装置を応用
した別の実施形態について説明する。図４は本実施形態
の積層型半導体装置を示す断面図である。Next, another embodiment to which the stacked semiconductor device of this embodiment is applied will be described. FIG. 4 is a sectional view showing the stacked semiconductor device of the present embodiment.
【００３７】図４に示す積層型半導体装置は、図１に示
した積層型半導体装置における上側の半導体装置とし
て、図１のように半導体素子の裏面どうしを放熱性接着
剤により接合した半導体装置ではなく、上側の半導体装
置において、半導体キャリア基板８ｂの裏面と第１の半
導体素子１の裏面とを放熱性接着剤１５により接合した
ものであり、図１に示した構造において、上側の半導体
装置が１８０度反転して接合した構造である。そして第
１の半導体素子１の裏面の略中央部には、薄型の金属製
プレート板２７を接合し、半導体キャリア基板８ｂの底
面のその金属製プレート板２７と対応する部分には凹部
２８が形成されて、金属製プレート板２７が入る構成で
あり、第１の半導体素子１の裏面、金属製プレート板２
７と半導体キャリア基板８ｂの凹部２８とは放熱性接着
剤１５により接合されている。なお、他の構成は図１に
示した構成と同じである。この構成においても、高密度
実装を実現するとともに、放熱性を向上させることがで
きる。The stacked semiconductor device shown in FIG. 4 is the same as the upper semiconductor device in the stacked semiconductor device shown in FIG. 1 except that the back surfaces of the semiconductor elements are joined by a heat-radiating adhesive as shown in FIG. Instead, in the upper semiconductor device, the rear surface of the semiconductor carrier substrate 8b and the rear surface of the first semiconductor element 1 are joined by a heat-radiating adhesive 15, and in the structure shown in FIG. It is a structure that is joined by being inverted by 180 degrees. A thin metal plate 27 is joined to a substantially central portion of the back surface of the first semiconductor element 1, and a concave portion 28 is formed in a portion of the bottom surface of the semiconductor carrier substrate 8b corresponding to the metal plate 27. Then, the metal plate plate 27 is inserted therein, and the back surface of the first semiconductor element 1 and the metal plate plate 2
7 and the concave portion 28 of the semiconductor carrier substrate 8b are joined by the heat radiation adhesive 15. The other configuration is the same as the configuration shown in FIG. Also in this configuration, high-density mounting can be realized, and heat dissipation can be improved.
【００３８】なお、各実施形態において、同一の半導体
キャリア８ａ上に種々の半導体装置を複数個積層させる
こともできるものである。In each embodiment, a plurality of various semiconductor devices can be stacked on the same semiconductor carrier 8a.
【００３９】以上、本実施形態のような構成により、発
熱体である２種の半導体素子からの熱エネルギ−を、電
子機器内の筐体を通じて効率良く熱放散することによ
り、積層化した半導体装置の高放熱化が図れるものであ
る。これにより、急激な半導体装置の温度上昇による半
導体装置の破壊を防止し、半導体装置の大容量化・高速
化及び更なる高密度実装化等が実現できるものである。As described above, according to the structure of the present embodiment, heat energy from the two types of semiconductor elements, which are heating elements, is efficiently dissipated through the housing in the electronic device, thereby forming a stacked semiconductor device. Can achieve high heat radiation. This prevents the semiconductor device from being destroyed due to an abrupt increase in the temperature of the semiconductor device, thereby realizing an increase in the capacity and speed of the semiconductor device, a higher density mounting, and the like.
【００４０】[0040]
【発明の効果】以上説明したように、本発明の積層型半
導体装置は、フリップチップ実装工法で実装した半導体
装置どうし、あるいはフリップチップ実装構造でなくて
も半導体装置裏面の外周部に電気的接続が取れる端子を
設けている半導体装置（但し積層化する際、必ず上側に
搭載される）と、フリップチップ実装構造の半導体装置
（下側に搭載）とを積層化し、互いの半導体素子の裏面
どうしを合わせて放熱性接着剤等を介して積層・接着す
るものである。As described above, the stacked semiconductor device of the present invention is electrically connected to the semiconductor device mounted by the flip-chip mounting method, or to the outer peripheral portion of the back surface of the semiconductor device even if the semiconductor device is not of the flip-chip mounting structure. A semiconductor device provided with a terminal from which the semiconductor chip can be removed (although it is always mounted on the upper side when stacking) and a semiconductor device having a flip-chip mounting structure (mounted on the lower side) are stacked, and the back surfaces of the semiconductor elements are mutually connected. Are laminated and bonded via a heat-radiating adhesive or the like.
【００４１】また、積層化した半導体装置における上側
の半導体装置の半導体キャリア基板あるいは半導体装置
の裏面中央部に設けた金属メッキ層または薄型の金属製
プレート板が完全に露出されていることにより、発熱し
た半導体素子からの熱を電子機器システム内の筐体を通
じて効率良く熱放散させることができるものである。Further, since the semiconductor carrier substrate of the upper semiconductor device in the stacked semiconductor devices or the metal plating layer or the thin metal plate plate provided at the center of the back surface of the semiconductor device is completely exposed, heat is generated. The heat from the semiconductor element can be efficiently dissipated through the housing in the electronic device system.
【００４２】これにより、高密度実装化を実現する上で
困難であった積層型半導体装置の大容量化・高機能化・
高信頼性化等を実現することができるものである。ま
た、個々の半導体装置をユーザ基板に実装するよりも、
更に実装面積の縮小化が図れるだけでなく、電気信号の
高速化も図ることができるものである。As a result, it has been difficult to realize high-density mounting, and it is difficult to increase the capacity and function of the stacked semiconductor device.
High reliability and the like can be realized. Also, rather than mounting individual semiconductor devices on a user board,
Furthermore, not only can the mounting area be reduced, but also the speed of the electrical signal can be increased.
【図１】本発明の一実施形態における積層型半導体装置
を示す断面図FIG. 1 is a sectional view showing a stacked semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施形態における積層型半導体装置
を示す断面図FIG. 2 is a sectional view showing a stacked semiconductor device according to one embodiment of the present invention;
【図３】本発明の一実施形態における積層型半導体装置
を示す断面図FIG. 3 is a sectional view showing a stacked semiconductor device according to one embodiment of the present invention;
【図４】本発明の一実施形態における積層型半導体装置
を示す断面図FIG. 4 is a sectional view showing a stacked semiconductor device according to one embodiment of the present invention;
【図５】従来の積層型半導体装置を示す断面図FIG. 5 is a cross-sectional view showing a conventional stacked semiconductor device.
【図６】従来の積層型半導体装置を示す断面図FIG. 6 is a cross-sectional view showing a conventional stacked semiconductor device.
１ 第１の半導体素子 ２ バンプ ３ リード ４ リードフレーム ５ 第２の半導体素子 ６ 封止樹脂 ７ 電極パッド ８ 半導体キャリア基板 ９ 電極 １０ 外部端子 １１ 導電性接着剤 １２ ボンディングパッド １３ 金属細線 １４ 導電性接着剤 １５ 放熱性接着剤 １６ 電極端子 １７ ボンディングパッド部 １８ 金属製プレート板 １９ 封止樹脂 ２０ マークインク ２１ 第１の半導体装置 ２２ 第２の半導体装置 ２３ 半導体キャリア基板 ２４ 筺体 ２５ 外部電極 ２６ 半導体装置 ２７ 金属製プレート板 ２８ 凹部 REFERENCE SIGNS LIST 1 first semiconductor element 2 bump 3 lead 4 lead frame 5 second semiconductor element 6 sealing resin 7 electrode pad 8 semiconductor carrier substrate 9 electrode 10 external terminal 11 conductive adhesive 12 bonding pad 13 fine metal wire 14 conductive adhesive Agent 15 Heat dissipating adhesive 16 Electrode terminal 17 Bonding pad 18 Metal plate 19 Sealing resin 20 Mark ink 21 First semiconductor device 22 Second semiconductor device 23 Semiconductor carrier substrate 24 Housing 25 External electrode 26 Semiconductor device 27 Metal plate 28 recess
Claims (5)
導体装置とよりなり、互いの半導体装置どうしを放熱性
接着剤を介して積層化して接合した積層型半導体装置で
あって、前記第１の半導体装置上に第２の半導体装置が
積層され、前記第１の半導体装置と第２の半導体装置と
が電気的に接続され、前記第２の半導体装置上に放熱用
の金属製プレート板が設けられ、前記金属製プレート板
が露出するように、前記第１の半導体装置と前記第２の
半導体装置との外囲を封止樹脂で封止したことを特徴と
する積層型半導体装置。1. A stacked semiconductor device comprising at least a first semiconductor device and a second semiconductor device, wherein the semiconductor devices are stacked and bonded together via a heat-radiating adhesive, and A second semiconductor device is stacked on the semiconductor device, the first semiconductor device and the second semiconductor device are electrically connected, and a metal plate plate for heat dissipation is provided on the second semiconductor device. A stacked semiconductor device, wherein the outer periphery of the first semiconductor device and the second semiconductor device is sealed with a sealing resin so that the metal plate plate is exposed.
端子と基板内接続した電極を有した絶縁性回路基板より
なる第１の半導体キャリア基板と、前記電極に対応して
その主面の電極パッドがバンプを介して接合された第１
の半導体素子とよりなる第１の半導体装置と、底面に外
部端子を有し、上面に前記外部端子と基板内接続した電
極を有した絶縁性回路基板よりなる第２の半導体キャリ
ア基板と、前記電極に対応してその主面の電極パッドが
バンプを介して接合された第２の半導体素子とよりなる
第２の半導体装置とが放熱性接着剤を介して積層化して
接合した積層型半導体装置であって、前記第１の半導体
素子の裏面と第２の半導体素子の裏面とが接合され、前
記第２の半導体キャリア基板の底面の外部端子と前記第
１の半導体キャリア基板の上面の電極とが金属細線で電
気的に接続され、前記第２の半導体キャリア基板の底面
上に放熱用の金属製プレート板が設けられ、前記金属製
プレート板が露出するように、前記第１の半導体キャリ
ア基板の上面領域の前記第２の半導体装置を含む領域を
封止樹脂で封止したことを特徴とする積層型半導体装
置。2. A first semiconductor carrier substrate comprising an insulating circuit board having an external terminal on a bottom surface and an electrode connected to the external terminal in the substrate on an upper surface, and a main surface corresponding to the electrode. The first electrode pad is bonded via bumps
A first semiconductor device comprising a semiconductor element, a second semiconductor carrier substrate comprising an insulating circuit substrate having an external terminal on a bottom surface and an electrode connected to the external terminal and the substrate on the upper surface, A stacked semiconductor device in which a second semiconductor device including a second semiconductor element having an electrode pad on the main surface corresponding to an electrode and bonded via a bump is stacked and bonded via a heat-radiating adhesive. Wherein the back surface of the first semiconductor element and the back surface of the second semiconductor element are joined, and an external terminal on a bottom surface of the second semiconductor carrier substrate and an electrode on an upper surface of the first semiconductor carrier substrate Are electrically connected by thin metal wires, a metal plate plate for heat dissipation is provided on the bottom surface of the second semiconductor carrier substrate, and the first semiconductor carrier substrate is exposed so that the metal plate plate is exposed. Top area Stacked semiconductor device characterized by sealed with sealing resin a region including the second semiconductor device.
端子と基板内接続した電極を有した絶縁性回路基板より
なる第１の半導体キャリア基板と、前記電極に対応して
その主面の電極パッドがバンプを介して接合された第１
の半導体素子とよりなる第１の半導体装置と、底面に外
部端子を有し、上面に前記外部端子と基板内接続した電
極を有した絶縁性回路基板よりなる第２の半導体キャリ
ア基板と、前記電極に対応してその主面の電極パッドが
バンプを介して接合された第２の半導体素子とよりなる
第２の半導体装置とが放熱性接着剤を介して積層化して
接合した積層型半導体装置であって、前記第１の半導体
素子の裏面と第２の半導体キャリア基板の底面とが金属
製プレート板を介して前記放熱性接着剤により接合さ
れ、前記第２の半導体キャリア基板の上面の電極と前記
第１の半導体キャリア基板の上面の電極とが金属細線で
電気的に接続され、前記第１の半導体キャリア基板の上
面領域の前記第２の半導体装置を含む領域を封止樹脂で
封止したことを特徴とする積層型半導体装置。3. A first semiconductor carrier substrate comprising an insulating circuit substrate having an external terminal on a bottom surface and an electrode connected to the external terminal and the substrate on the upper surface, and a main surface corresponding to the electrode. The first electrode pad is bonded via bumps
A first semiconductor device comprising a semiconductor element, a second semiconductor carrier substrate comprising an insulating circuit substrate having an external terminal on a bottom surface and an electrode connected to the external terminal and the substrate on the upper surface, A stacked semiconductor device in which a second semiconductor device including a second semiconductor element having an electrode pad on the main surface corresponding to an electrode and bonded via a bump is stacked and bonded via a heat-radiating adhesive. Wherein a back surface of the first semiconductor element and a bottom surface of a second semiconductor carrier substrate are joined by the heat-radiating adhesive via a metal plate plate, and an electrode on an upper surface of the second semiconductor carrier substrate is provided. And an electrode on an upper surface of the first semiconductor carrier substrate are electrically connected by a thin metal wire, and a region including the second semiconductor device in an upper surface region of the first semiconductor carrier substrate is sealed with a sealing resin. Features Stacked semiconductor device to.
ア基板との間隙、および第２の半導体素子と第２の半導
体キャリア基板との間隙には、それぞれ樹脂が充填封止
されていることを特徴とする請求項２または請求項３に
記載の積層型半導体装置。4. A resin is filled and sealed in a gap between the first semiconductor element and the first semiconductor carrier substrate and in a gap between the second semiconductor element and the second semiconductor carrier substrate. 4. The stacked semiconductor device according to claim 2, wherein:
バンプを形成し、そのバンプの先端部に導電性接着剤を
形成し、第２の半導体素子の電極パッドにバンプを形成
し、その先端部に導電性接着剤を形成する工程と、前記
第１の半導体チップをその主面側を下にして第１の半導
体キャリア基板の上面の電極に対応させ、バンプ上の導
電性接着剤を介して接合し、第２の半導体チップをその
主面側を下にして第２の半導体キャリア基板の上面の電
極に対応させ、バンプ上の導電性接着剤を介して接合す
る工程と、前記第１の半導体素子と第１の半導体キャリ
ア基板との間隙に封止樹脂を注入して充填封止し、前記
第２の半導体素子と第２の半導体キャリア基板との間隙
に封止樹脂を注入して充填封止する工程と、前記第２の
半導体素子側の第２の半導体キャリアの裏面の略中央部
に対して、放熱性接着剤を用いて、放熱用の金属製プレ
ート板を接合する工程と、前記第１の半導体キャリアに
接合された第１の半導体素子の裏面と、第２の半導体キ
ャリア基板が接合された第２の半導体素子の裏面とを放
熱性接着剤により接合して積層構造を構成する工程と、
前記第２の半導体素子が接合された第２の半導体キャリ
アの電極端子と前記第１の半導体キャリアの上面のボン
ディングパッド部とを金属細線により電気的に接続する
工程と、前記金属製プレート板が被らないように、前記
第１の半導体キャリア基板の上面領域をポッティング封
止樹脂で封止し、前記第１の半導体素子、第２の半導体
素子および金属細線による接続領域を封止する工程とよ
りなることを特徴とする積層型半導体装置の製造方法。5. A bump is formed on an electrode pad on the main surface of the first semiconductor element, a conductive adhesive is formed on the tip of the bump, and a bump is formed on an electrode pad of the second semiconductor element. A step of forming a conductive adhesive on the tip thereof, and a step of making the first semiconductor chip correspond to the electrode on the upper surface of the first semiconductor carrier substrate with its main surface side down, Bonding the second semiconductor chip via a conductive adhesive on bumps, with the second semiconductor chip facing the electrode on the upper surface of the second semiconductor carrier substrate with the main surface side down, and A sealing resin is injected into the gap between the first semiconductor element and the first semiconductor carrier substrate to be filled and sealed, and the sealing resin is injected into the gap between the second semiconductor element and the second semiconductor carrier substrate. Filling and sealing, and a second step on the second semiconductor element side. Bonding a heat-dissipating metal plate plate to a substantially central portion of the back surface of the semiconductor carrier using a heat-radiating adhesive; and forming a first semiconductor element bonded to the first semiconductor carrier. Bonding the back surface and the back surface of the second semiconductor element to which the second semiconductor carrier substrate is bonded with a heat-radiating adhesive to form a laminated structure;
Electrically connecting the electrode terminal of the second semiconductor carrier to which the second semiconductor element is bonded and the bonding pad portion on the upper surface of the first semiconductor carrier by a thin metal wire; Sealing the upper surface region of the first semiconductor carrier substrate with a potting sealing resin so as not to cover the first semiconductor carrier substrate, and sealing the connection region formed by the first semiconductor element, the second semiconductor element, and the thin metal wire; A method for manufacturing a stacked semiconductor device, comprising:
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|---|---|---|---|
| JP10227999A JP4075204B2 (en) | 1999-04-09 | 1999-04-09 | Multilayer semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10227999A JP4075204B2 (en) | 1999-04-09 | 1999-04-09 | Multilayer semiconductor device |
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| Publication Number | Publication Date |
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Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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