JP3450477B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer structure package. With the recent miniaturization of electronic devices, there is a demand for high-performance packages that have good mounting efficiency, light weight, and low cost even in semiconductor devices to be mounted. Therefore, the package is made to have a multi-layered structure, and it is desired that the package can be mounted at a high density at a lower cost.

[0002]

2. Description of the Related Art FIG. 12 is a block diagram of a conventional semiconductor device of a multi-layer BGA package. FIG. 12A is a sectional view,
FIG. 12B is a bottom view. A semiconductor device 11 shown in FIGS. 12A and 12B is a multi-layered BGA (BallG).
multi-layer substrate 1 in a rigid array package.
A semiconductor chip 13 is mounted in the unit 2. Multilayer board 1
2 is formed of, for example, glass epoxy, are given substrate 12 ₁ to 12 ₅ on which a wiring pattern is formed is stacked, the semiconductor chip 13 is mounted by an adhesive 14 on the substrate 12 ₁ as a base.

The substrates 12 ₂ and 12 ₃ are opened in the mounting region of the semiconductor chip 13, and the substrates 12 ₄ and 1 are further opened.
2 ₅ are sequentially opened with varying sizes. The semiconductor chip 13 and the predetermined pattern terminals on the substrates 12 ₃ and 12 ₄ are bonded by the wires 15 to make electrical connection. Furthermore, the substrate 12 ₁ to 12 ₅ are among the pattern is performed a predetermined electrical connection through-hole,
A predetermined number of solder balls 16 are provided on the substrate 12 ₅ for external connection. Also, cap 1 on the opening.
7 is attached.

A heat sink 18 for heat dissipation is attached to the side of the multilayer substrate 12 opposite to the solder balls 16. Since such a semiconductor device 11 has a multi-layer structure, it has excellent mountability and high speed, and the number of external terminals (solder balls 16) can be increased. Also,
Since the solder balls 16 are used as external terminals, PGA (Pi
It can be cheaper than an n grid array) package.

[0005]

However, the above-mentioned multilayer BG
In the semiconductor device 11 of the A package, the number of layers increases as the performance of the semiconductor chip 13 to be mounted is improved, and the structure becomes complicated and the manufacturing cost becomes high. In particular, if the number of layers exceeds a predetermined number, the cost tends to increase dramatically, and there is a problem that not only the package cost but also the overall cost reduction cannot be achieved.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of high-density mounting and cost reduction.

[0007]

According to a first aspect of the present invention, a predetermined pattern is formed and a predetermined number of semiconductor chips are mounted by an adhesive and electrically connected to the pattern. And a second substrate that is electrically connected to the first substrate by a connecting member and has a predetermined number of external terminals formed on one surface thereof .
The semiconductor chip on the substrate is covered and sealed with a sealing member.
The second substrate constitutes a semiconductor device in which an opening for positioning the semiconductor chip on the first substrate is formed.

According to a second aspect, at least the second substrate of the first substrate and the second substrate according to the first aspect is formed of a laminated substrate. In the third aspect, the external terminal according to the first aspect is formed of a ball-shaped or pin-shaped three-dimensional electrode. In a fourth aspect, the connection member according to the first aspect is formed of a conductive adhesive material containing a high-melting-point conductive metal in the number corresponding to electrical connection.

[0009] In claim 5, the second substrate according to claim 1, 2 or 4, wherein, the external terminal is formed on the entire surface or a partial area substrate for closing the opening is laminated.

According to a sixth aspect, the first aspect of the first or fifth aspect is provided.
A predetermined number of intermediate substrates electrically connected by the connecting member are provided between the first substrate and the second substrate. In a seventh aspect , a predetermined number of semiconductor chips are mounted on the second substrate according to the first, fifth or sixth aspect . Claim 8
A predetermined number of third substrates on which a predetermined number of semiconductor chips are mounted are electrically connected and interposed between the intermediate substrates of 6 .

According to a ninth aspect , in any one of the first to eighth aspects, a heat dissipation member is provided on the exposed surface of the first substrate. According to a tenth aspect of the present invention, a step of forming a first substrate on which a predetermined number of semiconductor chips are mounted, and a plurality of openings formed with the semiconductor chips on the first substrate are formed.
A step of stacking the substrates to form a second substrate, a step of aligning the first and second substrates with a molten metallic connection member for electrical connection therebetween, and a predetermined temperature And a step of melting the connection member to bond the first and second substrates to each other for electrical connection, and a step of forming a predetermined number of external terminals on the second substrate. A method of manufacturing a semiconductor device is configured.

In the eleventh aspect, the alignment is performed between the first and second substrates according to the tenth aspect by interposing a predetermined number of intermediate substrates electrically connected by the connecting member.
In a twelfth aspect , the alignment is performed by interposing a predetermined number of third substrates on which a predetermined number of semiconductor chips are mounted between the intermediate substrates according to the eleventh aspect . In claim 13 , on the second substrate according to any one of claims 10 to 12 ,
A predetermined number of semiconductor chips are mounted.

[0013]

As described above, according to the first to fourth or tenth aspects of the present invention, the first substrate on which a predetermined number of semiconductor chips are mounted and appropriately sealed, and the opening for positioning the semiconductor chips are formed. The second substrate, which is laminated on one side and has external terminals such as three-dimensional electrodes formed on one surface thereof, is positioned and connected through a connecting member such as a conductive adhesive material containing a high melting point conductive metal. As a result, since the first and second substrates are individually independent, the number of internal structure layers per substrate is reduced, the manufacturing process is simplified, and the yield can be improved and the cost can be reduced. Become.

According to the invention of claims 5 to 7, 11 or 13 , the second substrate on which a predetermined number of semiconductor chips are mounted is laminated with the substrate closing the opening, and external terminals are formed on the entire surface or part of the area. It is formed and is appropriately connected to the first substrate with an intermediate substrate interposed. As a result, it becomes possible to diversify and to improve the mounting density at low cost.

According to the invention of claim 8 or 12 , a predetermined number of third chips, each having a predetermined number of semiconductor chips mounted between the intermediate substrates, are further provided.
Interpose the substrate. As a result, it becomes possible to diversify and to improve the mounting density at low cost. In the invention of claim 9 , the heat dissipation member is provided on the exposed surface of the first substrate. This makes it possible to efficiently radiate the temperature rise due to high-density mounting.

[0016]

FIG. 1 is a block diagram of the first embodiment of the present invention. 1A is a bottom perspective view, and FIG. 1B is a cross-sectional view. A semiconductor device 21A shown in FIGS. 1A and 1B is composed of a first substrate 22 and a second substrate 23. As the first substrate 22, a ceramic multilayer substrate 24 in which ceramic substrates 24 _{1 to} 24 ₄ on which a pattern of metal wiring is formed is laminated, for example, in four layers is used, and on the ceramic multilayer substrate 24 (ceramic substrate 24 ₄ ). Au (gold) on the substrate
Leads 25, etc. are formed according to a predetermined number of terminals. Then, the semiconductor chip 26 is mounted with an adhesive 27 such as silver paste. The ceramic multilayer substrate 24 is electrically connected by through holes between the corresponding patterns of each ceramic substrate.

The mounted semiconductor chip 26 is electrically connected by being bonded to the leads 25 and wires 28 arranged around it. A sealing portion 29 is formed so as to cover the semiconductor chip 26 and the wires 28. On the other hand, the second substrate 23, the printed multilayer substrate 31 obtained by laminating a printed circuit board 31 _{1-31 4} the pattern of the metal wiring layers are formed in four layers, for example, are electrically connected by a through-hole between each substrate using To be in this case,
The semiconductor chip 2 when it is later connected to the first substrate 22.
An opening 32 is formed in a portion where 6 (sealing portion 29) is located.

Further, on the printed board 31 ₄ of the printed multilayer board 31, metal balls (which may be pins) 33 serving as three-dimensional electrodes as external terminals are provided on the printed board 31 ₄ by a predetermined number of pads ( (Not shown in the figure). Then, the semiconductor chip 26 (sealing portion 29) is positioned in the opening 32 of the second substrate 23, and the second
A predetermined pattern on the printed board 31 ₁ of the board 23 of
A connection member 34, which is a conductive adhesive containing a high-melting-point conductive metal, is interposed between the corresponding lead 25 of the first substrate 22 and electrically connected and fixed.

The electrical connection of the semiconductor chip 26 is
Not limited to the wire 28, flip chip, TAB (Tape)
You may perform by Automated Bonding). Therefore, FIG. 2 shows a manufacturing explanatory view of FIG. Also,
FIG. 3 shows a block diagram of the first substrate in FIG.
FIG. 4 shows a configuration diagram of the second substrate in FIG. In this case, FIG. 3A is a cross-sectional view of the first substrate, FIG. 3B is a plan view of the first substrate, and FIG. 4A is a cross-sectional view of the second substrate.
FIG. 4B is a plan view of the second substrate.

In FIG. 2, the first substrate 22 is first formed (step (S) 1a), and the second substrate 23 is formed.
Is formed. The first substrate 22 is shown in FIGS.
As shown in, in which the ceramic multilayer substrate 24 described above are stacked in multiple layers (four layers) by printing the alumina and the conductor of the firing and the alumina paste by a sheet lamination method or a printing multilayer method, the ceramic substrate 24 ₄ on The lead 25 and the wiring pattern 25a are formed by Au plating.

Then, the semiconductor chip 26 is mounted by the adhesive 27, and is electrically connected to the lead 25 by the wire 28. After that, the sealing portion (package) 29 is formed of the molding resin by transfer molding or potting the semiconductor chip 26 and the wire 28. On the other hand, the second substrate 23 is shown in FIGS.
As shown in FIG. 3, a printed multilayer board 31 is a four-layered structure in which printed boards having wiring patterns on both sides are electrically connected by through holes and laminated in four layers, and the semiconductor chip 26 (sealing portion 29) is formed in the central portion. Opening 32 for positioning
Are formed. And the printed circuit board 31 ₁
The connection members 34 of the high melting point molten metal are regularly formed on the upper surface.

Returning to FIG. 2, the first and second substrates 22 and 23 formed in FIGS. 3 and 4 are connected to the lead 25 of the first substrate 22 and the connecting member 34 on the second substrate 23. It is aligned with and (S2). After alignment, the connection member 34 is heated to a melting temperature by a reflow method and fixed to the first and second substrates 22 and 23 in an electrically connected state (S3).

The printed board 3 of the second board 23
On 1 _4, a low melting point molten metal of the metal balls (bumps) 33 such as solder, as shown in FIG. 1 is intended to be formed for example by the transfer method (S4). Such a semiconductor device 2
In 1A, the four-layer first substrate 22 and the four-layer second substrate 23 in each independent state are bonded to each other to form an 8-layer BGA package. By the way, in the case of forming a package having an eight-layer structure in the related art, the manufacturing process is complicated and the yield is poor and the cost is high.
Since the substrate 22 and the second substrate 23 are divided into multiple layers, the number of internal structure layers per substrate can be reduced. Thereby, the yield can be improved by the simplification of the manufacturing process and the cost can be reduced.

Since the first substrate 22 and the second substrate 23 are independent of each other, a test can be conducted for each substrate, reliability can be improved, and development is diversified. Therefore, the development cost can be reduced. Next, FIG. 5 shows a sectional configuration diagram of a second embodiment of the present invention. Semiconductor device 21B shown in FIG.
Is the printed circuit board 34 _4a of the second substrate 23 without forming an opening, and a hermetic closing the opening 32 is formed in another printed circuit board 34 _{1-34 3.} Further, the metal balls 34 are arranged and formed on the entire surface of the printed circuit board _344a , and other configurations are similar to those of the first embodiment.

According to this, the number of external terminals of the metal ball 33 can be increased, and it is possible to cope with the mounting of a high-performance semiconductor chip. In addition, FIG.
FIG. 7 shows a sectional configuration diagram of the third embodiment of the present invention. A semiconductor device 21C shown in FIG. 6 is obtained by interposing an intermediate substrate 41 between the first substrate 22 and the second substrate 23 in the second embodiment and connecting them by the same connecting member 34 as described above.
The other structure is the same as that of the second embodiment. In this case, the intermediate board 41 is a multilayer board in which, for example, four layers of printed boards are laminated.

That is, such a semiconductor device 21C
Is a BGA package having a 12-layer structure, which can be formed into a multi-layer structure at low cost. continue,
FIG. 7 shows a block diagram of a third embodiment of the present invention. In the semiconductor device 21D shown in FIG. 7, the first substrate 22 is the above-mentioned first substrate.
~ Similar to the third embodiment. In FIG. 7, the second substrate 2
3a is a printed circuit board 31 _{1 to} 31 without forming an opening.
₄ is laminated in four layers, and a predetermined pattern layer 42 is formed on the printed board 31 ₁ . And the semiconductor chip 2
6a is mounted by being connected to the pattern layer 42 and the bumps 43, and the semiconductor chip 26 is sealed with a molding resin by transfer molding, potting or the like to form the sealing portion 44. In addition, the printed circuit board 31
₄ of the metal balls 33 similar to the above is formed on the.

The semiconductor chip 26a may be connected by a wire or TAB instead of the bump 43 as described above. The second substrate 23a and the first substrate 22
And the three intermediate substrates 41 _{1 to} 41 ₃ are interposed between the first substrate 22, the second substrate 23, and the intermediate substrates 41 _{1 to} 41 ₃ by the same connecting member 34 as described above. To be done. In this case, each of the intermediate substrates 41 _{1 to} 41 ₃ is a four-layer printed multilayer substrate in which the openings 32a are formed, and a 20-layer structure package in which two semiconductor chips 26, 26a are mounted is configured.

As described above, the semiconductor device 21D has two halves.
So-called MCM on which conductor chips 26, 26a are mounted
(Multi-chip module) structure improves packaging density
In addition to the low cost and high performance of the multilayer structure
It can be a package. Next, FIG.
FIG. 9 shows a sectional configuration diagram of the fifth embodiment of the present invention. Shown in Figure 8
In the semiconductor device 21E, the second substrate 23 is
Similar to the example (FIG. 5). The first substrate 22a is shown in FIG.
Ceramic substrate 24 similar to (FIG. 1)₁~ 24_FourStacked
Ceramic multi-layer substrate 24
_FourTwo semiconductor chips 26 on top ₁, 26₂Adhesive 27
a and 27b.

Then, the pattern 25a formed on the ceramic substrate 24 ₄ and each of the semiconductor chips 26 ₁ and 26 ₂ are electrically connected by a wire 28 (a flip chip, a TAB or the like may be used), and a sealing portion 29a, It is sealed by 29b. Such a semiconductor device 21E
Unlike the conventional multi-layer package structure, the first substrate 2
Since 2a is flat, a plurality of semiconductor chips can be mounted and the packaging density can be improved at low cost.

Next, FIG. 9 shows a sectional view of the sixth embodiment of the present invention. In the semiconductor device 21F shown in FIG. 9, the first substrate 22a is the same as in the fifth embodiment (FIG. 8). Further, the second substrate 23a has two semiconductor chips 26a ₁ and 26a ₂ mounted by bumps (which may be wires, TAB or the like) instead of the one semiconductor chip 26a shown in FIG. 7 (fourth embodiment). It is sealed by the sealing portions 44a and 44b.

In this case, the printed board located at the end of the intermediate board _411a is not provided with an opening, but the opening formed in another printed board is sealed. This is similar to FIG. 7 (fourth embodiment). By configuring the semiconductor device 21F as described above, the packaging density can be improved at low cost.

FIG. 10 is a sectional view showing the configuration of the seventh embodiment of the present invention. A semiconductor device 21G shown in FIG. 10 has an intermediate substrate 41 ₄ added in the fourth embodiment (FIG. 7).
A third substrate 45 is interposed between the intermediate substrates 41 ₁ and 41 ₂ and the intermediate substrates 41 ₃ and 41 _4, and the first and second substrates
Substrates 22 and 23a are the same as in FIG. The third substrate 45 is one of the four-layer printed multi-layered printed circuit boards on which the semiconductor chip 26b is mounted and electrically connected by the wires 28 to form the sealing portion 4.
6, which is sealed with the semiconductor chip 26b (sealing portion 4) in an opening 32b formed in another printed circuit board.
6) is located.

Such a semiconductor device 21G constitutes a 28-layer structure BGA package on which three semiconductor chips 26, 26a and 26b are mounted, and the packaging density can be further improved at low cost. . As in the sixth and seventh embodiments, by appropriately adding an intermediate substrate and adding a predetermined number of third substrates 45,
Further, by appropriately adding the semiconductor chips 26, 26a, 26b on the first and second substrates 22a, 23a, it is possible to realize high-density mounting at low cost.

Next, FIG. 11 shows a block diagram of an eighth embodiment of the present invention. In the semiconductor device 21H shown in FIG. 11, a heat sink 47, which is a heat dissipation member made of, for example, aluminum, having good thermal conductivity is provided on the exposed surface of the first substrate 22 shown in the first embodiment (FIG. 1). The other configuration is similar to that of FIG. Since the heat sink 47 radiates heat, it is possible to avoid the influence of heat generation due to high integration of the semiconductor chip 26.

Incidentally, such a heat sink 47 can be applied to the above-mentioned second to seventh embodiments.

[0036]

As described above, the first to fourth or tenth aspects are as described above.
According to the invention, a first substrate, on which a predetermined number of semiconductor chips are mounted and appropriately sealed, and an opening for positioning the semiconductor chips are formed and laminated, and external terminals such as three-dimensional electrodes are formed on one surface. The first and second substrates are individually separated by connecting the second substrate on which is formed after alignment by interposing a connecting member such as a conductive adhesive material containing a high melting point conductive metal therebetween. As a result, the number of internal structure layers per substrate is reduced, the manufacturing process is simplified, and the yield can be improved and the cost can be reduced.

According to the invention of claims 5 to 7, 11 or 13 , the second substrate, on which a predetermined number of semiconductor chips are mounted, is stacked on the substrate covering the opening to form an external layer on the entire surface or a partial area. Since the terminals are formed and are connected to the first substrate with the intermediate substrate interposed as appropriate, diversification is possible and the packaging density can be improved at low cost. According to the invention of claim 8 or 12 , further, by interposing a predetermined number of third substrates on which a predetermined number of semiconductor chips are mounted between the intermediate substrates, it becomes possible to diversify and at a low cost the mounting density. Can be improved.

According to the ninth aspect of the present invention, by providing the heat radiation member on the exposed surface of the first substrate, it is possible to efficiently radiate the temperature rise due to the high-density mounting.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a manufacturing explanatory view of FIG. 1.

FIG. 3 is a configuration diagram of a first substrate in FIG.

4 is a configuration diagram of a second substrate in FIG.

FIG. 5 is a sectional configuration diagram of a second embodiment of the present invention.

FIG. 6 is a sectional configuration diagram of a third embodiment of the present invention.

FIG. 7 is a sectional configuration diagram of a fourth embodiment of the present invention.

FIG. 8 is a sectional configuration diagram of a fifth embodiment of the present invention.

FIG. 9 is a sectional configuration diagram of a sixth embodiment of the present invention.

FIG. 10 is a sectional configuration diagram of a seventh embodiment of the present invention.

FIG. 11 is a sectional configuration diagram of an eighth embodiment of the present invention.

FIG. 12 is a configuration diagram of a semiconductor device of a conventional multi-layer BGA package.

[Explanation of symbols]

21A-21H Semiconductor device 22 First substrate 23, 23a Second substrate 24 Ceramic Multilayer Substrate 25 leads 26, 26a, 26b Semiconductor chip 28 wires 29,44,46 Sealing part 31 Printed multilayer board 32, 32a opening 33 metal balls 34 Connection member 41 Intermediate board 43 bump 45 Third substrate 47 heat sink

Continuation of front page (56) Reference JP-A-61-268046 (JP, A) JP-A-4-370957 (JP, A) JP-A-4-69993 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) H01L 23/12

Claims (13)

(57) [Claims] 1. A predetermined pattern is formed and a predetermined number of semiconductors are formed.
Body chipsBy adhesiveEquipped with the pattern and electrical
A connected first substrate, Electrically connected to the first substrate by a connecting member.
The second terminal having a predetermined number of external terminals formed on one side.
Board, HaveThe semiconductor chip on the first substrate is covered with a sealing member.
And sealed, The second substrate positions the semiconductor chip on the first substrate.
A semiconductor having an opening formed therein
apparatus. 2. The semiconductor device according to claim 1, wherein at least the second substrate of the first substrate and the second substrate is formed of a laminated substrate. 3. The semiconductor device according to claim 1, wherein the external terminal is formed of a ball-shaped or pin-shaped three-dimensional electrode. 4. The semiconductor device according to claim 1, wherein the connection member is formed of a conductive adhesive material containing a high-melting-point conductive metal in a number corresponding to electrical connection. 5. The second substrate according to claim 1, 2 or 4 , wherein substrates for closing the opening are stacked and the external terminals are formed on the entire surface or a partial area. Semiconductor device. 6. The first substrate and the second substrate according to claim 1 or 5 .
The semiconductor device is characterized in that a predetermined number of intermediate substrates electrically connected to the substrate by the connection member are provided. 7. A semiconductor device comprising a predetermined number of semiconductor chips mounted on the second substrate according to claim 1, 5, or 6 . 8. A semiconductor device, wherein a predetermined number of third substrates on which a predetermined number of semiconductor chips are mounted are electrically connected and interposed between the intermediate substrates of claim 6 . In any one of the claims 9 claims 1-8, wherein a heat dissipation member to the exposed surface of the first substrate is provided. 10. A first device on which a predetermined number of semiconductor chips are mounted.
Forming a second substrate by stacking a plurality of substrates each having an opening for positioning a semiconductor chip on the first substrate, and forming a second substrate. A step of aligning the substrate with a molten metal connecting member for electrical connection, and melting the connecting member at a predetermined temperature to bond the first and second substrates to each other for electrical connection. And a step of forming a predetermined number of external terminals on the second substrate. A method of manufacturing a semiconductor device, comprising: 11. The semiconductor device according to claim 10 , wherein the alignment is performed by interposing a predetermined number of intermediate substrates electrically connected by the connection member between the first and second substrates. Device manufacturing method. 12. The manufacturing of a semiconductor device, wherein the alignment is performed by interposing a predetermined number of third substrates on which a predetermined number of semiconductor chips are mounted between the intermediate substrates according to claim 11. Method. 13. A method of manufacturing a semiconductor device, wherein a predetermined number of semiconductor chips are mounted on the second substrate according to claim 10 .