JPH09266266A - Semiconductor device, manufacturing method thereof and cap of the semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a semiconductor device having a ball grid array structure to improve the package density thereof by forming balls in an array on the outer face of a cap base. SOLUTION: A cap 20 comprises a cap base 21 composed of a plate-like insulative member having an approximately square plain shape, balls 22 formed like an array on the outer face of the base 21, interconnection 23 connected to the balls 22, through-holes 24 piercing the base 21, and interconnection layer 25 on the base 21. The number of the balls per unit area on the top face of a semiconductor device is increased by increasing the balls 22 on the cap 20, this facilitating the miniaturizing of the package. Thus, the package density of the semiconductor device can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ball grid array (hereinafter referred to as BGA) structure in which a plurality of solder balls are arranged in an array on one surface of a package for electrical and mechanical connection with a mother board. More particularly, the present invention relates to a semiconductor device having a BGA structure in at least one of a cap and a multilayer substrate including an insulating material, and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 21 is a sectional view showing a structure of a semiconductor device having a BGA structure used for conventional face down bonding. In FIG. 21, 1 is a semiconductor chip in which elements having a predetermined electrical function are formed,
Reference numeral 2 denotes a multilayer substrate having a cavity 3 in which the semiconductor chip 1 is mounted and a conductive path for electrically connecting the semiconductor chip 1 to the outside of the semiconductor device. Reference numeral 4 denotes a semiconductor chip 1 made of a material such as gold or aluminum. For connecting electrically to the wiring layer of the multilayer substrate 2 is a multilayer substrate 2
Solder balls that are arranged on the outer surface of the
Reference numeral 6 denotes a heat radiating plate to which the semiconductor chip 1 is adhered and which is attached to the insulating substrate 9 below the multi-layer substrate 2 to dissipate heat generated in the semiconductor chip 1, and 7 denotes an outline for hermetically sealing the semiconductor chip 1. A plate-shaped cap having a square planar shape, and 8 is a sealing material for bonding the cap 7 and the multilayer substrate 2 and filling a gap between the cap 7 and the multilayer substrate 2. The material forming the multilayer substrate 2 is ceramic, glass epoxy, BT (Bismaleimide Triazine)
It is an insulating material such as resin. The cap 7 is also made of an insulating material similar to that of the multilayer substrate 2. The multilayer substrate 2 is formed by stacking a plurality of insulating substrates 9. Wiring layers 10 are formed between the plurality of insulating substrates 9.
In addition, through holes 11 are formed through at least one insulating substrate 9 to electrically connect the plurality of wiring layers 10 to each other and electrically connect the balls 5 to the wiring layers 10. . The insulating substrate 9 is formed by hollowing out the center of a square plate in a square shape parallel to the outer peripheral side. The square-shaped region to be hollowed out becomes smaller in order from the upper first insulating substrate 9 to the lower fourth insulating substrate 9.

[0003]

Since the conventional semiconductor device and the cap of the semiconductor device are configured as described above, the balls 5 can be arranged only on the upper surface of the multilayer substrate 2,
There is a problem that it is difficult to improve the mounting density because the number of balls 5 that can be arranged per unit area of the package of the semiconductor device is limited. Further, conventionally, the sealing material 8 is composed of an adhesive material or the like having a resin as a main component, and in addition to that, the cap 8 is fitted into the multilayer substrate 2, so that the multilayer substrate 2 and the cap 8 are brought into contact with each other. There is a problem that it is difficult to improve airtightness because the area of the part is small. Further, the conventional wire 4 has a parasitic inductance, which makes it difficult to improve the electrical characteristics. There is a problem that noise is generated when trying to increase the operating frequency.

The present invention has been made to solve the above problems, and an object thereof is to improve the mounting density by disposing balls in the cap. Also,
It is an object of the present invention to improve airtightness by sealing with a metal material and by increasing the contact area between the cap and the multilayer substrate. Another object is to improve the electrical characteristics by reducing the parasitic inductance of the wire.

[0005]

A semiconductor device according to a first aspect of the present invention is a semiconductor device having a ball grid array structure used for face-down bonding, which comprises a chip on which elements are formed, A multilayer substrate having a first wiring layer arranged between a cavity accommodating the chip and an insulating substrate, and a first electrical connection means for electrically connecting the chip and the first wiring layer. An insulating base having an inner surface facing the cavity and an outer surface facing the outside of the semiconductor device, a plurality of balls provided on the outer surface of the base, a second wiring layer provided on the inner surface, and A cap having a first interlayer conductive path for penetrating a base portion and electrically connecting the plurality of balls to the second wiring layer;
And a second electrical connection means for connecting between the second wiring layers.

A semiconductor device according to a second invention is the semiconductor device according to the first invention, wherein the first electrical connection means is provided in the cavity for connecting the chip and the first wiring layer. A second wiring layer, the second wiring layer being provided in the same current path as the wire.
And a current flowing through the wire and a current flowing through the first wiring pattern are substantially opposite to each other.

A semiconductor device according to a third invention is the semiconductor device according to the first or second invention, wherein the semiconductor device is provided on the inner surface side of the cap, and includes the second wiring layer and the first electrical connection means. It further comprises an insulating means for insulating the spaces.

A semiconductor device according to a fourth invention is the semiconductor device according to any one of the first to third inventions, wherein the base is provided between a plurality of laminated insulating substrates and between the insulating substrates. A structure further comprising at least one inter-substrate wiring layer, and a second interlayer conductive path for electrically connecting the inter-substrate wiring layer and any one of the plurality of balls or the second wiring layer. To be done.

A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects of the present invention, wherein the cap has substantially the same outer edge portion when aligned with the multilayer substrate. It is characterized by having a shape.

A semiconductor device according to a sixth invention is the semiconductor device according to any one of the first to fifth inventions, wherein the second wiring layer includes second and third wiring patterns,
The cap further comprises a capacitor provided on the inner surface side of the cap and electrically connected to the second and third wiring patterns.

A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to the sixth aspect, wherein each of the second and third wiring patterns has an area that is approximately one half of that of the second wiring layer. And

A semiconductor device according to an eighth invention is the semiconductor device according to any one of the first to seventh inventions, wherein the base portion further has a first metal foil provided on an outer peripheral portion of the base portion. The multi-layer substrate has a second metal foil disposed around the first metal foil so as to be adjacent to the first metal foil when the base is fitted into the multi-layer substrate, It further comprises a metal brazing material portion welded over the entire circumference of the first and second metal foils so as to block an air passage between the cavity and the outside.

A semiconductor device according to a ninth invention is the semiconductor device according to any one of the first to eighth inventions, wherein the base is connected to a ball for supplying power among the plurality of balls. Opposite two that act as capacitors
It is characterized by further having one conductor layer.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of forming a first metal foil on an outer peripheral portion of an insulative cap, and a step of forming the first metal foil in the insulative case when the cap is fitted in the first case. Forming a second metal foil over the entire circumference of the opening of the case adjacent to the metal foil, and sealing the first and second metal foils with a metal brazing material. Composed.

An eleventh aspect of the present invention is a method of producing a semiconductor device according to the tenth aspect of the present invention, wherein the step of encapsulating with the metal brazing material is the first metal foil and the second step. The step of applying a flat plate annular metal brazing material that covers the gap of the metal foil to the gap, and the step of melting the metal brazing material while applying it to the gap to close the gap. Is characterized by.

A cap of a semiconductor device according to a twelfth aspect of the invention is provided on an insulating base having an inner surface facing a cavity in which a chip is mounted and an outer surface facing the outside of the semiconductor device, and the outer surface of the base. Multiple balls,
An inner surface side wiring layer provided on the inner surface; and a first interlayer conductive path which is provided through the base portion and electrically connects the plurality of balls to the inner surface side wiring layer. It

A cap of a semiconductor device according to a thirteenth invention is the cap of the semiconductor device according to the twelfth invention, wherein the base portion is provided between a plurality of laminated insulating substrates and at least one of the insulating substrates is provided. It further comprises one inter-substrate wiring layer, and a second interlayer conductive path for electrically connecting the inter-substrate wiring layer and any one of the plurality of balls or the inner surface side wiring layer.

A semiconductor device cap according to a fourteenth aspect of the present invention is the semiconductor device cap according to the thirteenth aspect of the present invention, wherein at least two of the at least one inter-substrate wiring layer and the inner surface side wiring layer of the base which face each other are opposed to each other. The two wiring layers form a capacitor.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. The configuration of the semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, 1 is a semiconductor chip in which elements having a predetermined electrical function are formed, 2 is a cavity 3 in which the semiconductor chip 1 is mounted, and a conductive material for electrically connecting the semiconductor chip 1 to the outside. Multi-layer substrate with paths, 4
Is a semiconductor chip 1 made of a material such as gold or aluminum
Wires for electrical connection between the electrodes provided on the surface of the multi-layer substrate 2 and the wiring layer of the multi-layer substrate 2, 5 is a solder ball disposed on the outer surface of the multi-layer substrate 2 and functions as a lead, and 6 is the back surface of the semiconductor chip 1. Is a heat-dissipating plate that is attached to the multi-layer substrate 2 and dissipates the heat generated in the semiconductor chip 1. The above-mentioned components are configured similarly to the conventional semiconductor device of FIG. Therefore, the multilayer substrate 2 is
It can be formed using an insulating material such as ceramic, glass epoxy, or BT resin. Here, the surface facing the cavity 3 which is a closed space surrounded by the cap base 21, the multilayer substrate 2 and the heat dissipation plate 6 is referred to as an inner surface, and faces the space 12 belonging to the atmosphere in which the semiconductor device is installed. That is, the surface that faces the outside world is called the outside surface.

In FIG. 1, 20 is a plate-like cap having a substantially square planar shape for hermetically sealing the semiconductor chip 1, and 26 is an electrical connection for electrically connecting the multilayer substrate 2 and the cap 20. A solder member 27 functioning as a connecting means is a sealing material similar to the sealing material 8 of FIG. 21 for bonding the cap 20 and the multilayer substrate 2 and filling the gap between the cap 20 and the multilayer substrate 2. Cap 20
Is a cap base 21 made of a plate-shaped insulating member having a substantially square planar shape, a plurality of solder balls 22 formed in an array on the outer surface of the cap base 21, and balls formed on the outer surface of the cap base 21. A through hole for electrically connecting a wiring 23 connected to 22 and a conductive member formed to penetrate the cap base 21 and connected to the wiring 23 on the outer surface and the inner surface of the cap base 21. 24 and a wiring layer 25 provided on the inner surface of the cap base 21 and patterned. Also, the cap base 21 is made of the same ceramic as the multilayer substrate 2,
It can be formed of an insulating material such as glass epoxy or BT resin. Compared with the conventional semiconductor device having the multilayer substrate 2 and the cap 7 shown in FIG. 21, the semiconductor device having the multilayer substrate 2 and the cap 20 shown in FIG. Since the number of balls 22 formed increases, the number of balls per unit area of the upper surface of the semiconductor device can be increased, and the package can be easily reduced, so that the packaging density can be improved. In addition,
Although not shown, by coating the outer surface side of the cap 20 with an insulating film, the space between the wirings 23 or the wirings 23
A short circuit between the ball 22 and the ball 22 is prevented.
For example, the through hole 24 is covered with a protective film such as a solder resist on the outer surface of the cap 20, the through hole 24 is blocked, and there is no ventilation between the cavity 3 and the space 12. Further, the through hole 24 may be formed by driving a metal rod, and in that case, the ventilation between the cavity 3 and the space 12 is further sufficiently blocked. These points also apply to other embodiments described below.

FIG. 2 is a plan view of the cap 20 shown in FIG. 1 viewed from the inner surface side. 2, 28 is a pad which is formed on the wiring layer 25 of FIG. 1 and is connected to the wiring layer 10 of the multilayer substrate 2 of FIG. 1 by the solder member 26, and 29 is wiring for connecting the pad 28 and the through hole 24. Layer 2
Wiring patterns formed by patterning 5 are designated wiring patterns 30 in the wiring pattern 29, and those having the same reference numerals as those in FIG. 1 are portions corresponding to the same reference numerals in FIG. The wiring pattern 29 routed to the inner surface of the cap 20 is electrically connected to the ball 22 formed on the outer surface of the cap 20 through the through hole 24.
As a material for forming the wiring pattern 29 of the cap 20, it is preferable to use a non-magnetic material such as copper or gold in order to reduce the inductance. Cap 20
It is desirable that the material constituting
A material having a relative magnetic permeability of 10 or less may be used.

FIG. 3 is a sectional view in which the semiconductor device shown in FIG. 2 in which the cap is fitted is cut along line 31-31 and a part of the section is enlarged. In FIG. 3, 32 is a pad formed on the wiring layer 10 and connected to the solder member 26 by the pad 29, 33 is an arrow indicating the direction of current flowing through the wire 4, and 34 is an arrow indicating the direction of current flowing through the wiring pattern 30. 1 and FIG. 2 have the same reference numerals as those in FIG. 1 or FIG. The wire 4 and the wiring pattern 30 shown in FIG. 3 belong to the same current path. For example, if the wiring pattern 30 is connected to an external ground voltage point, the loop of the ground current is almost opposite to each other in the wire 4 and the wiring pattern 30 as shown by arrows 33 and 34, so that the effective inductance of the ground is increased. Can be reduced. Therefore, noise such as ground bounce can be suppressed. This effect is greatest when the currents flowing through the wire 4 and the wiring pattern 30 are the same. The distance between the wiring pattern 29 formed on the inner surface of the cap 20 and the wire 4 is preferably about 50 to 500 μm for impedance matching during electrical connection between the cap 20 and the multilayer substrate 2.

Embodiment 2 FIG. Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. 4 is a sectional view showing a structure of a cap of a semiconductor device according to a second embodiment of the present invention. In FIG. 4, 40 is a cap, 41 is a first insulating substrate provided on the inner surface side of the cap 40 and having a substantially square planar shape, and 42 is arranged on the insulating substrate 41 so that the peripheral portions are aligned. The second insulating substrate 43 is formed on the second insulating substrate 42 so that the peripheral portions thereof are aligned with each other, and the third insulating substrate 43 provides the outer surface of the cap 40. 44 is the first insulating substrate 41. Of the signal line pattern formed on the lower surface of the cap 40, that is, the inner surface of the cap 40, an inter-board wiring layer 45 formed between the first insulating substrate 41 and the second insulating substrate 42, and a second insulating substrate 42. An inter-substrate wiring layer formed between the third insulating fields 43, and 47 is a third
Wiring pattern formed on the upper surface of the insulating substrate 43, that is, the outer surface of the cap 40, 48 is a pad for forming a ball and electrically connecting the ball and the wiring pattern 47, and 49 is an inter-substrate wiring layer 45, 46. And a through hole or a via hole for electrical connection with any one of the signal line patterns 44 or a combination thereof. Here, the cap 4 is provided to provide a conductive path.
A hole that penetrates from the outer surface to the inner surface of 0 is called a through hole, and a hole that penetrates one or two insulating substrates 41 to 43 is called a via hole.

The first to third insulating substrates 41 to 43 are
It is formed by using the same insulating material as the insulating member forming the multilayer substrate 2, such as ceramic, glass epoxy, BT resin, or the like. The inter-substrate wiring layers 45 and 46 formed between the first to third insulating substrates 41 to 43 are, for example, gold,
The first and third insulating substrates 41 and 43 are formed by metallizing conductive metals or alloys such as silver, copper, nickel, aluminum, tin, lead and solder. The first and third insulating substrates 41 and 43 are bonded to each other, for example, by the second insulating substrate 42. For example, the second insulating substrate 42 is formed of prepreg. The through holes or the via holes 49 may be formed by forming one hole for each of the first and third insulating substrates 41 and 43, or may be formed at the same time in a state where a plurality of them are bonded.

The power supply voltage Vdd may be supplied to the whole inter-substrate wiring layer 45 shown in FIG. 4, and the power supply voltage Vss may be supplied to the whole inter-substrate wiring layer 46. At this time, the inter-substrate wiring layers 45, 46 may have a solid pattern having substantially the same area as each area of the insulating substrates 41-43. By using the multilayer wiring as described above, the degree of freedom of the connection pattern is increased and the layout is facilitated.

By the way, the cap 4 as shown in FIG.
When 0 is fitted into the multilayer substrate 2, the thickness of the cap becomes thicker, so that the contact between the wire and the signal line pattern 44 becomes a problem. FIG. 5 is a cross-sectional view showing a state in which the insulating film 50 is provided between the wire 4 and the inner surface of the cap 40. Insulating film 5
0 is arranged so as to cover almost all of the inner surface of the cap 40 except the periphery where the pad 29 is formed. The material of the insulating film 50 reduces the capacitive coupling generated between the wire 4 and the signal line pattern 44 of the cap 40, so that the relative dielectric constant is 4 or less, and practically, the relative dielectric constant is 4 or less. .About.2 material, eg polyimide tape is preferred. In FIG. 5, reference numeral 51 is a solder ball formed on the pad 48, and other parts having the same reference numerals as those in FIG. 3 or 4 correspond to the same reference numerals in FIG. 3 or 4. Note that, as shown in FIG. 6, the insulating film 52 is composed of a plurality of striped members and has a comb-shaped cross section, whereby capacitive coupling can be further reduced.

Embodiment 3 Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 7 and 8. FIG. 7 is a partial cross-sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention. In FIG. 7, 6
Reference numeral 0 denotes a plate-like cap having a substantially square plane shape for hermetically sealing the semiconductor chip 1, 70 denotes a cavity 3 for mounting the semiconductor chip 1 and a conductive path connecting the semiconductor chip 1 and the outside of the semiconductor device. The multilayer substrate has 62, solder which is an electrical connecting means for connecting the multilayer substrate 70 and the cap 60, 64 is an adhesive agent for bonding the cap 60 and the multilayer substrate 70, and other components having the same reference numerals as those in FIG. This is a portion corresponding to the same reference numeral portion in FIG.

The multi-layer substrate 70 is constructed by stacking first to third insulating substrates 71 to 73. Each of the first to third insulating substrates 71 to 73 is formed by hollowing out a plate-shaped central portion having a substantially square planar shape of the same size in a square shape so as to be parallel to the outer peripheral side. , The square-shaped region is the first insulating substrate 71 to
It becomes smaller in order toward the third insulating substrate 73. Pads 77 are formed on the upper surface of the first insulating substrate 71 on the opposite side of the second insulating substrate 72. First insulating substrate 71
An interlayer conductive layer 74 is formed between the second insulating substrate 72 and the second insulating substrate 72. An interlayer conductive layer 75 is formed between the second insulating substrate 72 and the second insulating substrate 73. These interlayer conductive layers 74, 75 and the pad 77 are electrically connected by a via hole 76. Pad 63 of cap 60
Is provided in a region around the cap 60, which is in contact with the multilayer substrate 70. The pads 60 and 77 are
It is connected by solder 62. The cap 60 is formed so that the peripheral portion of the multilayer substrate 70 and the peripheral portion of the multilayer substrate 70 are aligned.
Combined with 0. The cap 60 and the multilayer substrate 70 are
Bonding is performed using the entire upper surface of the first insulating substrate 71 of the multilayer substrate 70, and since the bonding area is increased, airtightness is improved.

FIG. 8 is a plan view showing the structure of the adhesive agent formed into a sheet. The adhesive sheet 64 is provided with an opening portion 65 in accordance with the positions of the pads 63 and 77 in FIG. When connecting the cap 60 and the multi-layer substrate 70, first, the opening 65 of the adhesive sheet 64 and the pad 77 are aligned with each other, and the adhesive sheet 64 is adhered or connected to the multi-layer substrate 70. Fix it. Spherical solder is inserted into the opening 65. The cap 60 is placed on the multilayer substrate 70 while aligning at the ends, and heated at 180 to 200 ° C. for a certain time while applying pressure. The pad 63 and the pad 77 are connected by solder, and the cap 60 and the multilayer substrate 70 are adhered by a cured adhesive 64.

Fourth Embodiment Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 9 and 10. FIG. 9 is a plan view showing the inner surface of the cap of the semiconductor device. In FIG. 9, reference numeral 80 is a plate-shaped cap formed of an insulating material and having a substantially square planar shape.
Reference numeral 1 denotes a solid pattern formed on almost the entire area surrounded by the diagonal line connecting the upper right corner and the lower left corner of the inner surface of the cap 80, the right side and the lower side, and the power supply voltage Vdd is given to the cap 80. Is a solid pattern formed on almost the entire area surrounded by the diagonal line connecting the lower left corner and the left side and the upper side and supplied with the power supply voltage Vss. Reference numeral 83 is a chip capacitor having both ends connected to the solid patterns 81 and 82.
The solid patterns 81 and 82 are separated by a predetermined distance. The solid patterns 81 and 82 are the cap 8
It has an area of approximately one half of the inner surface of zero. The chip capacitor 83 is bonded to the solid patterns 81 and 82 by soldering at the same time as electrical connection. FIG. 10 shows 8 of FIG.
It is the figure which expanded a part of 4-84 line cross section. FIG.
0, the same reference numerals as those in FIG. 1 or 9 correspond to the same reference numerals in FIG. 1 or 9. FIG.
1 is the same as the semiconductor device shown in FIG. 1 except the solid patterns 81 and 82 and the chip capacitor 83. As shown in FIG. 10, the chip capacitor 83 for noise removal can be housed in the cavity 3. Also,
Balls for supplying power supply voltages Vdd and Vss to the solid patterns 81 and 82 can be mounted on the outer surface of the cap 80.
It is possible to effectively use the mounting area allocated to the semiconductor device in the area of the motherboard to improve the degree of integration. The solid patterns 81 and 82 also serve as pads for connecting the chip capacitors 83 and wirings for supplying power from the balls to the semiconductor chip 1. Solid pattern 81,
By connecting the chip capacitor 83 to 82, the resistance value between the chip capacitor 83 and the semiconductor chip 1 can be reduced and the noise removal effect can be enhanced.

Embodiment 5. Next, a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 11 and 12 are a plan view and a side view showing a structure of a cap base portion of a semiconductor device according to a fifth embodiment of the present invention. In FIG. 11 and FIG. 12, 21 is a plate-shaped cap base formed of an insulating material and having a substantially square planar shape, and 91 is the cap base 21.
Is a copper foil formed on the outer periphery of the outer surface of the. Balls, through holes, wiring layers, etc. are added to the cap base portion 21 shown in FIGS. 11 and 12 to form a cap. The semiconductor device shown in FIG. 13 is configured using such a cap. FIG. 13 is a sectional view showing the structure of the semiconductor device according to the fifth embodiment. In FIG. 13, 90 is a cap formed by using the cap base 21 of FIGS. 11 and 12, and 92 is a copper foil formed around the opening of the outer surface of the multilayer substrate 2 into which the cap 90 is fitted.
Reference numeral 93 is a solder fused to the copper foils 91 and 92, and those having the same reference numerals as those in FIG. 10 are portions corresponding to the same reference numerals in FIG. Since the gap between the cap 90 and the multilayer substrate 2 is filled with the solder 93, the airtightness is improved as compared with the conventional encapsulant mainly made of resin.

FIG. 14 is a sectional view showing another mode of the semiconductor device according to the fifth embodiment of the present invention. The semiconductor device shown in FIG. 14 is different from the semiconductor device of FIG. 13 in the place where the copper foil for sealing is formed. While the copper foils 91 and 92 of the semiconductor device of FIG. 13 are formed only on the outer surfaces of the multilayer substrate 2 and the cap 90, the copper foils 96 and 97 of the semiconductor device of FIG. Is formed in the region from the outer surface to the side surface. With such a configuration, the solder 98 penetrates deeper into the gap between the cap 95 and the multilayer substrate 2 than the solder 93, increases the contact area with the side surface, and improves the airtightness as compared with the above embodiment. In the above-described embodiment, the copper foils 91, 92, 96, 97 are added to the metal foil fused by solder.
Although a metal other than copper may be used, the same effect as that of the above-described embodiment is obtained. Further, a brazing material made of a metal other than solder may be used, and the same effect as that of the above-described embodiment can be obtained.

Embodiment 6 FIG. Next, a structure of a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 15 is a plan view showing a structure of a cap base portion used for a cap of a semiconductor device according to a sixth embodiment of the present invention, and FIG. 16 is a sectional view taken along line 104-104 of FIG.
It is a line sectional view. In FIG. 15 and FIG. 16, 101
Is a plate-shaped cap base having a substantially square planar shape formed of an insulating material, 96 is a copper foil formed on the outer periphery and side of the outer surface of the cap base 101, and 102 is the upper right corner of the outer surface of the cap base 101. And a lower left corner, a solid pattern formed in a region surrounded by the right side and the lower side of the copper foil 96 to which the power supply voltage Vdd is applied, and 103 is a diagonal line connecting the upper right corner and the lower left corner of the outer surface of the cap base 101. A solid pattern formed in a region surrounded by the left side and the upper side of the copper foil 96 and supplied with the power supply voltage Vss, 105 is a solder ball formed on the solid pattern 102 or 103, and 106 is formed by driving a metal rod. The through holes connected to the solid patterns 81 and 102 and having the same reference numerals as those in FIG. 14 are portions corresponding to the same reference numerals in FIG. 14.

The solid patterns 102 and 103 are copper foil 96.
Occupies most of the area surrounded by. The semiconductor device of FIG. 16 can reduce the number of through holes and further improves the airtightness as compared with the semiconductor device of FIG.

Embodiment 7 FIG. Next, a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention will be described with reference to FIGS. FIG. 17 is a plan view showing the structure of the solder foil used for manufacturing the semiconductor device. The solder foil 110 of FIG. 17 is a low melting point solder foil formed by punching out the center of a square foil into a square. This solder foil 110
Is composed of a low melting point solder having a melting point lower than that of the solder ball. FIG. 18 is a cross-sectional view showing the state of the semiconductor device in the step of sealing the cap with the solder foil. After preparing the solder foil 110, the solder foil 110
Is placed on the copper foil 96 of the cap 95 and the copper foil 97 of the multilayer substrate 2. At this time, the alignment is performed so that the solder foil 110 is placed on the entire gap between the copper foils 96 and 97. By reflowing the solder foil 110, the solder is poured into the gap between the copper foils 96 and 97 as shown in FIG. 14 by utilizing the capillary phenomenon. Sealing can be performed reliably in a short time, as compared with fusion bonding while moving along the copper foils 96 and 97 using rod-shaped solder. A metal brazing material having a low melting point outside the food table may be used, and the same effect as that of the above-described embodiment is obtained.

Embodiment 8 FIG. Next, a semiconductor device according to an eighth embodiment of the present invention will be described with reference to FIGS. 19 is a sectional view showing a structure of a semiconductor device according to an eighth embodiment of the present invention, and FIG. 20 is a schematic exploded view showing a relationship between balls and wiring layers. FIG.
20, 120 is a substantially square cap base formed by stacking two insulating substrates, 121 is a solder ball provided on the outer surface of the cap base 120,
Reference numeral 22 denotes a power supply voltage V provided inside the cap base 120.
ss is supplied in a substantially square solid pattern, 123 is a substantially square solid pattern provided on the inner surface of the cap base 120 and supplied with the power supply voltage Vdd, 124 is a via hole connecting the solid pattern 122 and the ball 121,
Reference numeral 25 is a through hole that connects the ball 121 and the solid pattern 123, 126 is a pad provided on the inner surface of the cap base 120, 127 is the pad 126 and the solid pattern 1.
It is a via hole connecting 22. Solid pattern 122
Is a through hole 125 penetrating the cap base 120.
Has an opening 128 so as not to contact the solid pattern 122.

The cap base 120 is made of ceramic, glass epoxy, BT resin or the like, but it is preferable to use a material having a high dielectric constant. Solid patterns 122, 1
23 are opposed to each other across the dielectric, the power supply voltage Vd
A relatively large electric capacity can be provided between the wirings that supply d and Vss. With the capacitance, noise of the supplied power supply voltages Vdd and Vss can be removed. In addition, the power supply voltage Vd is applied to the outer surface of the cap base 120.
Balls 121 for supplying d and Vss can be arranged,
Since it is not necessary to dispose the power supply ball 121 formed on the outer surface of the cap base 120 on the multilayer substrate side,
The packaging density can be improved. Needless to say, the features of the above-described embodiments can be combined.

[0038]

As described above, according to the semiconductor device of the first aspect of the present invention, the first electrical connecting means, the first wiring layer of the multilayer substrate, the second electrical connecting means, and the cap are provided. Since there is a conductive path to the chip via a plurality of balls provided on the outer surface of the base of the semiconductor device, the balls on the outer surface of the cap base can reduce the density of the balls of the semiconductor device, and the semiconductor device can be easily miniaturized. Therefore, there is an effect that the packaging density can be easily improved.

In the semiconductor device according to the second aspect of the invention, the current flowing through the wire and the current flowing through the first wiring pattern are
Since they have the same size and are oriented in opposite directions, the effective inductance between the wire and the first wiring pattern can be reduced, and noise can be reduced.

In the semiconductor device according to the third aspect of the present invention, since the second wiring layer and the first electrical connection means can be insulated by the insulating means, the cap becomes thicker and the second wiring layer and the first electrical connection means are insulated from each other. Even if the electrical connection means are close to each other, it is possible to prevent a failure due to the contact between them.

According to a fourth aspect of the semiconductor device of the present invention, a plurality of wiring layers including a second wiring layer and an inter-substrate wiring layer are provided, and the first and second interlayer conductive paths are appropriately provided between the ball and the chip. Since it is possible to combine and connect them to each other, there is an effect that the degree of freedom of layout is increased and wiring is facilitated.

According to the semiconductor device of the fifth aspect of the present invention, since the cap has a shape such that the outer edge portions thereof are substantially aligned when the cap is overlapped with the multilayer substrate, the multilayer substrate and the cap are formed. There is an effect that the contact area with the can be increased and the airtightness can be improved.

According to the semiconductor device of the sixth aspect, since the capacitor is provided on the inner surface side of the cap, the mounting density can be improved and the electrical characteristics can be improved as compared with the case where the capacitor is installed outside. The effect is that it can be improved.

According to the semiconductor device of the seventh aspect of the present invention, the second and third wiring patterns each have an area that is approximately half that of the second wiring layer. Therefore, the resistance value between the capacitor and the chip is large. There is an effect that the noise removal effect of the capacitor can be sufficiently brought out by reducing

According to the eighth aspect of the semiconductor device of the present invention, the metal brazing material is used for the first and second metal foils so as to fill the gap between the first and second metal foils with the metal brazing material. Since the material is welded, there is an effect that the air passage between the first space and the second space can be blocked by the metal to enhance the airtightness.

According to the semiconductor device of the ninth aspect of the present invention, since the base portion is provided with the wiring layer connected to the ball for supplying the power source and acting as the capacitor, the electrical characteristics are improved, Moreover, there is an effect that the packaging density can be improved.

According to the method of manufacturing a semiconductor device of the tenth aspect of the present invention, the first metal foil formed on the outer peripheral portion of the insulating cap and the opening of the case adjacent to the first metal foil are formed. Since the second metal foil formed over the entire circumference is sealed with the brazing material made of metal, there is an effect that the airtightness of the case and the cap can be improved as compared with the case of sealing with a resin.

According to the semiconductor device manufacturing method of the present invention, the flat plate-shaped metal brazing material that covers the gap between the first metal foil and the second metal foil is applied to the gap. Since it melts and fills the gap, there is an effect that the reliability of sealing and workability can be improved.

According to the cap of the semiconductor device of the present invention, the cap can be electrically connected to the outside from the inner wiring layer through the first interlayer conductive path and the plurality of balls. It is possible to reduce the number of leads in the case of being combined with, and to improve the packaging density of the semiconductor device.

According to a thirteenth aspect of the present invention, in the cap of the semiconductor device, the second wiring layer and the plurality of wiring layers between the substrates are provided, and the first and second interlayer conductive layers are provided between the ball and the chip. Since it is possible to appropriately combine and connect the paths, there is an effect that the degree of freedom in layout is increased and wiring is facilitated.

According to the cap of the semiconductor device of the fourteenth aspect of the present invention, at least two wiring layers facing each other of at least one inter-substrate wiring layer and the inner surface side wiring layer of the base portion form a capacitor. There is an effect that the packaging density of the device can be improved and the electrical characteristics can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a plan view showing an inner surface of the cap shown in FIG.

FIG. 3 is a partial cross-sectional view in which a part of FIG. 1 is enlarged.

FIG. 4 is a sectional view showing a structure of a cap according to a second embodiment of the present invention.

FIG. 5 is a partial cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a partial cross-sectional view showing the structure of a semiconductor device according to another aspect of the second embodiment of the present invention.

FIG. 7 is a partial sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a plan view showing a configuration of an adhesive sheet.

FIG. 9 is a plan view of a base portion of a cap according to Embodiment 4 of the present invention.

FIG. 10 is a partial cross sectional view showing the structure of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 11 is a plan view of the base portion of the cap according to the fifth embodiment of the present invention.

FIG. 12 is a side view of the base portion of the cap according to the fifth embodiment of the present invention.

FIG. 13 is a partial cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 14 is a partial cross sectional view showing the structure of a semiconductor device according to another aspect of the fifth embodiment of the present invention.

FIG. 15 is a plan view of a base portion of a cap according to Embodiment 6 of the present invention.

FIG. 16 is a partial cross sectional view showing the structure of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 17 is a plan view of a solder foil used in the method of manufacturing a semiconductor device according to the seventh embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the seventh embodiment of the present invention.

FIG. 19 is a sectional view showing a structure of a semiconductor device according to an eighth embodiment of the present invention.

FIG. 20 is an exploded view showing the structure of a semiconductor device according to an eighth embodiment of the present invention.

FIG. 21 is a sectional view showing a configuration of a conventional semiconductor device.

[Explanation of symbols]

1 semiconductor chip, 2,70 multilayer substrate, 4 wires,
20, 60, 90 cap, 21 cap base,
5,22,105,121 ball, 24,49 through hole, 50 insulating film, 83 chip capacitor, 8
1, 82, 122, 123 solid pattern, 91, 9
2,96,97 Copper foil, 110 Solder foil.

Claims (14)

[Claims] 1. A semiconductor device having a ball grid array structure used for face-down bonding, wherein a chip on which an element is formed, a cavity for accommodating the chip, and a first substrate arranged between an insulating substrate. A multi-layer substrate having a wiring layer, first electrical connection means for electrically connecting the chip to the first wiring layer, an inner surface facing the cavity and an outer surface facing the outside of the semiconductor device. Having an insulating base, a plurality of balls provided on the outer surface of the base, a second wiring layer provided on the inner surface, and the plurality of balls and the second wiring provided through the base. A cap having a first interlayer conductive path for electrically connecting the wiring layers, and a second for connecting between the first and second wiring layers.
And an electric connection means of the semiconductor device. 2. The first electrical connection means includes a wire stretched in the cavity for connecting the chip and the first wiring layer, and the second wiring layer is the wire. A first wiring pattern provided in the same current path as the above, wherein the current flowing through the wire and the current flowing through the first wiring pattern are directed in substantially opposite directions to each other. 1. The semiconductor device according to 1. 3. The cap is provided on the inner surface side,
3. The semiconductor device according to claim 1, further comprising insulating means for insulating between the second wiring layer and the first electrical connection means. 4. The base portion includes any one of a plurality of laminated insulating substrates, at least one inter-substrate wiring layer provided between layers of the insulating substrate, the inter-substrate wiring layer and the plurality of balls, or The semiconductor device according to any one of claims 1 to 3, further comprising a second interlayer conductive path for electrically connecting to the second wiring layer. 5. The cap according to any one of claims 1 to 4, wherein the cap has a shape such that an outer edge portion thereof is substantially aligned when the cap is overlapped with the multilayer substrate. Semiconductor device. 6. The second wiring layer includes second and third wiring patterns, is provided on the inner surface side of the cap, and is electrically connected to the second and third wiring patterns. 6. The semiconductor device according to claim 1, further comprising a capacitor. 7. The second and third wiring patterns are
7. The semiconductor device according to claim 6, wherein each of the second wiring layers has an area that is approximately one half of that of the second wiring layer. 8. The base further comprises a first metal foil provided on an outer peripheral portion of the base, wherein the multi-layer substrate is attached to the first metal foil when the base is fitted into the multi-layer substrate. A second metal foil disposed around the first metal foil so as to be adjacent to each other, and the first and second metal foils are arranged so as to block an air passage between the cavity and the outside. The semiconductor device according to any one of claims 1 to 7, further comprising a brazing material portion made of metal that is welded over the entire circumference of the metal foil. 9. The base according to claim 1, wherein the base further has two opposing conductor layers connected to balls for supplying power among the plurality of balls and serving as capacitors. The semiconductor device according to any one of claims. 10. A step of forming a first metal foil on an outer peripheral portion of an insulative cap, and an opening of the case adjacent to the first metal foil when the cap is fitted in an insulative case. And a step of sealing the first and second metal foils with a brazing material made of metal. 11. The step of encapsulating with the metal brazing material is a step of applying a flat plate annular metal brazing material covering the gap between the first metal foil and the second metal foil to the gap. 11. The method of manufacturing a semiconductor device according to claim 10, further comprising: a step of melting the brazing material made of metal while applying the brazing material to the gap to close the gap. 12. An insulative base having an inner surface facing a cavity in which a chip is mounted and an outer surface facing the outside of a semiconductor device, a plurality of balls provided on the outer surface of the base, and an inner surface provided on the inner surface. A cap for a semiconductor device, comprising: an inner wiring layer; and a first interlayer conductive path that is provided through the base and electrically connects the balls to the inner wiring layer. 13. The base portion includes any one of a plurality of laminated insulating substrates, at least one inter-substrate wiring layer provided between the insulating substrates, the inter-substrate wiring layer and the plurality of balls, or The cap of the semiconductor device according to claim 12, further comprising a second interlayer conductive path for electrically connecting to the inner surface side wiring layer. 14. The semiconductor according to claim 13, wherein at least two wiring layers facing each other of the at least one inter-substrate wiring layer and the inner wiring layer of the base form a capacitor. Equipment cap.