JP5544950B2 - Semiconductor device manufacturing method and semiconductor device mounting method - Google Patents

Semiconductor device manufacturing method and semiconductor device mounting method Download PDF

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JP5544950B2
JP5544950B2 JP2010058584A JP2010058584A JP5544950B2 JP 5544950 B2 JP5544950 B2 JP 5544950B2 JP 2010058584 A JP2010058584 A JP 2010058584A JP 2010058584 A JP2010058584 A JP 2010058584A JP 5544950 B2 JP5544950 B2 JP 5544950B2
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wiring
semiconductor device
solder
insulating substrate
terminal
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JP2011192852A (en
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裕康 定別当
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Description

本発明は、半導体装置の製造方法及び半導体装置の実装方法に関する。   The present invention relates to a semiconductor device manufacturing method and a semiconductor device mounting method.

従来の半導体装置では、基板にチップ部品を取り付け、型に樹脂を流し込み高圧にすることによりＬＳＩ等のチップ部品を封止した樹脂モールド化が進んでいる（例えば、特許文献１参照）。半導体装置の多機能化、微細ルール化に伴い、ＬＳＩの小型化、Ｉ／Ｏ端子の増大に伴う狭ピッチ化が進行している。   In a conventional semiconductor device, resin molding is progressing in which a chip component is attached to a substrate, a resin is poured into a mold, and the chip component such as an LSI is sealed by high pressure (for example, see Patent Document 1). As semiconductor devices become more multifunctional and have finer rules, LSIs are becoming smaller and pitches are being reduced as I / O terminals are increased.

特開２００３−２５８１９２号公報JP 2003-258192 A

ところで、チップ部品を樹脂で封止するには、以下の図１０（ａ）〜（ｄ）に示すようなプロセスが考えられる。
まず、図１０（ａ）に示すような絶縁基板１０２の上面に配線１０３を形成し、ソルダーレジスト１０６で被覆する。次に、図１０（ｂ）に示すように、絶縁基板１０２の配線１０３が設けられた面の中央部に半導体チップ１０４を接着剤等により固定する。そして、半導体チップ１０４の図示しない電極端子と配線１０３の一端部１０３ａとをボンディングワイヤー１０５により接続する。 By the way, in order to seal the chip component with resin, processes as shown in FIGS. 10A to 10D below can be considered.
First, the wiring 103 is formed on the upper surface of the insulating substrate 102 as shown in FIG. 10A and covered with the solder resist 106. Next, as shown in FIG. 10B, the semiconductor chip 104 is fixed to the central portion of the surface of the insulating substrate 102 where the wiring 103 is provided with an adhesive or the like. Then, an electrode terminal (not shown) of the semiconductor chip 104 and one end portion 103 a of the wiring 103 are connected by a bonding wire 105.

次に、図１０（ｃ）に示すように、樹脂材料を滴下して半導体チップ１０４、ボンディングワイヤー１０５及び配線１０３の一端部１０３ａを封止する封止樹脂１０７を形成する。その後、図１０（ｄ）に示すように、配線１０３の他端部１０３ｂに半田端子１０８を搭載する。   Next, as shown in FIG. 10C, a resin material is dropped to form a sealing resin 107 that seals the semiconductor chip 104, the bonding wire 105, and the one end 103 a of the wiring 103. Thereafter, as shown in FIG. 10 (d), the solder terminal 108 is mounted on the other end 103 b of the wiring 103.

半田端子１０８を印刷法により設けない場合、配線１０３の他端部１０３ｂに半田ボールを搭載することにより半田端子１０８を設けることになる。しかし、半田ボールを搭載する場合には、配線１０３の他端部１０３ｂに金メッキ処理を施す必要があり、工数が増え、半田ボールも高価なので、半田ペースト印刷法よりも大幅にコスト高になるという問題がある。   When the solder terminal 108 is not provided by a printing method, the solder terminal 108 is provided by mounting a solder ball on the other end portion 103 b of the wiring 103. However, when a solder ball is mounted, the other end portion 103b of the wiring 103 needs to be subjected to a gold plating process, which increases the number of steps and the solder ball is expensive, so that the cost is significantly higher than the solder paste printing method. There's a problem.

本発明の課題は、ローコストな半導体装置の製造方法及び半導体装置の実装方法を提供することである。   An object of the present invention is to provide a low-cost manufacturing method of a semiconductor device and a mounting method of the semiconductor device.

以上の課題を解決するために、本発明の一の態様によれば、絶縁基板の少なくとも一方の面に設けられた配線の一端に、半田印刷により半田端子を形成する第１工程と、前記第１工程後に、前記絶縁基板の前記配線が設けられた面に、前記配線より上方向に突出した状態で半導体チップを固定し、前記配線の他端と前記半導体チップの端子とを接続する第２工程と、前記第２工程後に、前記半導体チップを封止樹脂により封止する第３工程と、を含むことを特徴とする半導体装置の製造方法が提供される。 In order to solve the above problems, according to one aspect of the present invention, on at least one end of the wiring provided on the surface of the insulating substrate, a first step of forming a solder connection by the solder printing, the first After one step , a semiconductor chip is fixed to the surface of the insulating substrate on which the wiring is provided , protruding upward from the wiring, and the other end of the wiring is connected to the terminal of the semiconductor chip. There is provided a method for manufacturing a semiconductor device comprising: a step; and a third step of sealing the semiconductor chip with a sealing resin after the second step .

前記第３工程において、前記半導体チップは前記封止樹脂の材料を滴下するポッティングにより封止することを特徴とするものであってもよい。
前記配線上に、前記配線の前記一端と前記他端を露出させる開口が形成されたレジストを設けることを特徴とするものであってもよい。
前記第３工程において、前記配線の前記他端及び前記レジストの一部も前記封止樹脂により封止することを特徴とするものであってもよい。
一方の面の前記半田端子と対応する位置に他の半田端子が設けられたメイン基板に対し、前記半田端子と前記他の半田端子とを融着させることにより前記絶縁基板を前記メイン基板に固定する第４工程と、を含むことを特徴とするものであってもよい。
前記メイン基板には前記封止樹脂と対応する位置に穴が設けられていることを特徴とするものであってもよい。 In the third step, the semiconductor chip may be sealed by potting by dropping the material of the sealing resin.
A resist in which an opening exposing the one end and the other end of the wiring is formed on the wiring may be provided.
In the third step, the other end of the wiring and a part of the resist may be sealed with the sealing resin.
Fixing the insulating substrate to the main substrate by fusing the solder terminal and the other solder terminal to the main substrate provided with another solder terminal at a position corresponding to the solder terminal on one surface And a fourth step.
The main board may be provided with a hole at a position corresponding to the sealing resin.

本発明によれば、ローコストな半導体装置の製造方法及び半導体装置の実装方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of a low-cost semiconductor device and the mounting method of a semiconductor device can be provided.

本発明の実施形態に係る半導体装置１の平面図である。1 is a plan view of a semiconductor device 1 according to an embodiment of the present invention. 図１のII−II矢視断面図である。It is II-II arrow sectional drawing of FIG. 半導体装置１の製造方法の説明図である。FIG. 10 is an explanatory diagram of the manufacturing method of the semiconductor device 1. 半導体装置１の製造方法の説明図である。FIG. 10 is an explanatory diagram of the manufacturing method of the semiconductor device 1. 半導体装置１の製造方法の説明図である。FIG. 10 is an explanatory diagram of the manufacturing method of the semiconductor device 1. 半導体装置１が実装されるメイン基板１０を示す断面図である。It is sectional drawing which shows the main board | substrate 10 with which the semiconductor device 1 is mounted. 半導体装置１のメイン基板１０への実装方法の説明図である。FIG. 10 is an explanatory diagram of a method for mounting the semiconductor device 1 on the main substrate 10. 半導体装置１のメイン基板１０への実装方法の説明図である。FIG. 10 is an explanatory diagram of a method for mounting the semiconductor device 1 on the main substrate 10. （ａ）〜（ｃ）は半導体装置１に用いられる他の形態の絶縁基板を示す断面図である。(A)-(c) is sectional drawing which shows the insulating substrate of the other form used for the semiconductor device 1. FIG. （ａ）〜（ｄ）はチップ部品を樹脂で封止するプロセスの説明図である。(A)-(d) is explanatory drawing of the process of sealing a chip component with resin.

以下に、本発明を実施するための好ましい形態について図面を用いて説明する。但し、以下に述べる実施形態には、本発明を実施するために技術的に好ましい種々の限定が付されているが、発明の範囲を以下の実施形態及び図示例に限定するものではない。   Hereinafter, preferred embodiments for carrying out the present invention will be described with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

〔第１実施形態〕
図１は本発明の実施形態に係る半導体装置１の平面図であり、図２は図１のII−II矢視断面図である。図１、図２に示すように、半導体装置１は、絶縁基板２と、配線３と、半導体チップ４と、ボンディングワイヤー５と、ソルダーレジスト６と、封止樹脂７と、半田端子８と、等を備える。 [First Embodiment]
FIG. 1 is a plan view of a semiconductor device 1 according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG. As shown in FIGS. 1 and 2, the semiconductor device 1 includes an insulating substrate 2, a wiring 3, a semiconductor chip 4, a bonding wire 5, a solder resist 6, a sealing resin 7, a solder terminal 8, Etc.

絶縁基板２は、例えば、ガラス布基材エポキシ樹脂、ガラス布基材ポリイミド樹脂その他のガラス布基材絶縁性樹脂複合材といった繊維強化樹脂からなる。
配線３は、例えば銅等の導体からなる。複数の配線３が、絶縁基板２の一方の面に、絶縁基板２の中央側から外周側に向かって放射状に設けられている。
半導体チップ４は、シリコンの半導体基板に集積回路を設けたものである。半導体チップ４は、接着剤等により絶縁基板２の配線３が設けられた面の中央部に固定される。半導体チップ４には図示しない電極端子が設けられており、電極端子は配線３の中央側端部３ａとボンディングワイヤー５により接続される。 The insulating substrate 2 is made of, for example, a fiber reinforced resin such as a glass cloth base epoxy resin, a glass cloth base polyimide resin, or another glass cloth base insulating resin composite.
The wiring 3 is made of a conductor such as copper, for example. A plurality of wirings 3 are provided radially on one surface of the insulating substrate 2 from the center side of the insulating substrate 2 toward the outer peripheral side.
The semiconductor chip 4 is obtained by providing an integrated circuit on a silicon semiconductor substrate. The semiconductor chip 4 is fixed to the central portion of the surface on which the wiring 3 of the insulating substrate 2 is provided by an adhesive or the like. The semiconductor chip 4 is provided with an electrode terminal (not shown), and the electrode terminal is connected to the center side end 3 a of the wiring 3 by the bonding wire 5.

絶縁基板２の配線３が設けられた面は、ソルダーレジスト６により覆われている。ソルダーレジスト６には、半導体チップ４が固定される中央部分に開口６ａが設けられている。開口６ａにおいて、配線３の中央側端部３ａが露出されている。また、ソルダーレジスト６には、絶縁基板２の外周部において、配線３の外周側端部３ｂを露出させる開口６ｂが設けられている。   The surface of the insulating substrate 2 on which the wiring 3 is provided is covered with a solder resist 6. The solder resist 6 is provided with an opening 6a at a central portion where the semiconductor chip 4 is fixed. In the opening 6a, the center side end 3a of the wiring 3 is exposed. In addition, the solder resist 6 is provided with an opening 6 b in the outer peripheral portion of the insulating substrate 2 that exposes the outer peripheral side end 3 b of the wiring 3.

封止樹脂７は、開口６ａを塞ぐように設けられ、半導体チップ４、ボンディングワイヤー５及び配線３の一端部を封止する。封止樹脂７を設けることで、実装工程での汚れによる絶縁性低下を防ぎ機械強度を高めることができる。
半田端子８は、開口６ｂを塞ぐように設けられている。半田端子８は、配線３及びボンディングワイヤー５を介して半導体チップ４の電極端子と導通している。 The sealing resin 7 is provided so as to close the opening 6 a and seals one end of the semiconductor chip 4, the bonding wire 5, and the wiring 3. By providing the sealing resin 7, it is possible to prevent the insulation from being deteriorated due to dirt in the mounting process and to increase the mechanical strength.
The solder terminal 8 is provided so as to close the opening 6b. The solder terminal 8 is electrically connected to the electrode terminal of the semiconductor chip 4 through the wiring 3 and the bonding wire 5.

ここで、図３〜図５を用いて半導体装置１の製造方法について説明する。
まず、図３に示すように、絶縁基板２の上面に配線３を形成し、ソルダーレジスト６をパターニングする。
次に、図４に示すように、開口６ｂを塞ぐように半田端子８を形成する。半田端子８は、フラックスにスズ等からなる半田の粉末が混ざったペースト状のものを、印刷マスクを用いてスクリーン印刷法等により設けることができる。
次に、図５に示すように、絶縁基板２の配線３が設けられた面の中央部に半導体チップ４を接着剤等により固定する。そして、半導体チップ４の図示しない電極端子と配線３の中央側端部３ａとをボンディングワイヤー５により接続する。
その後、開口６ａを塞ぐように封止樹脂７の材料を滴下する（ポッティング）。滴下した樹脂材料が固化することで、半導体チップ４、ボンディングワイヤー５及び配線３の一端部を封止する封止樹脂７が形成される。以上により、図１、図２に示す半導体装置１が完成する。 Here, a manufacturing method of the semiconductor device 1 will be described with reference to FIGS.
First, as shown in FIG. 3, the wiring 3 is formed on the upper surface of the insulating substrate 2, and the solder resist 6 is patterned.
Next, as shown in FIG. 4, solder terminals 8 are formed so as to close the openings 6b. The solder terminal 8 can be provided by a screen printing method or the like using a printing mask with a paste in which solder powder made of tin or the like is mixed with flux.
Next, as shown in FIG. 5, the semiconductor chip 4 is fixed to the center of the surface of the insulating substrate 2 where the wiring 3 is provided with an adhesive or the like. Then, an electrode terminal (not shown) of the semiconductor chip 4 and the center side end 3 a of the wiring 3 are connected by a bonding wire 5.
Thereafter, the material of the sealing resin 7 is dropped so as to close the opening 6a (potting). By solidifying the dropped resin material, a sealing resin 7 for sealing one end of the semiconductor chip 4, the bonding wire 5, and the wiring 3 is formed. Thus, the semiconductor device 1 shown in FIGS. 1 and 2 is completed.

次に、半導体装置１を実装するメイン基板１０について説明する。図６は半導体装置１が実装されるメイン基板１０を示す断面図である。図６に示すように、メイン基板１０は、絶縁基板１２と、絶縁基板の一方の面に設けられた配線１３と、配線１３を被覆するソルダーレジスト１６と、等を備える。なお、メイン基板１０の半導体装置１が取り付けられる位置には、封止樹脂７が逃げるための逃げ穴１７が設けられている。また、ソルダーレジスト１６には、配線１３の端部１３ａを露出させる開口１６ａが設けられている。開口１６ａには、印刷法により半田端子１８が設けられる。   Next, the main substrate 10 on which the semiconductor device 1 is mounted will be described. FIG. 6 is a cross-sectional view showing the main substrate 10 on which the semiconductor device 1 is mounted. As shown in FIG. 6, the main substrate 10 includes an insulating substrate 12, a wiring 13 provided on one surface of the insulating substrate, a solder resist 16 that covers the wiring 13, and the like. Note that a relief hole 17 through which the sealing resin 7 escapes is provided at a position where the semiconductor device 1 of the main substrate 10 is attached. In addition, the solder resist 16 is provided with an opening 16 a that exposes the end 13 a of the wiring 13. Solder terminals 18 are provided in the openings 16a by a printing method.

次に、図６〜図８を用いて、半導体装置１のメイン基板１０への実装方法について説明する。まず、図６に示すように、ソルダーレジスト１６の開口１６ａを塞ぐように半田端子１８を形成する。
次に、図７に示すように、メイン基板１０の上部に、半導体装置１を載置する。このとき、半導体装置１の封止樹脂７及び半田端子８が設けられた面を下に向け、半田端子８を半田端子１８の上部に載置し、かつ、封止樹脂７が逃げ穴１７の内部となるように配置する。
次に、半導体装置１及びメイン基板１０を加熱して半田端子８、１８を融かし、冷却することで図８に示すように一体化させる（リフロー法）。以上のようにして半導体装置１のメイン基板１０への実装が完了する。 Next, a method for mounting the semiconductor device 1 on the main substrate 10 will be described with reference to FIGS. First, as shown in FIG. 6, solder terminals 18 are formed so as to close the openings 16 a of the solder resist 16.
Next, as shown in FIG. 7, the semiconductor device 1 is placed on the main substrate 10. At this time, the surface of the semiconductor device 1 on which the sealing resin 7 and the solder terminal 8 are provided faces downward, the solder terminal 8 is placed on the upper part of the solder terminal 18, and the sealing resin 7 Arrange to be inside.
Next, the semiconductor device 1 and the main substrate 10 are heated to melt the solder terminals 8 and 18 and cooled to be integrated as shown in FIG. 8 (reflow method). As described above, the mounting of the semiconductor device 1 on the main substrate 10 is completed.

このように、本発明によれば、半田端子８を設けてから封止樹脂７により半導体チップ４やボンディングワイヤー５を封止するため、封止樹脂７が半田印刷の妨げとならない。このため、あらかじめ半田端子８を印刷法により安価に設けることができる。このため、半導体装置１をローコストで製造し、実装することができる。
また、本発明によれば、配線３の他端部３ｂに半田端子８を設けてから封止樹脂７により半導体チップ４やボンディングワイヤー５を封止するため、配線３の他端部３ｂが露出したまま封止の熱に曝されることがなく、金メッキ処理を施す必要がない。このため、半導体装置１をローコストで製造し、実装することができる。
また、本発明によれば、半導体チップ４には電極端子が設けられており、電極端子は配線３の中央側端部３ａとボンディングワイヤー５により接続されるとしたが、これに限らず、半導体チップ４に設けられた電極端子と配線３の中央側端部３ａとが何らかの手段により接続されていれば良い。 Thus, according to the present invention, since the semiconductor chip 4 and the bonding wire 5 are sealed with the sealing resin 7 after the solder terminals 8 are provided, the sealing resin 7 does not hinder solder printing. For this reason, the solder terminal 8 can be previously provided at low cost by a printing method. For this reason, the semiconductor device 1 can be manufactured and mounted at low cost.
In addition, according to the present invention, since the semiconductor terminal 4 and the bonding wire 5 are sealed with the sealing resin 7 after the solder terminal 8 is provided on the other end 3b of the wiring 3, the other end 3b of the wiring 3 is exposed. As it is, it is not exposed to the heat of sealing, and it is not necessary to perform a gold plating process. For this reason, the semiconductor device 1 can be manufactured and mounted at low cost.
Further, according to the present invention, the semiconductor chip 4 is provided with the electrode terminal, and the electrode terminal is connected to the central side end 3a of the wiring 3 by the bonding wire 5. However, the present invention is not limited to this. It is only necessary that the electrode terminals provided on the chip 4 and the center side end 3a of the wiring 3 are connected by some means.

なお、半導体装置１に用いられる絶縁基板の形状は、上記実施例に限られない。例えば、図９（ａ）に示すように、絶縁基板２の一方の面に配線３、ソルダーレジスト６、半田端子８が設けられるとともに、他方の面にもソルダーレジスト６により被覆されたものを用いてもよい。あるいは、図９（ｂ）に示すように、絶縁基板２の配線３が設けられた面と反対側の面にグランドレイヤー３Ａが設けられ、絶縁基板２に設けられたスルーホール３Ｂにより配線３とグランドレイヤー３Ａとが接続されたものを用いてもよい。
あるいは、図９（ｃ）に示すように、絶縁基板２の両面にべたのグランドレイヤー３Ａ、３Ａが形成され、一方のグランドレイヤー３Ａ上に層間絶縁層２Ａが形成され、層間絶縁層２Ａ上に配線３、ソルダーレジスト６、半田端子８が設けられたものを用いてもよい。
また、リフローの際に半田端子８材料であるスズ等が配線３材料である銅等に拡散しないように、配線３の他端部３ｂ上にニッケル等からなるバリア層を設けても良い。 Note that the shape of the insulating substrate used in the semiconductor device 1 is not limited to the above embodiment. For example, as shown in FIG. 9A, wiring 3, solder resist 6, and solder terminal 8 are provided on one surface of the insulating substrate 2, and the other surface is covered with the solder resist 6. May be. Alternatively, as shown in FIG. 9B, a ground layer 3A is provided on the surface of the insulating substrate 2 opposite to the surface on which the wiring 3 is provided, and the wiring 3 is connected to the wiring 3 by a through hole 3B provided in the insulating substrate 2. What connected to the ground layer 3A may be used.
Alternatively, as shown in FIG. 9C, solid ground layers 3A and 3A are formed on both surfaces of the insulating substrate 2, an interlayer insulating layer 2A is formed on one ground layer 3A, and the interlayer insulating layer 2A is formed on the interlayer insulating layer 2A. A wiring board, solder resist 6, and solder terminal 8 may be used.
Further, a barrier layer made of nickel or the like may be provided on the other end portion 3b of the wiring 3 so that tin or the like that is the material of the solder terminal 8 does not diffuse into copper or the like that is the material of the wiring 3 during reflow.

１、１０１ 半導体装置
２、１２、１０２ 絶縁基板
３、１３、１０３ 配線
３ａ、３ｂ、１３ａ、１０３ａ、１０３ｂ 端部
４、１０４ 半導体チップ
５、１０５ ボンディングワイヤー
６、１０６ ソルダーレジスト
６ａ、６ｂ、１６ａ、１０６ａ、１０６ｂ 開口
７、１０７ 封止樹脂
８、１０８ 半田端子
１０ メイン基板
１７ 逃げ穴 DESCRIPTION OF SYMBOLS 1,101 Semiconductor device 2, 12, 102 Insulating substrate 3, 13, 103 Wiring 3a, 3b, 13a, 103a, 103b End part 4, 104 Semiconductor chip 5, 105 Bonding wire 6, 106 Solder resist 6a, 6b, 16a, 106a, 106b Opening 7, 107 Sealing resin 8, 108 Solder terminal 10 Main board 17 Escape hole

Claims (6)

絶縁基板の少なくとも一方の面に設けられた配線の一端に、半田印刷により半田端子を形成する第１工程と、
前記第１工程後に、前記絶縁基板の前記配線が設けられた面に、前記配線より上方向に突出した状態で半導体チップを固定し、前記配線の他端と前記半導体チップの端子とを接続する第２工程と、
前記第２工程後に、前記半導体チップを封止樹脂により封止する第３工程と、を含むことを特徴とする半導体装置の製造方法。 A first step of forming a solder terminal by solder printing on one end of the wiring provided on at least one surface of the insulating substrate;
After the first step , a semiconductor chip is fixed to the surface of the insulating substrate on which the wiring is provided and protrudes upward from the wiring, and the other end of the wiring is connected to a terminal of the semiconductor chip. A second step;
And a third step of sealing the semiconductor chip with a sealing resin after the second step . 前記第３工程において、前記半導体チップは前記封止樹脂の材料を滴下するポッティングにより封止することを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the third step, the semiconductor chip is sealed by potting in which a material of the sealing resin is dropped. 前記配線上に、前記配線の前記一端と前記他端を露出させる開口が形成されたレジストを設けることを特徴とする請求項１又は２に記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein a resist in which an opening exposing the one end and the other end of the wiring is formed on the wiring. 4. 前記第３工程において、前記配線の前記他端及び前記レジストの一部も前記封止樹脂により封止することを特徴とする請求項３に記載の半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 3, wherein, in the third step, the other end of the wiring and a part of the resist are also sealed with the sealing resin. 一方の面の前記半田端子と対応する位置に他の半田端子が設けられたメイン基板に対し、前記半田端子と前記他の半田端子とを融着させることにより前記絶縁基板を前記メイン基板に固定する第４工程と、を含むことを特徴とする請求項１乃至４の何れか一項に半導体装置の実装方法。   Fixing the insulating substrate to the main substrate by fusing the solder terminal and the other solder terminal to the main substrate provided with another solder terminal at a position corresponding to the solder terminal on one surface A semiconductor device mounting method according to claim 1, further comprising: a fourth step. 前記メイン基板には前記封止樹脂と対応する位置に穴が設けられていることを特徴とする請求項５に記載の半導体装置の実装方法。   6. The method for mounting a semiconductor device according to claim 5, wherein a hole is provided in the main substrate at a position corresponding to the sealing resin.
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