JP2010232616A - Semiconductor device, and wiring board - Google Patents

Semiconductor device, and wiring board Download PDF

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JP2010232616A
JP2010232616A JP2009081603A JP2009081603A JP2010232616A JP 2010232616 A JP2010232616 A JP 2010232616A JP 2009081603 A JP2009081603 A JP 2009081603A JP 2009081603 A JP2009081603 A JP 2009081603A JP 2010232616 A JP2010232616 A JP 2010232616A
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pad
wiring
mounting
semiconductor device
wiring board
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Yoshifumi Kanetaka
善史 金高
Shinji Watanabe
真司 渡邉
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NEC Corp
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NEC Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a wiring board, capable of high-density mounting without increasing the thickness of a wiring board. <P>SOLUTION: This semiconductor device 10 includes this wiring board 20, and an electronic component 30 mounted on the wiring board 20. The wiring board 20 includes a wiring pattern 21, an insulation layer 22, and auxiliary pads 23. The wiring pattern 21 includes wires 24 and mounting pads 25 each having a diameter larger than the width of the wire 24. The insulation layer 22 covers the surface of the wiring pattern 21. The auxiliary pad 23 has a diameter larger than that of the mounting pad 25, and is arranged on the insulation layer 22 corresponding to the mounting pad 25. The electronic component 30 includes electrodes 31 each connected to the auxiliary pad 23 or the auxiliary pad 23 and the mounting pad 25 through a conductive member 40. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置及び配線基板に関し、更に詳しくは、電子部品が導電部材を介して配線基板に実装される構造を有する半導体装置及び配線基板に関する。   The present invention relates to a semiconductor device and a wiring board, and more particularly to a semiconductor device and a wiring board having a structure in which an electronic component is mounted on the wiring board via a conductive member.

近年、携帯電話やノートPC等に代表される電子機器では、小型化、薄型化、及び高機能化が進められている。このため、電子部品を組み合わせたモジュール部品には、更なる高密度実装が求められており、例えば、電子部品ではピン数の増加や電極間の狭ピッチ化が進んでいる。   In recent years, electronic devices typified by mobile phones and notebook PCs have been reduced in size, thickness, and functionality. For this reason, module components combined with electronic components are required to have higher density mounting. For example, in electronic components, the number of pins is increased and the pitch between electrodes is being reduced.

高密度実装に好適に用いられている電子部品としては、例えば、ケース下面に電極が格子状に配列されたBGA(ball grid array)やCSP(chip size package)等を有するものが知られている。これらの電子部品は、例えば、ケースの側面に配置されたリードフレームを電極とするQFP(quad flat package)やSOP(small outline package)を有する電子部品に比べて、配線基板に実装する際の実装面積が小さくて済む。   As electronic parts that are suitably used for high-density mounting, for example, those having a BGA (ball grid array) or CSP (chip size package) in which electrodes are arranged in a grid on the lower surface of the case are known. . These electronic components are mounted when mounted on a wiring board, for example, compared to electronic components having QFP (quad flat package) or SOP (small outline package) using lead frames arranged on the side surfaces of the case as electrodes. The area is small.

特許文献1〜3には、このような高密度実装に好適な電子部品を、半田等の導電部材を介して実装する各種配線基板が記載されている。   Patent Documents 1 to 3 describe various wiring boards on which electronic components suitable for such high-density mounting are mounted via conductive members such as solder.

特許文献1には、下面に複数の電極が形成された電子部品と、この電子部品が実装される配線基板とを有する半導体装置が記載されている。配線基板は、表層面(基板表面)に配線が形成されたコア基板と、コア基板の上下両面に交互に積層された絶縁層及び導体回路層を含むビルドアップ層と、電子部品の複数の電極にそれぞれ接触する半田バンプ部(導電部材)とを有する。半田バンプ部の周囲には、バリア層が配置されている。バリア層は、絶縁層上に形成された応力緩和層の開口内に形成され、また、下面が上記導体回路層に接触している。   Patent Document 1 describes a semiconductor device having an electronic component having a plurality of electrodes formed on the lower surface and a wiring board on which the electronic component is mounted. The wiring board includes a core substrate having wiring formed on a surface layer (substrate surface), a buildup layer including insulating layers and conductor circuit layers alternately stacked on both upper and lower surfaces of the core substrate, and a plurality of electrodes of an electronic component And a solder bump part (conductive member) that contacts each of them. A barrier layer is disposed around the solder bump portion. The barrier layer is formed in the opening of the stress relaxation layer formed on the insulating layer, and the lower surface is in contact with the conductor circuit layer.

特許文献2には、表層面に形成された実装用パッドと、実装用パッドに対応して形成される開口を有し実装用パッドの表面を覆う絶縁層と、実装用パッド及び絶縁層上に設けられた第1及び第2の下地用金属層と、第2の下地用金属層上に形成されたバンプとを有する配線基板が記載されている。   In Patent Document 2, a mounting pad formed on a surface layer, an insulating layer having an opening formed corresponding to the mounting pad and covering the surface of the mounting pad, and the mounting pad and the insulating layer are provided. A wiring board having first and second base metal layers provided and bumps formed on the second base metal layer is described.

特許文献3には、表層面に形成された配線及び実装用パッドと、実装用パッドに対応して形成される開口を有し配線及び実装用パッドを覆う絶縁層と、開口内に形成された導電部材を介して実装用パッドと接続される補助パッドとを有する配線基板が記載されている。   In Patent Document 3, wirings and mounting pads formed on the surface layer, an insulating layer having openings formed corresponding to the mounting pads and covering the wirings and mounting pads, and formed in the openings A wiring board having an auxiliary pad connected to a mounting pad through a conductive member is described.

特開2006−066597号公報JP 2006-066597 A 特開2004−228295号公報JP 2004-228295 A 特開2007−184381号公報JP 2007-184381 A

上記電子部品でのピン数の増加や電極間の狭ピッチ化に伴い、配線基板上の隣り合う実装用パッドの間隔(ピッチ)は狭くなってきている。このため、配線基板の表層面に実装用パッドと干渉することなく、配線を引き回すことが困難となっている。   As the number of pins in the electronic component increases and the pitch between electrodes decreases, the spacing (pitch) between adjacent mounting pads on the wiring board has become narrower. For this reason, it is difficult to route the wiring on the surface layer surface of the wiring board without interfering with the mounting pads.

そこで、特許文献1では、コア基板の配線とビルドアップ層の導体回路層とをビアを介して電気的に接続し、高密度実装を図っている。しかし、この配線基板では、配線基板の内層で配線を引き回しているために層数が増え、更に、絶縁層上に応力緩和層が形成されているので、厚みが更に増すことになる。このため、配線基板と電子部品とを備えた半導体装置も厚くなってしまう。   Therefore, in Patent Document 1, the wiring of the core substrate and the conductor circuit layer of the build-up layer are electrically connected through vias to achieve high-density mounting. However, in this wiring board, the number of layers is increased because the wiring is routed in the inner layer of the wiring board, and the thickness is further increased because the stress relaxation layer is formed on the insulating layer. For this reason, the semiconductor device provided with the wiring board and the electronic component also becomes thick.

特許文献2では、腐食によるバンプの剥離を防止するために、第1及び第2の下地用金属層を実装用パッド及び絶縁層上に形成しているが、金属層を多層にしているので、配線基板が厚くなってしまう。   In Patent Document 2, the first and second base metal layers are formed on the mounting pad and the insulating layer in order to prevent the peeling of the bumps due to corrosion. The wiring board becomes thick.

さらに、特許文献3では、配線基板の表層面で配線を引き回すためには、実装用パッド間のピッチが狭くなるに伴い、配線の幅を小さくする必要があり、歩留まりの低下やコストの増加という問題が生じる。また、導電部材と補助パッドとは別々の部材と考えられ、更に、補助パッドが導電部材の上に形成されているので、製造プロセスが増えてしまう。   Further, in Patent Document 3, in order to route the wiring on the surface layer of the wiring board, it is necessary to reduce the width of the wiring as the pitch between the mounting pads becomes narrow, which means that the yield is reduced and the cost is increased. Problems arise. Further, the conductive member and the auxiliary pad are considered to be separate members, and further, the auxiliary pad is formed on the conductive member, so that the manufacturing process increases.

本発明は、配線基板の厚みを増すことなく、高密度実装が可能な半導体装置及び配線基板を提供することを目的とする。   An object of the present invention is to provide a semiconductor device and a wiring board that can be mounted at high density without increasing the thickness of the wiring board.

上記目的を達成するために、本発明は、配線と該配線の幅よりも大きな径を有する実装パッドとを含む配線パターンと、前記配線パターンの表面を覆う絶縁層と、前記実装パッドよりも大きな径を有し前記実装パッドに対応して前記絶縁層上に配設される補助パッドとを有する配線基板と、
前記補助パッド、又は、前記補助パッド及び実装パッドに導電部材を介して接続された電極を有し、前記配線基板上に実装された電子部品と、を備える半導体装置を提供する。
In order to achieve the above object, the present invention provides a wiring pattern including a wiring and a mounting pad having a diameter larger than the width of the wiring, an insulating layer covering the surface of the wiring pattern, and larger than the mounting pad. A wiring board having a diameter and an auxiliary pad disposed on the insulating layer corresponding to the mounting pad;
There is provided a semiconductor device comprising: the auxiliary pad, or an electronic component having an electrode connected to the auxiliary pad and the mounting pad through a conductive member and mounted on the wiring board.

また、本発明は、配線と該配線の幅よりも大きな径を有する実装パッドとを含む配線パターンと、前記実装パッドに対応して形成される第1の開口を有し前記配線パターンの表面を覆う絶縁層と、前記実装パッドよりも大きな径を有し前記実装パッドに対応して前記絶縁層上に配設される補助パッドとを有し、
前記補助パッドが、前記第1の開口を介して前記実装パッドに接続されている配線基板を提供する。
According to another aspect of the present invention, there is provided a wiring pattern including a wiring and a mounting pad having a diameter larger than the width of the wiring, and a first opening formed corresponding to the mounting pad. An insulating layer for covering, and an auxiliary pad having a diameter larger than that of the mounting pad and disposed on the insulating layer corresponding to the mounting pad;
Provided is a wiring substrate in which the auxiliary pad is connected to the mounting pad through the first opening.

さらに、本発明は、配線と該配線の幅よりも大きな径を有する実装パッドとを含む配線パターンと、前記実装パッドに対応して形成される第1の開口を有し前記配線パターンの表面を覆う絶縁層と、前記実装パッドよりも大きな径を有し前記実装パッドに対応して前記絶縁層上に配設される補助パッドとを有し、
前記補助パッドが、前記第1の開口の上部に第2の開口を有する配線基板を提供する。
Furthermore, the present invention includes a wiring pattern including a wiring and a mounting pad having a diameter larger than the width of the wiring, and a first opening formed corresponding to the mounting pad. An insulating layer for covering, and an auxiliary pad having a diameter larger than that of the mounting pad and disposed on the insulating layer corresponding to the mounting pad;
The auxiliary pad provides a wiring board having a second opening above the first opening.

本発明の半導体装置及び配線基板では、配線基板の厚みを増すことなく、高密度実装が可能となる。   In the semiconductor device and the wiring board of the present invention, high-density mounting is possible without increasing the thickness of the wiring board.

本発明の第1の実施形態に係る半導体装置の構成を示す断面図。1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. 図1に示す半導体装置の変形例の構成を示す断面図。Sectional drawing which shows the structure of the modification of the semiconductor device shown in FIG. (a)及び(b)は、比較例である半導体装置の構成を示す断面図。(A) And (b) is sectional drawing which shows the structure of the semiconductor device which is a comparative example. (a)及び(b)は、本発明の第2の実施形態に係る半導体装置の構成を示す断面図。(A) And (b) is sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. 図4(a)に示す半導体装置の変形例の構成を示す断面図。Sectional drawing which shows the structure of the modification of the semiconductor device shown to Fig.4 (a).

本発明の半導体装置は、最小基本構成として、配線基板と、配線基板上に実装された電子部品とを備える。配線基板は、配線パターンと、絶縁層と、補助パッドとを有する。配線パターンは、配線とこの配線の幅よりも大きな径を有する実装パッドとを含む。絶縁層は、配線パターンの表面を覆う。補助パッドは、実装パッドよりも大きな径を有し、実装パッドに対応して絶縁層上に配設される。電子部品は、補助パッド、又は、補助パッド及び実装パッドに導電部材を介して接続された電極を有する。   The semiconductor device of the present invention includes a wiring board and an electronic component mounted on the wiring board as a minimum basic configuration. The wiring board has a wiring pattern, an insulating layer, and an auxiliary pad. The wiring pattern includes a wiring and a mounting pad having a diameter larger than the width of the wiring. The insulating layer covers the surface of the wiring pattern. The auxiliary pad has a larger diameter than the mounting pad, and is disposed on the insulating layer corresponding to the mounting pad. The electronic component has an auxiliary pad or an electrode connected to the auxiliary pad and the mounting pad via a conductive member.

上記半導体装置では、実装パッドよりも大きな径を有する補助パッドを絶縁層上に配設したので、配線基板上に電子部品が実装される際に、導電部材が補助パッド、又は、補助パッド及び実装パッドに接続される。このため、配線基板の表層面に形成された実装パッドの径を小さくできるので、表層面で隣り合う実装パッドの間隔が大きくなる。その結果、配線基板の層数を増やして配線基板の内層で配線を引き回す必要がなく、配線基板の表層面で配線を引き回すことができる。従って、配線基板の厚みを増すことなく、高密度実装が可能となる。また、配線基板の層数が小さくなるので、配線基板を含めた半導体装置の薄型化を図ることができる。   In the semiconductor device, since the auxiliary pad having a larger diameter than the mounting pad is disposed on the insulating layer, when the electronic component is mounted on the wiring board, the conductive member is the auxiliary pad or the auxiliary pad and the mounting. Connected to the pad. For this reason, since the diameter of the mounting pad formed on the surface layer surface of the wiring board can be reduced, the interval between the mounting pads adjacent on the surface layer surface is increased. As a result, it is not necessary to increase the number of layers of the wiring substrate and route the wiring in the inner layer of the wiring substrate, and the wiring can be routed on the surface layer surface of the wiring substrate. Therefore, high-density mounting is possible without increasing the thickness of the wiring board. In addition, since the number of layers of the wiring board is reduced, the semiconductor device including the wiring board can be thinned.

以下、図面を参照し、本発明の例示的な実施の形態について詳細に説明する。
(第1の実施形態)
図1は、本発明の第1の実施形態に係る半導体装置の構成を示す断面図である。半導体装置10は、配線基板20と電子部品30とを備え、電子部品30が導電部材40を介して配線基板20上に実装された構造を有する。配線基板20は、配線パターン21と、絶縁層(絶縁部材)22と、補助パッド23とを有する。配線パターン21は、配線24と、この配線24の幅よりも大きな径を有する実装用パッド25とを含む。
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the first embodiment of the present invention. The semiconductor device 10 includes a wiring board 20 and an electronic component 30, and has a structure in which the electronic component 30 is mounted on the wiring board 20 via a conductive member 40. The wiring board 20 includes a wiring pattern 21, an insulating layer (insulating member) 22, and an auxiliary pad 23. The wiring pattern 21 includes a wiring 24 and a mounting pad 25 having a diameter larger than the width of the wiring 24.

絶縁層22は、実装用パッド25に対応して形成される第1の開口26を有し、配線パターン21の表面を覆う。絶縁層22は、例えば、ソルダーレジストで形成されている。絶縁層22をソルダーレジストで形成することで、配線24及び実装用パッド25を含む配線パターン21を形成するために必要なソルダーレジストを、そのまま流用することができるので、製造プロセスを簡素化できる。なお、絶縁層22は、ソルダーレジストに限定されるものではない。   The insulating layer 22 has a first opening 26 formed corresponding to the mounting pad 25 and covers the surface of the wiring pattern 21. The insulating layer 22 is made of, for example, a solder resist. By forming the insulating layer 22 with a solder resist, the solder resist necessary for forming the wiring pattern 21 including the wiring 24 and the mounting pad 25 can be used as it is, so that the manufacturing process can be simplified. The insulating layer 22 is not limited to a solder resist.

補助パッド23は、実装用パッド25よりも大きな径を有し、実装用パッド25に対応して絶縁層22上に配設されると共に、絶縁層22の第1の開口26を介して実装用パッド25に直接接続されている。補助パッド23の材質としては、導電性ペースト、導電性樹脂、導電性接着剤、Cu等の金属が挙げられるが、導電部材40に濡れ性を有するのであれば、適宜の材質を用いることができる。補助パッド23の材質を、導電性ペースト、導電性接着剤で構成すると、印刷工法、ディスペンス塗布等の既存の工法を用いて、絶縁層22上及び第1の開口26内に塗布することで、補助パッド23を形成できる。   The auxiliary pad 23 has a diameter larger than that of the mounting pad 25, is disposed on the insulating layer 22 corresponding to the mounting pad 25, and is mounted through the first opening 26 of the insulating layer 22. It is directly connected to the pad 25. Examples of the material of the auxiliary pad 23 include a conductive paste, a conductive resin, a conductive adhesive, and a metal such as Cu, but any material can be used as long as the conductive member 40 has wettability. . When the material of the auxiliary pad 23 is composed of a conductive paste or a conductive adhesive, it is applied on the insulating layer 22 and in the first opening 26 using an existing method such as a printing method or a dispensing method. The auxiliary pad 23 can be formed.

また、補助パッド23が、導電部材40に濡れ性を有する構成とすれば、導電部材40が補助パッド23から絶縁層22上に流出することを回避できる。なお、補助パッド23の材質が、導電部材40に濡れ性を有していない場合には、導電部材40に濡れ性を得るように、補助パッド23の表面にAuめっき等の処理を施してもよい。   Further, if the auxiliary pad 23 has a wettability with respect to the conductive member 40, the conductive member 40 can be prevented from flowing out from the auxiliary pad 23 onto the insulating layer 22. When the material of the auxiliary pad 23 does not have wettability to the conductive member 40, the surface of the auxiliary pad 23 may be subjected to treatment such as Au plating so as to obtain wettability to the conductive member 40. Good.

電子部品30は、BGAやCSP等であり、下面に複数配置された電極31を有する。電極31は、導電部材40を介して補助パッド23に電気的に接続されている。導電部材40は、例えば半田や導電性樹脂で形成されている。ここでの導電部材40は、電極31に予め接合された半田ボールである。半田材料としては、Sn−Pb系、Sn−Ag−Cu系、Sn−Ag系、Sn−Cu系、Sn−Sb系、Sn−Zn系、Sn−In系等が挙げられるが、これに限定されない。なお、図1は、実装用パッド25のセンターを含む断面を示しており、上記補助パッド23及び実装用パッド25の位置は、図示のように、電極31の位置に対応している。   The electronic component 30 is a BGA, a CSP, or the like, and has a plurality of electrodes 31 arranged on the lower surface. The electrode 31 is electrically connected to the auxiliary pad 23 via the conductive member 40. The conductive member 40 is made of, for example, solder or conductive resin. Here, the conductive member 40 is a solder ball bonded in advance to the electrode 31. Examples of the solder material include Sn—Pb, Sn—Ag—Cu, Sn—Ag, Sn—Cu, Sn—Sb, Sn—Zn, Sn—In, and the like. Not. 1 shows a cross section including the center of the mounting pad 25, and the positions of the auxiliary pad 23 and the mounting pad 25 correspond to the positions of the electrodes 31, as shown.

次に、半導体装置の製造方法について説明する。まず、配線基板20上に、配線24及び実装用パッド25を含む配線パターン21を形成し、その後に、配線24及び実装用パッド25を覆うように絶縁層22を形成する。次に、露光・現像を行い、実装用パッド25上の絶縁層22に第1の開口26を形成する。   Next, a method for manufacturing a semiconductor device will be described. First, the wiring pattern 21 including the wiring 24 and the mounting pad 25 is formed on the wiring substrate 20, and then the insulating layer 22 is formed so as to cover the wiring 24 and the mounting pad 25. Next, exposure and development are performed to form a first opening 26 in the insulating layer 22 on the mounting pad 25.

続いて、第1の開口26、及び第1の開口26の周囲の絶縁層22上に、補助パッド23を印刷工法で形成する。次いで、電子部品30の電極31に接合されている導電部材40と、実装用パッド25のセンターとを一致させた状態で、配線基板20上に電子部品30を搭載する。その後、リフロー工法等で熱を加えて導電部材40を溶融させて、配線基板20上に電子部品30が実装される。   Subsequently, the auxiliary pad 23 is formed on the first opening 26 and the insulating layer 22 around the first opening 26 by a printing method. Next, the electronic component 30 is mounted on the wiring board 20 in a state where the conductive member 40 bonded to the electrode 31 of the electronic component 30 is aligned with the center of the mounting pad 25. Thereafter, heat is applied by a reflow method or the like to melt the conductive member 40, and the electronic component 30 is mounted on the wiring board 20.

以上の工程を経て、図1に示す半導体装置10を製造できる。なお、本実施形態では、導電部材40を半田ボールとし、絶縁層22をソルダーレジストで形成し、更に、導電部材40の周辺にはアンダーフィルを充填していない構造を有している。しかし、配線基板20上の実装用パッド25に導電部材40を介して電子部品30を実装している構造であれば、特に限定されない。   Through the above steps, the semiconductor device 10 shown in FIG. 1 can be manufactured. In this embodiment, the conductive member 40 is a solder ball, the insulating layer 22 is formed of a solder resist, and the conductive member 40 is not filled with an underfill. However, there is no particular limitation as long as the electronic component 30 is mounted on the mounting pad 25 on the wiring board 20 via the conductive member 40.

次に、配線基板20での配線24の引き回しについて説明する。半導体装置10は、上記したように、電子部品30の電極31と配線基板20上の実装用パッド25が導電部材40を介して実装された構造を有している。この構造では、実装用パッド25から、他の電子部品30等との電気的接続を得るために、配線基板20の実装用パッド25と干渉せず、配線24を引き回す必要がある。   Next, routing of the wiring 24 on the wiring board 20 will be described. As described above, the semiconductor device 10 has a structure in which the electrode 31 of the electronic component 30 and the mounting pad 25 on the wiring board 20 are mounted via the conductive member 40. In this structure, it is necessary to route the wiring 24 without interfering with the mounting pad 25 of the wiring board 20 in order to obtain an electrical connection from the mounting pad 25 to another electronic component 30 or the like.

そこで、本実施形態では、実装用パッド25よりも大きな径を有し、実装用パッド25に第1の開口26を介して接続された補助パッド23を、絶縁層22上に配設した。このため、配線基板20上に電子部品30が実装された状態で、導電部材40が補助パッド23を介して実装用パッド25に電気的に接続される。つまり、導電部材40は、補助パッド23に直接接続され、且つ、実装用パッド25に間接的に接続される。このため、配線基板20の表層面に形成された実装用パッド25の径を小さくできる。   Therefore, in the present embodiment, the auxiliary pad 23 having a larger diameter than the mounting pad 25 and connected to the mounting pad 25 via the first opening 26 is disposed on the insulating layer 22. Therefore, the conductive member 40 is electrically connected to the mounting pad 25 via the auxiliary pad 23 in a state where the electronic component 30 is mounted on the wiring board 20. That is, the conductive member 40 is directly connected to the auxiliary pad 23 and indirectly connected to the mounting pad 25. For this reason, the diameter of the mounting pad 25 formed on the surface of the wiring board 20 can be reduced.

実装用パッド25の径を小さくすることで、表層面で隣り合う実装用パッド25の間隔が大きくなり、その結果、配線基板20の表層面に形成された配線24を、配線基板20の表層面で引き回すことができる。従って、本実施形態では、配線基板20の厚みを増すことなく、高密度実装が可能となる。また、配線基板20の層数が少なくて済むので、配線基板20を含めた半導体装置10の薄型化を図ることもできる。   By reducing the diameter of the mounting pad 25, the interval between the mounting pads 25 adjacent on the surface layer surface is increased, and as a result, the wiring 24 formed on the surface layer surface of the wiring substrate 20 is replaced with the surface layer surface of the wiring substrate 20. Can be routed with. Therefore, in this embodiment, high-density mounting is possible without increasing the thickness of the wiring board 20. Further, since the number of layers of the wiring board 20 can be reduced, the semiconductor device 10 including the wiring board 20 can be thinned.

次に、図2及び図3を参照して、電極のピッチが0.3mmのCSPである電子部品を配線基板上に実装した場合での、配線基板での配線の引き回しについて説明する。図2は、図1に示す半導体装置10の変形例の構成を示す断面図である。図3(a)及び(b)は、比較例である半導体装置の構成を示す断面図である。まず、図3を参照して比較例について説明する。   Next, with reference to FIG. 2 and FIG. 3, a description will be given of the routing of wiring on the wiring board when an electronic component that is a CSP having electrode pitches of 0.3 mm is mounted on the wiring board. FIG. 2 is a cross-sectional view showing a configuration of a modified example of the semiconductor device 10 shown in FIG. 3A and 3B are cross-sectional views illustrating a configuration of a semiconductor device as a comparative example. First, a comparative example will be described with reference to FIG.

図3(a)に示すように、ピッチ0.3mmのCSPである電子部品130では、電極131の径が約200μm(図中、A’)となる。半導体装置100は、第1の開口115を有する絶縁層114が、配線基板110の表層面に形成された実装用パッド112を覆っており、電子部品130の電極131が導電部材120を介して実装用パッド112に電気的に接続されている。   As shown in FIG. 3A, in the electronic component 130 which is a CSP having a pitch of 0.3 mm, the diameter of the electrode 131 is about 200 μm (A ′ in the figure). In the semiconductor device 100, the insulating layer 114 having the first opening 115 covers the mounting pad 112 formed on the surface layer surface of the wiring substrate 110, and the electrode 131 of the electronic component 130 is mounted via the conductive member 120. It is electrically connected to the pad 112 for use.

半導体装置100では、図示のように、配線基板110上の実装用パッド112の径も、電極131の径と同じ約200μm(図中、A’)である。このため、実装用パッド112が存在しない箇所、即ち、隣り合う実装用パッド112の間隔(図中、B’)は、約100μmとなる。このような狭い間隔では、配線基板110の表層面で、実装用パッド112と干渉せずに、配線111を引き回すことは困難となる。   In the semiconductor device 100, as shown in the figure, the diameter of the mounting pad 112 on the wiring substrate 110 is also about 200 μm (A ′ in the figure), which is the same as the diameter of the electrode 131. For this reason, the location where the mounting pads 112 do not exist, that is, the interval (B ′ in the figure) between the adjacent mounting pads 112 is about 100 μm. With such a narrow interval, it is difficult to route the wiring 111 without interfering with the mounting pads 112 on the surface layer surface of the wiring substrate 110.

そのために、半導体装置100では、配線111が、ビア113を介して実装用パッド112と電気的に接続され、配線基板110の内層で引き回された構造となる。この構造では、配線111が増える毎に配線基板110の層数が増加し、配線基板110自体が厚くなってしまう。   Therefore, the semiconductor device 100 has a structure in which the wiring 111 is electrically connected to the mounting pad 112 through the via 113 and is routed in the inner layer of the wiring substrate 110. In this structure, the number of layers of the wiring board 110 increases each time the wiring 111 increases, and the wiring board 110 itself becomes thick.

従って、比較例の半導体装置100では、高密度実装を図る際に、配線基板110が厚くなり、半導体装置100自体も厚みが増してしまう。   Therefore, in the semiconductor device 100 of the comparative example, when the high-density mounting is achieved, the wiring board 110 becomes thick, and the semiconductor device 100 itself increases in thickness.

続いて、図3(b)に示す比較例である半導体100Aは、実装用パッド112Aの径を小さくすることで、隣り合う実装用パッド112Aの間隔が狭くならない構造を採用したものである。半導体装置100Aでは、配線基板110Aの表層面に配線111Aと径の小さな実装用パッド112Aとを含む配線パターンが形成されている。また、第1の開口115Aを有する絶縁層114Aが、配線111A及び実装用パッド112Aを覆っている。   Subsequently, the semiconductor 100A as a comparative example shown in FIG. 3B employs a structure in which the distance between the adjacent mounting pads 112A is not reduced by reducing the diameter of the mounting pads 112A. In the semiconductor device 100A, a wiring pattern including the wiring 111A and a mounting pad 112A having a small diameter is formed on the surface of the wiring substrate 110A. An insulating layer 114A having a first opening 115A covers the wiring 111A and the mounting pad 112A.

ところが、半導体装置100Aでは、半田ボールである導電部材120Aを介して配線基板110A上に電子部品130を実装すると、実装用パッド112Aの径が小さいために、実装用パッド112Aに対して半田ボールが大き過ぎることになる。その結果、半導体装置100Aでは、半田ボールの溶融時に、図示のように、隣り合う半田ボールとショートし、更に、実装用パッド112Aと導電部材120Aとの接続強度が小さくなるので、信頼性が低下してしまう。   However, in the semiconductor device 100A, when the electronic component 130 is mounted on the wiring board 110A via the conductive member 120A, which is a solder ball, the solder ball is mounted on the mounting pad 112A because the diameter of the mounting pad 112A is small. It will be too big. As a result, in the semiconductor device 100A, when the solder ball is melted, as shown in the figure, the adjacent solder ball is short-circuited, and the connection strength between the mounting pad 112A and the conductive member 120A is reduced, so that the reliability is lowered. Resulting in.

これに対して、図2に示す本実施形態の半導体装置10Aでは、導電部材40Aが補助パッド23Aを介して実装用パッド25に接続されている。即ち、導電部材40Aが補助パッド23Aに直接接続され、且つ、実装用パッド25に間接的に接続されている。従って、電子部品30の電極31の径が上記同様に約200μmであっても、補助パッド23Aの外周径を約200μmとすることで、実装用パッド25の径を、例えば約100μm(図中、A)程度に小さくできる。   On the other hand, in the semiconductor device 10A of the present embodiment shown in FIG. 2, the conductive member 40A is connected to the mounting pad 25 via the auxiliary pad 23A. That is, the conductive member 40A is directly connected to the auxiliary pad 23A and indirectly connected to the mounting pad 25. Therefore, even if the diameter of the electrode 31 of the electronic component 30 is about 200 μm as described above, the diameter of the mounting pad 25 is set to about 100 μm (in the drawing, for example) by setting the outer peripheral diameter of the auxiliary pad 23A to about 200 μm. A) It can be made as small as possible.

実装用パッド25の径を小さくしたので、隣り合う実装用パッド25の間隔は、ソルダーレジストで形成された絶縁層22Aを介した補助パッド23Aの直下も含めて、約200μm(図中、B)となる。つまり、配線基板20Aでは、隣り合う実装用パッド25の間に、配線を引き回すための十分な間隔を確保できるので、表層面で配線を引き回すことが可能となり、配線基板20Aの層数を増やすことなく、高密度実装を図ることができる。このため、半導体装置10Aでは、薄型化が可能となる。   Since the diameter of the mounting pad 25 is reduced, the interval between the adjacent mounting pads 25 is about 200 μm (B in the figure) including directly under the auxiliary pad 23A via the insulating layer 22A formed of solder resist. It becomes. That is, in the wiring board 20A, a sufficient space for routing the wiring can be secured between the adjacent mounting pads 25, so that the wiring can be routed on the surface layer, and the number of layers of the wiring board 20A is increased. Therefore, high-density mounting can be achieved. For this reason, the semiconductor device 10A can be thinned.

一例として、配線の幅とスペース(L/s)を、40μm/40μmとすれば、隣り合う実装用パッド25の間で、且つ、絶縁層22A上に形成された補助パッド23Aの直下に、図示のように、複数(ここでは、2本)の配線24a,24bを引き回すことができる。つまり、配線基板20Aの表層面には、実装用パッド25と配線24a,24bとを含む配線パターン21Aが形成されている。   As an example, if the width and space (L / s) of the wiring is 40 μm / 40 μm, it is illustrated between the adjacent mounting pads 25 and immediately below the auxiliary pad 23A formed on the insulating layer 22A. As described above, a plurality of (in this case, two) wirings 24a and 24b can be routed. That is, the wiring pattern 21A including the mounting pad 25 and the wirings 24a and 24b is formed on the surface layer surface of the wiring board 20A.

このように、本実施形態の半導体装置10Aでは、絶縁層22A上に導電部材40Aと接続された補助パッド23Aを設けることで、補助パッド23Aの直下等、配線基板20Aの表層面に配線を引き回せる箇所が増える。そのため、配線基板20Aの層数を増やすことなく、高密度実装が可能となり、また、薄型化も図ることができる。   Thus, in the semiconductor device 10A of the present embodiment, by providing the auxiliary pad 23A connected to the conductive member 40A on the insulating layer 22A, the wiring is drawn on the surface layer surface of the wiring board 20A such as immediately below the auxiliary pad 23A. More points can be turned. Therefore, high-density mounting is possible without increasing the number of layers of the wiring board 20A, and the thickness can be reduced.

なお、本実施形態では、電子部品30の電極31のピッチを0.3mmとしたが、これに限定されず、他のピッチサイズであっても上記同様の効果を得ることができる。さらに、電子部品30の大きさ、形状についても、同様の効果が得られるので、特に限定されない。   In the present embodiment, the pitch of the electrodes 31 of the electronic component 30 is 0.3 mm. However, the present invention is not limited to this, and the same effect as described above can be obtained even with other pitch sizes. Further, the size and shape of the electronic component 30 are not particularly limited because the same effect can be obtained.

(第2の実施形態)
図4は、本発明の第2の実施形態に係る半導体装置の構成を示す断面図である。図4(a)に示す半導体装置10Bは、補助パッド23Bが第2の開口27を有している点で、図1に示した上記半導体装置10と異なる。
(Second Embodiment)
FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention. The semiconductor device 10B shown in FIG. 4A is different from the semiconductor device 10 shown in FIG. 1 in that the auxiliary pad 23B has the second opening 27.

半導体装置10Bでは、補助パッド23Bが第2の開口27を有していることで、電極31が、第1の開口26及び第2の開口27内に形成された導電部材40Bを介して、配線基板20Bの表層面の実装用パッド25に接続されている。このため、導電部材40Bが、補助パッド23Bだけでなく、実装用パッド25とも直接接続されるので、電気的信頼性が向上する。   In the semiconductor device 10B, since the auxiliary pad 23B has the second opening 27, the electrode 31 is wired via the first opening 26 and the conductive member 40B formed in the second opening 27. It is connected to a mounting pad 25 on the surface of the substrate 20B. For this reason, since the conductive member 40B is directly connected not only to the auxiliary pad 23B but also to the mounting pad 25, the electrical reliability is improved.

さらに、半導体装置10Bでは、導電部材40Bが、補助パッド23Bの第2の開口27、及び絶縁層22の第1の開口26内に形成され、且つ、補助パッド23Bが絶縁層22の第1の開口26の周りに形成されている。このため、導電部材40Bが絶縁層22上を流れて、隣り合う実装用パッド25とショートすることを防止できる。さらに、補助パッド23Bは、第2の開口27が形成されているので、上記半導体装置10の補助パッド23に比べて面積が小さく、材料の使用量が少なくて済み、低コスト化を図ることができる。   Further, in the semiconductor device 10B, the conductive member 40B is formed in the second opening 27 of the auxiliary pad 23B and the first opening 26 of the insulating layer 22, and the auxiliary pad 23B is the first opening of the insulating layer 22. It is formed around the opening 26. Therefore, it is possible to prevent the conductive member 40B from flowing on the insulating layer 22 and short-circuiting with the adjacent mounting pad 25. Further, since the auxiliary pad 23B is formed with the second opening 27, the auxiliary pad 23B has a smaller area than the auxiliary pad 23 of the semiconductor device 10 and uses less material, thereby reducing the cost. it can.

図4(b)に示す半導体装置10Cは、補助パッド23Cを形成する材質が、例えば、絶縁層22の第1の開口26及び補助パッド23Cの第2の開口27の壁面28に塗布されている点で、図4(a)に示す半導体装置10Bと異なる。この構造は、一例として、印刷工程やディスペンス工程で補助パッド23Cを形成する際に、位置ずれが生じ、塗布箇所が多少ずれた場合に得られる。   In the semiconductor device 10C shown in FIG. 4B, the material forming the auxiliary pad 23C is applied to, for example, the wall surfaces 28 of the first opening 26 of the insulating layer 22 and the second opening 27 of the auxiliary pad 23C. This is different from the semiconductor device 10B shown in FIG. As an example, this structure is obtained when the auxiliary pad 23C is formed in the printing process or the dispensing process, and a positional shift occurs and the application location is slightly shifted.

このような半導体装置10Cにおいても、電子部品30の電極31と配線基板20C上の実装用パッド25が導電部材40Cを介して実装された構造を有しているので、半導体装置10Bと同様の効果を得ることができる。   Such a semiconductor device 10C also has a structure in which the electrode 31 of the electronic component 30 and the mounting pad 25 on the wiring board 20C are mounted via the conductive member 40C. Therefore, the same effect as the semiconductor device 10B is obtained. Can be obtained.

図5は、図4(a)に示す半導体装置10Bの変形例の構成を示す断面図である。半導体装置10Dは、隣り合う実装用パッド25の間で、且つ、絶縁層22A上に形成された補助パッド23Dの直下に、図示のように、複数(ここでは、2本)の配線24a,24bを配線基板20Dの表層面で引き回している点で、上記半導体装置10Bと異なる。また、図5に示す配線24a,24bは、図4(a)に示した配線24と比べて、幅を小さくしている。なお、半導体装置10Dにおいても、電子部品30の電極31と配線基板20D上の実装用パッド25が導電部材40Dを介して実装された構造を有している。   FIG. 5 is a cross-sectional view showing a configuration of a modified example of the semiconductor device 10B shown in FIG. The semiconductor device 10D includes a plurality of (here, two) wirings 24a and 24b between adjacent mounting pads 25 and immediately below the auxiliary pad 23D formed on the insulating layer 22A as shown in the figure. Is different from the semiconductor device 10B in that it is routed on the surface of the wiring board 20D. Further, the wirings 24a and 24b shown in FIG. 5 have a smaller width than the wiring 24 shown in FIG. Note that the semiconductor device 10D also has a structure in which the electrode 31 of the electronic component 30 and the mounting pad 25 on the wiring board 20D are mounted via the conductive member 40D.

このため、半導体装置10Dでは、隣り合う実装用パッド25の間で、複数の配線24a,24bを十分に引き回すことができる。従って、配線基板20Dの層数を増やさずに、更なる高密度実装が可能となる。   For this reason, in the semiconductor device 10 </ b> D, the plurality of wirings 24 a and 24 b can be sufficiently routed between the adjacent mounting pads 25. Therefore, further high-density mounting is possible without increasing the number of layers of the wiring board 20D.

なお、上記した各実装用パッド及び補助パッドの平面形状は、正方形、長方形その他、種々の形状を採用できる。   In addition, the planar shape of each mounting pad and auxiliary pad described above can adopt a square, a rectangle, and other various shapes.

以上、本発明をその好適な実施形態に基づいて説明したが、本発明の半導体装置及び配線基板は、上記実施形態の構成にのみ限定されるものではなく、上記実施形態の構成から種々の修正及び変更を施したものも、本発明の範囲に含まれる。   As described above, the present invention has been described based on the preferred embodiments. However, the semiconductor device and the wiring board according to the present invention are not limited to the configurations of the above embodiments, and various modifications can be made from the configurations of the above embodiments. Further, modifications and changes are also included in the scope of the present invention.

10,10A〜10D:半導体装置
20,20A〜20D:配線基板
21,21A:配線パターン
22,22A:絶縁層
23,23A〜23D:補助パッド
24,24a,24b:配線
25:実装用パッド
26:第1の開口
27:第2の開口
28:壁面
30:電子部品
31:電極
40,40A〜40D:導電部材
10, 10A to 10D: Semiconductor devices 20, 20A to 20D: Wiring substrates 21, 21A: Wiring patterns 22, 22A: Insulating layers 23, 23A to 23D: Auxiliary pads 24, 24a, 24b: Wiring 25: Mounting pads 26: 1st opening 27: 2nd opening 28: Wall surface 30: Electronic component 31: Electrode 40, 40A-40D: Conductive member

Claims (8)

配線と該配線の幅よりも大きな径を有する実装パッドとを含む配線パターンと、前記配線パターンの表面を覆う絶縁層と、前記実装パッドよりも大きな径を有し前記実装パッドに対応して前記絶縁層上に配設される補助パッドとを有する配線基板と、
前記補助パッド、又は、前記補助パッド及び実装パッドに導電部材を介して接続された電極を有し、前記配線基板上に実装された電子部品と、を備える半導体装置。
A wiring pattern including a wiring and a mounting pad having a diameter larger than the width of the wiring; an insulating layer covering a surface of the wiring pattern; and a diameter larger than the mounting pad and corresponding to the mounting pad A wiring board having an auxiliary pad disposed on the insulating layer;
A semiconductor device comprising: the auxiliary pad, or an electronic component having an electrode connected to the auxiliary pad and the mounting pad through a conductive member and mounted on the wiring board.
前記絶縁層が前記実装パッドに対応して形成される第1の開口を有し、前記補助パッドが前記第1の開口の上部に形成された第2の開口を有し、前記第1及び第2の開口内に形成された前記導電部材を介して前記電極と前記実装パッドとが接続される、請求項1に記載の半導体装置。   The insulating layer has a first opening formed corresponding to the mounting pad, and the auxiliary pad has a second opening formed above the first opening. The semiconductor device according to claim 1, wherein the electrode and the mounting pad are connected via the conductive member formed in the opening of 2. 前記絶縁層が、前記実装パッドに対応して形成される第1の開口を有し、
前記補助パッドが、前記第1の開口を介して前記実装パッドに接続されており、且つ、前記導電部材を介して前記電極に接続されている、請求項1に記載の半導体装置。
The insulating layer has a first opening formed corresponding to the mounting pad;
The semiconductor device according to claim 1, wherein the auxiliary pad is connected to the mounting pad through the first opening and is connected to the electrode through the conductive member.
前記補助パッドが、前記導電部材を構成する半田に濡れ性を有する、請求項1〜3の何れか一に記載の半導体装置。   The semiconductor device according to claim 1, wherein the auxiliary pad has wettability with respect to solder constituting the conductive member. 前記絶縁層が、ソルダーレジストで形成される、請求項1〜4の何れか一に記載の半導体装置。   The semiconductor device according to claim 1, wherein the insulating layer is formed of a solder resist. 前記配線が、前記補助パッドの部分の直下に延在している、請求項1〜5の何れか一に記載の半導体装置。   The semiconductor device according to claim 1, wherein the wiring extends immediately below the auxiliary pad portion. 配線と該配線の幅よりも大きな径を有する実装パッドとを含む配線パターンと、前記実装パッドに対応して形成される第1の開口を有し前記配線パターンの表面を覆う絶縁層と、前記実装パッドよりも大きな径を有し前記実装パッドに対応して前記絶縁層上に配設される補助パッドとを有し、
前記補助パッドが、前記第1の開口を介して前記実装パッドに接続されている配線基板。
A wiring pattern including a wiring and a mounting pad having a diameter larger than the width of the wiring; an insulating layer having a first opening formed corresponding to the mounting pad and covering the surface of the wiring pattern; An auxiliary pad disposed on the insulating layer corresponding to the mounting pad and having a larger diameter than the mounting pad;
A wiring board in which the auxiliary pad is connected to the mounting pad through the first opening.
配線と該配線の幅よりも大きな径を有する実装パッドとを含む配線パターンと、前記実装パッドに対応して形成される第1の開口を有し前記配線パターンの表面を覆う絶縁層と、前記実装パッドよりも大きな径を有し前記実装パッドに対応して前記絶縁層上に配設される補助パッドとを有し、
前記補助パッドが、前記第1の開口の上部に第2の開口を有する配線基板。
A wiring pattern including a wiring and a mounting pad having a diameter larger than the width of the wiring; an insulating layer having a first opening formed corresponding to the mounting pad and covering the surface of the wiring pattern; An auxiliary pad disposed on the insulating layer corresponding to the mounting pad and having a larger diameter than the mounting pad;
The wiring board, wherein the auxiliary pad has a second opening above the first opening.
JP2009081603A 2009-03-30 2009-03-30 Semiconductor device, and wiring board Pending JP2010232616A (en)

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JP2014075518A (en) * 2012-10-05 2014-04-24 Nichia Chem Ind Ltd Light-emitting device
JP2016532302A (en) * 2014-07-28 2016-10-13 インテル・コーポレーション Multi-chip module semiconductor chip package with dense package wiring
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