TWI466611B - Printed circuit board having buried component, method for manufacturing same and chip package structure - Google Patents

Description

Chip package structure, circuit board with embedded components and manufacturing method thereof

The present invention relates to the field of circuit board manufacturing, and in particular, to a circuit board having a buried component, a chip package structure using the same, and a manufacturing method thereof.

Printed circuit boards have been widely used due to their high assembly density. For application of the board, please refer to the literature Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880, IEEE Trans On Components, Packaging, and Manufacturing Technology, 1992, 15(4): 1418-1425.

The electronic components of the printed circuit board of the prior art are mostly disposed on the outer side of the circuit board, thus increasing the overall volume of the printed circuit board; in addition, when the printed circuit board needs to be provided with more electronic components, due to the printed circuit board The surface area is limited and the number of electronic components is also greatly limited. The electronic component can be an active or passive component such as a resistor, a capacitor, or the like.

Therefore, it is necessary to provide a chip package structure with a smaller size and a more rational design, a circuit board having buried components, and a method of fabricating the same.

A method of fabricating a circuit board having embedded components, comprising the steps of providing a mating structure comprising a first dielectric layer and an electronic component, the first dielectric layer including opposing first and second surfaces The electronic component includes a plurality of conductive connection terminals, the electronic component is mounted on the first surface of the first dielectric layer, and a surface of the electronic component exposed on the first surface is flush with the first surface, the electronic component a plurality of conductive connection terminals are exposed on the first surface; a plurality of through holes penetrating the first surface and the second surface are formed in the first dielectric layer; and the first surface and the second surface are respectively formed by the electroplating process a conductive circuit layer and a second conductive circuit layer, and forming conductive vias electrically connecting the first conductive circuit layer and the second conductive circuit layer in the plurality of via holes, the first conductive circuit layer including the electronic component disposed on the electronic component a terminal connection line on a surface of the portion of the conductive connection terminal that is flush with the first surface; and a second dielectric layer and a third conductive circuit layer are sequentially formed on a side of the first conductive circuit layer, thereby forming A circuit board having a buried element.

A circuit board having a buried component includes a mating structure, a first conductive wiring layer, a second conductive wiring layer, a second dielectric layer, and a third conductive wiring layer. The first structure includes a first dielectric layer and an electronic component, the first dielectric layer includes an opposite first surface and a second surface, the electronic component includes a plurality of conductive connection terminals, and the electronic component is embedded in the first dielectric The first surface of the electrical layer and the surface of the electronic component exposed on the first surface are flush with the first surface, and the plurality of conductive connection terminals of the electronic component are exposed on the first surface. The first conductive circuit layer and the second conductive circuit layer are respectively disposed on the first surface and the second surface, and the first conductive circuit layer includes a surface of the electronic component that is partially flush with the first surface The terminal on the connection line. The second dielectric layer and the third conductive circuit layer are sequentially formed on one side of the first conductive circuit layer.

A chip package structure comprising a circuit board having a buried component and a wafer as described above. The circuit board having the embedded component further includes a third dielectric layer, a fourth conductive wiring layer, a first solder resist layer, and a second solder resist layer. The third dielectric layer and the fourth conductive circuit layer are sequentially formed on one side of the second conductive circuit layer, and the first solder resist layer and the second solder resist layer are respectively formed on the third conductive circuit layer and the fourth conductive line The first solder resist layer partially covers the third conductive circuit layer, and the third conductive circuit layer exposed on the first solder resist layer constitutes a first electrical connection pad, and the second solder resist layer partially covers the first conductive layer The fourth conductive circuit layer, the fourth conductive circuit layer exposed on the second solder resist layer constitutes a second electrical connection pad. The chip is packaged on the circuit board having the embedded component and electrically connected to the first electrical connection pad.

Compared with the prior art, the circuit board with the embedded component of the present embodiment places the electronic component inside the circuit board, and the number of components that can be disposed on the circuit board increases, which increases the flexibility of the design of the circuit board. In addition, the circuit board having the embedded component in this embodiment can be applied to an HDI high-density laminated board.

11. . . First dielectric layer

12. . . Electronic component

14. . . Carrier board

13. . . Release layer

121. . . Conductive connection terminal

112. . . First surface

114. . . Second surface

10. . . Chimeric structure

115. . . Through hole

15. . . First conductive circuit layer

16. . . Second conductive circuit layer

17. . . Conductive through hole

151. . . Terminal connection line

18. . . Second dielectric layer

19. . . Third conductive circuit layer

20. . . Third dielectric layer

twenty one. . . Fourth conductive circuit layer

twenty two. . . Conductive hole

twenty three. . . First solder mask

twenty four. . . Second solder mask

25. . . First electrical connection pad

26. . . Second electrical connection pad

30. . . Circuit board with embedded components

27. . . First surface treatment layer

28. . . Second surface treatment layer

29. . . Solder bump

40. . . Wafer

50. . . Chip package structure

34. . . Solder ball

1 is a cross-sectional view of two dielectric layers, two electronic components, and a carrier plate having a release layer on opposite sides, respectively, provided by an embodiment of the present invention.

2 is a cross-sectional view showing a multilayer structure in which the dielectric layer, the electronic component, and the carrier substrate of FIG. 1 are laminated in the order of a dielectric layer, an electronic component, a carrier, an electronic component, and a dielectric layer.

3 is a cross-sectional view showing a structure in which an electronic component formed by separating a carrier sheet in the multilayer structure of FIG. 2 is embedded in a dielectric layer.

4 is a cross-sectional view showing a through hole formed in the dielectric layer of FIG. 3.

5 is a cross-sectional view showing a conductive circuit layer formed on opposite sides of the dielectric layer of FIG. 4 and a conductive material formed in the via hole to form a conductive via.

Fig. 6 is a cross-sectional view showing the dielectric layer and the conductive wiring layer sequentially formed on the two conductive wiring layer sides in Fig. 5, respectively.

Fig. 7 is a cross-sectional view showing a circuit board having a buried element formed after forming a solder resist layer on the outermost conductive wiring layer of Fig. 6, respectively.

Figure 8 is a cross-sectional view showing a solder bump formed on one side of the circuit board of Figure 7.

9 is a cross-sectional view of a wafer package structure formed after the wafer is packaged on the circuit board having the embedded component of FIG.

Referring to FIG. 1 to FIG. 9 , a method for fabricating a chip package structure includes the following steps:

Step 1: Referring to FIG. 1 and FIG. 2, two first dielectric layers 11, two electronic components 12, and a carrier board 14 are provided. Separate layers 13 are respectively disposed on opposite sides of the carrier board 14, and are sequentially stacked. The first dielectric layer 11, the electronic component 12, the carrier board 14, the electronic component 12, and the first dielectric layer 11 are laminated together at a time.

The material of the two first dielectric layers 11 may be polyimide (PI), polyethylene terephthalate (PET) or polyethylene naphthalate (Polyethylene). Naphthalate, PEN), PP (Prepreg) or ABF (Ajinomoto Build-up film), etc., preferably PP or ABF, each of the first dielectric layers 11 includes an opposite first surface 112 and second surface 114. The electronic component 12 can be an active or passive component, such as a resistor, a capacitor, etc. In the embodiment, the electronic component 12 is a ceramic capacitor and includes two conductive connection terminals 121, that is, electrodes of a ceramic capacitor. The carrier board 14 is used to support and carry the two first dielectric layers 11 and two electronic components 12 during the pressing process. The material of the carrier board 14 may be PI, fiberglass laminate or metal such as copper. . The release layer 13 is formed by plasma processing or fluorine coating of a plastic film, or by forming a silicone release agent on a surface of a film material such as PET, PE, OPP, and the release layer 13 is used in subsequent steps. The two first dielectric layers 11 and the electronic component 12 and the carrier board 14 are mutually separated.

It can be understood that the number of the conductive connection terminals 121 may also be more than two, and is not limited to the embodiment.

Pressing the first dielectric layer 11, the electronic component 12, the carrier board 14, the electronic component 12, and the first dielectric layer 11 can be performed in a press machine. After pressing, the two electronic components 12 are respectively attached to the surface of the adjacent release layer 13; the first surface 112 of the two first dielectric layers 11 is opposite to the corresponding release layer 13 and is pressed by the pressing force. The lower surface is respectively attached to the surface of the corresponding release layer 13, and each electronic component 12 is fitted into the first surface 112 of the corresponding first dielectric layer 11, and each electronic component 12 is adjacent to the corresponding release layer. The surface of the first dielectric layer 11 is flush with the first surface 112 of the corresponding first dielectric layer 11, and the two conductive connection terminals 121 of each electronic component 12 are exposed on the first surface 112, each of the first dielectric layers 11. The thickness is greater than the thickness of the corresponding electronic component 12.

Step 2: Referring to FIG. 3, the carrier board 14 and the two release layers 13 are removed by a stripping process to obtain two electrons including the first dielectric layer 11 and the electrons embedded in the first dielectric layer 11. The fitting structure 10 of the element 12.

Since the release layer 13 is disposed between the carrier plate 14 and the first dielectric layer 11 and the electronic component 12, the carrier layer 14 and the release layer 13 can be conveniently removed by utilizing the peelability of the release layer 13. Thereby, the structures on opposite sides of the carrier plate 14 are separated from each other to form two fitting structures 10.

The two fitting structures 10 have the same structure, and one of them will be described below. The mating structure 10 includes a first dielectric layer 11 and an electronic component 12 mounted on the first surface 112 of the first dielectric layer 11. The electronic component 12 is exposed on the surface of the first surface 112 and the first The surface 112 is flush and the two conductive connection terminals 121 of the electronic component 12 are exposed on the first surface 112.

Step 3: Referring to FIG. 4, a plurality of vias 115 are formed in the dielectric layer through the first surface 112 and the second surface 114. The method of forming the plurality of vias 115 may be a laser etched hole or a mechanical boring.

Step 4: Referring to FIG. 5, a first conductive circuit layer 15 is formed on the surface of the first surface 112 and the electronic component 12 exposed on the first surface 112 by electroplating, and a second conductive layer is formed on the second surface 114. The circuit layer 16 and the conductive vias 17 for electrically conducting the first conductive wiring layer 15 and the second conductive wiring layer 16 are respectively formed in the plurality of via holes 115.

The method for forming the first conductive circuit layer 15, the second conductive circuit layer 16, and the conductive vias 17 by the method of electroplating specifically includes the following steps:

First, the fitting structure 10 is cleaned to remove surface stains and residual slags during the step 3 etching or drilling process, so that the surface of the fitting structure 10 and the inner wall of the through hole 115 are cleaned to facilitate subsequent steps. Going on.

Next, a conductive film is formed on the first surface 112 and the second surface 114 of the first dielectric layer 11, the surface of the electronic component 12 exposed on the first surface 112, and the inner wall of the via 115 by electroless copper plating ( The figure is not shown). It can be understood that the process of forming the conductive film may also be a black hole process, a black shadow process, etc., and is not limited to the embodiment.

Again, a patterned photoresist layer (not shown) is provided to expose regions pre-formed with the first conductive wiring layer 15, the second conductive wiring layer 16, and the conductive vias to the photoresist layer. The other areas are blocked by the photoresist layer.

Further, the fitting structure 10 in which the conductive film and the photoresist layer are formed is placed in a plating bath and connected to the electrode for electroplating, and an electroplated copper layer is formed on the conductive film exposed on the photoresist layer. In the electroplating process, an electroplated copper layer fills the via 115 to form the conductive via 17.

Finally, the photoresist layer is removed, and the conductive film blocked by the photoresist layer is etched away to form the first conductive wiring layer 15, the second conductive wiring layer 16, and the conductive vias 17.

The first conductive circuit layer 15 includes two terminal connection lines 151. The two terminal connection lines 151 are respectively formed at least partially on the surfaces of the two conductive connection terminals 121 to electrically connect the two conductive connection terminals 121, respectively.

It can be understood that one of the conductive connection terminals 121 may not be electrically connected to the first conductive circuit layer 15, but may be electrically connected to the second conductive circuit layer 16 through a conductive blind hole (not shown), and the other conductive connection terminal 121 is still electrically connected to the first conductive circuit layer 15 through the terminal connection line 151, that is, the partial conductive connection terminal 121 is electrically connected to the first conductive circuit layer 15, and the remaining conductive connection terminal 121 passes through the conductive blind hole and the second conductive circuit layer 16 Electrical connection is not limited to this embodiment. The conductive via hole is formed in the first dielectric layer 11 and forms a blind via through the second surface 114 and communicates with one of the conductive connection terminals 121 to expose the corresponding conductive connection terminal 121 from the blind via hole. On the second surface 114, while forming the first conductive circuit layer 15, the second conductive circuit layer 16, and the conductive via 17 by an electroplating process, forming the second conductive circuit layer 16 and the corresponding conductive in the blind via. A conductive blind hole electrically connected to the connection terminal 121.

Step 5: Referring to FIG. 6, a second dielectric layer 18 and a third conductive circuit layer 19 are sequentially formed on the first conductive circuit layer 15 side, and a third dielectric layer is sequentially formed on the second conductive circuit layer 16 side. The electric layer 20 and the fourth conductive wiring layer 21.

The second dielectric layer 18 and the third conductive wiring layer 19 and the third dielectric layer 20 and the fourth conductive wiring layer 21 can be respectively formed by a build-up method. The third conductive circuit layer 19 and the first conductive circuit layer 15 and the fourth conductive circuit layer 21 and the second conductive circuit layer 16 are respectively formed on the second dielectric layer 18 and The conductive holes 22 in the three dielectric layers 20 are electrically connected.

Step 6: Referring to FIG. 7 , the first solder resist layer 23 is partially covered on the third conductive circuit layer 19 , and the second solder resist layer 24 is partially covered on the fourth conductive trace layer 21 to be exposed to the first The third conductive circuit layer 19 of the solder resist layer 23 constitutes a plurality of first electrical connection pads 25, and the fourth conductive circuit layer 21 exposed to the second solder resist layer 24 constitutes a plurality of second electrical connection pads 26, thereby forming A circuit board 30 in which components are embedded.

In this embodiment, the first electrical connection pad 25 and the second electrical connection pad 26 are respectively arranged in an array, and the first electrical connection pad 25 is used to electrically exchange with the wafer (such as the wafer 40 in FIG. 9). The second electrical connection pad 26 is electrically connected to other electronic devices such as a circuit board.

It can be understood that more dielectric layers and conductive lines can be further disposed between the third conductive circuit layer 19 and the first conductive circuit layer 15 and between the fourth conductive circuit layer 21 and the second conductive circuit layer 16, respectively. Layers to form a circuit board with more conductive circuit layers. In addition, the number of the electronic components 12 in the circuit board 30 having the embedded component may also be plural, and is not limited to one of the embodiments.

As shown in FIG. 7, the circuit board 30 having the embedded component of the present embodiment includes a fitting structure 10, a first conductive wiring layer 15, a second conductive wiring layer 16, a second dielectric layer 18, and a third conductive wiring layer. 19. The third dielectric layer 20, the fourth conductive wiring layer 21, the first solder resist layer 23, and the second solder resist layer 24. The first conductive circuit layer 15 is formed on the first surface 112 of the first dielectric layer 11 and the electronic component 12 is exposed on the surface of the first surface 112. The second conductive circuit layer 16 is formed on the first dielectric layer 11 The second surface of the first conductive circuit layer 15 includes two terminal connection lines 151. The two terminal connection lines 151 are respectively formed at least partially on the surfaces of the two conductive connection terminals 121 to electrically connect the two conductive connections respectively. Terminal 121. A conductive via 17 electrically connecting the first conductive wiring layer 15 and the second conductive wiring layer 16 is formed in the first dielectric layer 11. The second dielectric layer 18 and the third conductive circuit layer 19 are sequentially formed on the first conductive circuit layer 15 side, and the third dielectric layer 20 and the fourth conductive circuit layer 21 are sequentially formed on the second conductive circuit layer. a side of the 16th, between the third conductive circuit layer 19 and the first conductive circuit layer 15, and between the fourth conductive circuit layer 21 and the second conductive circuit layer 16 are respectively formed on the second dielectric layer 18 and the conductive holes 22 in the third dielectric layer 20 are electrically connected. The first solder resist layer 23 is formed on the third conductive circuit layer 19 and partially covers the third conductive circuit layer 19. The third conductive circuit layer 19 exposed on the first solder resist layer 23 constitutes a plurality of first electrical properties. The second solder resist layer 24 is formed on the fourth conductive circuit layer 21 and partially covers the fourth conductive circuit layer 21, and the fourth conductive circuit layer 21 exposed on the second solder resist layer 24 constitutes a plurality of The second electrical connection pad 26.

Step 7: Referring to FIG. 8 , the first electrical connection pad 25 and the second electrical connection pad 26 are surface-plated, and the first electrical connection pad 25 and the second electrical connection pad 26 respectively form a first surface. The surface treatment layer 27 and the second surface treatment layer 28 are formed with solder bumps 29 on the surface of the first surface treatment layer 27.

The first surface treatment layer 27 and the second surface treatment layer 28 serve to protect the first electrical connection pads 25 and the second electrical connection pads 26 from oxidation. The plurality of first surface treatment layers 27 and the second surface treatment layer 28 are electrically connected to the corresponding first electrical connection pads 25 and second electrical connection pads 26, respectively. It can be understood that the method of forming the first surface treatment layer 27 and the second surface treatment layer 28 may also be replaced by nickel plating gold, nickel immersion gold, nickel plating palladium gold, tin plating, etc., which is not limited to the embodiment. .

In this embodiment, a plurality of solder bumps 29 are respectively formed on the surface of the first surface treatment layer 27 on the plurality of first electrical connection pads 25 by electroplating or printing, and the plurality of solder bumps 29 are protruded. On the surface of the first solder resist layer 23. The solder bumps 29 may be columnar, spherical, or the like. In this embodiment, they are columnar, and the material thereof is generally mainly tin. It can be understood that the first surface treatment layer 27 and the second surface treatment layer 28 can also be omitted. At this time, the solder bumps 29 are directly formed on the surface of the first electrical connection pad 25.

Step 8: Referring to FIG. 9, a wafer 40 is provided, and the wafer 40 is electrically connected to the plurality of first electrical connection pads 25 and packaged on the circuit board 30 having embedded components to form a chip package structure 50.

In this embodiment, the wafer 40 is a flip-chip wafer having a plurality of contact bumps (not shown) corresponding to the plurality of first electrical connection pads 25, respectively. The bumps are also typically made of solder and the material is primarily tin. The connection of the plurality of contact bumps to the corresponding solder bumps 29 may be performed by first disposing the wafer 40 on the circuit board 30 having the embedded component and respectively making the plurality of contact bumps and the corresponding solder bumps. 29 phase contact; then, the wafer 40 and the circuit board 30 having the embedded component are passed through a reflow oven, and the contact bump and the solder bump 29 are fusion-bonded to form a solder ball 34 and cooled and solidified, thereby making the contact bump The solder bumps 29 are connected to each other and electrically connected. It can be understood that the wafer 40 can also be a wire bonding (WB) wafer, and can be packaged on the circuit board 30 having the embedded component by a conventional packaging method, which is not limited to the embodiment.

As shown in FIG. 9, the chip package structure 50 of the present embodiment includes a circuit board 30 having buried components and a wafer 40 packaged on the circuit board 30 having embedded components. The wafer 40 is electrically connected to the circuit board 30 having the embedded component through a plurality of solder balls 34 formed between the first electrical connection pad 25 and the wafer 40. One end of each solder ball 34 is soldered to the first electric The connecting pads 25 are connected to the wafer 40 at opposite ends. The material of the solder balls 34 generally comprises mainly tin.

With respect to the prior art, the circuit board 30 with the embedded component of the present embodiment places the electronic component 12 inside the circuit board, and the number of components that can be disposed on the circuit board is increased, which increases the flexibility of the design of the circuit board. In addition, the circuit board 30 having the embedded component in the present embodiment can be applied to an HDI high-density laminated board.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be covered by the following claims.

50. . . Chip package structure

40. . . Wafer

25. . . First electrical connection pad

27. . . First surface treatment layer

34. . . Solder ball

twenty three. . . First solder mask

Claims (12)

A method of fabricating a circuit board having embedded components, comprising the steps of:
Providing a fitting structure comprising a first dielectric layer including an opposite first surface and a second surface, the electronic component comprising a plurality of conductive connection terminals, the electronic component being embedded The first surface of the first dielectric layer and the surface of the electronic component exposed on the first surface are flush with the first surface, and the plurality of conductive connection terminals of the electronic component are exposed on the first surface;
Forming a plurality of through holes penetrating the first surface and the second surface in the first dielectric layer;
Forming a first conductive circuit layer and a second conductive circuit layer on the first surface and the second surface, respectively, by an electroplating process, and forming a conductive connection electrically connecting the first conductive circuit layer and the second conductive circuit layer in the plurality of via holes a via hole, the first conductive circuit layer includes a terminal connection line disposed on a surface of the electronic component with the conductive connection terminal flush with the first surface; and a second dielectric layer is sequentially formed on the first conductive circuit layer side The electrical layer and the third conductive wiring layer form a circuit board having embedded components. The method of fabricating a circuit board having a buried component according to claim 1, wherein the first conductive wiring layer further comprises other partial conductive connection terminals disposed in the plurality of conductive terminals of the electronic component and the first surface Terminal connection lines on a flat surface. A method of fabricating a circuit board having a buried component according to claim 1, wherein when the first conductive wiring layer and the second conductive wiring layer are respectively formed on the first surface and the second surface by an electroplating process, A conductive via hole electrically connected to the other portion of the plurality of conductive terminals of the electronic component and the second conductive circuit layer is formed in the first dielectric layer. A method of fabricating a circuit board having a buried component as described in claim 1, wherein the method of fabricating the same comprises the steps of: providing two first dielectric layers, two electronic components, and a carrier board, Separate layers are respectively disposed on the opposite sides of the board, and the first dielectric layer, the electronic component, the carrier board, the electronic component, and the first dielectric layer are laminated and laminated one at a time; and the carrier is formed by a stripping process The plate and the two release layers are removed to provide two mating structures including a first dielectric layer and electronic components embedded in the first dielectric layer. A method of fabricating a circuit board having a buried component according to claim 1, further comprising the steps of: sequentially forming a third dielectric layer and a fourth conductive wiring layer on a side of the second conductive wiring layer, and Forming a first solder resist layer and a second solder resist layer on the third conductive circuit layer and the fourth conductive circuit layer, respectively, the first solder resist layer partially covering the third conductive circuit layer, exposed to the first solder resist layer The third conductive circuit layer constitutes a first electrical connection pad, the second solder resist layer partially covers the fourth conductive circuit layer, and the fourth conductive circuit layer exposed on the second solder resist layer constitutes a second electrical connection pad. A circuit board having embedded components, comprising:
a fitting structure comprising a first dielectric layer and an electronic component, the first dielectric layer comprising opposite first and second surfaces, the electronic component comprising a plurality of conductive connection terminals, the electronic component being embedded a first surface of the first dielectric layer and a surface of the first surface exposed to the first surface is flush with the first surface, and a plurality of conductive connection terminals of the electronic component are exposed on the first surface;
a first conductive circuit layer and a second conductive circuit layer respectively disposed on the first surface and the second surface, the first conductive circuit layer comprising a surface of the electronic component that is partially flush with the first surface The upper terminal connection line; and the second dielectric layer and the third conductive line layer are sequentially formed on one side of the first conductive line layer. The circuit board with embedded components of claim 6, wherein the first conductive circuit layer further comprises a terminal connection line disposed on a surface of the other portion of the electronic component that is electrically flush with the first surface . The circuit board with embedded components of claim 6, wherein the first dielectric layer has electrical connection with other portions of the plurality of conductive terminals of the electronic component and the second conductive circuit layer. Conductive blind holes. The circuit board with embedded components according to claim 6, wherein the circuit board having the embedded component further comprises a third dielectric layer, a fourth conductive circuit layer, a first solder resist layer and a second solder resist layer The third dielectric layer and the fourth conductive circuit layer are sequentially formed on one side of the second conductive circuit layer, and the first solder resist layer and the second solder resist layer are respectively formed on the third conductive circuit layer and the fourth conductive layer On the circuit layer, the first solder resist layer partially covers the third conductive circuit layer, and the third conductive circuit layer exposed on the first solder resist layer constitutes a first electrical connection pad, and the second solder resist layer partially covers the The fourth conductive circuit layer, the fourth conductive circuit layer exposed on the second solder resist layer constitutes a second electrical connection pad. A chip package structure comprising the circuit board and the wafer having the embedded component according to claim 9, the chip being packaged on the circuit board having the embedded component and electrically connected to the first electrical connection pad. The chip package structure of claim 10, wherein the first conductive wiring layer further comprises a terminal connection line disposed on a surface of the other portion of the electronic component that is electrically flush with the first surface. The chip package structure of claim 10, wherein the first dielectric layer has conductive vias electrically connected to other portions of the plurality of conductive terminals of the electronic component and the second conductive circuit layer.