CN105448856B - Chip-packaging structure, preparation method and chip package base plate - Google Patents
Chip-packaging structure, preparation method and chip package base plate Download PDFInfo
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- CN105448856B CN105448856B CN201410439461.9A CN201410439461A CN105448856B CN 105448856 B CN105448856 B CN 105448856B CN 201410439461 A CN201410439461 A CN 201410439461A CN 105448856 B CN105448856 B CN 105448856B
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Abstract
A kind of preparation method of chip-packaging structure, including step：One copper foil is provided, metal backup is formed in the presumptive area of the copper foil surface；Multiple engagement pads, dielectric layer are sequentially formed on the surface of the copper foil；Multiple openings are formed in dielectric layer and multiple grooves are formed on the metal backup, and outs open mutually connects one by one with the groove；Conductive pole is formed in the opening of part, conductive projection is formed in the groove of connection and opening, and conductive circuit layer is formed on the surface of dielectric layer；The copper foil and the metal backup are removed, the position where the metal backup forms an accepting groove, and multiple conductive projections protrude from the bottom surface of the accepting groove；And a chip is contained in the accepting groove and is welded in the conductive projection surface in the accepting groove, form the chip-packaging structure.The invention further relates to a kind of chip package base plate and structure.
Description
Technical field
The present invention relates to circuit board making field, more particularly to a kind of chip-packaging structure, preparation method and chip package
Substrate.
Background technology
Chip package base plate can provide electrical connection, protection, support, radiating, assembling and other effects for chip, to realize more pins
Change, reduce encapsulating products volume, improve the purpose of electrical property and thermal diffusivity, VHD or multi-chip module.Normally, core
Piece package substrate put connect chip after form chip-packaging structure, wherein, the chip in chip-packaging structure protrude from chip envelope
Substrate is filled, so that the integral thickness of chip-packaging structure increases, is unfavorable for the miniaturized design of chip-packaging structure.
The content of the invention
Therefore, it is necessary to provide a kind of relatively thin chip-packaging structure, preparation method and chip package base plate.
A kind of preparation method of chip-packaging structure, including step：A copper foil is provided, in the fate of the copper foil surface
Domain forms a metal backup；Multiple first engagement pads are formed on the surface of the copper foil, wherein, first engagement pad with it is described
Metal backup is located at the same surface of the copper foil；One first dielectric layer is formed, makes the first dielectric layer cladding described first
The copper foil that engagement pad, the metal backup and covering are exposed from first engagement pad, the metal backup
Surface；Multiple first openings and multiple second openings are formed in first dielectric layer, and are formed on the metal backup
Multiple grooves, each first engagement pad are partly exposed in first opening, and each second opening is equal
It is connected with a groove；The first conductive pole is respectively formed in each first opening, in each second opening
And conductive projection is respectively formed in the groove communicated therewith, and form the first conducting wire on the surface of first dielectric layer
Layer, wherein, first engagement pad and first conductive circuit layer are electrically connected by first conductive pole, and described first
Conductive circuit layer is electrically connected with the conductive projection；The copper foil and the metal backup are removed, described first is exposed and connects
Touch pad, the position where the metal backup form an accepting groove, and the multiple conductive projection protrudes from the accepting groove
Bottom surface；And a chip is contained in the accepting groove, and the chip is welded on the conductive projection surface, so as to
Form the chip-packaging structure.
A kind of chip-packaging structure, including it is one first dielectric layer, multiple first engagement pads, one first conductive circuit layer, more
Individual first conductive pole, multiple conductive projections and a chip.First dielectric layer includes relative first surface and second surface,
First dielectric layer has been internally formed an accepting groove from the first surface to first dielectric layer.First engagement pad
It is embedded in first dielectric layer and surface flushes with the first surface.First conductive circuit layer is formed at described
The second surface of first dielectric layer.Each first conductive pole through first dielectric layer and electrically connects one described the
One engagement pad and first conductive circuit layer.The multiple conductive projection is through first dielectric layer and with described the
One conductive circuit layer electrically connects, and the multiple conductive projection protrudes from the bottom surface of the accepting groove.The chip is contained in
Electrically connected in the accepting groove and with the multiple conductive projection.
A kind of chip package base plate, including it is one first dielectric layer, multiple first engagement pads, one first conductive circuit layer, more
Individual first conductive pole and multiple conductive projections.First dielectric layer includes relative first surface and second surface, and described
One dielectric layer has been internally formed an accepting groove from the first surface to first dielectric layer.First engagement pad is embedded at
In in first dielectric layer and surface flushes with the first surface.First conductive circuit layer is formed at described first and is situated between
The second surface of electric layer.Each first conductive pole through first dielectric layer and electrically connects first contact
Pad and first conductive circuit layer.The multiple conductive projection is through first dielectric layer and conductive with described first
Line layer electrically connects, and the multiple conductive projection protrudes from the bottom surface of the accepting groove, and the accepting groove is used to house one
Chip, the multiple conductive projection are used to electrically connect the chip being contained in the accepting groove.
Relative to prior art, the embodiment of the present invention is in chip-packaging structure, its preparation method and chip package base plate shape
Into the accepting groove, chip can be encapsulated in the accepting groove, so as to reduce the chip package base plate and structure
Thickness, be advantageous to the slimming of the chip package base plate and structure；Led in addition, common chip package base plate is both needed to be formed
Electrical pad is to electrically connect chip, and the conductive projection for protruding from bottom surface of this case can substitute conductive pad electrical connection chip, so as to reduce
Circuit board making step and cost of manufacture.
Brief description of the drawings
Fig. 1 is the sectional view for the chip-packaging structure for being welded with chip that first embodiment of the invention provides.
Fig. 2 is that second embodiment of the invention provides the sectional view being bonded on loading plate after copper foil.
Fig. 3 is the sectional view formed the copper foil surface in Fig. 2 after metal backup.
Fig. 4 is the sectional view after Fig. 3 copper foil surface forms the first engagement pad.
Fig. 5 is the sectional view that copper foil surface in Fig. 4 is formed after the first dielectric layer, opening, metal backup groove.
Fig. 6 is that conductive pole is formed in opening and groove in Figure 5, and the first dielectric layer surface forms the first conducting wire
Sectional view after layer.
Fig. 7 is that the first conducting wire layer surface in Fig. 6 formed into second, third dielectric layer, the second conducting wire plate,
Two engagement pads, the sectional view of the first circuit board intermediate obtained after welding resisting layer.
Fig. 8 is the second circuit obtained after removing the loading plate of the second circuit board intermediate in Fig. 7 and separated type material
The sectional view of plate intermediate.
Fig. 9 is the chip package base obtained after removing the copper foil of the second circuit board intermediate in Fig. 7 and metal backup
The sectional view of plate.
Main element symbol description
Chip-packaging structure 100
First dielectric layer 122
First surface 1221
Second surface 1222
Accepting groove 1223
Bottom surface 1224
First engagement pad 121
First conductive circuit layer 128
First conductive pole 126
Conductive projection 127
Second dielectric layer 129
Second conductive circuit layer 130
3rd dielectric layer 131
Second engagement pad 132
Second conductive pole 133
3rd conductive pole 134
Chip 136
First soldered ball 137
Underfill colloid 138
Welding resisting layer 135
Chip packing-body 102
Second soldered ball 139
Loading plate 110
Copper foil 120
First area 111
Second area 112
3rd region 113
Glue-line 114
Separated type material 115
Metal backup 116
First opening 123
Second opening 124
Groove 125
First circuit board intermediate 200
Second circuit board intermediate 210
Chip package base plate 220
Following embodiment will combine above-mentioned accompanying drawing and further illustrate the present invention.
Embodiment
Referring to Fig. 1, first embodiment of the invention provides a kind of chip-packaging structure 100, including：One first dielectric layer
122, first dielectric layer 122 includes relative first surface 1221 and second surface 1222, and first dielectric layer 122 is certainly
The first surface 1221 has been internally formed an accepting groove 1223 to first dielectric layer 122, and the accepting groove 1223 has
The bottom surface 1224 parallel with the first surface 1221 and second surface 1222；Multiple first engagement pads 121, described first connects
Touch pad 121 is embedded in first dielectric layer 122 and surface flushes with the first surface 1221；One first conductive circuit layer
128, first conductive circuit layer 128 is formed at the second surface 1222 of first dielectric layer 122；Multiple first conductive poles
126, the multiple first conductive pole 126 extends through first dielectric layer 122 and electrically connects first engagement pad
121 and first conductive circuit layer 128；Multiple conductive projections 127, the multiple conductive projection 127 run through described first
Dielectric layer 122 simultaneously electrically connects with first conductive circuit layer 128, and the multiple conductive projection 127 protrudes from the receipts
The bottom surface 1224 of tank 1223, the end face diameter of connection first conductive circuit layer 128 of the conductive projection 127 are more than far
From the end face diameter of first conductive circuit layer 128；One second dielectric layer 129, second dielectric layer 129 are formed at described
Surface of first conductive circuit layer 128 away from first dielectric layer 122, second dielectric layer 129 cover described first and led
Electric line layer 128 and first dielectric layer 122 in first conductive circuit layer 128；One second conducting wire
Layer 130, second conductive circuit layer 130 is formed at table of second dielectric layer 129 away from first dielectric layer 122
Face, second conductive circuit layer 130 are electrically connected by multiple second conductive poles 133 and first conductive circuit layer 128；
One the 3rd dielectric layer 131, the 3rd dielectric layer 131 are formed at second conductive circuit layer 130 away from second dielectric
The surface of layer 129, the 3rd dielectric layer 131 cover second conductive circuit layer 130 and exposed to second conductor wires
Second dielectric layer 129 in road floor 130；Multiple second engagement pads 132, second engagement pad 132 are formed at described
Surface of three dielectric layers 131 away from second dielectric layer 129, second engagement pad 132 pass through multiple 3rd conductive poles 134
It is electrically connected with second conductive circuit layer 130, the surface of the first engagement pad 121 is formed with the second soldered ball 139, for electricity
Connect a circuit board；One welding resisting layer 135, the welding resisting layer 135 are formed at the 3rd dielectric layer 131 away from second dielectric
The surface of layer 129, and second engagement pad 132 is exposed from the welding resisting layer 135；An at least chip 136, the core
Piece 136 is electrically connected by multiple first soldered balls 137 and the conductive projection 127, and the side and bottom of the chip 136 are formed
There is a underfill colloid (underfill) 138, surface of the chip 136 away from the 3rd dielectric layer 131 is less than described the
Surface of one engagement pad 121 away from the 3rd dielectric layer 131, or with first engagement pad 121 away from the 3rd dielectric
The surface of layer 131 flushes；One chip packing-body 102, the chip packing-body 102 are welded in the first engagement pad surface.
Fig. 2-9 are referred to, second embodiment of the invention provides a kind of preparation method of said chip encapsulating structure 100, bag
Include following steps：
The first step, referring to Fig. 2, providing a loading plate 110, copper is covered each by the opposite sides of the loading plate 110
Paper tinsel 120, and the copper foil 120 only edge is affixed with the loading plate 110.
The loading plate 110 can be the rigid support materials such as resin plate, ceramic wafer, metallic plate.The people of loading plate 110
To be divided into the first area 111 in three regions, respectively peripheral annular, the secondth area of the ring-type to connect with first area 111
The 3rd region 113 enclosed in domain 112, and second area 112.The first area 111 is garbage area, in chip-packaging structure
Need to remove in 100 manufacturing process.3rd region 113 corresponds to the region of pasting chip.It is appreciated that the chip package
Each intermediate products in the manufacturing process of structure 100 can continue to use the division of above-mentioned zone.
The step of being bonded copper foil 120 includes：First, there is provided two glue-lines 114, wherein, the shape and chi of the glue-line 114
Two glue-lines 114 are fitted in the loading plate 110 by very little and the shape and size all same of the loading plate 110 respectively
Two apparent surfaces, and the glue-line 114 is alignd with the loading plate 110；Afterwards, there is provided two separated type materials 115, institute
The size for stating separated type material 115 is less than the size of the loading plate 110, and two separated type materials 115 are fitted in into two respectively
The centre position of the individual glue-line 114, and make the glue-line 114 that exposes from the periphery of separated type material 115 annular in shape；There is provided
Two copper foils 120, two copper foils 120 are fitted in the phase of the loading plate 110 by the glue-line 114 of the ring-type respectively
To surface, so as to make the copper foil 120 only edge and the loading plate 110 bonding.Wherein, the separated type material 115 can be with
For resinae mould release membrance, metal foil/plate etc..
In other embodiments, the separated type material 115 can not also be bonded, and the glue-line of a ring-type is only provided, makes institute
State the only edge of copper foil 120 and the loading plate 110 is bonding.
Second step, referring to Fig. 3, the surface of two copper foils 120 in the 3rd region 113 forms metal gear respectively
Block 116.
Wherein, the metal backup 116 can be formed by the mode such as electroplating, printing or attach.The metal backup 116
It is generally rectangular shaped, its thickness is more than the thickness with chip to be mounted.Preferably, the material of the metal backup 116 be copper with
Outer metal, more preferably zinc, described in it can be removed in subsequent step by the etching solution etching different from copper etchant solution
During metal backup 116, so as to not etch on circuit board the copper for needing to retain.
3rd step, referring to Fig. 4, the surface of two copper foils 120 in second area 112 make to be formed it is multiple
First engagement pad 121.
Specifically, first, the surface of two copper foils 120 in second area 112 is respectively formed the anti-plated of patterning
Film layer (not shown), make the copper foil 120 being exposed from the anti-film plating layer of patterning and will be formed multiple first
Engagement pad 121 is corresponding；Afterwards, plating is so that the table for the copper foil 120 being exposed in the anti-film plating layer from patterning
Face forms electrodeposited coating, and the electrodeposited coating is the first engagement pad 121；Then, the anti-film plating layer of the patterning is removed.
Preferably, first engagement pad 121 section parallel with the loading plate 110 is circle.
4th step, referring to Fig. 5, the remote loading plate of first engagement pad 121 in the both sides of loading plate 110
110 side is respectively formed the first dielectric layer 122, wherein, first dielectric layer 122 coats first engagement pad 121, described
The copper foil 120 that metal backup 116 and covering are exposed from first engagement pad 121, the metal backup 116
Surface；Multiple first openings 123 and multiple second openings 124 are formed in first dielectric layer 122, and in the metal
Multiple grooves 125 are formed on block 116.Wherein, each first opening 123 with a phase of the first engagement pad 121
It is corresponding, and each first engagement pad 121 part is in first opening 123；The multiple second opens
Mouth 124 is both formed in the second area, and each second opening 124 is connected with a groove 125.
Specifically, first, the both sides of the loading plate 110 after the first engagement pad 121 is formed are bonded film and consolidated
Change the film, so as to form first dielectric layer 122；Afterwards, in first dielectric layer by way of laser pit
Multiple openings 124 of first opening 123, second are formed on 122, and multiple grooves are formed on the metal backup 116
125.The film can be glass fiber fabric base, paper substrate, composite base, aramid fiber nonwoven fabric base or synthetic fibers base etc. containing enhancing
The prepreg of material, or the prepreg of pure resin, the film can after the hot processing procedure such as hot pressing or heat baking
To switch to solid state from semi-cured state.
5th step, referring to Fig. 6, the first conductive pole 126 is respectively formed in each first opening 123, in each institute
State and conductive projection 127 is respectively formed in the second opening 124 and the groove 125 communicated therewith, and in first dielectric layer 122
Surface forms the first conductive circuit layer 128.Wherein, positioned at first engagement pad 121 of the homonymy of loading plate 110 and described
First conductive circuit layer 128 is electrically connected by first conductive pole 126 of homonymy, positioned at the homonymy of loading plate 110
First conductive circuit layer 128 is also electrically connected with the conductive projection 127.
The arrangement density of the conductive projection 127 is more than the arrangement density of first conductive pole 126, that is, adjacent two
The spacing being smaller than between two neighboring first conductive pole 126 between the individual conductive projection 127.Described first leads
Electric post 126, conductive projection 127 and first conductive circuit layer 128 are formed by way of plating.First conductive pole
126th, conductive projection 127 is structure as a whole with first conductive circuit layer.First conductive pole 126 and the conductive projection
127 be substantially in round table-like, and is that the end face diameter of the close loading plate 110 is less than the end of the remote loading plate 110
Face diameter.The height of first conductive pole 126 is much larger than the height of the conductive projection 127.Preferably, described first is conductive
Diameter of the post 126 close to the end face of the loading plate 110 is more than the conductive projection 127 close to the end face of the loading plate 110
Diameter；The diameter for the first engagement pad 121 being electrically connected with first conductive pole 126 is more than the conductive projection 127
Diameter close to the end face of the loading plate 110；Surface of first conductive pole 126 away from the loading plate 110 with it is described
The surface of the remote loading plate 110 of conductive projection 127 is substantially flush.
6th step, referring to Fig. 7, two sides of first conductive circuit layer 128 away from the loading plate 110 according to
The second dielectric layer 129 of secondary formation, the second conductive circuit layer 130, the 3rd dielectric layer 131, the second engagement pad 132, welding resisting layer 135,
So as to form a first circuit board intermediate 200.Wherein, second dielectric layer 129 be bonded in first conductive pole 126,
The surface of conductive projection 127 and first conductive circuit layer 128 away from the loading plate 110.It is same positioned at the loading plate 110
Second conductive circuit layer 130 of side is electrically connected with first conductive circuit layer 128 by multiple phases of second conductive pole 133
Connect, second conductive circuit layer 130 and second engagement pad 132 positioned at the homonymy of loading plate 110 pass through multiple the
Three conductive poles 134 are electrically connected.
Specifically, first, in surface equal joint adhesive of two first conductive circuit layers 128 away from the loading plate 110
Piece, solidify the film and form second dielectric layer 129；Then, in second dielectric layer by way of laser pit
Multiple openings are formed on 129, part first conductive circuit layer 128 is exposed from the opening；Then, electricity is passed through
The mode of plating forms second conductive pole 133 in the opening, and simultaneously in the part table of second dielectric layer 129
Face forms second conductive circuit layer 130；Same method forms the 3rd dielectric layer 131, the 3rd conductive pole 134 and
Two engagement pads 132；Afterwards again the part surface of the surface of the 3rd dielectric layer 131 and each second engagement pad 132 formed it is anti-
Layer 135, second engagement pad 132 exposed to the welding resisting layer 135 are used for and other circuit board electrical connections.Preferably,
Each first engagement pad 121, the thickness of the second engagement pad 132 are all higher than first conductive circuit layer 128 and described second
The thickness of conductive circuit layer 130.
In other embodiments, can be by not forming second dielectric layer 129, the second conductive circuit layer 130 or shape
Second dielectric layer 129, the second conductive circuit layer 130 into multigroup circulation obtain the circuit board package knot of other numbers of plies
Structure；The welding resisting layer 135 can not also be formed.
7th step, referring to Fig. 8, cut along the boundary line of the first area 111 and the second area 112 to be formed it is anti-
First circuit board intermediate 200 after layer 135, and the loading plate 110 and separated type material 115 are separated and removed, obtain two
Individual second circuit board intermediate 210.
Because the copper foil 120 only with the loading plate 110 at first area 111 it is bonding, therefore, along the first area
After 111 cut with the boundary line of the second area 112, the loading plate 110 and separated type material 115 because not with the copper foil
120 is bonding and can remove, so as to obtain the second circuit board intermediates 210 of two phase separations.
8th step, referring to Fig. 9, etching removes the copper foil 120 and metal gear of the second circuit board intermediate 210 respectively
Block 116, an accepting groove 1223 is formed in the position where the metal backup 116, and expose first engagement pad 121 and
The conductive projection 127, so as to obtain chip package base plate 220.
The accepting groove 1223 has the bottom surface 1224 parallel with the first surface 1221 and second surface 1222, institute
State accepting groove 1223 be used for house a chip, the multiple conductive projection 127 protrudes from the bottom surface of the accepting groove 1223
1224, the part that the multiple conductive projection 127 protrudes from the bottom surface 1224 of the accepting groove 1223 is used to electrically connect the core
Piece.
9th step, referring to Fig. 1, in the chip 136 of 127 surface soldered of conductive projection one, make the chip 136 and institute
State conductive projection 127 to electrically connect, in the chip packing-body 102 of surface soldered one of first engagement pad 121, and in the second contact
The surface of pad 132 forms the second soldered ball 139, so as to form the chip-packaging structure 100.
Specifically, first, formed on each surface of the conductive projection 127 away from first conductive circuit layer 128
First soldered ball 137；Afterwards, the chip 136 is welded on first soldered ball 137 so that the chip 136 with it is described
Conductive projection 127 electrically connects；Then, underfill colloid 138 is injected in the side of chip 136 and bottom, with the fixation chip
136, so as to which the chip 136 is packaged in the accepting groove 1223；Then, there is provided a chip packing-body 102, by the core
Piece packaging body 102 is welded in the surface of first engagement pad 121, and forms the second soldered ball on the surface of the second engagement pad 132
139, the chip-packaging structure 100 is formed, the chip-packaging structure 100 for being welded with chip packing-body 102 is a kind of encapsulation
Body laminated construction (package-on-package, POP).Relative to prior art, the chip-packaging structure of the embodiment of the present invention
100th, preparation method and chip package base plate 220 form the accepting groove 1223, and the chip 136 can be encapsulated in the receipts
In tank 1223, so as to reduce the thickness of the chip package base plate and structure, be advantageous to the chip package base plate and
The slimming of structure；In addition, the conductive projection 127 for protruding from bottom surface 1224 of this case can use less weldering in welding chip
Material, so as to reduce the phenomenon that solder extends out, not only contributes to its electric connection, moreover it is possible to which the densification for being advantageous to conductive projection is set
Meter；Further, the use of this case loading plate 110 can form the chip package base plate and structure of no sandwich layer, be also beneficial to described
The slimming of chip package base plate and structure, also, the use of this case loading plate 110 can form two chip package base plates simultaneously
220, it can also further reduce circuit board making cost and improve circuit board making efficiency.
It is understood that for the person of ordinary skill of the art, it can be conceived with the technique according to the invention and done
Go out other various corresponding changes and deformation, and all these changes and deformation should all belong to the protection model of the claims in the present invention
Enclose.
Claims (16)
1. a kind of preparation method of chip-packaging structure, including step：
One copper foil is provided, a metal backup is formed in the presumptive area of the copper foil surface；
Multiple first engagement pads are formed on the surface of the copper foil, wherein, first engagement pad is located at the metal backup
The same surface of the copper foil；
Form one first dielectric layer, make first dielectric layer coat first engagement pad, the metal backup and covering from
The surface for the copper foil being exposed in first engagement pad, the metal backup；Formed in first dielectric layer more
Individual first opening and multiple second openings, and multiple grooves are formed on the metal backup, each first engagement pad
In first opening, each second opening is connected with a groove for part；
The first conductive pole is respectively formed in each first opening, in each second opening and the groove communicated therewith
Conductive projection is respectively formed, and the first conductive circuit layer is formed on the surface of first dielectric layer, wherein, first contact
Pad and first conductive circuit layer are electrically connected by first conductive pole, first conductive circuit layer and the conduction
Projection is electrically connected；
The copper foil and the metal backup are removed, exposes first engagement pad, the position shape where the metal backup
Into an accepting groove, the multiple conductive projection protrudes from the bottom surface of the accepting groove；And a chip is contained in the receipts
In tank, and the chip is welded on the conductive projection surface, so as to form the chip-packaging structure.
2. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that by way of laser pit
Multiple first openings, the second opening are formed on first dielectric layer, and is formed on the metal backup multiple recessed
Groove；First conductive pole and the conductive projection are that diameter close to the end face of the copper foil is less than in round table-like
The diameter of end face away from the copper foil.
3. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that the arrangement of the conductive projection is close
Arrangement density of the degree more than first conductive pole.
4. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that first conductive pole, conduction
Projection and first conductive circuit layer are formed by way of plating.
5. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that forming the first conductive pole, leading
After electric projection and the first conductive circuit layer, and before the removal copper foil and the metal backup, in addition to step：
The first conductive circuit layer side sequentially forms the second dielectric layer and the second engagement pad, first conductive circuit layer and described the
Two engagement pads are electrically connected by multiple second conductive poles.
6. the preparation method of chip-packaging structure as claimed in claim 5, it is characterised in that welded on the conductive projection surface
After connecing a chip, also soldered ball is formed on the surface of second engagement pad.
7. the preparation method of chip-packaging structure as claimed in claim 5, it is characterised in that each first engagement pad,
The thickness of two engagement pads is all higher than the thickness of first conductive circuit layer.
8. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that, will after the copper foil is provided
The copper foil is fitted on a loading plate, before the copper foil and the metal backup is removed, first removes the loading plate.
9. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that by electroplating, printing or attach
Form the metal backup.
10. a kind of chip-packaging structure, including：
One first dielectric layer, first dielectric layer include relative first surface and second surface, and first dielectric layer is certainly
The first surface has been internally formed an accepting groove to first dielectric layer；
Multiple first engagement pads, first engagement pad are embedded in first dielectric layer and surface and the first surface
Flush；
One first conductive circuit layer, first conductive circuit layer are formed at the second surface of first dielectric layer；
Multiple first conductive poles, each first conductive pole is through first dielectric layer and electrical connection one described first
Engagement pad and first conductive circuit layer；
Multiple conductive projections, the multiple conductive projection through first dielectric layer and with first conductive circuit layer
Electrical connection, and the multiple conductive projection protrudes from the bottom surface of the accepting groove；And a chip, the chip are contained in described
Electrically connected in accepting groove and with the multiple conductive projection.
11. chip-packaging structure as claimed in claim 10, it is characterised in that first conductive pole and the conductive projection
It is in round table-like, and is that the diameter of the end face of the close first surface is less than the straight of the end face of the remote first surface
Footpath.
12. chip-packaging structure as claimed in claim 10, it is characterised in that the arrangement density of the conductive projection is more than institute
State the arrangement density of the first conductive pole.
13. chip-packaging structure as claimed in claim 10, it is characterised in that also include：
Second dielectric layer, second dielectric layer are formed at the first conductive circuit layer side, and second dielectric layer covers institute
State the first conductive circuit layer and first dielectric layer in first conductive circuit layer；And
Multiple second engagement pads, second engagement pad are formed at the second dielectric layer side, first conductive circuit layer with
Second engagement pad is electrically connected by multiple second conductive poles, and second engagement pad is used to electrically connect a circuit board.
14. chip-packaging structure as claimed in claim 13, it is characterised in that each first engagement pad, the second engagement pad
Thickness be all higher than the thickness of first conductive circuit layer.
15. chip-packaging structure as claimed in claim 10, it is characterised in that also including a chip packing-body, the chip
Packaging body is welded in the first engagement pad surface.
16. a kind of chip package base plate, including：
One first dielectric layer, first dielectric layer include relative first surface and second surface, and first dielectric layer is certainly
The first surface has been internally formed an accepting groove to first dielectric layer；
Multiple first engagement pads, first engagement pad are embedded in first dielectric layer and surface and the first surface
Flush；
One first conductive circuit layer, first conductive circuit layer are formed at the second surface of first dielectric layer；
Multiple first conductive poles, each first conductive pole is through first dielectric layer and electrical connection one described first
Engagement pad and first conductive circuit layer；And
Multiple conductive projections, the multiple conductive projection through first dielectric layer and with first conductive circuit layer
Electrical connection, and the multiple conductive projection protrudes from the bottom surface of the accepting groove, the accepting groove is used to house a chip, institute
State multiple conductive projections be used for electrically connect be contained in the chip in the accepting groove.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410439461.9A CN105448856B (en) | 2014-09-01 | 2014-09-01 | Chip-packaging structure, preparation method and chip package base plate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410439461.9A CN105448856B (en) | 2014-09-01 | 2014-09-01 | Chip-packaging structure, preparation method and chip package base plate |
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| CN105448856B true CN105448856B (en) | 2018-04-06 |
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| CN105792548B (en) * | 2016-05-23 | 2018-12-14 | 上海美维科技有限公司 | A method of ladder slot structure printed circuit board is made with plating and engraving method |
| CN107424973B (en) * | 2016-05-23 | 2020-01-21 | 凤凰先驱股份有限公司 | Package substrate and method for fabricating the same |
| CN106229309B (en) * | 2016-07-20 | 2019-05-07 | 日月光半导体(上海)有限公司 | Package substrate and its manufacturing method |
| CN108231337A (en) * | 2016-12-09 | 2018-06-29 | 乾坤科技股份有限公司 | Electronic module |
| KR20200064551A (en) * | 2018-11-29 | 2020-06-08 | 삼성전기주식회사 | Electronic component |
| CN112151459B (en) * | 2019-06-26 | 2023-03-24 | 庆鼎精密电子（淮安）有限公司 | Package circuit structure and manufacturing method thereof |
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| KR101046394B1 (en) * | 2010-02-03 | 2011-07-05 | 주식회사 하이닉스반도체 | Stack package |
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| JP2002016327A (en) * | 2000-04-24 | 2002-01-18 | Ngk Spark Plug Co Ltd | Wiring board and its manufacturing method |
| CN202839599U (en) * | 2012-08-23 | 2013-03-27 | 江阴长电先进封装有限公司 | Chip-embedded-type three-dimensional wafer-level packaging structure |
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