CN105448856A - Chip package structure, method of making same and chip package substrate - Google Patents
Chip package structure, method of making same and chip package substrate Download PDFInfo
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- CN105448856A CN105448856A CN201410439461.9A CN201410439461A CN105448856A CN 105448856 A CN105448856 A CN 105448856A CN 201410439461 A CN201410439461 A CN 201410439461A CN 105448856 A CN105448856 A CN 105448856A
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Abstract
A method of making a chip package structure comprises the steps of providing a copper foil, and forming a metal stopper on a predetermined region of the surface of the copper foil; sequentially forming a plurality of contact pads and a dielectric layer on the surface of the copper foil; forming a plurality of dielectric layer openings in the dielectric layer and forming a plurality of grooves in the metal stopper, some dielectric layer openings communicating with the grooves respectively; forming conductive columns in the some dielectric layer openings, forming a conductive projections in the communicated grooves and the dielectric layer openings, and forming a conductive circuit layer on the surface of the dielectric layer; removing the copper foil and the metal stopper, and forming an accommodating groove in the position of the metal stopper, with the plurality of conductive projections projecting from the bottom of the accommodating groove; and accommodating a chip in the accommodating groove and welding to the surface of the conductive projections in the accommodating groove to form the chip package structure. The invention further relates to a chip package substrate and structure.
Description
Technical field
The present invention relates to circuit board making field, particularly relate to a kind of chip-packaging structure, manufacture method and chip package base plate.
Background technology
Chip package base plate can be chip and provides the effects such as electrical connection, protection, support, heat radiation, assembling, to realize many pinizations, reduces encapsulating products volume, improves the object of electrical property and thermal diffusivity, super-high density or multi-chip module.Normally, chip package base plate put connect chip after form chip-packaging structure, wherein, the chip in chip-packaging structure protrudes from chip package base plate, thus the integral thickness of chip-packaging structure is increased, and is unfavorable for the miniaturized design of chip-packaging structure.
Summary of the invention
Therefore, be necessary to provide a kind of thinner chip-packaging structure, manufacture method and chip package base plate.
A manufacture method for chip-packaging structure, comprises step: provide a Copper Foil, forms a metal backup in the presumptive area of described copper foil surface; Form multiple first contact pad on the surface of described Copper Foil, wherein, described first contact pad and described metal backup are positioned at the same surface of described Copper Foil; Form one first dielectric layer, the surface of the described Copper Foil that coated described first contact pad of described first dielectric layer, described metal backup and covering are come out from described first contact pad, described metal backup; Multiple first dielectric layer opening and multiple second dielectric layer opening is formed at described first dielectric layer, and multiple groove is formed on described metal backup, each described first contact pad all part is exposed in described first dielectric layer opening, and each described second dielectric layer opening is all connected with a described groove; The first conductive pole is all formed in each described first dielectric layer opening, all conductive projection is formed in each described second dielectric layer opening and the groove that is communicated with it, and form the first conductive circuit layer on the surface of described first dielectric layer, wherein, described first contact pad and described first conductive circuit layer are electrically connected by described first conductive pole, and described first conductive circuit layer and described conductive projection are electrically connected; Remove described Copper Foil and described metal backup, expose described first contact pad, the position at described metal backup place defines an accepting groove, and described multiple conductive projection all protrudes from the bottom surface of described accepting groove; And a chip is contained in described accepting groove, and by described chips welding in surperficial at described conductive projection, thus form described chip-packaging structure.
A kind of chip-packaging structure, comprises one first dielectric layer, multiple first contact pad, one first conductive circuit layer, multiple first conductive pole, multiple conductive projection and a chip.Described first dielectric layer comprises relative first surface and second surface, and described first dielectric layer is formed with an accepting groove from described first surface to described first dielectric layer inside.Described first contact pad is embedded in described first dielectric layer and surface flushes with described first surface.Described first conductive circuit layer is formed at the second surface of described first dielectric layer.Each described first conductive pole all runs through described first dielectric layer and is electrically connected described first contact pad and described first conductive circuit layer.Described multiple conductive projection all runs through described first dielectric layer and is all electrically connected with described first conductive circuit layer, and described multiple conductive projection all protrudes from the bottom surface of described accepting groove.Described chip to be contained in described accepting groove and to be electrically connected with described multiple conductive projection.
A kind of chip package base plate, comprises one first dielectric layer, multiple first contact pad, one first conductive circuit layer, multiple first conductive pole and multiple conductive projection.Described first dielectric layer comprises relative first surface and second surface, and described first dielectric layer is formed with an accepting groove from described first surface to described first dielectric layer inside.Described first contact pad is embedded in described first dielectric layer and surface flushes with described first surface.Described first conductive circuit layer is formed at the second surface of described first dielectric layer.Each described first conductive pole all runs through described first dielectric layer and is electrically connected described first contact pad and described first conductive circuit layer.Described multiple conductive projection all runs through described first dielectric layer and is all electrically connected with described first conductive circuit layer, and described multiple conductive projection all protrudes from the bottom surface of described accepting groove, described accepting groove is for accommodating a chip, and described multiple conductive projection is for being electrically connected the described chip be contained in described accepting groove.
Relative to prior art, the embodiment of the present invention defines described accepting groove at chip-packaging structure, its manufacture method and chip package base plate, chip can be encapsulated in described accepting groove, thus the thickness of described chip package base plate and structure can be reduced, be conducive to the slimming of described chip package base plate and structure; In addition, common chip package base plate all needs to form conductive pad to be electrically connected chip, and the conductive projection protruding from bottom surface of this case can substitute conductive pad electrical connection chip, thus decreases circuit board making step and cost of manufacture.
Accompanying drawing explanation
Fig. 1 is the cutaway view being welded with the chip-packaging structure of chip that first embodiment of the invention provides.
Fig. 2 is the cutaway view after second embodiment of the invention is provided in Copper Foil that loading plate fits.
Copper foil surface in Fig. 2 is formed the cutaway view after metal backup by Fig. 3.
Fig. 4 is the cutaway view after the copper foil surface of Fig. 3 forms the first contact pad.
Fig. 5 is the cutaway view after copper foil surface in the diagram forms the first dielectric layer, dielectric layer opening, metal backup groove.
Fig. 6 forms conductive pole in dielectric layer opening in Figure 5 and groove, and the first dielectric layer surface forms cutaway view after the first conductive circuit layer.
The first conductive circuit layer surface in Fig. 6 is formed second, third dielectric layer, the second conducting wire plate, the second contact pad, the cutaway view of the first circuit board intermediate obtained after welding resisting layer by Fig. 7.
Fig. 8 is the cutaway view of the second circuit board intermediate obtained after the loading plate of the second circuit board intermediate in Fig. 7 and separated type material being removed.
Fig. 9 is the cutaway view of the chip package base plate obtained after the Copper Foil of the second circuit board intermediate in Fig. 7 and metal backup being removed.
Main element symbol description
| Chip-packaging structure | 100 |
| First dielectric layer | 122 |
| First surface | 1221 |
| Second surface | 1222 |
| Accepting groove | 1223 |
| Bottom surface | 1224 |
| First contact pad | 121 |
| First conductive circuit layer | 128 |
| First conductive pole | 126 |
| Conductive projection | 127 |
| Second dielectric layer | 129 |
| Second conductive circuit layer | 130 |
| 3rd dielectric layer | 131 |
| Second contact pad | 132 |
| Second conductive pole | 133 |
| 3rd conductive pole | 134 |
| Chip | 136 |
| First soldered ball | 137 |
| Underfill colloid | 138 |
| Welding resisting layer | 135 |
| Chip packing-body | 102 |
| Second soldered ball | 139 |
| Loading plate | 110 |
| Copper Foil | 120 |
| First area | 111 |
| Second area | 112 |
| 3rd region | 113 |
| Glue-line | 114 |
| Separated type material | 115 |
| Metal backup | 116 |
| First dielectric layer opening | 123 |
| Second dielectric layer opening | 124 |
| Groove | 125 |
| First circuit board intermediate | 200 |
| Second circuit board intermediate | 210 |
| Chip package base plate | 220 |
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Refer to Fig. 1, first embodiment of the invention provides a kind of chip-packaging structure 100, comprise: one first dielectric layer 122, described first dielectric layer 122 comprises relative first surface 1221 and second surface 1222, described first dielectric layer 122 is formed with an accepting groove 1223 from described first surface 1221 to described first dielectric layer 122 inside, and described accepting groove 1223 has the bottom surface 1224 paralleled with described first surface 1221 and second surface 1222; Multiple first contact pad 121, described first contact pad 121 is embedded in described first dielectric layer 122 and surface and flushes with described first surface 1221; One first conductive circuit layer 128, described first conductive circuit layer 128 is formed at the second surface 1222 of described first dielectric layer 122; Multiple first conductive pole 126, described multiple first conductive pole 126 runs through described first dielectric layer 122 respectively and is electrically connected described first contact pad 121 and described first conductive circuit layer 128; Multiple conductive projection 127, described multiple conductive projection 127 all runs through described first dielectric layer 122 and is electrically connected with described first conductive circuit layer 128, and described multiple conductive projection 127 all protrudes from the bottom surface 1224 of described accepting groove 1223, the end face diameter of described first conductive circuit layer 128 of connection of described conductive projection 127 is greater than the end face diameter away from described first conductive circuit layer 128; One second dielectric layer 129, described second dielectric layer 129 is formed at the surface of described first conductive circuit layer 128 away from described first dielectric layer 122, and described second dielectric layer 129 covers described first conductive circuit layer 128 and is exposed to described first dielectric layer 122 in described first conductive circuit layer 128; One second conductive circuit layer 130, described second conductive circuit layer 130 is formed at the surface of described second dielectric layer 129 away from described first dielectric layer 122, and described second conductive circuit layer 130 is electrically connected with described first conductive circuit layer 128 by multiple second conductive pole 133; One the 3rd dielectric layer 131, described 3rd dielectric layer 131 is formed at the surface of described second conductive circuit layer 130 away from described second dielectric layer 129, and described 3rd dielectric layer 131 covers described second conductive circuit layer 130 and is exposed to described second dielectric layer 129 in described second conductive circuit layer 130; Multiple second contact pad 132, described second contact pad 132 is formed at the surface of described 3rd dielectric layer 131 away from described second dielectric layer 129, described second contact pad 132 is electrically connected with described second conductive circuit layer 130 by multiple 3rd conductive pole 134, described first contact pad 121 surface is formed with the second soldered ball 139, for being electrically connected a circuit board; One welding resisting layer 135, described welding resisting layer 135 is formed at the surface of described 3rd dielectric layer 131 away from described second dielectric layer 129, and described second contact pad 132 comes out from described welding resisting layer 135; At least one chip 136, described chip 136 is electrically connected with described conductive projection 127 by multiple first soldered ball 137, the side of described chip 136 and bottom are formed with underfill colloid (underfill) 138, described chip 136, or to flush with the surface of described first contact pad 121 away from described 3rd dielectric layer 131 lower than the surface of described first contact pad 121 away from described 3rd dielectric layer 131 away from the surface of described 3rd dielectric layer 131; One chip packing-body 102, described chip packing-body 102 is welded in described first contact pad surface.
Refer to Fig. 2-9, second embodiment of the invention provides a kind of manufacture method of said chip encapsulating structure 100, comprises the steps:
The first step, refers to Fig. 2, provides a loading plate 110, covers Copper Foil 120 respectively in the relative both sides of described loading plate 110, and only edge and described loading plate 110 are affixed to make described Copper Foil 120.
Described loading plate 110 can be the rigid support materials such as resin plate, ceramic wafer, metallic plate.Described loading plate 110 people, for being divided into three regions, is respectively the first area 111 of peripheral annular, the second area 112 of the ring-type connected with first area 111, and the 3rd region 113 of enclosing in second area 112.Described first area 111 is garbage area, needs to remove in chip-packaging structure 100 manufacturing process.Described 3rd region 113 corresponds to the region of pasting chip.Be appreciated that each intermediate products in described chip-packaging structure 100 manufacturing process all can continue to use the division of above-mentioned zone.
The step of laminating Copper Foil 120 comprises: first, two glue-lines 114 are provided, wherein, shape and the size of the shape of described glue-line 114 and size and described loading plate 110 are all identical, two described glue-lines 114 are fitted in respectively two apparent surfaces of described loading plate 110, and described glue-line 114 is alignd with described loading plate 110; Afterwards, two separated type materials 115 are provided, the size of described separated type material 115 is less than the size of described loading plate 110, two described separated type materials 115 is fitted in respectively the centre position of two described glue-lines 114, and makes the described glue-line 114 that exposes from described separated type material 115 periphery in the form of a ring; Two Copper Foils 120 are provided, two described Copper Foils 120 are fitted in the apparent surface of described loading plate 110 respectively by the glue-line 114 of described ring-type, thus, make described Copper Foil 120 only edge and described loading plate 110 bonding.Wherein, described separated type material 115 can be resinae release film, metal forming/plate etc.
In other embodiments, described separated type material 115 of also can not fitting, and the glue-line of a ring-type is only provided, make described Copper Foil 120 only edge and described loading plate 110 bonding.
Second step, refers to Fig. 3, and the surface of two in the 3rd region 113 described Copper Foils 120 forms metal backup 116 respectively.
Wherein, described metal backup 116 can be formed by modes such as plating, printing or attachings.Described metal backup 116 is roughly square, and its thickness is greater than the thickness with chip to be mounted.Preferably, the material of described metal backup 116 is the metal beyond copper, be more preferably zinc, during so that described metal backup 116 can be removed by the etching solution different from copper etchant solution etching in subsequent step, thus copper circuit board needing retain can not be etched into.
3rd step, refers to Fig. 4, and the surface of two in second area 112 described Copper Foils 120 all makes and forms multiple first contact pad 121.
Particularly, first, the surface of two in second area 112 described Copper Foils 120 all forms the anti-film plating layer (not shown) of patterning, makes the described Copper Foil 120 that comes out from the anti-film plating layer of patterning corresponding with multiple first contact pads 121 that will be formed; Afterwards, electroplate thus form electrodeposited coating on the surface of the described Copper Foil 120 come out from the anti-film plating layer of patterning, described electrodeposited coating is the first contact pad 121; Then, the anti-film plating layer of described patterning is removed.
Preferably, the cross section that described first contact pad 121 is parallel with described loading plate 110 is circular.
4th step, refer to Fig. 5, the first dielectric layer 122 is all formed in the side away from described loading plate 110 of described first contact pad 121 of loading plate 110 both sides, wherein, coated described first contact pad 121 of described first dielectric layer 122, described metal backup 116 and cover the surface of described Copper Foil 120 of coming out from described first contact pad 121, described metal backup 116; Form multiple first dielectric layer opening 123 and multiple second dielectric layer opening 124 at described first dielectric layer 122, and form multiple groove 125 on described metal backup 116.Wherein, all described with one the first contact pad 121 of each described first dielectric layer opening 123 is corresponding, and each described first contact pad 121 is all partly exposed in described first dielectric layer opening 123; Described multiple second dielectric layer opening 124 is all formed at described second area, and all described with one groove 125 of each described second dielectric layer opening 124 is connected.
Particularly, first, all fitting film solidify described film in the both sides of the described loading plate 110 after formation first contact pad 121, thus forms described first dielectric layer 122; Afterwards, on described first dielectric layer 122, form multiple described first dielectric layer opening 123, second dielectric layer opening 124 by the mode of laser pit, and form multiple groove 125 on described metal backup 116.Described film can be the prepreg containing reinforcing material such as glass fiber fabric base, paper substrate, composite base, aramid fiber nonwoven fabric base or synthetic fibers base, also can be the prepreg of pure resin, described film can transfer solid state to from semi-cured state after the hot processing procedures such as hot pressing or heat baking.
5th step, refer to Fig. 6, the first conductive pole 126 is all formed in each described first dielectric layer opening 123, in each described second dielectric layer opening 124 and the groove 125 that is communicated with it, all form conductive projection 127, and form the first conductive circuit layer 128 on the surface of described first dielectric layer 122.Wherein, described first contact pad 121 and described first conductive circuit layer 128 that are positioned at described loading plate 110 homonymy are electrically connected by described first conductive pole 126 of homonymy, and described first conductive circuit layer 128 being positioned at described loading plate 110 homonymy is also electrically connected with described conductive projection 127.
The arrangement density of described conductive projection 127 is greater than the arrangement density of described first conductive pole 126, and also, the spacing between adjacent two described conductive projections 127 is less than the spacing between adjacent two described first conductive poles 126.Described first conductive pole 126, conductive projection 127 and described first conductive circuit layer 128 are formed by the mode of plating.Described first conductive pole 126, conductive projection 127 are structure as a whole with described first conductive circuit layer.Described first conductive pole 126 and described conductive projection 127 are all roughly in round table-like, and the end face diameter being close described loading plate 110 is less than the end face diameter away from described loading plate 110.The height of described first conductive pole 126 is much larger than the height of described conductive projection 127.Preferably, described first conductive pole 126 is greater than the diameter of described conductive projection 127 near the end face of described loading plate 110 near the diameter of the end face of described loading plate 110; With described first conductive pole 126 be electrically connected the diameter of the first contact pad 121 be greater than the diameter of described conductive projection 127 near the end face of described loading plate 110; Described first conductive pole 126 roughly flushes away from the surface of described loading plate 110 and the surface away from described loading plate 110 of described conductive projection 127.
6th step, refer to Fig. 7, described in two, the first conductive circuit layer 128 forms the second dielectric layer 129, second conductive circuit layer 130, the 3rd dielectric layer 131, second contact pad 132, welding resisting layer 135 all successively away from the side of described loading plate 110, thus forms a first circuit board intermediate 200.Wherein, described second dielectric layer 129 is bonded in described first conductive pole 126, conductive projection 127 and described first conductive circuit layer 128 surface away from described loading plate 110.Described second conductive circuit layer 130 being positioned at described loading plate 110 homonymy is electrically connected by multiple second conductive pole 133 with described first conductive circuit layer 128, and described second conductive circuit layer 130 being positioned at described loading plate 110 homonymy is electrically connected by multiple 3rd conductive pole 134 with described second contact pad 132.
Particularly, first, described in two, the first conductive circuit layer 128 all to be fitted film away from the surface of described loading plate 110, solidifies described film and forms described second dielectric layer 129; Then, on described second dielectric layer 129, form multiple dielectric layer opening by the mode of laser pit, described first conductive circuit layer 128 of part is come out from described dielectric layer opening; Then, in described dielectric layer opening, form described second conductive pole 133 by the mode of plating, and form described second conductive circuit layer 130 at the part surface of described second dielectric layer 129 simultaneously; Same method forms described 3rd dielectric layer the 131, three conductive pole 134 and the second contact pad 132; The part surface of described 3rd dielectric layer 131 surface and each second contact pad 132 forms welding resisting layer 135 more afterwards, is exposed to described second contact pad 132 of described welding resisting layer 135 for being electrically connected with other circuit boards.Preferably, the thickness of each described first contact pad 121, second contact pad 132 is all greater than the thickness of described first conductive circuit layer 128 and described second conductive circuit layer 130.
In other embodiments, can by not forming described second dielectric layer 129, second conductive circuit layer 130 or forming the circuit board package structure that described second dielectric layer 129, second conductive circuit layer 130 organizing circulation obtains other numbers of plies more; Described welding resisting layer 135 can not also be formed.
7th step, refer to Fig. 8, cut the first circuit board intermediate 200 after forming welding resisting layer 135 along described first area 111 with the boundary line of described second area 112, and described loading plate 110 and separated type material 115 are separated removal, obtain two second circuit board intermediates 210.
Because described Copper Foil 120 is only bonding at first area 111 place with described loading plate 110, therefore, after cutting along described first area 111 and the boundary line of described second area 112, described loading plate 110 and separated type material 115 can be removed because of not bonding with described Copper Foil 120, thus can obtain two second circuit board intermediates 210 be separated.
8th step, refer to Fig. 9, Copper Foil 120 and the metal backup 116 of described second circuit board intermediate 210 is removed in etching respectively, an accepting groove 1223 is formed in the position at described metal backup 116 place, and expose described first contact pad 121 and described conductive projection 127, thus obtain chip package base plate 220.
Described accepting groove 1223 has the bottom surface 1224 paralleled with described first surface 1221 and second surface 1222, described accepting groove 1223 is for accommodating a chip, described multiple conductive projection 127 all protrudes from the bottom surface 1224 of described accepting groove 1223, and described multiple conductive projection 127 protrudes from the part of the bottom surface 1224 of described accepting groove 1223 for being electrically connected described chip.
9th step, refer to Fig. 1, at described conductive projection 127 surface soldered one chip 136, described chip 136 is electrically connected with described conductive projection 127, at surface soldered one chip packing-body 102 of described first contact pad 121, and form the second soldered ball 139 on the surface of the second contact pad 132, thus form described chip-packaging structure 100.
Particularly, first, the first soldered ball 137 is formed at each described conductive projection 127 away from the surface of described first conductive circuit layer 128; Afterwards, described chip 136 is welded on described first soldered ball 137, thus described chip 136 is electrically connected with described conductive projection 127; Then, inject underfill colloid 138 in chip 136 side and bottom, with fixing described chip 136, thus described chip 136 is packaged in described accepting groove 1223; Then, one chip packing-body 102 is provided, described chip packing-body 102 is welded in the surface of described first contact pad 121, and form the second soldered ball 139 on the surface of the second contact pad 132, form described chip-packaging structure 100, the chip-packaging structure 100 being welded with chip packing-body 102 is a kind of packaging body laminated construction (package-on-package, POP).Relative to prior art, the chip-packaging structure 100 of the embodiment of the present invention, manufacture method and chip package base plate 220 define described accepting groove 1223, described chip 136 can be encapsulated in described accepting groove 1223, thus the thickness of described chip package base plate and structure can be reduced, be conducive to the slimming of described chip package base plate and structure; In addition, the conductive projection 127 protruding from bottom surface 1224 of this case can use less solder when welding chip, thus the phenomenon that reduction solder extends out, be not only conducive to it and be electrically connected, the densification design of conductive projection can also be conducive to; Further, the use of this case loading plate 110 can form chip package base plate without sandwich layer and structure, also the slimming of described chip package base plate and structure is conducive to, and, this case loading plate 110 uses can form two chip package base plates 220 simultaneously, can also reduce circuit board making cost further and improve circuit board making efficiency.
Be understandable that, for the person of ordinary skill of the art, other various corresponding change and distortion can be made by technical conceive according to the present invention, and all these change the protection range that all should belong to the claims in the present invention with distortion.
Claims (17)
1. a manufacture method for chip-packaging structure, comprises step:
One Copper Foil is provided, forms a metal backup in the presumptive area of described copper foil surface;
Form multiple first contact pad on the surface of described Copper Foil, wherein, described first contact pad and described metal backup are positioned at the same surface of described Copper Foil;
Form one first dielectric layer, the surface of the described Copper Foil that coated described first contact pad of described first dielectric layer, described metal backup and covering are come out from described first contact pad, described metal backup;
Multiple first dielectric layer opening and multiple second dielectric layer opening is formed at described first dielectric layer, and multiple groove is formed on described metal backup, each described first contact pad all part is exposed in described first dielectric layer opening, and each described second dielectric layer opening is all connected with a described groove;
The first conductive pole is all formed in each described first dielectric layer opening, all conductive projection is formed in each described second dielectric layer opening and the groove that is communicated with it, and form the first conductive circuit layer on the surface of described first dielectric layer, wherein, described first contact pad and described first conductive circuit layer are electrically connected by described first conductive pole, and described first conductive circuit layer and described conductive projection are electrically connected;
Remove described Copper Foil and described metal backup, expose described first contact pad, the position at described metal backup place defines an accepting groove, and described multiple conductive projection all protrudes from the bottom surface of described accepting groove; And
One chip is contained in described accepting groove, and by described chips welding in surperficial at described conductive projection, thus form described chip-packaging structure.
2. the manufacture method of chip-packaging structure as claimed in claim 1, it is characterized in that, on described first dielectric layer, form multiple described first dielectric layer opening, the second dielectric layer opening by the mode of laser pit, and form multiple groove on described metal backup; Described first conductive pole and described conductive projection are all roughly in round table-like, and the diameter being the end face of close described Copper Foil is less than the diameter of the end face away from described Copper Foil.
3. the manufacture method of chip-packaging structure as claimed in claim 1, it is characterized in that, the arrangement density of described conductive projection is greater than the arrangement density of described first conductive pole.
4. the manufacture method of chip-packaging structure as claimed in claim 1, is characterized in that, described first conductive pole, conductive projection and described first conductive circuit layer are formed by the mode of plating.
5. the manufacture method of chip-packaging structure as claimed in claim 1, it is characterized in that, after formation first conductive pole, conductive projection and the first conductive circuit layer, and before removing described Copper Foil and described metal backup, also comprise step: form the second dielectric layer and the second contact pad successively in described first conductive circuit layer side, described first conductive circuit layer and described second contact pad are electrically connected by multiple second conductive pole.
6. the manufacture method of chip-packaging structure as claimed in claim 5, is characterized in that, after described conductive projection surface soldered one chip, also forms soldered ball on the surface of described second contact pad.
7. the manufacture method of chip-packaging structure as claimed in claim 5, it is characterized in that, the thickness of each described first contact pad, the second contact pad is all greater than the thickness of described first conductive circuit layer.
8. the manufacture method of chip-packaging structure as claimed in claim 1, is characterized in that, after providing described Copper Foil, fitted in by described Copper Foil on a loading plate, before the described Copper Foil of removal and described metal backup, first removes described loading plate.
9. the manufacture method of chip-packaging structure as claimed in claim 1, is characterized in that, forms described metal backup by plating, printing or attaching.
10. a chip-packaging structure, comprising:
One first dielectric layer, described first dielectric layer comprises relative first surface and second surface, and described first dielectric layer is formed with an accepting groove from described first surface to described first dielectric layer inside;
Multiple first contact pad, described first contact pad is embedded in described first dielectric layer and surface flushes with described first surface;
One first conductive circuit layer, described first conductive circuit layer is formed at the second surface of described first dielectric layer;
Multiple first conductive pole, each described first conductive pole all runs through described first dielectric layer and is electrically connected described first contact pad and described first conductive circuit layer;
Multiple conductive projection, described multiple conductive projection all runs through described first dielectric layer and is all electrically connected with described first conductive circuit layer, and described multiple conductive projection all protrudes from the bottom surface of described accepting groove; And
One chip, described chip to be contained in described accepting groove and to be electrically connected with described multiple conductive projection.
11. chip-packaging structures as claimed in claim 10, is characterized in that, described first conductive pole and described conductive projection are all roughly in round table-like, and the diameter being the end face of close described first surface is less than the diameter of the end face away from described first surface.
12. chip-packaging structures as claimed in claim 10, is characterized in that, the arrangement density of described conductive projection is greater than the arrangement density of described first conductive pole.
13. chip-packaging structures as claimed in claim 10, is characterized in that, also comprise:
Second dielectric layer, described second dielectric layer is formed at described first conductive circuit layer side, described first dielectric layer that described second dielectric layer covers described first conductive circuit layer and is exposed in described first conductive circuit layer; And
Multiple second contact pad, described second contact pad is formed at described second dielectric layer side, and described first conductive circuit layer and described second contact pad are electrically connected by multiple second conductive pole, and described second contact pad is for being electrically connected a circuit board.
14. chip-packaging structures as claimed in claim 13, is characterized in that, the thickness of each described first contact pad, the second contact pad is all greater than the thickness of described first conductive circuit layer.
15. chip-packaging structures as claimed in claim 10, is characterized in that, also comprise a chip packing-body, and described chip packing-body is welded in described first contact pad surface.
16. chip-packaging structures as claimed in claim 10, is characterized in that, the material of described metal backup is zinc.
17. 1 kinds of chip package base plates, comprising:
One first dielectric layer, described first dielectric layer comprises relative first surface and second surface, and described first dielectric layer is formed with an accepting groove from described first surface to described first dielectric layer inside;
Multiple first contact pad, described first contact pad is embedded in described first dielectric layer and surface flushes with described first surface;
One first conductive circuit layer, described first conductive circuit layer is formed at the second surface of described first dielectric layer;
Multiple first conductive pole, each described first conductive pole all runs through described first dielectric layer and is electrically connected described first contact pad and described first conductive circuit layer; And
Multiple conductive projection, described multiple conductive projection all runs through described first dielectric layer and is all electrically connected with described first conductive circuit layer, and described multiple conductive projection all protrudes from the bottom surface of described accepting groove, described accepting groove is for accommodating a chip, and described multiple conductive projection is for being electrically connected the described chip be contained in described accepting groove.
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| CN201410439461.9A CN105448856B (en) | 2014-09-01 | 2014-09-01 | Chip-packaging structure, preparation method and chip package base plate |
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| CN106229309A (en) * | 2016-07-20 | 2016-12-14 | 日月光半导体(上海)有限公司 | Base plate for packaging and manufacture method thereof |
| CN107424973A (en) * | 2016-05-23 | 2017-12-01 | 恒劲科技股份有限公司 | Package substrate and its preparation method |
| CN108231755A (en) * | 2016-12-09 | 2018-06-29 | 乾坤科技股份有限公司 | Electronic module |
| CN111243861A (en) * | 2018-11-29 | 2020-06-05 | 三星电机株式会社 | Electronic assembly |
| CN112151459A (en) * | 2019-06-26 | 2020-12-29 | 庆鼎精密电子（淮安）有限公司 | Package circuit structure and manufacturing method thereof |
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| CN105792548A (en) * | 2016-05-23 | 2016-07-20 | 上海美维科技有限公司 | Method for manufacturing printed circuit board with stepped slot structure through electroplating and etching method |
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| CN106229309B (en) * | 2016-07-20 | 2019-05-07 | 日月光半导体(上海)有限公司 | Package substrate and its manufacturing method |
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| CN111243861A (en) * | 2018-11-29 | 2020-06-05 | 三星电机株式会社 | Electronic assembly |
| CN112151459A (en) * | 2019-06-26 | 2020-12-29 | 庆鼎精密电子（淮安）有限公司 | Package circuit structure and manufacturing method thereof |
| CN112151459B (en) * | 2019-06-26 | 2023-03-24 | 庆鼎精密电子（淮安）有限公司 | Package circuit structure and manufacturing method thereof |
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