JP2004319848A - Semiconductor device and its manufacturing process - Google Patents

Semiconductor device and its manufacturing process Download PDF

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JP2004319848A
JP2004319848A JP2003113210A JP2003113210A JP2004319848A JP 2004319848 A JP2004319848 A JP 2004319848A JP 2003113210 A JP2003113210 A JP 2003113210A JP 2003113210 A JP2003113210 A JP 2003113210A JP 2004319848 A JP2004319848 A JP 2004319848A
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semiconductor chip
cavity
copper
substrate
formed
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JP4208631B2 (en
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Takatsugu Komatsu
隆次 小松
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Nippon Micron Kk
日本ミクロン株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a compound function which can be provided as a thin and compact product where a semiconductor chip is mounted on a wiring board while being embedded. <P>SOLUTION: A substrate where a wiring pattern 17 is connected electrically between layers through copper bumps is formed by hot pressing a copper foil provided with copper bumps through a prepreg 20. The wiring pattern 17 is formed on the outer surface of the substrate by etching the copper foil exposed to the outer surface of the substrate according to a specified pattern. One side of the substrate is then counterbored to form a cavity 22 for mounting a semiconductor chip, the end face of a copper bump 16b is exposed to the mounting surface of the semiconductor chip on the inner surface of the cavity 22 and the copper bump 16b and the semiconductor chip 30 are connected electrically. The semiconductor chip 30 is then mounted in the cavity 22 and the cavity 22 is filled with resin 24 thus sealing the semiconductor chip 30. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は半導体装置およびその製造方法に関し、より詳細には銅箔と一体に銅バンプが形成されてなる銅バンプ付き銅箔を用いて形成した半導体装置およびその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof is formed using a copper bumps copper foil formed by copper bumps formed copper foil and integrally more.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
半導体チップを搭載する配線基板は、半導体チップの高集積化とともに配線パターンが高密度に形成される一方、基板の薄型化が図られている。 Wiring board for mounting a semiconductor chip, while the wiring pattern with the high integration of the semiconductor chip are formed at a high density, thinning of the substrate is achieved. また、半導体装置は一つのパッケージに単一の半導体チップを搭載した製品の他に、一つのパッケージに複数の半導体チップを搭載した複合型の製品も製造されている。 Further, the semiconductor device to other products with a single semiconductor chip in one package, also composite products having a plurality of semiconductor chips in one package has been manufactured.
このような配線基板を製造する方法としては、ビアを介して層間で配線パターンを電気的に接続しながら配線パターンを順次積層する、いわゆるビルドアップ法等の製造方法が行われている。 Such a method of wiring for producing a substrate, sequentially stacked electrically connected while the wiring pattern a wiring pattern between layers through vias manufacturing method of a so-called build-up method or the like is performed.
【0003】 [0003]
ところで、最近、銅箔と一体に銅バンプを形成した銅バンプ付き銅箔を用いて、配線基板を形成する方法が提案されている(たとえば、特許文献1、特許文献2参照)。 Recently, using copper bumps copper foil to form a copper bump foil integrally, a method of forming a wiring board has been proposed (e.g., Patent Document 1, Patent Document 2). この銅バンプ付き銅箔は、銅箔をエッチングすることによって配線パターンを形成することができ、銅バンプを層間で配線パターンを電気的に接続するビアとすることにより、配線パターンを積層して形成する配線基板の製造に利用することができる。 The copper bumps copper foil, it is possible to form a wiring pattern by etching the copper foil, by a via for electrically connecting the wiring pattern of copper bumps in layers, and the wiring pattern is laminated it can be utilized for the production of a wiring board.
銅バンプ付き銅箔は厚さ100μm以下といったように薄く形成されるから、配線基板の薄型化を図ることが可能であり、銅バンプが小径に形成されることから配線パターンを高密度に配置することが可能になる。 Since with the copper bumps copper foil is thin as such or less in thickness 100 [mu] m, it is possible to reduce the thickness of the wiring substrate, is arranged at a high density wiring pattern from the copper bumps are formed smaller in diameter it becomes possible. また、銅バンプをビアに使用することにより、レーザ加工によって絶縁層にビア穴を形成したり、めっきを施したりする必要がなく、配線基板を容易に製造することが可能となる。 Further, by using the copper bumps in the via, may be formed via holes in the insulating layer by laser processing, plating it is not necessary or subjected to, it is possible wiring board is easily manufactured.
【0004】 [0004]
一方、本出願人は、配線基板の製造方法として、内層に配線パターンが形成された基板の一方の面側から切削刃によりザグリ加工を施して内層の所要部位を露出させる方法によってキャビティを形成し、キャビティに半導体チップを搭載して配線基板を製造する方法を提案している(たとえば、特許文献3参照)。 On the other hand, the applicant, as a method of manufacturing a wiring substrate, forming a cavity by a method for exposing a predetermined portion of the inner layer is subjected to spot facing by a cutting edge from one side of the substrate on which a wiring pattern is formed in the inner layer It has proposed a method of manufacturing a wiring board by mounting a semiconductor chip in the cavity (e.g., see Patent Document 3). このザグリ加工を利用して半導体チップを搭載するキャビティを形成する方法は、配線基板の変形を防止し、信頼性の高い半導体装置として提供できるという利点がある。 A method of forming a cavity for mounting a semiconductor chip by using the spot facing is to prevent deformation of the wiring board, it can be advantageously provided as a highly reliable semiconductor device.
【0005】 [0005]
【特許文献1】 [Patent Document 1]
特開2001−326459号公報【特許文献2】 JP 2001-326459 Publication [Patent Document 2]
特開2002−26479号公報【特許文献3】 JP 2002-26479 Publication Patent Document 3]
特開2002−26479号公報【0006】 Japanese Unexamined Patent Publication No. 2002-26479 Publication [0006]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
上述したように、内層に配線パターンが形成された基板にザグリ加工を施して半導体チップを搭載するキャビティを形成し、キャビティに半導体チップを搭載して半導体装置を形成する方法は、基板を薄く形成することができれば、半導体装置を薄型化することは可能である。 As described above, the method of the substrate on which a wiring pattern is formed on the inner layer is subjected to spot facing to form a cavity for mounting a semiconductor chip, a semiconductor device by mounting a semiconductor chip in the cavity, the thin substrate formed if it is possible to, it is possible to reduce the thickness of the semiconductor device. しかしながら、従来のビルドアップ法等により配線パターンを積層して形成する配線基板の製造方法の場合は、必ずしも配線基板を効果的に薄く形成することはできないという課題があり、配線基板の製造工程が複雑になるという課題があった。 However, in the case of a method of manufacturing a wiring board formed by laminating a wiring pattern by a conventional build-up process or the like, there is always a problem that it is impossible to effectively form a thin wiring substrate, the manufacturing process of the wiring board there is a problem that becomes complicated.
【0007】 [0007]
また、配線基板に半導体チップを搭載するキャビティを形成するため、キャビティを形成する部位に対応して窓あけした基板を積層して配線基板を製造する方法による場合は、基板を積層した際にキャビティの内側に下層の基板が押し込まれて湾曲した形状になること、またプリプレグを介して基板を積層する際にプリプレグの流れ性が不十分だと、積層した基板間に樹脂の未充填によって隙間が生じたり、プリプレグの流れ性が大きい場合にはキャビティ内に樹脂が滲み出てしまうという課題があった。 Further, in order to form a cavity for mounting a semiconductor chip on a wiring substrate, the case of the method by laminating substrate was drilled window corresponding to the site to form a cavity for producing a wiring board, a cavity when the laminated substrate of the underlying substrate may become curved shape pushed inwardly, also when the insufficient fluidity of the prepreg when stacking the substrates through a prepreg, a gap by unfilled resin between laminated substrate occur or, if the flow properties of the prepreg is large there is a problem that oozes resin into the cavity.
【0008】 [0008]
そこで、本発明はこれらの課題を解決すべくなされたものであり、その目的とするところは、配線パターンを容易に高密度に形成することができ、容易に薄型に形成することができる半導体装置およびその製造方法を提供するにある。 The present invention has been made to solve these problems, it is an object of the wiring pattern can be easily densely formed easily semiconductor device can be formed to be thin and to provide a manufacturing method thereof.
【0009】 [0009]
【課題を解決するための手段】 In order to solve the problems]
上記目的を達成するため、本発明は次の構成を備える。 To achieve the above object, the present invention has following structures.
すなわち、配線基板に形成されたキャビティ内に半導体チップが樹脂により封止されて搭載された半導体装置において、前記配線基板がフィルドビアあるいは内層のパッドを介して層間で配線パターンが電気的に接続され、前記キャビティがザグリ加工されてキャビティ内面の半導体チップの搭載面に前記フィルドビアあるいは内層のパッド端面が露出し、該フィルドビアあるいは内層のパッドの端面と前記半導体チップとが電気的に接続されていることを特徴とする。 In other words, the semiconductor chip in which is formed on the wiring board cavity in a semiconductor device mounted is sealed with a resin, the wiring pattern in an interlayer said wiring board through the filled vias or inner layer of the pad are electrically connected, said cavity is exposed counterbore processed the filled vias or inner layer of the pad end face on the mounting surface of the semiconductor chip cavity inner surface, the the end surface of the filled via or inner layer of the pad semiconductor chip and are electrically connected and features.
【0010】 [0010]
また、配線基板に形成されたキャビティ内に半導体チップが樹脂により封止されて搭載された半導体装置において、前記配線基板が、銅バンプ付き銅箔により配線パターンが形成されるとともに、銅バンプにより層間の配線パターンが電気的に接続して形成され、前記キャビティがザグリ加工され、キャビティ内面の半導体チップの搭載面に前記銅バンプの端面が露出して形成され、該銅バンプの端面と前記半導体チップとが電気的に接続されていることを特徴とする。 In the semiconductor device mounted sealed semiconductor chip with a resin in which is formed on the wiring substrate cavity, the wiring substrate, with the wiring pattern is formed by copper bumps copper foil, an interlayer of copper bumps the formation wiring pattern is electrically connected, wherein the cavity is counterbored, the end surface of the copper bump on the mounting surface of the semiconductor chip cavity inner face is formed by exposing said semiconductor chip and the end surface of the copper bump Doo is characterized in that it is electrically connected.
また、前記配線基板のキャビティが形成された面側の、前記キャビティが形成された領域を含む配線基板の全域が、配線パターンが形成されあるいは回路部品が搭載される回路領域として形成されていることを特徴とする。 Further, the cavity formed surface side of the wiring board, the entire wiring substrate including the area where the cavity is formed, the wiring pattern is formed, or circuit component is formed as a circuit area to be mounted the features.
また、前記銅バンプの端面と半導体チップとが、フリップチップ接続によって電気的に接続されていること、前記銅バンプの端面と半導体チップとがワイヤボンディング接続によって電気的に接続されていることを特徴とする。 Further, features and end face and the semiconductor chip of the copper bumps, that are electrically connected by flip chip connection, that the end face and the semiconductor chip of the copper bumps are electrically connected by wire bonding to.
【0011】 [0011]
また、半導体装置の製造方法において、プリプレグを介して銅バンプ付き銅箔を加圧および加熱して、銅バンプにより層間で配線パターンを電気的に接続した基板を形成し、基板の外面に露出する銅箔を所定パターンにエッチングすることにより、基板の外面に配線パターンを形成し、前記基板の一方の面側からザグリ加工を施して、半導体チップを搭載するキャビティを形成するとともに、キャビティの内面の半導体チップの搭載面に銅バンプの端面を露出させ、該銅バンプと半導体チップとを電気的に接続して、前記キャビティ内に半導体チップを搭載し、キャビティに樹脂を充填して半導体チップを封止することを特徴とする。 In the method for manufacturing a semiconductor device, a copper foil with copper bumps through the prepreg under pressure and heat, the substrate of connecting the wiring pattern layers by copper bumps electrically formed, it is exposed to the outer surface of the substrate by etching a copper foil into a predetermined pattern to form a wiring pattern on the outer surface of the substrate is subjected to a counter boring from one side of the substrate, to form a cavity for mounting a semiconductor chip, the inner surface of the cavity the mounting surface of the semiconductor chip to expose the end surfaces of the copper bumps, and electrically connects the copper bumps and the semiconductor chip, the semiconductor chip is mounted in the cavity, sealing the semiconductor chip by filling a resin into the cavity characterized in that it stop.
また、前記基板のキャビティを形成した面側の全域に所定のパターンで配線パターンを形成することを特徴とする。 Further, and forming a wiring pattern in a predetermined pattern over the entire cavity formed by the surface side of the substrate.
【0012】 [0012]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
以下、本発明の好適な実施の形態について、添付図面とともに詳細に説明する。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. 図1、2は本発明に係る半導体装置の製造方法を示す説明図である。 Figure 2 is an explanatory view showing a method of manufacturing a semiconductor device according to the present invention.
図1(a)は半導体装置を構成する配線基板のコア部分となる樹脂基板10を示す。 Figure 1 (a) shows the resin substrate 10 of the core portion of the wiring board constituting the semiconductor device. この樹脂基板10は両面銅張り基板に貫通孔を形成し、貫通孔にスルーホールめっきを施して貫通孔に導体部12を形成し、基板の両面の銅箔を所定のパターンにエッチングして基板の両面に配線パターン14を形成して得られたものである。 The resin substrate 10 is formed a through hole in the double-sided copper clad substrate is subjected to a through-hole plating the through-hole conductors 12 formed in the through hole, by etching a copper foil both sides of the substrate in a predetermined pattern substrate it is on both sides of those obtained by forming the wiring pattern 14. 導体部12はめっきによって貫通孔を充填するように形成してもよいし、貫通孔の内壁面に導体層を形成して、両面の配線パターン14が電気的に接続されるようにしてもよい。 Conductor portion 12 may be formed so as to fill the through hole by plating, and forming a conductor layer on the inner wall surface of the through-holes, may be both surfaces of the wiring patterns 14 are electrically connected .
【0013】 [0013]
なお、実際の製造工程では多数個取り用の大判の樹脂基板をワークとし、大判のワークに所要の加工を施して半導体装置を製造する。 In practice in the manufacturing process is a large-sized resin substrate for multi-piece a work, to manufacture a semiconductor device by applying predetermined processing to the large-sized workpiece. 図1(a)では、説明上、多数個取り用の樹脂基板のうち個別の半導体装置となる一単位部分を示している。 In FIG. 1 (a), the description illustrates one unit portion which is a separate semiconductor device of the resin substrate for multi-piece. 以下の図においても同様である。 The same applies to the following FIG.
【0014】 [0014]
図1(b)は、樹脂基板10の上層と下層に配線パターンを積層して形成する工程を示している。 FIG. 1 (b) shows a step of forming by stacking a wiring pattern on the upper layer and lower layer of the resin substrate 10. 同図で16、18が配線パターンを形成するために用いる銅バンプ付き銅箔である。 A copper foil copper bumps used for 16, 18 in the figure to form a wiring pattern. 16a、16bが銅バンプ付き銅箔16に一体に形成されている銅バンプ、18aが銅バンプ付き銅箔18に一体に形成されている銅バンプである。 16a, the copper bumps 16b are formed integrally with the copper bumps copper foil 16, 18a is copper bumps formed integrally with the copper bumps with a copper foil 18. 銅バンプ16a、18aは、樹脂基板10に形成されている配線パターン14の平面配置に位置合わせして形成され、銅バンプ16bは基板に搭載される半導体チップの接続電極の平面配置に位置合わせして形成されている。 Copper bumps 16a, 18a are formed in alignment in the plane arrangement of the wiring patterns 14 formed on the resin substrate 10, the copper bumps 16b are aligning and the planar arrangement of the connection electrodes of the semiconductor chip mounted on the substrate It is formed Te.
【0015】 [0015]
なお、本実施形態では半導体チップをフリップチップ接続によって銅バンプ16bと電気的に接続するから、銅バンプ16bは半導体チップの接続電極と同一の平面配置としているが、半導体チップと銅バンプ16bとをワイヤボンディングによって電気的に接続する場合は、半導体チップとのボンディング位置に合わせて銅バンプ16bの配置位置を設定する。 Incidentally, since connecting copper bumps 16b electrically the semiconductor chip by flip chip bonding in this embodiment, although the copper bumps 16b are the same planar arrangement and the connection electrodes of the semiconductor chip, the semiconductor chip and the copper bumps 16b when electrically connected by wire bonding, setting the arrangement position of the copper bumps 16b in accordance with the bonding position of the semiconductor chip.
【0016】 [0016]
図1(b)において、20は銅バンプ付き銅箔16、18を樹脂基板10に一体に接合するためのプリプレグである。 In FIG. 1 (b), 20 is a prepreg for bonding together copper bumps copper foil 16, 18 on the resin substrate 10. 銅バンプ付き銅箔16、18を、プリプレグ20とともに樹脂基板10を両面から挟むようにして加圧および加熱すると、銅バンプ付き銅箔16の銅バンプ16a、18aの頂部が、樹脂基板10に形成されている配線パターン14にくい込み、銅バンプ16a、18aと配線パターン14とが電気的に導通した状態で接合される。 Copper bumps copper foil 16 and 18, when together with the prepreg 20 so as to sandwich the resin substrate 10 from both sides to pressure and heat, the copper bumps 16a of the copper bumps copper foil 16, the top of 18a, are formed in the resin substrate 10 bite into the wiring pattern 14 are, copper bumps 16a, 18a and the wiring pattern 14 are bonded in a state of electrical continuity. 銅バンプ16a、18aは頂部が細径に形成され、配線パターン14にくい込んで電気的導通が確実になされるように形成されている。 Copper bumps 16a, 18a are formed on the top portion diameter, electric conduction is formed so as be reliably bite into the wiring patterns 14.
そして、プリプレグが溶融して硬化することにより、銅バンプ16a、18aが配線パターン14にくい込んだ状態で銅バンプ付き銅箔16、18が樹脂基板10に一体に接合される。 By prepreg is cured by melting, copper bumps 16a, copper bumps copper foil 16, 18 18a in a state that bite into the wiring patterns 14 are integrally bonded to the resin substrate 10. 図1(c)に、銅バンプ付き銅箔16、18がプリプレグ20を介して樹脂基板10に接合された状態を示す。 In FIG. 1 (c), it shows a state where copper bumps copper foil 16, 18 is bonded to the resin substrate 10 through the prepreg 20.
【0017】 [0017]
図2(a)は、樹脂基板10に銅バンプ付き銅箔16、18を接合した後、銅バンプ付き銅箔16の銅箔と銅バンプ付き銅箔18の銅箔を所定パターンにエッチングして配線パターン17、19を形成した状態を示す。 2 (a) it is, after bonding the copper bumps copper foil 16, 18 on the resin substrate 10, by etching the copper foil of a copper foil and copper bumps copper foil 18 of copper bumps with a copper foil 16 in a predetermined pattern showing a state of forming a wiring pattern 17, 19.
銅バンプ付き銅箔16、18は銅箔と銅バンプ16a、16b、18aとがあらかじめ一体形成されているから、銅箔をエッチングして配線パターンを形成することによって銅バンプ16a、16b、18aと電気的に接続した状態で配線パターン17、19を得ることができる。 Copper bumps copper foil 16, 18 copper foil and copper bumps 16a, 16b, because the 18a is previously integrally formed, copper bumps 16a by forming a wiring pattern the copper foil by etching, 16b, and 18a it is possible to obtain a wiring pattern 17, 19 while electrically connected.
【0018】 [0018]
図2(b)は、半導体チップと接続する銅バンプ16bが形成された側とは反対面側である基板の一方の面側から基板をザグリ加工して、半導体チップを搭載するキャビティ22を形成した状態を示す。 2 (b) is the side where the copper bumps 16b are formed to be connected to the semiconductor chip by spot facing the substrate from one side of the substrate which is opposite side, forming a cavity 22 for mounting a semiconductor chip It shows the state. ザグリ加工ではザグリ加工用の切削刃を回転させながら基板の一方の面側から基板内に進入させ、プリプレグ20、樹脂基板10の所要部位を切削してキャビティ22を形成する。 In counterbored is advanced while rotating the cutting blade for counter boring from one side of the substrate in the substrate, the prepreg 20, by cutting the required site of the resin substrate 10 to form a cavity 22.
本実施形態では、基板の下面で起立形状に形成されている銅バンプ16bの端面Aが、キャビティ22の内面の半導体チップを搭載する搭載面に露出するようにザグリ加工する。 In this embodiment, the end surface A of the copper bumps 16b formed in the standing shape on the lower surface of the substrate, which spot facing to be exposed on the mounting surface for mounting a semiconductor chip of the inner surface of the cavity 22. 銅バンプ16bの端面の高さ位置を切削刃により検知しながら、切削刃による切削位置を制御することによって、図のように基板の一方の面側でキャビティ22が開口するように形成することができる。 While detecting the height position of the end surface of the copper bump 16b by cutting edge, by controlling the cutting position by the cutting blade, that a cavity 22 in one side of the substrate as shown in FIG. Is formed so as to open it can.
【0019】 [0019]
ザグリ加工によってキャビティ22を形成した後、銅バンプ16bの露出している端面に、ニッケルめっき、金めっき等の所要のめっきを施し、大判のワークのまま各々のキャビティ22に半導体チップ30を搭載する。 After forming the cavity 22 by spot facing, the end face exposed copper bump 16b, nickel plating, subjecting the required plating such as gold plating, mounting the semiconductor chip 30 to each cavity 22 remains large-sized workpiece . なお、大判のワークを個片に切断した後に、個々に半導体チップ30を搭載してもよい。 Note that after cutting the large-sized workpiece into pieces may be individually mounting the semiconductor chip 30.
図2(c)は、半導体チップ30の接続電極と銅バンプ16bとを位置合わせして、フリップチップ接続によって半導体チップ30を搭載し、その後、半導体チップ30を樹脂24によってアンダーフィルした状態を示す。 FIG. 2 (c) are aligned with the connection electrode and the copper bumps 16b of the semiconductor chip 30, the semiconductor chip 30 is mounted by flip chip bonding, then, shows a state in which the semiconductor chip 30 and the underfill of resin 24 . 図では樹脂24によって半導体チップ30の外面を封止するようにしているが、樹脂24は少なくとも半導体チップ30の接続電極と銅バンプ30との接続部をアンダーフィルできればよく半導体チップ30の外面部分まで完全に封止しなければならないものではない。 Although the figure so as to seal the outer surface of the semiconductor chip 30 by a resin 24, to the outer surface portion of the resin 24 at least the connection electrode and the copper bumps 30 semiconductor chip 30 need only underfill connection portion between the semiconductor chip 30 completely it does not have to be sealed.
【0020】 [0020]
図3は、基板の配線パターン19に外部接続端子26を接合して実装可能な半導体装置を形成した状態を示す。 Figure 3 shows a state in which a mountable semiconductor device by bonding an external connection terminal 26 to the wiring pattern 19 of the substrate. 図3に示す例はフェイスダウン型の半導体装置として形成した例である。 Example shown in FIG. 3 is an example of forming a face-down type semiconductor device. もちろん、半導体装置はフェイスダウン型に限るものではない。 Of course, the semiconductor device is not limited to the face-down type.
銅バンプ16a、18aが層間で配線パターンを電気的に接続するビアとして使用されており、銅バンプ16bは半導体チップ30と配線パターン17とを電気的に接続するビアとして使用されている。 Copper bumps 16a, 18a are used as a via for electrically connecting the wiring pattern layers, the copper bumps 16b is used as a via for electrically connecting the semiconductor chip 30 and the wiring patterns 17.
本実施形態の半導体装置は樹脂基板10をコア部分とし、銅バンプ付き銅箔16、18を利用して形成されたものであり、厚さ0.3〜0.5mm程度のきわめて薄型の半導体装置として得られる。 The semiconductor device of the present embodiment is a resin substrate 10 and the core portion, which is formed by utilizing a copper bump copper foil 16, 18, having a thickness of about 0.3~0.5mm very thin semiconductor device It is obtained as.
【0021】 [0021]
上記実施形態の半導体装置は半導体チップ30をフリップチップ接続によって搭載した例であるが、図4は半導体チップ30をワイヤボンディング接続によって搭載した例を示す。 Although the semiconductor device of the above embodiment is an example of mounting the semiconductor chip 30 by the flip chip connection, Figure 4 shows an example of mounting the semiconductor chip 30 by wire bonding connection. 28がボンディングワイヤである。 28 is a bonding wire. 半導体チップ30をワイヤボンディング接続によって搭載する場合は、キャビティ22内で半導体チップ30を搭載する位置から銅バンプ16bを若干偏位させて配置した銅バンプ付き銅箔を使用するようにすればよい。 When mounting the semiconductor chip 30 by wire bonding connection, it is sufficient to use the copper bumps foil arranged slightly being displaced copper bumps 16b from the position for mounting the semiconductor chip 30 in the cavity 22. 銅バンプ付き銅箔16としてサーマルビアとして利用する銅バンプ16cを形成したものを使用してもよい。 It may be used after forming a copper bump 16c used as a thermal via a copper bumped foil 16. 銅バンプ16cについてもザグリ加工により端面を露出させることで、好適なサーマルビアとして利用することができる。 Also to expose the end face by countersinking process for copper bumps 16c, it can be utilized as a suitable thermal via.
【0022】 [0022]
上述したように、本発明に係る半導体装置の製造方法においては、樹脂基板10と銅バンプ付き銅箔16、18を利用して配線基板を形成した後、ザグリ加工によって半導体チップ30を搭載するキャビティ22を形成している。 As described above, in the method of manufacturing a semiconductor device according to the present invention, which after the formation of the wiring board by using a resin substrate 10 and the copper bumps copper foil 16, the semiconductor chip 30 by spot facing mounting cavity to form a 22. このようにザグリ加工によってキャビティ22を形成する方法による場合は、配線層を積層して形成する工程で基板が反ったりせず、基板を変形させずに製造できることから、薄型の半導体装置を製造する方法としてきわめて有効である。 If by the method of forming the cavity 22 in this manner by the spot facing, not warped a substrate in the step of forming by stacking a wiring layer, since it can be produced without deforming the substrate to produce a thin semiconductor device it is very effective as a method.
また、ザグリ加工による場合は、キャビティ22を形成する際にキャビティの深さ位置を正確に加工することが可能であり、薄型のパッケージであってもキャビティを容易に正確に加工できるという利点がある。 Also, the case of counterbored, it is possible to accurately machined depth position of the cavity in forming a cavity 22, there is an advantage that the cavity be thin package can be easily and accurately machined .
【0023】 [0023]
とくに、本実施形態では、樹脂基板10と銅バンプ付き銅箔16、18を組み合わせて配線基板を形成しているから、従来のビルドアップ法等によって配線パターンを積層して基板を作成する方法と比較して薄型の基板を容易に形成することができるという利点がある。 In particular, in this embodiment, since a combination of the resin substrate 10 and the copper bumps copper foil 16, 18 form a wiring board, a method of making a substrate by laminating a wiring pattern by a conventional build-up process or the like compared to the advantage that it is possible to easily form a thin substrate. 銅バンプ付き銅箔を利用して配線基板を作成する方法の場合は、ビルドアップ法による場合のように絶縁層にレーザ加工を施してビア穴を形成したり、基板にめっきを施して導体層を形成したりする工程が不要になるからである。 For methods utilizing copper bump copper foil to create the wiring board, or a via hole is subjected to laser processing in the insulating layer as in the case of the build-up method, the conductive layer plated on the substrate a step of or form is because unnecessary.
【0024】 [0024]
また、銅バンプ付き銅箔では銅バンプをきわめて小径に形成することが可能であるから、フリップチップ接続における電極配置、ワイヤボンディング接続のボンディング部の配置に合わせて銅バンプを形成することは容易である。 Further, since the copper bumps foil can be formed into very small diameter copper bumps, electrodes arranged in a flip-chip connection, by forming a copper bump in accordance with the arrangement of the bonding portion of the wire bonding connection is easy is there. 銅バンプ付き銅箔を使用して配線基板を形成した場合は、銅バンプが層間で配線パターンを電気的に接続するビアとして利用されることと、銅バンプの端面を露出させるようにザグリ加工するだけで銅バンプの端面が半導体チップとの接続部に形成することができるという利点がある。 If using copper bumps copper foil to form a wiring substrate, which spot facing to the the copper bumps are utilized as a via for electrically connecting the wiring pattern layers to expose the end surface of the copper bump there is an advantage in that it is the end face of the copper bumps alone is formed in the connecting portion between the semiconductor chip. 銅バンプはフィルドビアと同様に端面の全域が導体となっているから、ザグリ加工によって露出する端面の全体が接続用の端子部として利用できるからである。 Copper bumps is because since the entire region of the end face as with the filled via is a conductor, the whole of the end face which is exposed by the spot facing can be used as terminal portions for connection.
【0025】 [0025]
図3、4に示す半導体装置において配線基板の半導体チップ30を搭載した面側については、キャビティ22を形成した領域を除いた領域に配線パターン19が形成されている。 For equipped with side semiconductor chip 30 of the wiring substrate in the semiconductor device shown in FIGS. 3 and 4, the area on the wiring pattern 19 excluding the region formed a cavity 22 is formed. 半導体チップ30は樹脂24によって完全に封止されているから、半導体チップ30を搭載した面側についてはキャビティ22を形成した領域を含めてその全面を配線パターンを形成する領域として利用することが可能である。 Since the semiconductor chip 30 is completely sealed by the resin 24, for mounting the side of the semiconductor chip 30 can be used as a region for forming the entire wiring pattern including a region formed a cavity 22 it is.
【0026】 [0026]
図5は、キャビティ22を形成した領域を含めて基板の全面を配線パターンを形成する領域として利用する半導体装置の製造例を示す。 Figure 5 shows an example of producing a semiconductor device used as a region for forming a wiring pattern on the entire surface of the substrate including the region formed a cavity 22.
図5(a)は、基板にザグリ加工を施して形成したキャビティに半導体チップ30をフリップチップ接続によって搭載し、半導体チップ30を樹脂24によって封止した基板40に、プリプレグ32を介して銅バンプ付き銅箔34を接合する工程を示す。 5 (a) is a copper bump semiconductor chip 30 in the cavity formed by performing spot facing mounted by flip chip bonding, the semiconductor chip 30 to the substrate 40 sealed with a resin 24 to the substrate, via the prepreg 32 showing the step of bonding the attached copper foil 34. この製造方法の場合には、基板40に銅バンプ付き銅箔34を接合するようにするからキャビティ22を樹脂24によって充填するようにしておくのがよい。 In the case of this production method, the cavity 22 from so as to bond the copper bumps copper foil 34 on the substrate 40 good idea so as to fill a resin 24. 銅バンプ付き銅箔34には基板40の一方の端面に形成されている配線パターン19と位置合わせして銅バンプ34aが形成されている。 The copper bumped foil 34 of copper bumps 34a are formed in alignment with one wiring pattern 19 formed on the end face of the substrate 40.
【0027】 [0027]
図5(b)は、プリプレグ32および銅バンプ付き銅箔34を基板40に対して加圧および加熱し、プリプレグ32を介して銅バンプ付き銅箔34を基板40に接合した状態を示す。 FIG. 5 (b), a prepreg 32 and a copper bump copper foil 34 subjected to pressure and heating the substrate 40, the copper bumps copper foil 34 through the prepreg 32 shows a state bonded to the substrate 40.
図5(c)は、銅バンプ付き銅箔34の銅箔34bを所定パターンにエッチングして基板40の一方の面に配線パターン36を形成した状態を示す。 5 (c) shows a copper foil 34b of the copper bumps copper foil 34 is etched into a predetermined pattern either state of forming a wiring pattern 36 on the surface of the substrate 40. 銅箔34をエッチングすることにより、基板40の一方の面の全域を配線パターン36を形成する領域とした半導体装置を得ることができる。 By the copper foil 34 is etched, it is possible to obtain a semiconductor device in which a region for forming the wiring pattern 36 to the entire area of ​​one surface of the substrate 40.
【0028】 [0028]
このように、半導体チップ30を搭載した面側でキャビティ22を形成した領域を含む基板の全域を配線パターンを形成する領域とすることにより、基板内で配線パターンを引き回すことが容易に可能となり、基板の外面上に回路部品を搭載するといった複合化が可能となる。 Thus, by the region for forming the wiring pattern the entire area of ​​the substrate including a region formed a cavity 22 in the semiconductor chip 30 equipped with side, it is easily possible and will be routed wiring pattern in the substrate, it is possible to composite such mounting the circuit component on the outer surface of the substrate. これによって、基板内に半導体チップ30が埋設するようにして搭載され、より複合機能を備えた半導体装置として提供することが可能となる。 Thus, the semiconductor chip 30 is mounted so as to embed in the substrate, it is possible to provide a semiconductor device having a more complex function.
【0029】 [0029]
上記実施形態では、一つのパッケージに一つの半導体チップ30を搭載した例を示したが、一つのパッケージに複数の半導体チップを搭載するように形成することももちろん可能であり、これによってより複合化された半導体装置として提供することが可能となる。 In the above embodiment, an example provided with a single semiconductor chip 30 in a single package, it is also of course possible to form in one package so as to mount a plurality of semiconductor chips, thereby further compounding it is possible to provide a semiconductor device. また、半導体装置にキャパシタや抵抗等の回路部品を搭載することによって、さらに複合機能を備えた半導体装置とすることができる。 Further, by mounting the capacitors and circuit components such as a resistor in a semiconductor device can be further semiconductor device having multiple functions.
一つの半導体装置内に複数の半導体チップや回路部品を搭載する方法としては、一つのキャビティ内に複数の半導体チップや回路部品を搭載する方法も可能であるし、一つの半導体装置内にザグリ加工によって複数のキャビティを形成し、各々のキャビティに一または複数の半導体チップを搭載するといった方法も可能である。 As a method for mounting a plurality of semiconductor chips and circuit components in a single semiconductor device, to a method for mounting a plurality of semiconductor chips and circuit components into one cavity is also possible, spot facing in one semiconductor device a plurality of cavities formed by a method such as mounting one or more semiconductor chips in each of the cavities are possible.
【0030】 [0030]
また、図6は配線基板のコアに樹脂基板10を使用せず、銅バンプ付き銅箔のみを用いて配線基板を形成する例を示す。 Also, FIG. 6 without using a resin substrate 10 into the core of the wiring substrate, an example of forming a wiring board using only the copper foil with the copper bumps.
図6(a)は、プリプレグ20を銅バンプ11aが形成された銅バンプ付き銅箔11と銅箔11bとにより挟む配置とし、加圧および加熱して基板のコア部分を形成する工程を示す。 6 (a) is a prepreg 20 and arranged to sandwich the copper copper bumps foil 11 bumps 11a are formed and the copper foil 11b, pressed and heated to a process of forming a core portion of the substrate. プリプレグ20を介して銅バンプ付き銅箔11と銅箔11bとを一体化した後、銅バンプ付き銅箔11の銅箔部分と銅箔11bとを所定のパターンにエッチングして配線パターン11c、11dを形成してコアとする。 After integrating the copper bumps copper foil 11 and the copper foil 11b through the prepreg 20, the copper bumps copper foil 11 foil portions and the copper foil 11b and etching in a predetermined pattern to the wiring patterns 11c, 11d to form a the core.
【0031】 [0031]
図6(b)は、銅バンプ付き銅箔11を用いて形成したコア部分の両面に、図1(b)に示すと同様に、プリプレグ20を介して銅バンプ付き銅箔16、18を加圧および加熱して圧着する工程を示す。 6 (b) it is, on both surfaces of a core portion formed by using a copper bump copper foil 11, as well as shown in FIG. 1 (b), the copper bumps copper foil 16 through the prepreg 20 pressurized showing the step of pressure bonding with pressure and heat.
図6(c)は、プリプレグ20を介して銅バンプ付き銅箔16、18が一体的に接合された基板を示す。 Figure 6 (c) shows a substrate copper bumps copper foil 16 through the prepreg 20 is integrally joined.
図6(d)は、ザグリ加工により基板にキャビティ22を形成するとともに、銅バンプ16bの端面を露出させ、半導体チップ30をフリップチップ接続により搭載し、樹脂24により半導体チップ30を封止した状態を示す。 Figure 6 (d) to form a cavity 22 to the substrate by spot facing, state to expose the end surface of the copper bump 16b, and the semiconductor chip 30 is mounted by flip chip bonding, sealing the semiconductor chip 30 by a resin 24 It is shown. このように、樹脂基板を使用せず、銅バンプ付き銅箔のみを用いて基板を形成することも可能である。 Thus, without using a resin substrate, it is also possible to form the substrate using only the copper foil with the copper bumps.
【0032】 [0032]
前述したように、本発明に係る半導体装置の製造方法においては、多数個取り用の大判の基板をワークとして製造することによって、効率的な製造が可能となる。 As described above, in the method for manufacturing a semiconductor device according to the present invention, by producing a large-sized substrate for multi-piece as the work, thereby enabling efficient production. 大判の銅バンプ付き銅箔およびプリプレグを使用し、銅バンプ付き銅箔を位置合わせするようにして加圧および加熱して大判の基板を形成し、ザグリ加工を施して半導体チップ30を搭載するキャビティを形成すると同時に半導体チップ30と電気的に接続する接続部を形成することにより、きわめて効率的に半導体装置を製造することが可能となる。 Using the large-sized copper bumps copper foil and prepreg, copper bumps copper foil so as to align pressure and heat to form a large-sized substrate, mounting a semiconductor chip 30 is subjected to spot facing cavity simultaneously makes a by forming a semiconductor chip 30 electrically connected portion connected, it is possible to produce very efficiently a semiconductor device.
【0033】 [0033]
なお、上記実施形態においては銅バンプ付き銅箔の好適利用例として、ザグリ加工を適用して半導体チップあるいはキャパシタ、抵抗等の回路部品を基板内に内蔵した半導体装置の製造方法について説明した。 In the embodiment described above as a preferred example of the use of the copper foil with copper bumps, semiconductor chips or capacitors by applying the spot facing, the circuit components such as resistors and method for manufacturing a semiconductor device having a built-in substrate. 銅バンプ付き銅箔は銅バンプが層間で配線パターン等を電気的に接続する導体(ビア)として有効に使用できること、ザグリ加工した際に銅バンプの端面全体が導体として露出することでフリップチップ接続の端子として好適に利用できるという利点がある。 With copper bump foil is of copper bumps can be effectively used as a conductor (via) for electrically connecting the wiring pattern and the like between layers, flip chip connection in the entire end surface of the copper bumps are exposed as a conductor when the spot facing there is an advantage that the terminal can be suitably used. このことは、銅バンプ付き銅箔に限らず、層間の電気的接続に使用するビアをフィルドビアとして形成した場合も、同様に本発明の半導体装置の製造方法を適用することができる。 This is not limited to copper bumped foil, even when forming the vias used for electrical connection between layers as filled vias, it may be similarly applied to a method of manufacturing a semiconductor device of the present invention. フィルドビアはたとえばめっきよってビア穴を充填する、銅あるいは銀ペーストによって形成するといった方法によって形成できる。 Filled via, for example plating Thus filling the via holes can be formed by methods such as formed by a copper or silver paste.
【0034】 [0034]
なお、フィルドビアによる場合の他に、図7(a)に示すように、内層にパッド状に配線パターン50を設けた積層板に対して、積層板の下面側からレーザ加工によってビア穴を形成し、めっきによりビア穴の内面に導体層を形成してビア形成した後、積層板の上面側からザグリ加工を施して半導体チップ等を収納するキャビティ52を形成する(図7(b))ようにすることも可能である。 In addition to the case of filled via, as shown in FIG. 7 (a), the laminated plate having a wiring pattern 50 on the pad-like in the inner layer to form a via hole by laser processing from the lower surface side of the laminate after via formation by forming a conductor layer on the inner surface of the via hole by plating from the upper surface side of the laminate is subjected to spot facing to form a cavity 52 for housing a semiconductor chip or the like (FIG. 7 (b)) as it is also possible to. ザグリ加工によってキャビティ52の底面に配線パターン50が露出し配線パターン50はビア54を介して基板の外面に形成される接続部と電気的に接続する。 Spot facing the exposed wiring pattern 50 on the bottom surface of the cavity 52 wiring pattern 50 is electrically connected to the connection portion formed on the outer surface of the substrate through a via 54. キャビティ52に半導体チップあるいは回路基板等を搭載した後、プリプレグを積層してキャビティ52を充填し、ビア54の凹部を充填する。 After mounting the semiconductor chip or the circuit board or the like in the cavity 52, by laminating a prepreg filled cavity 52, to fill the recesses of the vias 54. なお、内層のパッド用の配線パターン50を形成せず、ビア穴を形成してビア穴の内面にめっきを施した後、ビア穴の凹部をプリプレグにより充填し、ザグリ加工によりキャビティ52の内定面にビアの端面を露出させるようにしてパッケージを形成することもできる。 Incidentally, without forming the wiring pattern 50 for the inner layer of the pad, after plating the inner surface of the via hole to form a via hole, the recess of the via hole was filled with the prepreg, prospective surface of the cavity 52 by spot facing it is also possible to form a package so as to expose the end surfaces of the vias.
【0035】 [0035]
上述したように、フリップチップ接続によって半導体チップを搭載する場合のように実装用の接続部がきわめて微小間隔で多数個存在するような場合には、接続部分ではんだが他の接続パターンに付着して短絡するといった問題を確実に回避する必要がある。 As described above, when a number in the connection portion is extremely small gap for implementation as in the case of mounting a semiconductor chip by flip-chip connection pieces as present, the solder adheres to the other connection pattern in the connection portion it is necessary to reliably avoid problems such as a short circuit Te. 削り出し加工によってこれらの接続部分を露出させるようにすることは可能であるが、他のパターンとの短絡を防止する方法としては、接続端面のみが露出する形態、すなわち上述したように銅バンプあるいはフィルドビア等の端面を露出させるようにザグリ加工する方法はきわめて有効である。 By machining shaving it is possible to expose these connecting portions, as a method for preventing a short circuit between the other pattern, form only the connection end face is exposed, namely copper bumps or as described above how to spot facing to expose the end face, such as filled via is very effective. 本発明は銅バンプによって層間を接続する場合に限らず、上述したように、フィルドビアあるいは内層のパッドを設けたパッケージを形成する場合にも適用することが可能である。 The present invention is not limited to the case of connecting the layers of copper bumps, as described above, it can also be applied in the case of forming a package having a filled via or inner layer of the pad.
【0036】 [0036]
【発明の効果】 【Effect of the invention】
本発明に係る半導体装置およびその製造方法によれば、配線基板に半導体チップを埋設するようにして搭載した製品としてきわめて薄型でコンパクトな製品として提供することができる。 According to the semiconductor device and the manufacturing method thereof according to the present invention, it can be provided as a compact product with very thin as products equipped so as to embed the semiconductor chip on a wiring board. とくに、銅バンプ付き銅箔を利用することによって、層間で配線パターンを容易に電気的に接続して構成することができ、複合機能を備えた半導体装置としても提供することができる等の著効を奏する。 In particular, by utilizing the copper bumps copper foil, it can be configured easily electrically connect the wiring pattern layers, remarkable effect of such may be provided as a semiconductor device having multiple functions achieve the.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】本発明に係る半導体装置の製造方法を示す説明図である。 It is an explanatory view showing a method for manufacturing a semiconductor device according to the invention; FIG.
【図2】本発明に係る半導体装置の製造方法を示す説明図である。 It is an explanatory view showing a method for manufacturing a semiconductor device according to the invention; FIG.
【図3】外部接続端子を接合した状態の半導体装置の断面図である。 3 is a cross-sectional view of a semiconductor device in a state of bonding the external connection terminal.
【図4】半導体装置の他の実施形態を示す断面図である。 4 is a sectional view showing another embodiment of a semiconductor device.
【図5】半導体装置の他の製造方法を示す説明図である。 5 is an explanatory diagram showing another method of manufacturing the semiconductor device.
【図6】半導体装置のさらに他の製造方法を示す説明図である。 6 is an explanatory diagram showing still another method of manufacturing a semiconductor device.
【図7】半導体装置のさらに他の製造方法を示す説明図である。 7 is an explanatory diagram showing still another method of manufacturing a semiconductor device.
【符号の説明】 DESCRIPTION OF SYMBOLS
10 樹脂基板11 銅バンプ付き銅箔12 導体部14、17、19、36 配線パターン16、18、34 銅バンプ付き銅箔16a、16b、16c、18a 銅バンプ20、30、32 プリプレグ22 キャビティ24 樹脂26 外部接続端子30 半導体チップ40 基板50 配線パターン52 キャビティ 10 resin substrate 11 of copper bumps foil 12 conductor portion 14,17,19,36 wiring patterns 16,18,34 copper bumps foil 16a, 16b, 16c, 18a copper bumps 20, 30, 32 prepreg 22 cavity 24 resin 26 external connection terminal 30 semiconductor chip 40 substrate 50 wiring pattern 52 cavity

Claims (7)

  1. 配線基板に形成されたキャビティ内に半導体チップが樹脂により封止されて搭載された半導体装置において、 In the semiconductor device mounted sealed semiconductor chip with a resin into a cavity formed in the wiring board,
    前記配線基板がフィルドビアあるいは内層のパッドを介して層間で配線パターンが電気的に接続され、 The wiring board is a wiring pattern between layers through the filled vias or inner layer of the pad are electrically connected,
    前記キャビティがザグリ加工されてキャビティ内面の半導体チップの搭載面に前記フィルドビアあるいは内層のパッド端面が露出し、 Said cavity said filled vias or inner layer of the pad end face exposed on the mounting surface of the semiconductor chip cavity inner face is spot facing,
    該フィルドビアあるいは内層のパッドの端面と前記半導体チップとが電気的に接続されていることを特徴とする半導体装置。 Wherein a said an end surface of the filled via or inner layer of the pad semiconductor chip and are electrically connected.
  2. 配線基板に形成されたキャビティ内に半導体チップが樹脂により封止されて搭載された半導体装置において、 In the semiconductor device mounted sealed semiconductor chip with a resin into a cavity formed in the wiring board,
    前記配線基板が、銅バンプ付き銅箔により配線パターンが形成されるとともに、銅バンプにより層間の配線パターンが電気的に接続して形成され、 The wiring substrate, with the wiring pattern is formed by copper bumps foil, interlayer wiring pattern is formed by electrically connecting the copper bumps,
    前記キャビティがザグリ加工され、キャビティ内面の半導体チップの搭載面に前記銅バンプの端面が露出して形成され、 The cavity is counterbored, the end surface of the copper bump is formed is exposed to the mounting surface of the semiconductor chip cavity inner face,
    該銅バンプの端面と前記半導体チップとが電気的に接続されていることを特徴とする半導体装置。 Semiconductor device and an end face of the copper bumps and said semiconductor chip are electrically connected.
  3. 前記配線基板のキャビティが形成された面側の、前記キャビティが形成された領域を含む配線基板の全域が、配線パターンが形成されあるいは回路部品が搭載される回路領域として形成されていることを特徴とする請求項1または2記載の半導体装置。 Wherein the cavity is formed side of the wiring board, the entire wiring substrate including the area where the cavity is formed, the wiring pattern is formed, or circuit component is formed as a circuit area to be mounted the semiconductor device according to claim 1 or 2 wherein the.
  4. 前記銅バンプの端面と半導体チップとが、フリップチップ接続によって電気的に接続されていることを特徴とする請求項2または3記載の半導体装置。 Wherein the end face and the semiconductor chip of the copper bumps, semiconductor devices that claim 2 or 3, wherein which is electrically connected by flip chip bonding.
  5. 前記銅バンプの端面と半導体チップとがワイヤボンディング接続によって電気的に接続されていることを特徴とする請求項2または3記載の半導体装置。 The semiconductor device according to claim 2 or 3 further characterized in that the end face and the semiconductor chip of the copper bumps are electrically connected by wire bonding.
  6. プリプレグを介して銅バンプ付き銅箔を加圧および加熱して、銅バンプにより層間で配線パターンを電気的に接続した基板を形成し、 Copper bumps copper foil by pressure and heat through the prepreg, to form a substrate for electrically connecting the wiring pattern layers by copper bumps,
    基板の外面に露出する銅箔を所定パターンにエッチングすることにより、基板の外面に配線パターンを形成し、 By etching the copper foil exposed on the outer surface of the substrate in a predetermined pattern to form a wiring pattern on the outer surface of the substrate,
    前記基板の一方の面側からザグリ加工を施して、半導体チップを搭載するキャビティを形成するとともに、キャビティの内面の半導体チップの搭載面に銅バンプの端面を露出させ、 Subjected to counter boring from one side of the substrate, to form a cavity for mounting a semiconductor chip, to expose the end surface of the copper bump on the mounting surface of the semiconductor chip of the inner surface of the cavity,
    該銅バンプと半導体チップとを電気的に接続して、前記キャビティ内に半導体チップを搭載し、 By connecting the copper bumps and the semiconductor chip electrically, the semiconductor chip is mounted in the cavity,
    キャビティに樹脂を充填して半導体チップを封止することを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device characterized by sealing the semiconductor chip by filling a resin into the cavity.
  7. 前記基板のキャビティを形成した面側の全域に所定のパターンで配線パターンを形成することを特徴とする請求項6記載の半導体装置の製造方法。 The method according to claim 6, wherein the forming the wiring pattern in a predetermined pattern over the entire surface on which to form a cavity of the substrate.
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