KR102011840B1

KR102011840B1 - Method of manufacturing circuit board and chip package and circuit board prepared by the same

Info

Publication number: KR102011840B1
Application number: KR1020130020670A
Authority: KR
Inventors: 이상민
Original assignee: 해성디에스 주식회사
Priority date: 2012-10-19
Filing date: 2013-02-26
Publication date: 2019-08-19
Also published as: TWI569696B; KR20140050511A; TW201417651A

Abstract

The present invention provides a method for manufacturing a semiconductor device, comprising: preparing a base substrate including a core layer and a conductive layer formed on at least one surface of the core layer and having an inner circuit pattern; Forming a laminated material to cover the conductive layer; Collectively forming at least one cavity in the stacking material exposing the core layer and the conductive layer; Curing the laminate material in which the cavity is formed to form a laminate; And forming a conductive layer having an outer circuit pattern on an outer surface of the laminate. It provides a method of manufacturing a circuit board, including.

Description

Method of manufacturing circuit board and chip package and circuit board manufactured by the method {Method of manufacturing circuit board and chip package and circuit board prepared by the same}

The present invention relates to a method for manufacturing a circuit board and a chip package including a cavity, and a circuit board manufactured by the method.

In recent years, the number of parts has increased due to the smaller size of electronic devices and the consumer's preference for a single product having various functions. For this reason, a technique for mounting a large number of electronic components at high density on a circuit board is required.

A multi-layer circuit board is a component of an electronic device in which an electronic component is mounted by stacking a plurality of substrates in a multilayer manner. Multi-layered circuit boards can perform many complicated functions electrically compared to single-sided or double-sided boards, and are widely used in various electronic devices because they enable high-density mounting of electronic components.

In particular, in recent years, system integration technology is required to reduce the size and lightness of electronic products, and a technology for manufacturing a cavity type PCB (Cavity PCB) is attracting attention as a corresponding technology. In the case of Cavity PCB, it is a problem that occurs in embedded PCB because the component is not completely embedded in the cavity and it is mounted in the cavity where the empty space is formed in the direction in which the chip is mounted. It has technical advantages that are very efficient in reworking parts and inspecting parts.

However, there are very few applications in PCBs, a layer-by-layer technology of cavity PCBs. The reason for this is that it is difficult to process the cavity area accurately, and there is a problem of damaging the internal circuit of the cavity during plating, etching, etc., which occurs during the PCB process, and it is very difficult to form.

In particular, the method of selectively processing the position of the cavity using a laser drill in the printed circuit board in which the finished product is laminated is difficult to control the depth, and thus often destroys the inner circuit pattern and the inner insulation layer. In addition, when machining a cavity using a router, the difference in processing precision is very severe and the cavity must be formed separately, which is a problem of mass production due to problems in product reliability and low productivity during mass production. In addition, the method of selectively forming the cavity by precisely punching the position of the cavity through the punching machine in the state of the finished product inevitably causes damage to the cavity outer wall, and the damage of the cavity outer wall is caused by moisture absorption. Delamination, damage to the bottom surface of the cavity will occur, leading to a price increase due to the manufacturing cost of the punching jig and a very narrow width of the cavity design. On the other hand, when the cavity is processed and laminated in advance before lamination of the insulating layer, it is difficult to control the flow of the thermosetting resin used as the insulating layer, so that smear is easily generated and an additional desmear process is required. In addition, it is difficult to completely remove the smear, so there is a problem in that the reliability of the substrate is lowered and the productivity is inferior.

KR2011-0093406 10

One embodiment of the present invention is to provide a method for manufacturing a circuit board and a chip package, and a circuit board manufactured by the method, the manufacturing process is simplified and the process cost is reduced.

According to an embodiment of the present invention for achieving the above object, preparing a base substrate including a core layer and a conductive layer formed on at least one surface of the core layer and provided with an inner circuit pattern; Forming a laminated material to cover the conductive layer; Collectively forming at least one cavity in the stacking material exposing the core layer and the conductive layer; Curing the laminate material in which the cavity is formed to form a laminate; And forming a conductive layer having an outer circuit pattern on an outer surface of the laminate. It provides a method of manufacturing a circuit board, including.

The laminate material includes a structural material and a matrix impregnated with the structural material.

The structural material includes a glass fabric and a silica filler.

The binder includes a B-stage thermosetting resin.

In the forming of the laminate, heat is applied to crosslink the B-stage thermosetting resin to a C-stage thermosetting resin.

The equivalent of the thermosetting resin of the B-stage is less than the equivalent of the thermosetting resin of the C-stage.

The process temperature at the time of forming the laminated material is lower than the process temperature at the time of curing the laminated material.

A wet etching method is used in which a solution is used to remove the laminated material of the portion where the cavity is to be formed.

The solution includes a glass etchant.

The core layer includes the same material as the laminate.

The laminated material is a metal layer formed on the outer surface facing the base substrate.

Prior to forming the cavity, removing the metal layer of the portion where the cavity is to be formed; It further includes.

A circuit board manufactured by the method described above is featured.

Preparing a base substrate including a core layer and a conductive layer formed on at least one surface of the core layer and having an inner circuit pattern; Forming a laminated material to cover the conductive layer; Collectively forming at least one cavity in the stacking material exposing the core layer and the conductive layer; Curing the laminate material in which the cavity is formed to form a laminate; Forming a conductive layer having an outer circuit pattern on an outer surface of the laminate; Mounting a semiconductor chip in the cavity and electrically connecting the semiconductor chip and the conductive layer; It discloses a method of manufacturing a chip package comprising a.

A chip package manufactured by the method described above is featured.

According to one embodiment of the present invention as described above, the manufacturing process of the circuit board is simplified, the process cost can be reduced and the price competitiveness can be improved.

1, 2, 5, 6, 7 and 9 are cross-sectional views schematically showing a method of manufacturing a circuit board according to an embodiment of the present invention.
3 illustrates the laminated material of FIG. 2 in more detail.
Figure 4 shows the molding availability of the thermosetting resin with temperature.
8 is a graph schematically showing a process temperature per cycle of a method of manufacturing a circuit board according to an embodiment of the present invention.
10 and 11 are schematic views illustrating a chip package manufactured by a method of manufacturing a chip package according to an embodiment of the present invention.

As the present invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms “comprises” or “having” are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present disclosure does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, with reference to the preferred embodiment of the present invention shown in the accompanying drawings will be described in detail the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

1, 2, 5, 6, 7 and 9 are cross-sectional views schematically illustrating a method of manufacturing a circuit board according to an embodiment of the present invention, and FIG. 3 illustrates the laminated material of FIG. 2 in more detail. Figure 4 shows the molding availability of the thermosetting resin with temperature. 8 is a graph schematically showing a process temperature per cycle of a method of manufacturing a circuit board according to an embodiment of the present invention.

First, referring to FIG. 1, a base substrate 100 is prepared.

The base substrate 100 is a portion in which the inner circuit pattern 121 is formed to perform an electric signal transfer function from the circuit board. The base substrate 100 includes a conductive layer 120 having inner circuit patterns 121 formed on both surfaces of the core layer 115.

The core layer 115 is made of the same material as the laminate (215 of FIG. 7) to be described later. In detail, the core layer 115 includes a thermosetting resin that is fully cured identically to the laminate (215 in FIG. 7).

The conductive layer 120 may include a material that conducts electricity such as copper (Cu) or silver (Ag), but the material is not limited thereto. The conductive layer 120 may be formed on each of both surfaces of the core layer 115 by a screen printing method or a roll coater.

Meanwhile, the inner circuit pattern 121 includes a subtractive method, a semi-additive method (SAP), and a modified semi-eddie including a tenting and a panel / pattern method. Additive including Modified Semi-Additive (MSAP), Advanced Modified Semi-Additive (AMSAP) and Full-Additive (FAP) It can form by various patterning methods, such as a method. Briefly, the subtractive method is a method of selectively removing unnecessary portions other than the conductor from the conductive layer 120 by etching or the like to form a circuit pattern. The additive method is a material of a conductive material by plating or the like on the core layer 115. Selectively precipitates to form a circuit pattern, and since the method is well known, a detailed description thereof will be omitted. In the drawing, the result of forming the inner circuit pattern 121 by the tenting method is illustrated.

The base substrate 100 may be formed on the upper and lower portions of the core layer 115, and may include through holes or via holes for energizing the inner circuit patterns 121. In FIG. 1, two through holes are plated inside, but the shape and number of through holes are not limited thereto. On the other hand, the thickness, material, shape, configuration, etc. of the base substrate 100 is not limited to those shown and described above may be implemented in various ways as needed.

Next, referring to FIG. 2, a build up material 210 is formed on the base substrate 100.

The stack material 210 insulates the inner circuit pattern 121 and the outer circuit pattern 221 of FIG. 9 when manufacturing a multilayer circuit board. The laminate material 210 includes a structural member (212 of FIG. 3) and a bonding material (211 of FIG. 3) (matrix) impregnated into the structural member 212.

3 illustrates the laminated material 210 of FIG. 2 in more detail.

The structural member 212 is a substance added to increase the mechanical, chemical strength and durability of the laminate (215 of FIG. 7). For example, the structural member 212 includes a glass-based material. In detail, the structural member 212 may include a glass fiber fabric 214 and a silica filler 216. The glass fabric 214 is woven into the laminate (215 of FIG. 7) or laminate 210 with a linear structure to support the overall structure of the laminate (215 of FIG. 7), for example in reinforced concrete The analogy acts as a rebar. Silica-based filler 216 (silica filler) is dispersed in the laminate (215 of Figure 7) or the laminated material 210 as a particulate structure to increase the strength and durability, for example, the role of gravel when compared to reinforced concrete Do it.

The binder 211 is a material impregnated with the structural member 212 and serves to insulate between the conductive layers 120 of different layers. The binder 211 includes a thermosetting resin such as an epoxy resin. According to one embodiment of the present invention, the binder 211 included in the laminated material 210 is characterized in that the B-stage thermosetting resin. Hereinafter, the characteristics of the thermosetting resin of the B-stage will be described in detail.

4 shows a stage according to the temperature of the thermosetting resin.

Referring to Figure 4, the x-axis represents the temperature, the y-axis shows the molding characteristics of the thermosetting resin with temperature. That is, as it moves in the x-axis direction, the temperature increases from low temperature to high temperature, and as it moves in the y-axis direction, the fluidity of the thermosetting resin increases.

Thermosetting resins include at least B-stage and C-stage.

B-stage means the uncured state of the thermosetting resin, the intermediate stage of the curing reaction, or the previous stage of complete curing. B-stage thermosetting resins include polymers that do not undergo crosslinking reaction by heat. Therefore, the B-stage thermosetting resin increases the kinetic energy of the polymers when heat is applied to have fluidity or soften, and when contacted with a predetermined solution, solution molecules penetrate between the polymers and swell. .

As described above, the binder 211 included in the laminated material 210 may be a B-stage thermosetting resin. Therefore, when heat is applied to the stacking material 210, it may be molded to have a predetermined fluidity. Referring to FIG. 4, when a predetermined heat is applied to the thermosetting resin of the B-stage, the curing is not performed, but the resin becomes soft enough to be molded. Therefore, when a predetermined heat is applied to the laminated material 210 stacked on the base substrate 100, the B-stage thermosetting resin included in the laminated material 210 becomes moldable, and the inner circuit is applied when laminating by applying a predetermined pressure. The gap between the patterns 121 is filled. The temperature applied during the molding of the thermosetting resin is a temperature until the thermosetting resin becomes a C-stage, and in the case of epoxy resin, the temperature may be about 120 degrees Celsius to about 180 degrees. Meanwhile, as will be described in detail later with reference to FIG. 6, the binder 211 included in the laminated material 210 is weak in chemical resistance because it is a thermosetting resin of B-stage. Therefore, since etching with a solution is possible, the cavity CV may be formed by a wet etching method.

Next, C-stage means a state in which the thermosetting resin is completely cured. That is, it means the state which has a structure which thermosetting resin crosslinked by adding heat energy, and thermosetting resin crosslinked by the stable bond. Therefore, since the size of the polymer is increased due to the crosslinking, the equivalent of the thermosetting resin of the C-stage is larger than the equivalent of the thermosetting resin of the B-stage. Such a C-stage thermosetting resin is impossible to be molded by applying heat, and does not melt or dissolve even in a predetermined solution (insoluble, infusible). Meanwhile, as will be described in detail later with reference to FIG. 7, the binder 211 included in the laminate (215 of FIG. 7) is a C-stage thermosetting resin, and the B-stage thermosetting resin included in the laminated material 210 is completely cured. (fully cured) Therefore, the laminate 215 cannot be molded, the chemical resistance is increased, and the strength and durability are also strong.

Meanwhile, as illustrated in FIG. 2, the stack material 210 may have a metal layer 220 formed on each of outer surfaces of the base substrate 100 that face the base substrate 100. The metal layer 220 may be formed of a material such as copper (Cu), silver (Ag), or the like.

However, the embodiment of the present invention is not limited to FIG. 2, and the metal layer 220 is formed on the outer surface of the laminated material 210 separately after applying the laminated material 210 on which the metal layer 220 is not formed to the base substrate 100. The 220 may be formed by a screen printing method or a method using a roll coater.

Next, referring to FIG. 5, the metal layer 220 of the portion where the cavity CV is to be formed is removed.

In detail, the process of FIG. 5 is referred to as window processing, and the present invention is characterized in that the cavity (CV) in the laminated material 210 is formed by a wet etching method. Therefore, when the metal layer 220 is formed on the laminated material 210, the window processing process is included.

Although not shown, the dry film register DRF is applied, exposed and developed to form a pattern in the portion 223 where the cavity CV is to be formed. Next, the metal layer 220 of the portion 223 on which the cavity CV is to be formed is removed by etching using the dry film resistor DFR having the pattern as a mask. The dry film register (DFR) is then stripped. In addition, the window processing can use another well-known method other than the method mentioned above.

Next, referring to FIG. 6, at least one cavity CV is collectively formed in the stack material 210. In FIG. 6, only one cavity CV is illustrated, but a plurality of cavities may be formed according to a product design.

The cavity CV is a space in which the semiconductor chip is mounted and is formed by removing the stack material 210. The cavity CV is an opening formed to expose the conductive layer 120 provided with the core layer 115 and the inner circuit pattern 121 under the laminated material 210. The cavity CV is formed under the laminated material 210. 120) is distinguished from the exposed via hole. On the other hand, since the cavity CV is an empty space in which the semiconductor chip is to be mounted thereafter, the via hole is plated inside and has a different function from a via hole in which a via serving as a conductive member is formed. In addition, the cavity (CV) is different from the via hole in that the semiconductor chip should have a width and a width enough to be mounted.

In detail, the cavity CV is formed by a method of wet etching. The cavity CV is formed by removing the laminated material 210 exposed to the portion 223 where the cavity CV is to be formed by using the metal layer 220 as a self-aligned mask. As described with reference to FIG. 3, the stack material 210 includes a binder 211 and a structural member 212. Therefore, the solution used for the wet etching should be able to remove the structural member 212 in addition to the binder 211. The solution includes a glass etchant from which the structural material 212 of the glass component can be removed.

The method of removing the stacked material 210 may be performed in one process, but may be repeated in a plurality of processes. For example, the binder 211 included in the laminated material 210 of the portion 221 where the cavity CV is to be formed is removed by the first solution that removes the binder 211 in the first step, and the second solution is removed. The structural member 212 included in the laminated material 210 of the portion 221 on which the cavity CV is to be formed may be removed by the second solution that removes the structural member 212 in the step. Of course, if necessary, after the second step, the first step may be repeated again, and the order of the first and second steps may be reversed.

Here, the first solution may be a basic solution such as sodium permanganate or sodium hydroxide, an organic solvent such as acetone, or other acidic solution. On the other hand, the second solution may be an acid solution such as hydrofluoric acid (HF) or a known glass etching agent. On the other hand, before removing the binder in the first step, it is possible to use an acid, alkali or neutral type etching aids to swell the thermosetting resin.

According to one embodiment of the present invention, the cavity (CV) is formed by a wet etching method in a state in which the laminated material 210 is formed.

As described above, since the laminated material 210 includes a B-stage thermosetting resin, the cavity CV may be formed by a wet etching method. In the case where the laminated material 210 is formed on both sides of the base substrate 100 and then immediately cured, the B-stage thermosetting resin is completely hardened and wet-etched because it is changed into a C-stage thermosetting resin having strong chemical resistance. It is impossible to form the cavity CV by the method. However, according to one embodiment of the present invention, since the cavity (CV) is formed before the laminate material 210 is formed and the laminate is cured into the laminate (215 of FIG. 7), a wet etching method may be employed. .

Meanwhile, as described above with reference to FIG. 1, the core layer 115 includes a C-stage thermosetting resin similarly to the laminate (215 of FIG. 7). Therefore, even when the core layer 115 is exposed to the etching solution in the process of forming the cavity CV, the etching solution is not damaged. That is, since the core layer 115 and the laminated material 210 include thermosetting resins in different states, the core layer 115 and the laminated material 210 have etching selectivity. In addition, in the case of the conductive layer 120, since the laminated material 210 and the material itself are different, the conductive layer 120 does not react with the etching solution for removing the laminated material 210.

According to one embodiment of the present invention, by forming a cavity (CV) by a wet etching method, it is possible to solve the problem of the method of processing the cavity in a printed circuit board in which the laminated state of the conventional finished product is formed and can form the cavity There is an advantage. In addition, the problem of damage to the outer wall shown in the method of precisely punching the position of the cavity in the state of the finished product is eliminated and there is no need to use a punching jig or the like, so that various types of cavities can be designed at low cost. In addition, there is an effect that eliminates the problem of smears and reduce the manufacturing cost and process time.

Next, referring to FIG. 7, the laminate material 215 in which the cavity CV is formed is completely cured to form the laminate 215.

In detail, the laminate 215 includes the binder (211 of FIG. 3) and the structural member (212 of FIG. 3) in the same manner as the laminate material 210, but the binder included in the laminate 215 is C-stage thermosetting. It is characterized by being resin. The forming of the laminate 215 is a step of applying a B-stage thermosetting resin included in the laminate material 210 to heat the C-stage thermosetting resin. That is, the thermosetting resins are crosslinked with each other by applying thermal energy to form a structure in which the thermosetting resins are crosslinked with stable bonds. As a result, the laminate has increased chemical resistance, strength, and durability.

On the other hand, the temperature for completely curing the laminated material 210 is preferably higher than the temperature for forming the laminated material 210 of FIG. For example, curing may be performed for several minutes at a temperature of about 200 degrees Celsius or more.

8 is a graph schematically showing a process temperature per cycle of a method of manufacturing a circuit board according to an embodiment of the present invention.

In the method of manufacturing a circuit board according to an embodiment of the present invention, the laminate 215 is formed from the laminate material 210 discontinuously. That is, the forming and molding of the laminated material 210 at a temperature of T1 occurs in the t1 section. The step t3, which hardens the stack material 210 to form the stack 215, is performed discontinuously in the t1 section. Instead, the step of forming the cavity CV in the t2 section between t3 and t1 is performed. After etching the cavity CV, the laminate material 210 is cured at a temperature of T2 in step t3 to form the laminate 215.

On the other hand, the process temperature of the step t1 of forming the laminated material 210 and forming the laminated material 210 so as to penetrate between the inner layer circuit pattern, to completely cure the laminated material 210 to manufacture the laminated body 215 It is characterized in that it is lower than the process temperature of step t3. This is because the thermal energy for causing the polymer to crosslink is greater than the thermal energy necessary for improving the fluidity of the polymer.

According to an exemplary embodiment of the present invention, the laminate 215 of the final circuit board may include a polymer having strength and durability, and may have a suitable physical property in a package, but may be a non-continuous process and a wet etching method. It has the characteristic of forming a cavity (CV) collectively. Therefore, the method of manufacturing a circuit board according to an embodiment of the present invention has an advantage in that a circuit board including physical properties suitable for a user's request can be manufactured in a process in which lead time, investment cost, and facility cost are reduced.

Next, referring to FIG. 9, an outer circuit pattern 221 is formed on the metal layer 220 provided on the outer surface of the laminate 215. The method of forming the outer circuit pattern 221 may be performed in the same manner as the method of forming the inner circuit pattern 121. Although not shown, a circuit board may be manufactured by additionally processing via holes, printing a protective layer, and surface treatment.

10 and 11 are diagrams schematically illustrating chip packages manufactured by the method of manufacturing chip packages 300 and 300a according to an exemplary embodiment of the present invention.

The chip package of FIGS. 10 and 11 further includes a semiconductor chip mounted on the circuit board 200 of FIG. 9.

10 and 11, a semiconductor chip is mounted on the circuit board 200 of FIG. 9. As illustrated in FIG. 10, one semiconductor chip 30 may be mounted on the circuit board 200. However, the present invention is not limited thereto, and a plurality of semiconductor chips 31 and 32 may be mounted on the circuit board as shown in FIG. 11. 11 illustrates an example in which two semiconductor chips are mounted, but the embodiment is not limited thereto, and three or more semiconductor chips may be mounted on a circuit board.

At least one semiconductor chip 30, 31, 32 is mounted inside the cavity CV. In the case of FIG. 11, one semiconductor chip 31 may be mounted inside the cavity CV, and the other semiconductor chip 32 may be mounted outside the cavity CV. The semiconductor chips 30, 31, and 32 may be electrically connected to the conductive layer 120 having the exposed inner circuit pattern 121 or the metal layer 220 having the outer circuit pattern 221 formed thereon by bonding wires. Thereby, the chip package which is a circuit board in which the semiconductor chip was mounted can be manufactured.

According to an embodiment of the present invention, as the cavity CV is formed on the circuit board 200, the semiconductor chip 30 is mounted inside the cavity CV as shown in FIG. 10 to further reduce the thickness of the chip package 300. You can. In addition, since the semiconductor chip 30 mounted inside the cavity CV may have a thicker thickness, it is apt to reduce back grinding of the semiconductor chip, thereby increasing the yield of the chip and having economic advantages. In addition, as shown in FIG. 11, the semiconductor chip 31 is mounted inside the cavity CV so that a larger number of semiconductor chips may be mounted in the same thickness as the chip package using the circuit board without the cavity.

Although not shown, a conductive member such as a bump may be further formed on the metal layer disposed on the opposite side of the surface on which the cavity is formed in the circuit board. In addition, the chip package may be completed by sealing part or all of the semiconductor chip, the bonding wires, and the circuit board with a mold resin such as an epoxy mold compound.

Meanwhile, in the above-described embodiment, the multilayer circuit board in which the conductive layers and the metal layers 120 and 220 are four layers in total (4-layer) has been described, but the present invention is not limited thereto. Of course, it can be applied to the manufacturing method of the circuit board of various layers, such as 8-layer.

In addition, a predetermined via hole, a plated through hole (PTH), a circuit pattern of a predetermined shape, and the like are illustrated in the drawings for describing the exemplary embodiment of the present invention, but are for convenience of description. However, the present invention is not limited thereto, and other forms, different numbers, and other patterns may be included without departing from the manufacturing method according to the present invention.

In the present specification, the present invention has been described with reference to limited embodiments, but various embodiments are possible within the scope of the present invention. In addition, although not described, equivalent means will also be referred to as incorporated in the present invention. Therefore, the true scope of the present invention will be defined by the claims below.

100: base substrate 115: core layer
120, 220: conductive layer, metal layer
121, 221: inner circuit pattern, outer circuit pattern
210: laminated material 215: laminated body
CV: Cavity 211: Binder
212: structural material

Claims

Preparing a base substrate including a core layer and a first conductive layer formed on at least one surface of the core layer and having an inner circuit pattern;
Forming a laminated material to cover the first conductive layer;
Forming a metal layer on an outer surface of the laminated material facing the base substrate;
Removing a portion of the metal layer in which at least one cavity is to be formed;
Collectively forming at least one cavity in the stacking material exposing the core layer and the first conductive layer;
Curing the laminate material in which the cavity is formed to form a laminate; And
And removing a second portion of the metal layer to form a second conductive layer having an outer circuit pattern on an outer surface of the laminate.
The forming of the cavity may include a circuit using a wet etching method using a metal layer from which the portion has been removed as a mask to remove the laminated material exposed to the portion where the cavity is to be formed by using a solution. Method of manufacturing a substrate.

The method of claim 1,
The laminated material includes a binder impregnated in the structural member, the binder comprises a B-stage thermosetting resin.

The method of claim 2,
Forming the laminate,
Method of manufacturing a circuit board by cross-linking the thermosetting resin of the B-stage by applying heat to the thermosetting resin of the C-stage.

The method of claim 3,
The equivalent of the thermosetting resin of the B-stage is less than the equivalent of the thermosetting resin of the C-stage, the manufacturing method of the circuit board.

The method of claim 1,
The process temperature when forming the laminated material is lower than the process temperature when curing the laminated material.

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The method of claim 1,
The solution is a method of manufacturing a circuit board containing a glass etchant.

The method of claim 1
And the core layer is made of the same material as the laminate.

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A circuit board manufactured by the manufacturing method of any one of claims 1 to 5, 7 and 8.

Preparing a base substrate including a core layer and a first conductive layer formed on at least one surface of the core layer and having an inner circuit pattern;
Forming a laminated material to cover the first conductive layer;
Forming a metal layer on an outer surface of the laminated material facing the base substrate;
Removing a portion of the metal layer in which at least one cavity is to be formed;
Collectively forming at least one cavity in the stacking material exposing the core layer and the first conductive layer;
Curing the laminate material in which the cavity is formed to form a laminate;
Removing a second portion of the metal layer to form a second conductive layer having an outer circuit pattern on an outer surface of the laminate; And
Mounting a semiconductor chip in the cavity and electrically connecting the semiconductor chip with at least one of the first conductive layer and the second conductive layer;
The forming of the cavity may include a chip using a wet etching method using a metal layer from which the portion is removed to remove the laminated material exposed to the portion where the cavity is to be formed using a solution. Method of making the package.

The method of claim 12,
The laminate material comprises a binder impregnated in the structural member, the binder comprises a B-stage thermosetting resin manufacturing method of the chip package.

The method of claim 13,
Forming the laminate,
The cross-linking reaction of the thermosetting resin of the B-stage by applying heat to make a thermosetting resin of the C-stage, chip package manufacturing method.

The method of claim 14,
The equivalent of the thermosetting resin of the B-stage is smaller than the equivalent of the thermosetting resin of the C-stage, the manufacturing method of the chip package.

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