KR101253514B1 - Method of resolving substrate warpage problem due to differences in thermal coefficients and electronic component embedded printed circuit board manufactured thereof - Google Patents

Method of resolving substrate warpage problem due to differences in thermal coefficients and electronic component embedded printed circuit board manufactured thereof Download PDF

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KR101253514B1
KR101253514B1 KR1020110110637A KR20110110637A KR101253514B1 KR 101253514 B1 KR101253514 B1 KR 101253514B1 KR 1020110110637 A KR1020110110637 A KR 1020110110637A KR 20110110637 A KR20110110637 A KR 20110110637A KR 101253514 B1 KR101253514 B1 KR 101253514B1
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electronic component
cavity
insulating layer
printed circuit
circuit board
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김기훈
고영주
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아페리오(주)
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape

Abstract

PURPOSE: A solving method of a substrate warpage problem due to heat expansion contraction rate difference and an electronic component built-in printed circuit board applying the method are provided to prevent a warpage occurrence of the substrate by using a laminate-molded material in which maintaining more than 50% of the content of the ceramic filler. CONSTITUTION: A cavity is manufactured in an internal layer insulating layer(180) of a hardened status. An electronic component(170) is built in the cavity. A first insulation layer and a copper foil(190) of a semi-hardened status are laminated on the electronic component. A via hole is formed after the first insulation layer is solidified. The via hole electronically connects the copper foil of the substrate outside layer and an input-output terminal bump of the electronic component.

Description

열팽창수축률 차이로 인한 기판 휨 문제 해결방법 및 이를 적용한 전자부품 내장형 인쇄회로기판{METHOD OF RESOLVING SUBSTRATE WARPAGE PROBLEM DUE TO DIFFERENCES IN THERMAL COEFFICIENTS AND ELECTRONIC COMPONENT EMBEDDED PRINTED CIRCUIT BOARD MANUFACTURED THEREOF} METHOD OF RESOLVING SUBSTRATE WARPAGE PROBLEM DUE TO DIFFERENCES IN THERMAL COEFFICIENTS AND ELECTRONIC COMPONENT EMBEDDED PRINTED CIRCUIT BOARD MANUFACTURED THEREOF}

본 발명은 전자부품 내장형(electronic component-embedded) 인쇄회로기판(printed circuit board; PCB) 또는 패키지기판(package board) 제조기술에 관한 것으로, 특히 기판에 내장되는 전자부품과, 전자부품을 에워싸는 밀봉 절연층 및 동박들 사이의 열팽창계수(coefficient of thermal expansion: CTE) 차이로 인하여 발생하는 적층기판의 박리(delamination) 문제 또는 크랙(crack) 발생 문제를 해결한 전자부품 내장형 인쇄회로기판 제조공법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component-embedded printed circuit board (PCB) or package board manufacturing technology, and in particular, an electronic component embedded in a substrate and a sealing insulation surrounding the electronic component. The present invention relates to a method for manufacturing an electronic component embedded printed circuit board which solves a problem of delamination or cracking of a laminated board caused by a difference in coefficient of thermal expansion (CTE) between layers and copper foils. .

최근 들어, 웨이퍼 레벨의 칩(chip)을 인쇄회로기판 속에 직접 내장하여 제작하는 내장형 인쇄회로기판(Embedded Printed Circuit Board) 기술에 대한 연구개발이 활발히 진행되고 있다. 칩을 기판 속에 내장하게 되면, 전자부품의 사이즈가 축소되어 전자기기의 소형화 및 경량화에 도움이 되며, 기생성분을 제거할 수 있어서 회로의 동작주파수를 증대시킬 수 있음은 물론, 잡음을 일으키는 외부 전자파의 영향을 차단하는 장점이 있다. Recently, research and development of embedded printed circuit board technology, which directly fabricates a wafer-level chip in a printed circuit board, has been actively conducted. When the chip is embedded in the substrate, the size of the electronic components is reduced, which helps to reduce the size and weight of the electronic device, and eliminates parasitic components, thereby increasing the operating frequency of the circuit, as well as generating external electromagnetic waves. It has the advantage of blocking the effects of.

더욱이, 스마트폰 또는 스마트 패드 등과 같은 휴대용 전자기기의 시장이 폭발적으로 커지면서, 경박단소 제품에 대처할 수 있는 칩 내장형 인쇄회로기판 제조가 절실히 요구되고 있다. 인쇄회로기판을 경박단소화하기 위해서 다양한 종류의 전자부품, 예를 들어 반도체 칩과 같은 능동소자뿐 아니라, 저항 및 캐패시터와 같은 수동소자들을 인쇄회로기판에 내장시키고 있다. In addition, as the market for portable electronic devices such as smart phones or smart pads has exploded, there is an urgent need for manufacturing chip embedded printed circuit boards that can cope with light and thin products. In order to reduce the size of the printed circuit board, various types of electronic components, for example, active devices such as semiconductor chips, as well as passive devices such as resistors and capacitors are embedded in the printed circuit board.

이하, 본 발명의 명세서에서는 기판에 내장할 수 있는 반도체 칩, 다이, 모듈, 저항, 캐패시터 등 다양한 전자소자들을 모두 총칭해서 '전자부품(electronic component)'이라 칭하기로 한다. Hereinafter, in the specification of the present invention, various electronic devices, such as semiconductor chips, dies, modules, resistors, and capacitors, which can be embedded in a substrate, are collectively referred to as "electronic components."

내층에 캐비티를 가공해서 전자부품을 캐비티 속에 내장하는 기술은, 본원 출원발명의 출원인의 선등록 특허발명, 예를 들어 대한민국 특허공개 제10-2008-79391호, 대한민국 특허공개 제10-2008-79384호, 대한민국 특허공개 제10-2008-79388호에 상세히 설명되어 있다. The technique of processing the cavity in the inner layer and embedding the electronic component in the cavity is disclosed in the applicant's prior registered patent invention, for example, Korean Patent Publication No. 10-2008-79391, Korean Patent Publication No. 10-2008-79384 Korean Patent Publication No. 10-2008-79388.

전술한 종래기술에 개시된 전자부품 내장 기술은, 내층 절연층에 캐비티를 제작하고, 절연층 하단에 접착 필름을 부착한 후, 전자부품을 캐비티 속으로 밀어넣어 접착 필름 위에 안착시키고, 다시 그 위에 프리프레그(PREPREG)와 같은 반경화상태의 유동성 수지를 적층하고 가열 압착함으로써 전자부품의 상부와 측부와 하부를 절연물질로 에워싸는 구조를 취하고 있다. 그리고 나면, 비아홀을 형성하고 동도금을 실시해서 전자부품의 단자와 외층의 동박을 전기적으로 접속하는 방식을 개시하고 있다. The electronic component embedding technology disclosed in the above-described prior art manufactures a cavity in an inner layer insulating layer, attaches an adhesive film to the bottom of the insulating layer, and then slides the electronic part into the cavity to be seated on the adhesive film, and then pre-preps it thereon. By laminating and heat-pressing a semi-curable fluid resin such as PREGREG, the upper part, the side part and the lower part of the electronic part are surrounded by an insulating material. Then, the via hole is formed, copper plating is performed, and the method of electrically connecting the terminal of an electronic component and copper foil of an outer layer is disclosed.

그런데, 반도체 칩과 같은 전자부품의 열팽창계수는 CTE ≤ 20 ppm/℃의 범위에 있는데 반하여, 내장된 전자부품 주위를 에워싸는 프리프레그 또는 에폭시 수지, 레진 등의 열팽창계수는 CTE ≥ 30 ppm/℃ 이상의 범위에 있다.By the way, the thermal expansion coefficient of electronic components such as semiconductor chips is in the range of CTE ≤ 20 ppm / ℃, the thermal expansion coefficient of prepreg, epoxy resin, resin, etc. surrounding the embedded electronic components is CTE ≥ 30 ppm / ℃ Is in range.

그 결과, 전자부품을 내장해서 가열 가압 적층 성형하는 과정 중은 물론 적층 공정을 완료하고 나면, 기판을 구성하는 부품들의 열팽창 및 수축의 정도 차이로 인하여 기판이 휘어서 적층 구조가 박리(delamination) 되는 문제가 발생하고, 심지어는 크랙(crack) 또는 워피지(warpage)가 발생하곤 한다. As a result, after the completion of the lamination process as well as during the heat press lamination by embedding the electronic component, the substrate is bent due to the difference in thermal expansion and contraction of the components constituting the substrate, and thus the laminated structure is delaminated. Occurs and even cracks or warpage occur.

따라서, 본 발명의 목적은 전자부품 내장형 인쇄회로기판을 구성하는 부품들의 열팽창 및 열수축의 차이로 인해 기판이 휘거나 손상되는 문제를 해결한 전자부품 내장형 인쇄회로기판 및 제조방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide an electronic component embedded printed circuit board and a manufacturing method which solves a problem that a substrate is bent or damaged due to a difference in thermal expansion and thermal contraction of components constituting the electronic component embedded printed circuit board.

상기 목적을 달성하기 위하여, 본 발명은 캐비티 속에 전자부품을 수납하고 절연층과 동박을 적층해서 성형하기 위해 사용하는 절연층을, CTE가 최대 20 ppm/℃ 이하를 충족하는 절연층을 사용하는 것을 특징으로 한다. 본 발명은, CTE ≤ 20 ppm/℃를 충족하기 위하여, 세라믹 필러(ceramic filler)가 적어도 50% 이상이 되는 에폭시 수지 자재를 사용하는 것을 특징으로 한다. In order to achieve the above object, the present invention is to use an insulating layer for storing the electronic components in the cavity and laminated and molded the insulating layer and copper foil, using an insulating layer that meets the CTE up to 20 ppm / ℃ or less. It features. The present invention is characterized by using an epoxy resin material having a ceramic filler of at least 50% or more to satisfy CTE ≦ 20 ppm / ° C.

에폭시 수지 내에 분산처리된 실리카(SiO2) 성분의 알갱이, 즉 세라믹 필러의 함량을 50 % 이상으로 유지한 적층성형 자재를 사용함으로써, 캐비티 속에 내장한 전자부품과 좌우상하를 둘러싼 절연성 수지 사이의 열팽창계수 차이가 발생하는 것을 방지할 수 있다. 그 결과, 적층 성형 과정에서 기판에 크랙이 생기거나 또는 박리(delamination), 워피지(warpage)가 발생하는 것을 방지할 수 있다. Thermal expansion between the electronic components embedded in the cavity and the insulating resin surrounding the upper and lower sides by using a granulated material containing silica (SiO 2 ) components dispersed in an epoxy resin, that is, a laminated molding material having a ceramic filler content of 50% or more. The coefficient difference can be prevented from occurring. As a result, cracks, delamination or warpage can be prevented from occurring in the substrate in the lamination process.

도1a 내지 도1l은 본 발명에 따라 전자부품 내장형 인쇄회로기판을 제작하는 과정을 나타낸 도면.
도2는 본 발명에 따른 제작된 전자부품 내장 인쇄회로기판을 개략적으로 나타낸 도면.1A to 1L illustrate a process of manufacturing an electronic component embedded printed circuit board according to the present invention.
Figure 2 is a schematic view showing a printed circuit board embedded electronic component according to the present invention.

본 발명은, 경화상태의 내층 절연층에 캐비티를 제작하고, 캐비티 속에 전자부품을 내장하고, 캐비티 속에 수납한 전자부품 위에 반경화상태의 제1 절연층과 동박을 적층하고, 가열 가압하여 라미네이트 하여 상기 전자부품을 에워싸도록 하여 상기 제1 절연층을 경화시킨 후, 기판 외층 표면의 동박과 전자부품의 입출력단자 범프를 전기접속하는 비아홀을 형성하는 전자부품 내장형 인쇄회로기판 제조방법에 있어서, 상기 제1 절연층의 열팽창계수는 CTE ≤ 20 ppm/℃ 범위에 있는 것을 특징으로 하는 부품내장형 인쇄회로기판 제조방법을 제공한다.According to the present invention, a cavity is fabricated in a hardened inner insulating layer, an electronic component is embedded in a cavity, a semi-cured first insulating layer and a copper foil are laminated on an electronic component housed in a cavity, and heated and pressed to laminate. The method of manufacturing an electronic component embedded printed circuit board according to claim 1, wherein the electronic component is enclosed to cure the first insulating layer, and a via hole is electrically connected between the copper foil on the outer surface of the substrate and the input / output terminal bumps of the electronic component. The thermal expansion coefficient of the first insulating layer provides a method for manufacturing a component-embedded printed circuit board, characterized in that the CTE ≤ 20 ppm / ℃ range.

본 발명은 전자부품을 수납하는 캐비티를 구비한 내층 절연층; 전자부품이 수납된 캐비티 공간으로 흘러들어 상기 전자부품을 상하좌우로 에워싸고 내층 절연층 위에 적층 성형되는 제1 절연층; 캐비티 내부에 수납된 전자부품; 및 제1 절연층 상부에 형성된 동박 회로와 전자부품의 입출력단자 범프를 전기접속하도록 제1 절연층을 관통하여 형성된 비아홀로 구성되고, 상기 제1 절연층의 열팽창계수는 CTE ≤ 20 ppm/℃ 범위에 있는 것을 특징으로 하는 전자부품내장형 인쇄회로기판을 제공한다.The present invention is an inner layer insulating layer having a cavity for containing the electronic component; A first insulating layer flowing into the cavity space in which the electronic components are stored, surrounding the electronic components up, down, left and right, and laminated on the inner insulation layer; Electronic components housed inside the cavity; And via holes formed through the first insulating layer to electrically connect the copper foil circuit formed on the first insulating layer to the input / output terminal bumps of the electronic component, wherein the thermal expansion coefficient of the first insulating layer is in the range of CTE ≦ 20 ppm / ° C. Provided is an electronic component embedded printed circuit board.

이하에서는 첨부도면 도1 및 도2를 참조해서 본 발명의 양호한 실시예를 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings, Figures 1 and 2 will be described in detail a preferred embodiment of the present invention.

본 발명의 바람직한 실시예로서, 동박적층판(CCL; copper cladded laminate)과 같은 원자재에서 시작할 수 있으나, 반드시 이에 국한할 필요는 없다. 도1a는 본 발명의 양호한 실시예로서, 경화상태(C 스테이지)의 절연층(100) 양면에 동박(110a, 110b)이 덮여 있는 자재를 나타내고 있다. As a preferred embodiment of the present invention, it is possible to start with a raw material such as a copper cladded laminate (CCL), but it is not necessarily limited thereto. FIG. 1A illustrates a material in which copper foils 110a and 110b are covered on both sides of the insulating layer 100 in a hardened state (C stage) as a preferred embodiment of the present invention.

도1b를 참조하면, 기판에 드릴 공정을 수행해서 향후 후속 공정에서 정렬을 위해 사용할 가이드 홀(guide hole; 120)을 가공하는 과정을 볼 수 있다. 이어서, 도1c를 참조하면, 기판의 양면 동박(100a, 100b)을 선택적으로 식각함으로써 향후 후속 공정에서 사용할 정렬마크(fiducial mark; 130)를 형성한다. 본 발명의 양호한 실시예로서, 도1c에 나타낸 정렬마크(130)는, 향후 전자부품을 제 위치에 정확히 안착하는 단계, 비아홀을 형성하는 단계 등과 같이 정렬이 필요한 단계에 정렬을 위한 레퍼런스(reference)로 사용하게 된다. 절연층(100)은 C 스테이지로 경화된 에폭시 수지가 사용될 수 있으며, 섬유질이 보강된 수지층이 사용될 수 있다. Referring to FIG. 1B, a process of drilling a guide hole 120 to be used for alignment in a subsequent process may be performed by performing a drill process on a substrate. Subsequently, referring to FIG. 1C, the double-sided copper foils 100a and 100b of the substrate are selectively etched to form fiducial marks 130 to be used in subsequent processes. As a preferred embodiment of the present invention, the alignment mark 130 shown in FIG. Will be used. As the insulating layer 100, an epoxy resin cured in a C stage may be used, and a resin layer reinforced with fiber may be used.

도1d를 참조하면, 전자부품(칩)을 안착해서 내장하고자 하는 부위를 식각 제거함으로써 캐비티(150)를 형성한다. 캐비티 가공은 기계적 드릴, 레이저 드릴 또는 기타 화학적 식각 방식으로 가공할 수 있다. Referring to FIG. 1D, the cavity 150 is formed by etching and removing an area to be embedded by mounting an electronic component (chip). Cavity machining can be performed by mechanical drills, laser drills or other chemical etching methods.

이어서, 도1e를 참조하면, 기판의 하부에 접착층(160)을 형성한다. 본 발명에 따른 접착층(160)의 양호한 실시예로서, 접착제, 접착 필름, 또는 접착 테이프 등이 사용될 수 있으며, 기계적 강도를 제공하기 위해서 지지층 위에 접착층이 도포된 구조물을 사용할 수 있다. 본 발명에 따른 접착층(160)의 양호한 실시예로서, 폴리이미드(polyimide) 계열의 접착 재료가 사용될 수 있다. Next, referring to FIG. 1E, an adhesive layer 160 is formed under the substrate. As a preferred embodiment of the adhesive layer 160 according to the present invention, an adhesive, an adhesive film, an adhesive tape, or the like may be used, and a structure in which an adhesive layer is applied on a support layer may be used to provide mechanical strength. As a preferred embodiment of the adhesive layer 160 according to the present invention, a polyimide-based adhesive material may be used.

본 발명에 따른 접착층(160)의 또 다른 양호한 실시예로서, 접착필름, 페이스트 타입의 잉크, 또는 필러블 잉크(peelable ink) 등이 사용될 수 있으며, 기계적 강도를 제공하기 위해서 지지층 위에 접착층이 도포된 구조물을 사용할 수 있다. 여기서, 본 발명에 사용되는 접착층(160)은 화학용액에 의해 용해될 수 있는 것을 특징으로 하며, 후속 공정에서 물리적으로 벗겨내는 대신에 화학적으로 제거하는 과정을 겪게 된다. As another preferred embodiment of the adhesive layer 160 according to the present invention, an adhesive film, paste type ink, or peelable ink, etc. may be used, and the adhesive layer is applied on the support layer to provide mechanical strength. The structure can be used. Here, the adhesive layer 160 used in the present invention is characterized in that it can be dissolved by a chemical solution, and undergoes a process of chemical removal instead of physical peeling off in a subsequent process.

본 발명의 양호한 실시예로서, 드라이필름과 같은 접착필름을 사용하는 경우 수산화나트륨 또는 탄산나트륨과 같은 용액을 사용해서 필름을 화학적으로 용해시켜 기판으로부터 분리 제거할 수 있다. 본 발명의 양호한 실시예로서, 반경화상태의 페이스트 잉크 또는 필러블 잉크를 코팅하고 양생해서 필름을 형성하면, 필름의 표면은 끈적끈적한 접착력이 발생하게 되며, 전자부품을 실장한 후 아민(amine) 계열의 약품을 이용해서 페이스트 잉크를 화학적으로 제거할 수 있다. As a preferred embodiment of the present invention, in the case of using an adhesive film such as a dry film, a solution such as sodium hydroxide or sodium carbonate may be used to chemically dissolve the film to remove it from the substrate. In a preferred embodiment of the present invention, when the paste ink or the peelable ink of the semi-cured state is coated and cured to form a film, the surface of the film has a sticky adhesive force, and after mounting the electronic component, an amine A series of chemicals can be used to chemically remove the paste ink.

도1f를 참조하면, 전자부품(170)을 캐비티(150) 속에 밀어넣어, 전자부품(170)이 접착층(160) 위에 안착하도록 한다. 이때에, 전자부품의 정밀한 안착 위치 조정을 위해 정렬마크(130)가 사용될 수 있다. 다시 도1f를 참조하면, 안착한 전자부품(170)은 입출력 단자(I/O Terminal)로서 범프(bump; 171)를 구비하고 있으며, 전자부품(170)의 높이가 캐비티(150)의 깊이와 거의 동일하거나 상대적으로 높은 것을 특징으로 하고 있다. Referring to FIG. 1F, the electronic component 170 is pushed into the cavity 150 to allow the electronic component 170 to rest on the adhesive layer 160. At this time, the alignment mark 130 may be used for precise mounting position adjustment of the electronic component. Referring again to FIG. 1F, the seated electronic component 170 includes a bump 171 as an input / output terminal, and the height of the electronic component 170 is substantially equal to the depth of the cavity 150. It is characterized by the same or relatively high.

만일 캐비티(150) 속에 수납할 전자부품(170)의 두께가 캐비티(150)의 깊이보다 작다면, 접착층(160) 위에 높이조절용 자재를 적층한 후 접착제를 이용해서 높이 조절용 자재 위에 전자부품(170)을 실장함으로써, 최종적으로 전자부품(170)의 입출력단자 범프(171)가 캐비티 레벨보다 위로 돌출되도록 할 수 있다. If the thickness of the electronic component 170 to be stored in the cavity 150 is smaller than the depth of the cavity 150, the height adjusting material is laminated on the adhesive layer 160, and then the electronic component 170 is placed on the height adjusting material using an adhesive. ), The input / output terminal bump 171 of the electronic component 170 can finally protrude above the cavity level.

그리고 나면, 절연층(180)과 동박(190)을 적층하고 가열 가압 라미네이트 한다. 도1g는 본 발명에 따라, 절연층(180)과 동박(190)을 적층한 모습을 나타낸 도면이다. 도1g를 참조하면, 가열가압 라미네이트 과정에서 절연층은 캐비티(150) 속의 빈 공간으로 흘러들어가서 전자부품(170)을 상하좌우 에워싸게 된다. Then, the insulating layer 180 and the copper foil 190 are laminated and heated under pressure lamination. 1G is a view showing a state in which the insulating layer 180 and the copper foil 190 are laminated according to the present invention. Referring to FIG. 1G, in the heating and pressing lamination process, the insulating layer flows into an empty space in the cavity 150 to surround the electronic component 170 up, down, left, and right.

여기서, 본 발명은 절연층(180)의 열팽창계수 CTE를 최대 20 ppm/℃ 이하를 충족하는 절연층을 사용하는 것을 특징으로 한다. 본 발명은, CTE ≤ 20 ppm/℃를 충족하기 위하여, 세라믹 필러(ceramic filler)의 함량을 적어도 50% 이상이 되는 에폭시 수지 자재를 사용하는 것을 특징으로 한다. Here, the present invention is characterized by using an insulating layer that satisfies the thermal expansion coefficient CTE of the insulating layer 180 up to 20 ppm / ℃ or less. The present invention is characterized by using an epoxy resin material having a content of ceramic filler of at least 50% or more to satisfy CTE ≦ 20 ppm / ° C.

본 발명의 양호한 실시예로서, 일본 아지노모토 사의 ABF 필름, 히타치 케미컬사의 제품, 또는 스미또모 메이크 라이트사의 제품을 사용할 수 있다. As a preferred embodiment of the present invention, an ABF film manufactured by Ajinomoto, Japan, a product of Hitachi Chemical, or a product of Sumitomo Make Light, can be used.

이어서, 도1h를 참조하면, 기판 하부의 접착층(160)을 제거한다. 기판 하부의 접착층(160)은 폴리이미드 계열의 접착성 테이프 또는 필름 형태를 사용하므로, 쉽게 벗겨 낼 수 있다. 이때에, 접착층 하단에 지지층이 있는 경우에는, 접착층과 지지층을 함께 벗겨낸다.1H, the adhesive layer 160 under the substrate is removed. Since the adhesive layer 160 under the substrate uses a polyimide-based adhesive tape or film form, the adhesive layer 160 can be easily peeled off. At this time, when there is a support layer at the bottom of the adhesive layer, the adhesive layer and the support layer are peeled off together.

이어서, 도1i를 참조하면, 기판 하부에 또다시 절연층(200)과 동박(210)을 적층하고 가열 가압 라미네이트 한다. 이어서, 도1j를 참조하면, 정렬마크(130) 상부에 위치한 동박(190)을 국부적으로 제거함으로써, 정렬마크(130)를 노출시켜 후속공정에서 정렬마크로 계속하여 사용할 수 있도록 한다.Subsequently, referring to FIG. 1I, the insulating layer 200 and the copper foil 210 are laminated again under the substrate and heated and laminated. Subsequently, referring to FIG. 1J, by locally removing the copper foil 190 located above the alignment mark 130, the alignment mark 130 is exposed to continue to be used as the alignment mark in a subsequent process.

도1k를 참조하면, 외층의 동박(190, 210)과 내장된 전자부품(170) 사이의 전기접속, 외층 동박(190, 210) 사이의 전기적 접속을 위해 비아홀(220, 230)을 가공한다. 비아홀 가공이 완료되면, 도1l에 도시된 대로, 비아홀 도금을 실시하여 전기 접속을 시도한다. Referring to FIG. 1K, via holes 220 and 230 are processed for electrical connection between copper foils 190 and 210 of the outer layer and embedded electronic components 170 and electrical connection between outer copper foils 190 and 210. When via hole processing is complete, via hole plating is performed to attempt electrical connection, as shown in FIG. 1L.

도2는 본 발명에 따른 전자부품 내장기판을 개략적으로 나타낸 도면이다. 도2를 참조하면, 내층의 절연층에 제작된 캐비티 속에 전자부품(170)이 내장되어 있으며, 전자부품(170)의 상하좌우 주위에는 절연층(180)으로 밀봉 적층 성형되어 있다. 2 is a view schematically showing an electronic component embedded substrate according to the present invention. Referring to FIG. 2, the electronic component 170 is embedded in a cavity fabricated in the insulating layer of the inner layer, and the laminate is sealed and molded with the insulating layer 180 around the top, bottom, left, and right sides of the electronic component 170.

본 발명은, 절연층(180)의 열팽창계수 CTE를 최대 20 ppm/℃ 이하를 충족하는 절연층을 사용하는 것을 특징으로 한다. 본 발명은, CTE ≤ 20 ppm/℃를 충족하기 위하여, 세라믹 필러(ceramic filler)의 함량을 적어도 50% 이상이 되는 에폭시 수지 자재를 사용하는 것을 특징으로 한다. 본 발명의 양호한 실시예로서, 일본 아지노모토 사의 ABF 필름, 히타치 케미컬사의 제품, 또는 스미또모 메이크 라이트사의 제품을 사용할 수 있다. The present invention is characterized by using an insulating layer that satisfies the thermal expansion coefficient CTE of the insulating layer 180 at most 20 ppm / ° C. or less. The present invention is characterized by using an epoxy resin material having a content of ceramic filler of at least 50% or more to satisfy CTE ≦ 20 ppm / ° C. As a preferred embodiment of the present invention, an ABF film manufactured by Ajinomoto, Japan, a product of Hitachi Chemical, or a product of Sumitomo Make Light, can be used.

전술한 내용은 후술할 발명의 특허 청구 범위를 더욱 잘 이해할 수 있도록 본 발명의 특징과 기술적 장점을 다소 폭넓게 개선하였다. 본 발명의 특허 청구 범위를 구성하는 부가적인 특징과 장점들이 이하에서 상술 될 것이다. 개시된 본 발명의 개념과 특정 실시예는 본 발명과 유사 목적을 수행하기 위한 다른 구조의 설계나 수정의 기본으로서 즉시 사용될 수 있음이 당해 기술 분야의 숙련된 사람들에 의해 인식되어야 한다. The foregoing has somewhat improved the features and technical advantages of the present invention in order to better understand the claims of the invention described below. Additional features and advantages that constitute the claims of the present invention will be described in detail below. It should be appreciated by those skilled in the art that the disclosed concepts and specific embodiments of the invention can be used immediately as a basis for designing or modifying other structures to accomplish the invention and similar purposes.

또한, 본 발명에서 개시된 발명 개념과 실시예가 본 발명의 동일 목적을 수행하기 위하여 다른 구조로 수정하거나 설계하기 위한 기초로서 당해 기술 분야의 숙련된 사람들에 의해 사용될 수 있을 것이다. 또한, 당해 기술 분야의 숙련된 사람에 의한 그와 같은 수정 또는 변경된 등가 구조는 특허 청구 범위에서 기술한 발명의 사상이나 범위를 벗어나지 않는 한도 내에서 다양한 진화, 치환 및 변경이 가능하다. In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures to accomplish the same purpose of the present invention. It will be apparent to those skilled in the art that various modifications, substitutions and alterations can be made hereto without departing from the spirit or scope of the invention as defined in the appended claims.

이상과 같이, 본 발명은 에폭시 수지 내에 분산처리된 실리카(SiO2) 성분의 알갱이, 즉 세라믹 필러의 함량을 50 % 이상으로 유지한 적층성형 자재를 사용함으로써, 캐비티 속에 내장한 전자부품과 좌우상하를 둘러싼 절연성 수지 사이의 열팽창계수 차이가 발생하는 것을 방지할 수 있다. As described above, the present invention uses the granulated material of the silica (SiO 2 ) component dispersed in the epoxy resin, that is, the laminated molding material in which the content of the ceramic filler is maintained at 50% or more, and the electronic component embedded in the cavity It is possible to prevent the difference in the coefficient of thermal expansion between the insulating resin surrounding the.

그 결과, 적층 성형 과정에서 기판에 크랙이 생기거나 또는 박리 (delamination), 워피지(warpage)가 발생하는 것을 방지할 수 있다. 본 발명은 인쇄회로기판 제작, 특히 반도체 칩 내장형 인쇄회로기판 또는 패키지기판 제조 시에 응용할 수 있어 제품의 수율을 증가시키고 신뢰성을 증대시킬 수 있는 장점이 있다. As a result, cracks, delamination or warpage can be prevented from occurring in the substrate in the lamination process. The present invention can be applied to the production of printed circuit board, in particular, semiconductor chip embedded printed circuit board or package substrate has the advantage of increasing the yield of the product and increase the reliability.

100, 180, 200 : 절연층
110a, 110b, 190, 210 : 동박
120 : 가이드 홀
130 : 정렬마크
150 : 캐비티
160 : 접착층
170 : 전자부품
171 : 범프
220, 230 : 비아홀100, 180, 200: insulation layer
110a, 110b, 190, 210: copper foil
120: guide hole
130: alignment mark
150: cavity
160: adhesive layer
170: electronic component
171: bump
220, 230: Via Hole

Claims (4)

경화상태의 내층 절연층에 캐비티를 제작하고, 캐비티 속에 전자부품을 내장하고, 캐비티 속에 수납한 전자부품 위에 반경화상태의 제1 절연층과 동박을 적층하고, 가열 가압하여 라미네이트 하여 상기 전자부품을 에워싸도록 하여 상기 제1 절연층을 경화시킨 후, 기판 외층 표면의 동박과 전자부품의 입출력단자 범프를 전기접속하는 비아홀을 형성하는 전자부품 내장형 인쇄회로기판 제조방법에 있어서, 상기 제1 절연층은 세라믹 필러 함량이 적어도 50% 이상인 에폭시 수지로서 열팽창계수가 CTE ≤ 20 ppm/℃ 범위에 있는 것을 특징으로 하는 전자부품내장형 인쇄회로기판 제조방법. The cavity is fabricated in a hardened inner insulation layer, the electronic component is embedded in the cavity, the first insulating layer and the copper foil in a semi-cured state are laminated on the electronic component stored in the cavity, and heated and pressed to laminate the electronic component. The method of manufacturing an electronic component embedded printed circuit board according to claim 1, wherein the first insulating layer is hardened to form a via hole for electrically connecting the copper foil on the outer surface of the substrate to the input / output terminal bumps of the electronic component. A method of manufacturing an electronic component-embedded printed circuit board, wherein the epoxy resin has a ceramic filler content of at least 50% and a thermal expansion coefficient is in a range of CTE ≤ 20 ppm / ° C. 삭제delete 전자부품을 수납하는 캐비티를 구비한 내층 절연층;
전자부품이 수납된 캐비티 공간으로 흘러들어 상기 전자부품을 상하좌우로 에워싸고 내층 절연층 위에 적층 성형되는 제1 절연층;
캐비티 내부에 수납된 전자부품; 및
제1 절연층 상부에 형성된 동박 회로와 전자부품의 입출력단자 범프를 전기접속하도록 제1 절연층을 관통하여 형성된 비아홀
로 구성되고, 상기 제1 절연층은 세라믹 필러 함량이 적어도 50% 이상인 에폭시 수지로서 열팽창계수는 CTE ≤ 20 ppm/℃ 범위에 있는 것을 특징으로 하는 전자부품내장형 인쇄회로기판.An inner layer insulating layer having a cavity for storing electronic components;
A first insulating layer flowing into the cavity space in which the electronic components are stored, surrounding the electronic components up, down, left and right, and laminated on the inner insulation layer;
Electronic components housed inside the cavity; And
Via holes formed through the first insulating layer to electrically connect the copper foil circuit formed on the first insulating layer to the input / output terminal bumps of the electronic component.
Wherein the first insulating layer is an epoxy resin having a ceramic filler content of at least 50% or more, and a coefficient of thermal expansion is in the range of CTE ≤ 20 ppm / ° C. 삭제delete
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