TW546999B - Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board - Google Patents

Abstract

A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multi-layer printed circuit board 10. Therefore, it is possible to electrically connect the IC chip 20 to the multi-layer printed circuit board 10 without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on an aluminum pad 24, it is possible to prevent a resin residue on the pad 24 and to improve the connection characteristics between the die pad 24 and a via hole 60 and reliability.

Description

546999 V. Description of the Invention (1) [Technical Field] The present invention relates to semiconductor devices such as 1C wafers, and a method for manufacturing semiconductor devices, and more particularly to a multilayer printed circuit board with a built-in semiconductor element and a multilayer printed circuit board. Of manufacturing method. [Background Art] A 1C chip is electrically connected to a printed circuit board by a construction method such as wire bonding, TAB, or flip-chip bonding. The IC chip is connected to the printed circuit board by an adhesive, and the pad of the printed circuit board and the pad of the c chip are continuously connected by a wire such as a metal, and then thermally hardened to protect the 1C chip and the wire. Encapsulating resin such as flexible resin. The tree is thin and ... ”3 η After the pad of the 1C crystal printed circuit board is continuously connected together by soldering a wire called a lead, etc., it is encapsulated with resin. Separating the dagger between the 1c chip and the crotch of the printed circuit board, however, each proceeded with a convex space. A connection is made between the 1 c chip and the printed circuit board via a connection pin. Each of these bows (pins, pins, bumps) ❿ for the electrical piece = connection: broken, wrong action of the original :: rotten money 'so it becomes the same as 1 (; crystal, each packaging side, thermoplastic resin For encapsulation, IC chip ICs start with bubbles such as epoxy resins, and when they are filled with this resin, they contain bubbles, which reduces reliability. Damage to parts and corrosion of IC pads, 7 plastic resin packaging It must be combined with each part 546999 V. Description of the invention (2) The plunger and model for resin filling are made, and even the thermosetting resin cannot be selected considering the lead parts and solder resist (s〇). (ide, ;; r-wM) and other resins, so it has also become a cause of higher costs. The outer ::: surface, as described above, can not be printed wiring | (structured substrate) external women's clothing 1C crystal 4 Therefore, by burying semiconductor elements in the substrate, two layers, forming a laminated layer to obtain electrical continuity, conventional techniques have been disclosed in JP-A-9-32U08 (USP58751 00) and JP-A-10_256429. 'Japanese Patent Application No. 1 1 -1 26978 etc. Japanese Patent Application No. 9-32U08 (USP58751 〇〇) 'The semiconductor elements forming stud bumps on the die pad are embedded in the printed wiring board, and wiring is formed on the stud bumps to obtain electrical connection. However, the stud bumps are onion-shaped and The height changes greatly, and when the interlayer insulation layer is formed, the performance is reduced, and even if the interlayer window is formed, it is not easy to connect = the bumps are planted one by one 'can not be installed together ... produced by nature; The structure of the semiconductor element on the Taomei board is electrically connected in the form of flip-chip bonding. However, the ceramic properties are poor, and semiconductor elements cannot be accommodated ... the bumps = also increase. Therefore, the smoothness of the interlayer insulation layer is impaired, and Decrease the whole ^ Continued 0 JP-A No. 1 1 -1 26978, unveiled in the receiving part of the gap; Yuan, and other electronic parts are connected to the conductor circuit, and the printed wiring board is stored through the interlayer window. However, because There is a gap in the accommodating part, = the position is shifted, and it also causes the connection with the pad of the semiconductor element. 546999

Therefore, the die pad is susceptible to oxidation. The purpose is to provide a semiconductor element that is not electrically connected through the pins, so that the die pad and the conductor circuit are directly connected to each other, and the film increases the problem of resistance. The present invention is a method for directly manufacturing a printed wiring board by obtaining a component in view of the above problems. In addition, there are many manufacturing methods for solving the problem of high semiconductor devices due to disconnection of the hot part wiring generated by the embedded semi-semiconductor device. In addition, the printed wiring board cannot be effectively used. In order to solve this problem, the present invention solves the problem that the built-in semi-conductor 0 conductor elements of Lai-Nan 0 are contained in a resin-made printed wiring board, and warping occurs in the printed wiring board, thereby reducing reliability. The above-mentioned problem is to provide a printed circuit board with a built-in reliability layer and the multilayer printed wiring board to efficiently manufacture a semiconductor device with a high built-in reliability. The above-mentioned problem is to provide a multilayer printed wiring board that efficiently produces a conductive element. In addition, when a multi-layer printed wiring board composed of a substrate in which semiconductor elements are embedded, housed, or housed is used as a structure substrate, a chip set, etc., it is connected to an external substrate (called a daughter board or a mother board). ) Electrical connection, and can perform functions. Therefore, 'the multilayer printed wiring board must be provided with a BGA and a conductive connection pin (PGA). The BGA and PGA! Are formed by disposing a solder pad on a solder photoresist layer on the surface of a multilayer printed wiring board. However, a solder bump is provided on the surface layer of a substrate embedded with a semiconductor element, and a functional test and a reliability test are electrically connected to the external substrate.

546999 5. In the description of the invention (4), 'confirm that peeling occurs in the interlayer insulation layer, solder photoresist, solder bump, solder bumps = interlayer resin insulation layer, and corrosion-resistant metal, etc. Solder layer migration. In particular, cracks occur on the interlayer insulation layer and =: = = and positional deviations. Therefore, it can be understood that the pad connection and reliability of the + conductor element are reduced. 'Block and conductor circuit The purpose of electrical properties is to provide electrical continuity, especially the creation of crystals in semiconductor components. The present invention is a multilayer printed wiring board that solves the above problems and has high reliability. The multilayer printed wiring board has been studied in detail by the inventors. The last name is the fruit grain, and a transition layer is formed. And; 兮 西 $ 二 二 叫 二 卞 守 Ｍ 70 pieces of crystals • te λ \ h ^ ^ k / another layer of semiconductor elements, even if buried, stored, and harvested in For printed wiring boards, interlayer sounds are applied to form the interlayer window to obtain the desired size and shape. Reasons for setting a transition layer on the die pad of the K-wafer K wafer. 1C crystal: General Is Shao and other systems When the interlayer window is formed into an interlayer insulating layer, if the original crystal is exposed, the resin layer on the surface of the pad after the .4 image is likely to leave resin. Therefore, it is easy to cause the image liquid. It may cause discoloration of the pads. On the other hand, when "layer windows are formed by lasers", there is a danger of burning the pads. In addition, under the condition of not burning, resin residues may occur on the pads during operation. In the subsequent steps, immersion with acid and oxidant or etching solution, after various tempering (anneal) steps, there will be discoloration and dissolution of the plutonium of the 1C wafer. In addition, the plutonium of the 1C wafer is about 40 // m The diameter is made, the interlayer window is large, because there must be position tolerance, it is easy to cause position shift, etc., non-continuity, etc. 546999 V. Description of the invention (6) The following describes the transition layer defined by the present invention. The 10-chip mounting technology that is not used in the conventional technology is directly placed. The 1C wafer is directly connected to the printed wiring board, and the intermediate interposer is placed in the middle. It is characterized by more than 2 layers of gold. Or , Which is larger than the semiconductor element The die pad of the Vulture 1 L wafer. The electrical continuity and positional consistency of the chip are suppressed, and the interlayer window of the laser and etching solution may be damaged, which is not suitable for the Japanese pad. ^ Directly On the interlayer window and substrate of the gold π insulating layer forming the conductor layer of the printed wiring board: TF: TF is a built-in 1Cg substrate used in the present invention, and # 4 槲 日 日 荣 λα 日 片 4's electronic parts can be used Resin is made of oxygenation tree, which is a special reinforcement material and heartwood. It is a tree of oxidized g and fat, BT resin, age resin, etc .: Oxygen tree users. In addition, you can also use-^^ 用―General printed wiring board is made of resin sheet with metal film, resin film laminated board, sheet panel, wax will completely dissolve when there is no temperature, but 'Apply 35. . . All of the above-mentioned 1C wafers are over-conductive metal films. The metal is physically vaporized, and it is better to form Yashima, gold, copper, etc. It is better to be thick-walled. Particularly good is 〇 · "~ 丨 · 〇. Also formed on this metal film is a metal film on the helmet side, and a metal film can be provided with more than one layer of nickel, aluminum, and electrolytic plating. Excellent. The thickness is preferably 0.01 to 5 Å, and δ, gold, silver, or the like is formed to 5 · 0, particularly preferably 0. Bu 3.0. 2160-3798-pf.ptd $ 9 pages 546999 V. Description of the invention (7)-The metal film is given thickness by electroless or electrolytic plating. The types of electroplating are nickel, copper, gold, silver, lead, iron, and the like. Because the electrical, economical, and subsequent superimposed conductor layers are mainly copper, copper is preferred. The thickness is preferably performed in the range of Bu. Thicker than this thickness causes undercuts when the last name is engraved, and voids occur at the interface between the formed transition layer and the interlayer window. After that, an etching photoresist is formed, and the metal outside the transition layer is exposed and developed to perform etching, and an & transition layer is formed on the die pad of the IC wafer.

In addition to the method for manufacturing the above-mentioned transition layer, a thin-film photoresist may be formed on the metal film formed on the 1C wafer and the core substrate to remove the portion of the transition layer. After thickness is provided by electrolytic plating, the photoresist is peeled off to Touching the etching solution, a transition layer is formed on the pad of the IC wafer similarly. As a result of detailed research, the inventor has learned that a heat sink is installed inside a semiconductor element buried in a printed wiring board, and heat generated in the semiconductor element is dissipated without bending or disconnection in the printed wiring board. Feng t =: t semiconductor elements are made of laminated wiring with resin, and the + conductor TL and the printed wiring board can be properly connected. Heat sink ΪSemiconductor element 'via conductive adhesive 4: The thermal conductivity of the adhesive is high and can be efficient; the heat generated by the semiconductor element is dissipated in the "state", and the chain has an upper layer, if the layer has The prepreg of the through hole containing the 1c wafer is Hii pressed. The epoxy resin is extruded from the prepreg and covered with I. The top of the core becomes the core base 4 which is hardened from the preform. So it becomes 'W Qiantan'. When forming a superimposed layer, but when;

546999 V. Description of the invention (9) The invention in the 35th aspect of the patent application is that the terminal is bonded to the sheet on the sheet at the bottom of the through hole of the core substrate to mount the semiconductor element, and the resin is filled in the through hole. The sheet is peeled off to form a laminated layer. That is, since a semiconductor element is mounted with a terminal bonding sheet, and after the sheet is peeled off, a laminated layer is formed on the semiconductor element, and the wiring of the terminal and the laminated layer can be electrically connected appropriately. Multilayer printed wiring board. The method for manufacturing a multilayer printed wiring board with the scope of application for patent No. 36 has at least the following steps (a) to (i): (a) coating a sheet on the bottom of a through hole formed on the core substrate;

(b) bonding a terminal to the sheet to mount a semiconductor element on the sheet at the bottom of the via; (c) filling the via with a resin; (d) pressing and temporarily hardening the resin; (e) ) Peeling the sheet; (f) grinding the bottom side of the core substrate to expose the bottom of the semiconductor element; (g) temporarily hardening the resin; (h) installing a heat radiation plate on the bottom of the semiconductor element; and (i) the A stacked layer is formed on the semiconductor element.

The invention according to the 36th aspect of the patent application is that a semiconductor element is mounted on the sheet at the bottom of the through hole of the core substrate by bonding to the sheet, and after filling the resin in the through hole, the sheet is peeled off to form a stack.合 层。 Combined layers. That is, since a semiconductor element is mounted with a terminal bonding sheet, after the sheet is peeled off, a laminated layer is formed on the semiconductor element, and the wiring of the terminal and the laminated layer can be properly electrically connected.

546999

V. Description of the Invention (ίο) Continuing, it is possible to manufacture highly reliable semiconductor elements with built-in multilayer printed wiring boards. In addition, since the bottom side of the core substrate is polished to expose the bottom of the semiconducting semiconductor 二 -αa 十 ^ / L f, a heat radiation plate can be attached to the bottom of the 70 semiconductors, and the operation stability of the conductor element can be improved. ^ ^ It is appropriate to use a UV tape that reduces the adhesion by UV irradiation as a sheet covering the through holes of the core and A plate. Because of UV irradiation, the semiconductor “secondary” sub-adhesive is peeled off without leaving any residue. The terminal and the wiring of the laminated layer can be electrically connected, and a highly reliable semiconductor element can be built with a multi-layer $ 2 wiring board. The core substrate is printed on multiple layers. By borrowing it, the plate can be inserted and retracted in the middle and the electrical properties of the conductor window. On the outer half plate of the middle plate, it is appropriate to pressurize the resin under reduced pressure. By reducing the pressure, There will be air bubbles remaining between the core and the resin, as well as in the middle of the resin, which can improve the reliability of the S brush wiring board. Μ The through hole formed in the core substrate is also provided with a suitable taper. The through hole of the core substrate and the resin There are no air bubbles or grooves between them. "Improve the reliability of the multilayer printed wiring board. Also, it can ensure the core beauty. X soil

2 The multilayer printed wiring board described in item 41 of the patent scope, the interlayer insulation layer is repeatedly formed on the substrate where the semiconductor element is buried or housed, the interlayer window is formed in the aforementioned interlayer insulation layer, and An external connection terminal is formed on a region directly above the semiconductor element in the substrate. ^ The invention according to item 41 of the scope of benefit distinguishes the area on the substrate of the built-in multilayer printed circuit MEMS component from the product area of the semiconductor component that is not built-in. Thus, the area on the substrate on which the semiconductor element is not built

546999 V. Description of the Invention (11) The domain is equipped with external connection terminals (BGA / PGA). The above-mentioned peeling of the external connection terminals and the like occurs due to the difference in thermal expansion coefficient of the semiconductor element, the external substrate, and the interlayer insulating layer K and. That is, the thermal expansion coefficient of the ceramic composition and the external substrate is small, and the expansion and contraction due to the thermal expansion clothing is also small = On the one hand, the interlayer insulating layer of the resin composition and the solder photoresist layer, the components, and the external substrate have a larger thermal expansion coefficient To;: shrink is also large. The thermal expansion coefficient *, stress is concentrated around the external connection = (BGA / PGA), etc., and peeling or cracking occurs. ~ In short, it is possible to reduce the thermal expansion by arranging the external terminal ⑼ / to hide the area on the substrate of the semiconductor element.): Not inside =, it only occurs around the external terminal (BGA / PGA), etc. The peeling off and position of the extension terminal (BGA / PGA) of the Bu Department has improved the electrical continuity and reliability. Here, the external connection terminal is used to construct the IC crystal. The external substrate, the so-called mother board, is used for connection 2 of the daughter board. 4 daughter boards refer to BGA, PGA, and solder bumps. The invention of item π in the case of π ”if the invention of item 42 is

The wiring board is technically characterized by the pad / knife of the aforementioned half piece, forming a transition layer for connection with the aforementioned interlayer window formed on the lowest acoustic conductor 7L. The 9-layer'L inter-layer insulation layer applies for the 42nd invention of the patent scope to cover the transition layer. Preventing the use of solvents that may be left on the grains by the use of a steel part on the grain pad prevents the use of solvents: Γ ^ Page 14 2160-3798-pf.ptd 546999 V. Description of the invention (12) In the next step It is immersed in acid and oxidant or etching solution, and it will not cause discoloration and dissolution of the grain pad in various tempering. Can prevent the oxygen of the die pad; film formation. This improves the continuity and reliability of the die pad and the interlayer window. In addition, by using a die pad having a diameter larger than 20 on the die pad of the 1C wafer, it can be confirmed that the interlayer f is grounded. The preferred transition layer is:

Those above the diameter. @ π IJ μmr The invention of item 43 in the scope of the patent, please claim the item 41 of the layered printed wiring board. Its technical feature is to fill the recessed through hole of resin filling material between the buried person, the receiver or the receiver. The 43th invention of the semiconductor element hole range, 'the substrate is improved by filling a resin filling material between the recessed portion of the substrate or the through element.' This resin filling material, because of the gentle stress, prevents the core substrate from The network of cracks and interlayer trees wants to buckle in a day. Therefore, the solder bumps can be stopped and the position can be shifted, so you can mention: Thunder, to prevent the solder bumps from being decharged # # ， $ ^ k 呵Electrical continuity and reliability. Thermosetting composites can be used as resin fillers, resins, thermoplastic resins, or the like

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 (A), (B), ^ Manufacturing process diagram of a semiconductor element. ) Is a manufacturing process diagram of the second figure (A), (B), (Γ, 〆) of the first embodiment of the present invention. (C) is a semiconductor element of the first embodiment.

546999 V. Description of the invention (13) FIGS. 3 (A) and (B) are manufacturing process diagrams of the semiconductor device of the first embodiment. FIG. 4 (A) is a plan view of the silicon wafer 20A of Example 1, and (B) is a plan view of a singulated semiconductor element. 5 (A), (B), and (C) are manufacturing process diagrams of a semiconductor device according to a first modification of the embodiment. (A), (B), and (C) of FIG. 6 are manufacturing process diagrams of the semiconductor device according to the first modification of the first embodiment. Figures 7 (A) and (B) are semiconductors which are the first modification of the first embodiment

Manufacturing element diagram of the body element. Fig. 8 (A), (B), (C), (D) are examples! A manufacturing process diagram of a second modification of the semiconductor device. Figure 9 (A), (B), (c), (D) are examples! A manufacturing process diagram of a first modification of the semiconductor device. Figures 10 (A), (B), (c), and (D) are manufacturing process drawings of the multilayer printed wiring board of Example i. Figures 11 (i), (β), and (C) are manufacturing process diagrams of the multilayer printed wiring board of Example 1.

Fig. 12 (A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board of Example i. Figure 1 3 (A), (B) ^ (C) #A ^ ^ 1. Manufacturing process diagram of the wiring board. … &Amp; 1 # 夕 层 印刷 Figure 14 is a cross-sectional view of the multilayer printed wiring board of Example 1. Fig. 15, (β), (C), (D) are the first embodiment

2160-3798-pf.ptd p. 16 546999

5. Description of the invention (14) Production of multilayer printed wiring board according to the first modification FIG. 16 is a cross-sectional view of the first modification 实施 of the first embodiment. Fig. 17 of the multilayer printed wiring board of the example is a graph showing the results of Example 1 and Example. Summary of Semiconductor Element in First Modification FIG. 18 is a graph showing the results of semiconductor elements in the second modification and the third modification. Figs. 19 (A), (B), and (C) are diagrams showing the steps of manufacturing a printed wiring board in accordance with the second embodiment of the present invention. Figures 20 (B), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board of Example 2. 21 (A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board of Example 2. FIG. Figures 22 (A), (B), and (C) are diagrams showing the manufacturing steps of the multilayer printed wiring board of Example 2. Figures 23 (A), (B), and (C) are diagrams showing the manufacturing steps of the multilayer printed wiring board of Example 2. FIG. 24 is a cross-sectional view of a multilayer printed wiring board of Example 2. FIG. Figures 25 (A), (B), (C), and (D) are manufacturing process diagrams of a multilayer printed wiring board according to the first modification of the second embodiment. Fig. 26 is a sectional view of a multilayer printed wiring board according to a first modification of the second embodiment. Figures 27 (A), (B), and (C) are diagrams showing manufacturing steps of a multilayer printed wiring board according to a second modification of the second embodiment.

2160-3798-pf-Ptd Page 17 546999 V. Description of the invention (15) Figure 28 (A), (B), (C) are manufacturing steps of the multilayer printed wiring board according to the third embodiment of the present invention . Figures 29 (A), (B), and (C) are diagrams showing the manufacturing steps of the multilayer printed wiring board of Example 3. (C) is the multi-layer printing of Example 3 (C) is the multi-layer printing of Example 3 (C) is the multi-layer printing of Example 3 Fig. 30 (A), (B) Manufacturing process diagram of a wiring board. Fig. 31 (A), (B) Manufacturing process diagram of a wiring board. Figure 32 (A), (B) Manufacturing process diagram of the wiring board. Fig. 33 is a cross-sectional view of a multilayer printed wiring board according to a third embodiment. 34 (A), (B), (C), and (D) are manufacturing steps of a multilayer printed wiring board according to the first other example of the third embodiment. Fig. 35 is a sectional view of a multilayer printed wiring board according to a first alternative example of the third embodiment. Figures 36 (A), (B), and (C) are manufacturing process diagrams of a multilayer printed wiring board according to the first modification of the third embodiment. Fig. 37 (A), (B), (C) are the first modification of the third embodiment

Example manufacturing process diagram of a multilayer printed wiring board. Figs. 38 (A), (B), and (C) are manufacturing process diagrams of a multilayer printed wiring board according to a first modification of the third embodiment. Figures 39 (A), (B), and (C) are diagrams showing manufacturing steps of a multilayer printed wiring board according to a first modification of the third embodiment. Figure 40 (A), (B), (C) are the first modification of the third embodiment

2160-3798-pf.ptd Page 18 546999 V. Description of the invention (16) The manufacturing steps of the multilayer printed wiring board. Figure 41 is a cross-sectional view of a multilayer printed wiring board according to a first modification of the third embodiment. 42 (A), (B), (C), and (D) are manufacturing steps of a multilayer printed wiring board according to a first modification of the first modification. Fig. 43 is a cross-sectional view of a multilayer printed wiring board according to a first modification of the first modification. Figs. 44 (A), (B), and (C) are diagrams showing the steps of manufacturing a multilayer printed wiring board according to the first modified example and the second modified example of the third embodiment. 45 (A), (B), (C), (D), and (E) are manufacturing steps of a multilayer printed wiring board according to the second modification of the third embodiment. 46 (A), (B), (C), and (D) are manufacturing process diagrams of a multilayer printed wiring board according to a second modification of the third embodiment. 47 (A), (B), and (C) are diagrams showing the manufacturing steps of a multilayer printed wiring board according to a second modification of the third embodiment. Figs. 48 (A), (B), and (C) are diagrams showing manufacturing steps of the multilayer printed wiring board according to the second modification of the third embodiment. Figures 49 (A), (B), and (C) are manufacturing process diagrams of a multilayer printed wiring board according to a second modification of the third embodiment. Fig. 50 is a cross-sectional view of a multilayer printed wiring board according to a second modification of the third embodiment. (A), (B), (C), and (D) of FIG. 51 are manufacturing steps of a multilayer printed wiring board according to the second modification of the third embodiment. Fig. 52 shows a multilayer printed wiring board according to the first modification of the second modification.

2160-3798-pf.ptd Page 19 546999 V. Description of the invention (17) Sectional view. Fig. 53 (A), (B), (C), (D), and (E) are manufacturing process diagrams of the multilayer printed wiring board according to the fourth embodiment of the present invention. (A), (B), (C), (D), and (E) of FIG. 54 are manufacturing steps of the multilayer printed wiring board of the fourth embodiment. 55 (A), (B), (C), and (D) are diagrams showing the manufacturing steps of the multilayer printed wiring board of Example 4. FIG. Figures 56 (A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board of Example 4.

Figures 5 to 7 are sectional views of the multilayer printed wiring board of Example 4. Figs. 58 (A), (B), (C), and (D) are diagrams showing manufacturing steps of the multilayer printed wiring board according to the fifth embodiment of the present invention. Figures 5 and 9 (A) (B) and (C) are diagrams showing the manufacturing steps of the multilayer printed wiring board of Example 5. Figures 60 (A), (B), and (c) are diagrams showing the manufacturing steps of the multilayer printed wiring board of Example 5. FIG. 61 (A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board of Example 5. FIG. Figs. 62 (A) and (B) are the manufacturing steps of the multilayer printed wiring board of Example 5. Fig. 63 is a sectional view of the multilayer printed wiring board of Example 5. Figs. Figure 64 is a cross-sectional view of a multilayer printed wiring board of Example 5. Fig. 65 is a sectional view of E-E in Fig. 63. Figure 6 (A) is a plan view of the multilayer printed wiring board of Example 5.

^ — 2160-3798-pf.ptd Page 20, 546999 V. Description of the invention (18) '~ " --- Figure, (B) is a plan view of a multilayer printed wiring board with bumps arranged in a thousand birds, (C) This is a plan view of a multilayer printed wiring board of a comparative example. Figures (A), (B) and (C) are diagrams showing the manufacturing steps of a multilayer printed wiring board according to another example of the fifth embodiment. Figs. 6 (8), (β), and (C) are diagrams showing manufacturing steps of a multilayer printed wiring board according to a first modified example of the present invention. Figs. 69 (A), (β), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the first modification. Figs. 70 (A), (β), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the first modification. Examples Examples of the present invention will be described below with reference to the drawings. A. The semiconductor element f is described with reference to FIG. 3 (A) showing the cross section of the semiconductor element 20 and the fourth country fu, 1 showing the plan view. The structure of the semiconductor element (1C Japanese film) of Example 1. [Embodiment 1] On FIG. 3 (B), household crystals + +, f 1 and 99, and semiconductor elements 20 with green ions are provided with crystal grains • 塾 22, shells,] forming the main | = An opening to protect Lai is formed. A thin film layer 33 and a transition layer 38 of a thick additional layer. The transition layer 38 'is formed of a metal film. Composed of 37. In other words, 'continued with more than 2 levels, refer to Figure] to Figure 4 and refer to Figure 3 (B) and the above 2160-3798-pf.ptd

21st stomach 546999 V. Description of the invention (19) The method of manufacturing a semiconductor device. (1) First, the wiring 21 and the die pad 2 2 are formed on the stone eve wafer 20A shown in FIG. 1 (A) by a predetermined method (refer to FIGS. 1 (β) and 1 (B). Figure 4 (A) of the plan view, and Figure 1 (^) captures a section B-B of Figure 4 (A)). (2) Next, a protective film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided in the die pad 22 (Fig. 1 (C)). (3) Physical evaporation of silicon wafer 20A, such as evaporation and sputtering, is performed to form a conductive metal film (thin film layer) 33 in its entirety. (Figure 2 (A)). The degree is preferably formed in the range of 0 · 〇 (Π ~ 2.0 // m. Below this range = %%, and a thin film layer cannot be fully formed. When the thickness is above this range, the thickness of the film formed by Syngene The most appropriate range is from 0.01 to 10 vm. A metal selected from tin, chromium, titanium, nickel, lead, cobalt, gold, and copper is preferably used. These metals are used as grains. The protective film is also deteriorated. In Example 1, the thin film layer 33 was formed by sputtering. The adhesion between chromium and metal is good, and the invasion of moisture can be suppressed. Furthermore, copper is added on top Application material. It is also possible to form two layers of copper and copper in a vacuum reaction chamber. At this time, after the thickness is m (4), a photoresist layer of photosensitive photoresist and dry film photoresist is formed on the thin film layer 33. Through a photomask (not shown) on the photoresist layer, and n: there is a layer 38 and a thick additional layer (electrolytic plating film) 37 (Fig. 2 (b) /.)

2160-3798-pf.ptd Page 22 546999 V. Description of the invention (20) The types of plating are copper, copper, gold, silver, Asia, iron, etc. Because the electrical characteristics, economy, and the superposed conductor layer formed in the subsequent steps are mainly copper, copper is preferably used. In Example 1, copper was used. The thickness is preferably performed in a range of 1 to 20 // m. (5) After the plating photoresist 35 is removed with an alkali solution, etc., the plating is removed with an after-treatment solution such as sulfuric acid-nitrogen peroxide water, vaporized first iron, vaporized second copper, second copper complex-organic acid salt, and the like. A metal film 33 is formed under the photoresist 35, and a transition layer 38 is formed on the substrate 22 of the 1C wafer (FIG. 2 (C)). (6) Next, a rough screen 38 α is formed by etching the surface of the transition layer 38 by spraying an etchant on the substrate with a spray (FIG. 3 (A)). The roughened surface can also be formed using electroless electroforging and redox treatment. (7) Finally, the silicon wafer 20A forming the transition layer 38 is divided into single pieces by dicing or the like to form a semiconductor device 20 (FIG. 3 (B) and FIG. 3 (B) and FIG. 3) (B) a plan view). After that, if necessary, operation confirmation and electrical inspection of the divided semiconductor device 20 may be performed. Since the semiconductor element 20 is formed with a transition layer 38 that is larger than the die pad 22, the precision of the inspection of the probe valley is increased. [First Alternative Example of Embodiment 1]

In Example 1 described above, the thin hafnium layer 33 is formed of chromium. In contrast, in the first alternative example, the thin film layer 33 is formed of titanium. Titanium is applied by vapor deposition gas sputtering. Titanium and metal have good adhesion, which can inhibit the invasion of moisture. [Second Alternative Example of Embodiment 1] In Embodiment 1 described above, the thin film layer 33 is formed of chromium. In contrast, in the first alternative example, the thin film layer 33 is formed of tin. Titanium is deposited by vapor deposition

2160-3798-pf.ptd Page 23 546999 V. Application Note (21). Titanium and metal have good adhesion, which can inhibit the entry of moisture. [Third Alternative Example of Embodiment 1] Nine In the above-mentioned Embodiment 1 ', the thin film layer 33 is formed of chromium. In contrast, in a third alternative, the thin-film layer 33 is formed of lead. [A fourth alternative example of the first embodiment] In the first embodiment, the thin film layer 33 is formed of chromium. In contrast, in the fourth alternative example, the thin film layer 33 is formed of nickel. Nickel is formed by sputtering. Titanium and metal have good adhesion, which can inhibit the invasion of moisture. [Fifth alternative example of embodiment 1] In the above-mentioned embodiment 1 ', the thin film layer 33 is formed of chromium. On the other hand, in a fifth example, the thin film layer 33 is formed of cobalt. Furthermore, in each case, copper may be further laminated on the thin film layer. [First Modified Example of Embodiment 1] A semiconductor device 20 according to a first modified example of Embodiment 丨 will be described with reference to Fig. 7 (B). Referring to FIG. 3 (B), in the semiconductor device of the first embodiment described above, the transition layer 38 has a two-layer structure composed of a thin film layer 33 and a thick additional layer 37. On the other hand, in the first modified example, as shown in FIG. 7 (B), the transition layer 38 is constituted by a three-drawer composed of a first thin film layer 33, a second thin film layer 36, and a thick additional layer 37. We will continue to describe a method of manufacturing a semiconductor device according to the first modification described above with reference to FIG. 7 (b) with reference to FIGS. 5 to 7. U) Baixian, on the silicon wafer 20α shown in FIG. 5 (A), a wiring 21 and a die pad 22 are formed (FIG. 5 (β)). (2) Next, a protective film 24 is formed on the die pad 22 and the wiring (No. 5 546999 V. Description of the Invention (22) Figure (C)). (3) Gold formed by physical sputtering such as sputtering on silicon wafer 20A Gold, steel nickel, titanium and metal have good adhesion 7: 2 and the electrical characteristics will not be inferior! The thin film Shexian ^ can suppress the intrusion of moisture. The electrical metal film (the first thin film layer) (Figs. 5 and 5), the comprehensive formation guide is preferably formed in a range of 0 · 0 (Π ~ 2 · 0 // m. In >)). This thickness is less able to form a thin concrete layer. The thickness of the film changes in the area above and below the fan garden. The most suitable range is 0.001 ~. If it is formed, it is preferable to use one selected from the group consisting of tin, chromium, titanium, nickel, and sub-Y "m. These metals are used as the protective film of the grain pad. Cobaltization. Chromium 1. In the first modified example, the first thin film layer 33 is in the shape of chromium. U) On the first thin film layer 33, the second thin film layer 36 is laminated by any one of sputtering and hafnium. (Figure 6, ...) The metal that can be laminated on electrolytic plating is selected from the group consisting of nickel, copper, gold, and silver. In this case; copper: any one of the forms is better. Because copper is cheaper. Nickel has good adhesion to the film, which is difficult! ^ Electrical transmission is preferably 〇 · 〇 卜 5.0 · '_ Especially preferably, it is 3 Å and cracks. The thickness is formed by electroless plating 2 thin film layer 36. The first modified example is the combination of the first thin film layer and the second thin film layer of copper, chromium-nickel, titanium-copper, titanium-nickel, and the like. ~ The advantages of the performance are better than other combinations. After π electric transmission (5), a photoresist layer is formed on the second thin film layer 36. The photoresist layer is placed on the photoresist layer, and exposed and developed. (The non-formed portion 35a is not shown in the figure. An electrolytic plating is applied to the photoresist layer, and a thick additional layer (electrolytic plating film) 37 is provided on the resist 35 (Fig. 6 (β '成 部 35a). Form 546999 V. Invention Explanation (23) --- The types of electroplating are copper, nickel, gold, silver, yazuo, iron, etc. Because of the electrical and economic properties and the subsequent formation of the superposed conductor layer is mainly copper, it is better. Copper is used. The first modification is copper. The thickness is preferably in the range of 200 vm. (6) After removing the plating resist 35 with a test solution, etc., the sulfuric acid-hydrogen peroxide water is used to vaporize the second The remaining liquid of iron, vaporized second copper, second copper complex-organic acid salt, etc. removes the second thin film layer 36 and the metal film 33 under the plating photoresist 35, and forms a transition on the pad 22 of the IC wafer Layer 38 (Figure 6 (C)).

(7) Next, the surface of the transition layer 38 is etched to form a rough day surface 38 α by spraying an etchant on the substrate with a spray (Fig. (A)). The roughened surface can also be formed using electroless plating and redox treatment. (8) Finally, the silicon wafer 20A forming the transition layer 38 is divided into blocks and the like and divided into a single piece to form a semiconductor element 20 (Fig. 7 (B).) [The first i of the first modification of the first embodiment Other Examples] In the first modified example described above, the first thin film layer 33 is formed of chromium, the thin film layer 36 is formed of electroless copper electroplating, and the thick additional layer 37 is formed by electric ore. In contrast, in the first alternative example ' The first film layer 3 ^

Therefore, the second thin film layer 36 is formed by sputtering copper, and the thick additional layer 37 θ ρ is formed by copper plating. The thickness of each layer is chrome 疋 to electrolytic copper 15_. Copper, electrolysis [Second alternative of the first modification of Example 1] In the second alternative, the first thin film layer 3 3 is formed of titanium, the second thin film layer 36 is formed, and the thickness is formed by electrolytic copper plating. Additional thickness of electroless steel shape is 0.07 / zm of titanium, copper 1 · 0 # πι, electrolytic copper 5μM

546999 V. Description of the invention (24) [Third other example of the first modified example of the first embodiment] In the third other example, the first thin film chip layer 36 'is formed of titanium and the thick deposit is formed by electrolytic copper ore: Layer: The copper formation degree of the flooded ore is given as titanium 0.06 // m, steel 0.5, and electrolytic copper 15 cores. Thickness of each layer [Fourth alternative example of the first modified example of Embodiment 1] In the fourth alternative example, the i-th thin film sound recording is formed of chromium to form the second thin-film layer 36, and the copper is decomposed by f ^ The thickness of the ore layer is 0.07 mm chromium, and the additional layer 37 is thick. Each [Fifth alternative example of the i-th modified example of Embodiment 1] electrolytic steel 15_. Nickel shape = = The first thin film layer 33 is formed of titanium, and the electroless ore is used as the layer: layer 0 6 ′ is formed by electrolytic copper ore to form a thick layer. Each "prediction is 0.05 # m of titanium, nickel plating i.2 // m, [Second modification of Example 1] electrolytic copper 15 / zm. ΪΪΓ diagram of the example: The semiconductor element 2 of the second modification is shown. The second change of Example 1 is roughly the same. The operation is in Camp V; Figure 3 (B) and the above real additivM bumps into the real yoke Example 1, using a semi-additive (semi transition household 38 W in photoresistor) The non-formed part forms a thick additional layer 37 to form the second one. In the second modification, the addition of the surname is used to cut the heart. After the thick additional layer 37 is uniformly formed, a photoresist is set to remove the first resistive non-etching The formation portion forms the transition layer 38. The manufacturing method of the second modification will be described with reference to FIG.

(Figure 2U) and as shown in the above Example 1, a conductive metal film is fully formed on the silicon wafer 20A film (physical vapor deposition of a film, etc.) and "film layer" 3. (Section 8 (A)). The thickness is preferably

2160-3798-pf.ptd page 27 546999. The range above this range is 0.01 to L0, a protective film of titanium, nickel, lead, and thallium, a grain pad, and electrochromium. Above the chromium thin film layer 33 (Fig. 8 (B)) Lead, iron, etc. Because the bulk layer is mainly copper with a thickness of 1.0 to 2 0, light will be formed on the void layer 37 at the etching interface described later. 5. Description of the invention (25) The range of 0 · 001 ~ 2 · 0 // ιυ forms a thin film layer on the surface. The thickness varies. The most appropriate range is to use a metal selected from tin, #, and these metals as grains and the like as a protective crystal modification. The thin film layer is sputtering (2) An electrolytic shovel is applied to (electrolytic plating film) 37 (copper, An example of a change in the superposition of nickel, gold, silver, and Yahoubin is the use of steel. $ When it is thicker than this range, the transition layer and the interlayer window are behind (3) when the thickness is below the thick enclosure. 05。 Can not be fully 'will produce a formed film. The formed metal is better, the junction, gold, copper one. And the electrical characteristics will not deteriorate. The characteristics will not deteriorate. In the second change thickness to 0.05.

Thickly add additional layers uniformly. The types of records to be formed are electrical, economical, and, preferably, copper is used, and the range of 2 // m is better. Will cause undercuts when in shape. X resist layer 35 (Fig. 8 (c) (4) Remove photoresist 35 with an etching solution such as sulfuric acid-per-gas hydrogenated water, second ferric chloride, second copper diisocyanate-organic acid chloride etc.) After the non-shaped second metal film 33 and the thick additional layer 37, the photoresist 35 is peeled off, and a transition layer 38 is formed on the κ crystal 22 (FIG. 8 (D)). In the subsequent steps, the fragrance pad example 1 is the same, so the description is omitted. Xiao Shi [First alternative of the second modification of the first embodiment] In the second modification described above, the thin film layer 33 is formed of chromium. Accordingly, the first alternative example is the thin film layer 33 formed of titanium. ...

2160-3798-pf.ptd

546999 V. Description of the Invention (26) [Third Modification of First Embodiment] A semiconductor device 20 according to a third modification will be described with reference to FIG. 9. Referring to FIG. 8 and referring to the semiconductor device of the second modification, the transition layer 38 has a two-layer structure composed of a thin film layer 33 and a thick additional layer 37. In contrast, in the third modified example, as shown in FIG. 9 (D), the transition layer 38 has a three-layer structure composed of a first thin film layer 33, a second thin film layer 36, and a thick additional layer 37. A manufacturing method of the third modified example will be described with reference to FIG. 9. As in the first modification of Example 1 with reference to FIG. 6 (A), the thin film layer 33 is laminated with a white film layer 36 by sputtering, evaporation, and electroless plating (FIG. 9). (A)). In this case, the metal that can be laminated is preferably copper, gold, or silver. In particular, use either copper or nickel. # 二 ί. Because steel is cheap and electricity is good. Nickel, often supplied with the film for unpacking1, is difficult to lift off and crack. In the third modified example, the combination of the first thin film layer and the second thin film layer, which is non-electrolytic, is the advantage of chromium uniformity, i.e., steel, titanium, and nickel. The advantages of bonding to metals and electrical transmission are better than other combinations. (2) Electrolytic plating, copper, gold, silver, and sublayers 6 are applied uniformly on W)). Thick production, thick additional layer 37 made of iron (Fig. 9, thickness is preferably 1 ~ 20 // Π1.). A photoresist layer 35 is then formed on the thick additional layer 37 (Fig. 9 (C)

(4) Sulfuric acid-peroxidation, oxygenated water, gasification of second iron, gasification of second copper

2160-3798-pf.ptd Page 29 546999 V. Description of the invention (27) The photoresist is removed by an etchant such as a bi-copper complex-organic acid salt 3, and the first thin film layer 33, the second thin film layer 36 and After the thick additional layer 37, the photoresist 35 is peeled off, and a transition layer 38 is formed on the pad 22 of the 1C wafer (FIG. 9). The subsequent steps are the same as those in the first embodiment, so the description is omitted. [The third modification of the first embodiment 1st other example] In the third modified example described above, the i-th thin film layer 33 is formed of a chrome-shaped thin film layer 36 made of electroless copper, and the #additional layer 3 is formed by electroplating. The second thin film layer 33 is made of chromium, the second thin film layer 36 is made of sputtered copper, and the thick additional layer 37 is formed.

Formation of copper ore. The thickness of each layer is chromium 0.07_, copper 0 copper 15 // Hi. From electrolysis [Second other example of the third modified example of Example 1] In the second example, the upper thin film layer 33 is formed of titanium, and the second thin film layer 36 is formed. 37 / thickness is 0.07 // m titanium, copper 1.0m, electrolytic copper, [Third other example of the first modified example of Example 1] In the third other example, the first thin film is formed of titanium Layer 3 3, /

The second thin film layer 36 is plated with electrolytic steel to form a thick additional layer. The copper formation degree of running ore is 0.07 / zm of titanium, 0.5 // m of copper, and the thickness of electrolytic copper [4th other example of the first modification of Example 1] 'In the fourth other example, it is formed by chromium The first thin film layer 33 is formed of nickel and the second thin film layer 36 is formed by electrolytic copper plating. The thickness of the de-electroplated layer is 0.06 // m of chromium, Ni 2 · 2, and electrolytic layer 37 is added. Each [Fifth alternative example of the first modified example of Embodiment 1] ^ # m °

546999

V. Explanation of the invention (28) In the fifth example, the first thin film layer 33 is made of titanium, the second thin film layer 36 is made of electroless nickel, and the thick additional layer 37 is formed by electrolytic copper plating. 7 The thickness of the layer For titanium 0.07 / ζιη, electricity nickel 1.1 // m, electrolytic copper. B. The multilayer printed wiring board containing semiconductor elements will be described, and the semiconductor element (jc wafer) of the third modified example described above will be described. 20 The multilayer printed wiring is embedded, housed, and housed in the recesses, gaps, and openings of the core substrate. The composition of the board. Sweat [Example 1]

The multilayer printed wiring board 10 shown in FIG. 14 is a core substrate 30 of a wafer 1 (a wafer 20) and an interlayer resin insulation layer 50 in the first embodiment (see FIG. 3 (B)). It is composed of an interlayer resin insulation layer 50. On the interlayer resin insulation layer 50, a via window 60 and a conductor circuit 58 are formed, and on the interlayer resin insulation layer 150, a via window 160 and a conductor circuit 158 are formed. A solder photoresist layer 7 is disposed on the resin insulating layer 150. A conductor circuit 158 under the opening 71 of the solder photoresist layer 70 is provided with an external connection (not shown) for a mother board, a daughter board, and the like. Solder bumps 76 connected to the substrate.

In the multilayer printed wiring board of this embodiment, a 1C wafer 20 'is built in the core substrate 30, and a transition layer 38 is disposed on a pad of the IC wafer 20. Therefore, it is not necessary to use lead parts and packaging resin, and it is possible to obtain electrical connection between the c chip and the multilayer printed wiring board (construction substrate). In addition, because the transition layer 38 is formed on the wafer portion, the IC wafer portion is planarized, and the upper interlayer insulating layer 50 is also planarized, and the film thickness becomes uniform. Furthermore, the transition layer forms the upper layer. The shape of the interlayer window 60 can also maintain the stability of the shape. Also, 'the provision of a steel transition layer 38 on the die pad 22 can prevent the pad 546999. 5. Residual resin on the description of the invention (29) 2 2 Even if it is immersed in acid and oxidant or etching solution in the subsequent steps, the discoloration and dissolution of the pad 22 will not occur through various tempering steps. This can improve the continuity between the pad and the interlayer window of the IC chip and Reliability. Furthermore, a 60 / zm-diameter interlayer window can be continuously connected through a transition layer 38 having a diameter of 60 // m or more on the 40 / zm-diameter pad 22. Continuing, refer to FIGS. 10 to 13 The drawings illustrate a method for manufacturing the multilayer printed wiring board described above with reference to FIGS.

(1) First, use insulating glass substrate (core substrate) 30, which is a prepreg with a core material such as glass cloth impregnated with resin such as epoxy, as the starting material (Figure 10 (A)). Next, on one side of the core substrate 30, a recessed portion 32 for 1C wafer accommodation is formed as a recessed portion (FIG. 10 (B)). Here, although the recessed portion is provided by processing the recessed portion, and the insulating resin substrate provided with an opening is bonded to the resin insulating substrate provided without an opening, a core substrate having a receiving portion can be formed. (2) After that, the adhesive material 34 is applied to the recessed portion 32 by a printer. In this case, infusion can be used in addition to the cloth. Then, the 1C wafer 20 is placed on the bonding material 34 (Fig. 10 (C)).

(3) Squeeze or press on the top surface of the IC chip 20 to be completely contained in the recess 32 (Fig. 10 (D)). Thereby, the core substrate 30 can be smoothed. At this time, 'adhering material 3 4' has such a material on the IC chip 20 because 'as described later, a resin layer is provided on the IC chip 20 and an opening for a glazing window is provided by a laser, which will not affect the The connection between the transition layer and the via window has an impact. (4) After the above steps, the thermosetting resin sheet with a thickness of 50 v m is heated to 50 to 150 ° C and laminated with vacuum pressure at a pressure of 5 kg / cm2.

546999

V. Description of the invention (30) An interlayer resin insulating layer 50 (Fig. (A)). The vacuum compression time is 10mmHg. , With (5), followed by a gas laser with a wavelength of 1 q · 4 am, and a beam diameter of 5 mm, a hot mode (t0p hot mode), and a pulse wave (5). 0 #second, aperture of the mask: 0 · 5mnl, 1-range conditions, an interlayer resin insulating layer 50 is provided with an opening of an interposer window with a diameter of 80 // m 48

(Refer to FIG. 11 (β)). Use 60 ° C permanganic acid to remove the resin residue in the opening 48. By providing a copper transition layer 38 on the die pad 22, the resin on the die pad 24 can be prevented from remaining, and the connection and reliability of the die pad 24 and an interlayer window 60 described later can be improved. In addition, a 60 Am diameter via window 48 can be reliably connected to a grain size 塾 22 of 40 ° through a transition layer 38 of 60 / m or more. In this case, the resin residue is removed by using over-acid acid, but a desmear treatment may also be performed using an oxygen plasma and a corona treatment. (6) Next, the roughened surface 50 0 α of the interlayer resin insulating layer 50 is not immersed by being immersed in an oxidizing agent such as chromic acid or permanganate (refer to FIG. 11 (c)).

). The roughened surface 50 α is preferably formed in a range of 0 ·: [~ 5 // m. One example is immersion in a sodium permanganate solution at 50 g / i at a temperature of 60 ° C for 5 to 25 minutes, and a roughened surface of 2 to 3 // m 50 α is set. In addition to the above, SV-4540 manufactured by Japan Vacuum Technology Co., Ltd. may be used for plasma treatment to form a roughened surface 50 α on the surface of the interlayer resin insulating layer 50. At this time, argon was used as an inert gas, and plasma treatment was performed for 2 minutes under the conditions of an electric power of 200 W, an air pressure of 0.6 Pa, and a temperature of 70 ° C. (7) A metal is provided on the interlayer resin insulating layer 50 forming the roughened surface 5 0 α

2160-3798-pf.ptd Page 33 546999 V. Description of the invention (31) Layer 52 (refer to Figure 12 (A)). The metal layer 52 is formed by electroless plating. Catalysts such as palladium (pallidium) are applied to the surface of the interlayer resin insulating layer 50 in advance, and immersed in an electroless plating solution for 5 to 60 minutes, and a plating film having a range of 0.1 to 5 m is set. Metal layer 52. One example [Aqueous solution of electroless plating]

NiS04 Tartrate Copper Sulfate HCHO NaOH

0-003 mo 1/1 0.200 mo 1/1 0.030 mo 1/1 0.050 mo 1/1 0.100 mol / 1 specific bite 100mg / l polyethylene glycol (PEG) 0 · 10 g / 1 impregnated in 3 4 ° C liquid temperature for 40 minutes. In addition, SV-4540 manufactured by Japan Vacuum Technology Co., Ltd. can be used instead of electroplating, sputtering using Ni & Cu as a target, air pressure 0.6 Pa, temperature 80 ° C, power 20 0W, and time 5 minutes. Conditions are performed, and a Ni / Cu metal layer 52 is formed on the surface of the interlayer resin insulating layer 50. At this time, the thickness of the formed Ni / Cu metal layer 52 is 0.2.

(8) After completing the above-mentioned substrate 30, a commercially-available photosensitive dry film is attached, and a photomask sheet is placed, and after exposure at 10 mJ / cm2, it is processed with 0.8% sodium carbonate imaging treatment and set 15 Am plated photoresist 54. Next, electrolytic plating was applied to the following conditions to form an electrolytic resistive film having a thickness of 15 mm (see FIG. 12 (B)). Furthermore, the addition to the electrolytic plating solution

546999 V. Description of Invention (32)

Manufacture, force MF 5F HL agent is 7 y y ^ μ > [Electrolytic plating aqueous solution] sulfuric acid 2.24 mol / l copper sulfate 0.26 mol / 1 Manufacture, formula > p Hl additive (7 y y y C Ten A: / 19.5 m 1/1 [Electrolytic plating conditions] Current density lA / dm2 Time 6 5 minutes

Temperature 2 2 ± 2 ° C (9) After stripping and removing the photoresist 54 with 5% NaOH, a mixed solution of nitric acid, sulfuric acid and thorium peroxide is used to etch the metal layer 5 2 under the photoresist to dissolve and remove to form a metal. The conductor circuit 58 and the interlayer window 60 with a thickness of 16 // 111 composed of the layer 52 and the electrolytic plating film 56 are formed into a roughened surface 5 8 α, 6 0 α ( Refer to Figure 12 (¢)). (10) Next, by repeating the above steps (4) to (9), the upper acoustic layer 150 and the conductor circuit 158 (including the interlayer window 16) are formed again (refer to (A)). μ _

(11) Next, 60% by weight of a cresolase (cres〇1) phenol-formaldehyde-fixed Uovoiak) type epoxy resin (manufactured by Nippon Chemical Co., Ltd.) ^ alkylated, low-armed person who gives photosensitivity 丞 ~~~~ Compound (〇1 igomer) (for Hayago 4000) 46.67 parts by weight, soluble salmon identification company ", shocurol A-type epoxy resin (oilization >, 80% by weight of methyl ethyl hydrazone) Double manufacturing, £ .1 (: 〇16 1001) 15 heavy

546999 V. Description of the invention (33) Quantitative part, Miwa hardener (manufactured by Shikoku Kasei Co., Ltd., 2 £ 4 Μ Z _ CN) 1 · 6 parts by weight, polyvalent alkyl monomer with photosensitive monomer (Japanese version) Pharmaceutical manufacturing, R604) 3 parts by weight, same polyvalent hospital-based monomers (Kyoeisha Chemical Manufacturing, DPE6A) 1 · 5 parts by weight, dispersing defoamer (manufactured by Y / Y 3, S-65) 0.71 The weight part is dissolved in DMDG and put into a container, and the mixture is adjusted to a mixed composition after being dropped and mixed. Then, the photoinitiator benzophenone (manufactured by Kanto Chemical) is added to the mixed composition. 2.0 weight part 2. Light sensitizer Michler (sketone) (manufactured by Kanto Kasei) 0.2 parts by weight, and a solder photoresist composition (organic) whose viscosity at 25 ° C is adjusted to 2.0 pats (organic) Resin insulation).

In addition, the viscosity measurement was obtained by using a B-type viscosity agent (ie, DVL B type manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm with a field of a rotor ν0.4, and 6 rpm with a rotor No. 3. (12) Next, the above-mentioned solder ^ resist composition is coated on the substrate 30 at a thickness of 20 // m, and dried at 70t20 minutes and 70t30 minutes. Drying = 彳 ^, so that solder is drawn A 5 mm thick mask of the pattern of the photoresist opening is exposed to the solder photoresist layer 70 and exposed to 1 000 mJ / cm2 of ultraviolet light, and processed with DMTG &Valley; to form a 2000-diameter opening 7丨 (Refer to Figure 13 (B: +). Also, commercially available solder resists can be used.

(ϋ) Next, a solder photoresist layer (organic resin insulation layer) 70 will be formed: "f contains chloride (2,3xio-im〇i / i), hypophosphite m〇1 / 1), Sodium citrate (1.6x 10, 〇1 / 1) = -4.5 in an electroless plating solution for 20 minutes, recording the bond ㈣. The substrate was then placed in a cyanide containing ΓΐΛ 6x

546999 V. Description of the invention (34) 10 3 mol / l), ammonium gasification (I 9 x 10-lm〇1 / 1), sodium citrate (I 2 X 1 0 1 mo 1/1), Ziyalu Sodium (1 · 7 χ 1〇-1 m〇J / 1) in the electroless forging fluid 'soaked at 80 C for 7.5 minutes, and formed a thickness of 0.03 on the recording chain layer π // m gold plating layer 74, and a solder tin 75 is formed on the conductor circuit 158 " (see FIG. 13 (C)). (14) After that, a solder paste is printed on the opening 7 of the solder photoresist layer 70, and solder bumps 76 are formed by refiow at 2000C. By incorporating the 1C chip 20 therein, a multilayer circuit board 10 having solder bumps 76 can be obtained (see FIG. 14). Fresh tin paste can use Sn / Pb, Sn / Sb, Sn / Ag, Sn / Ag / (: u, etc.) Of course, it is also possible to use radiation low-α-type solder paste. In the above-mentioned embodiment, the interlayer resin The insulating layers 50 and i 50 are made of a dagger-shaped resin sheet. The thermosetting resin sheet contains a hardly soluble resin, grain 5 particles, a hardener, and other components. Each of them will be explained below. The epoxy-soluble: granules obtained from the thermosetting resin sheet: ί = ί Those who dissolve soluble particles (hereinafter referred to as second cold steep particles) in acidifying agent or disperse hardly soluble resins in acid or oxidizer). He Fei I 乂 卜 祜 feng is here! : Door :: The present invention uses < " hardly soluble " " soluble ", which is • in: When in a solution composed of the same acid oxidant, it is relatively abbreviated as "difficult." ”In contrast, particles with a slow dissolution rate (two;: = particle f ′ are examples of soluble resin particles in acids or oxidants (hereinafter referred to as soluble resin particles), soluble in acids or oxidants 2160-3798-pf.ptd

Page 37 546999-V. Inorganic particles of invention description (35) (T is called ^ soluble soluble metal particles (+), soluble particles in acid or oxidant can be used alone, ", cola metal particles) Etc. The shape of the above-mentioned soluble particles is not particularly useful. Flaky, etc. The shape of the above-mentioned soluble particles < 1 is, for example, spherical and broken into a rough t: like shape that can form unevenness with average thickness. Because the range of the average particle diameter of the soluble particles mentioned above may also contain two or more kinds of 1 to 10. The average particle diameter of the particle diameter is 0. bu .. 5_may: = 1 level contains two soluble particles, etc. # 此The granules can also be formed with excellent adhesion. Furthermore, the length of the longest portion of the soluble particles, such as the surface and the conductor circuit, is implemented. The particle position of the particles is, for example, a thermosetting resin, The plasticity tree is a well-established solution, and the solution composed of being impregnated with an acid or an oxidizing agent is particularly limited to a solution that dissolves faster than the above-mentioned poorly soluble resin. Λ / fat, fat is lipid fluoride = may be-selected from the above Resin, or heart seed =

As the second soluble resin particles, resin particles made of rubber can also be used. Examples of the aforementioned rubber include various modified polybutadiene rubbers such as polybutadiene rubber, epoxy modification, modification, (fluorenyl) acrylonitrile modification, and the like (fluorenyl) acrylonitrile containing butadiene. Diene rubber, etc. By using the above-mentioned rubber, the soluble resin particles are easily dissolved in an acid or an oxidizing agent.

2160-3798-pf.ptd 546999 1 V. Explanation of the invention (36) Finally, the soluble acid is dissolved by using acid and the oxidant is used to dissolve. It can also be dissolved by oxygen concentration. Therefore, when it is not on the surface of the resin, it can also be low. After the roughened surface is formed, it will give the residue of vaporized plutonium, as the post-catalyst, the catalyst will not oxidize. 7 In the case of mediation, the particles composed of the above-mentioned soluble inorganic particles HW & substances, calcium compounds, potassium compounds, species, and groups composed of aluminum compounds are given. Examples of hydrogen, chemical compounds, etc. 'The above calcium compounds can be used for acid removal, the above magnesium compounds can be used together, etc. These compounds can be used. For example, λ can be used in combination with two stone stones. 'At least-the species is selected from copper, nickel, seeds, etc. In addition, these soluble gold particles are coated with a resin on the surface layer. In order to ensure insulation, the above-mentioned soluble particles may be mixed with two kinds, and the combination of the soluble particles is preferably For resin granules 2, this and both Ground adjustment and insoluble =, meanwhile, the interlayer resin insulation layer can be easily broken, and the interlayer resin insulation layer and conductor made of / :: t raw resin film 2160-3798-pf.ptd page 39 546999 5. Description of the invention (37) The above-mentioned insoluble resin does not peel off between circuits. When the roughened surface is formed on the interlayer resin insulation layer, as long as the shape of the roughened surface can be maintained, it must be stabilized, such as thermosetting resin, thermoplasticity. Resin, the above-mentioned complex I selection = Limit 5 丄 can also be a photosensitive resin that imparts the sensitivity of the above resin; m photosensitive resin can be used for exposure and development ^ formation of the interlayer mouth 帛 π. 隹 layer tree Among the above-mentioned insulating layer shapes, those containing a thermosetting resin are preferred. Thereby, the shape of the roughened surface can be maintained by a plating solution or various heat treatments. A specific example of the poorly soluble resin is epoxy, for example. Resins, phenol resins, phenoxy resins, polyimide resins, polyphenylene resins, polyolefin resins, and fluorine resins. The resins can be used alone or in combination of two or more. In addition, preferably at 1 point Among them, epoxy resin having two or more epoxy groups can form the aforementioned roughened surface, and is also excellent in heat resistance and the like, so that stress concentration does not occur in the metal layer even under thermal cycling conditions, and It is difficult to cause the metal layer to peel off. The epoxy resin may be, for example, Cresol 〇1 novolak epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy, Phenolic novolac solid epoxy resin, alkylphenol novolac solid epoxy ring f · oxygen resin, bisphenol F epoxy resin, naphthalene epoxy resin, dicyclopentadiene epoxy resin, phenols Epoxides, condensates of aromatic aldehydes with phenolic hydroxyl groups, glycidy 1 isocyanurates, cyanurates, alicyclic epoxy resins, etc. The above can be used alone or

2160-3798-pf.ptd Page 40 546999 V. Description of the invention (38) Two or more types are used together. In this regard, the first class of the present invention is excellent. In the above-mentioned poorly soluble resin, it is preferable that the above-mentioned soluble particles are rough / uneven ones having a uniform roughness. Since the flat window and the through hole can be formed, the tightness of the interlayer can be surely formed on the resin film. In addition, the resin of soluble particles in the metal layer of the conductor circuit only is used only in the surface layer portion of the roughened surface, which can be exposed without an acid or an oxidant. Between the conductor circuits and the insulating layer other than the surface layer portion of the resin film It is absolutely maintained that the thickness of the uneven surface is thinner than that of the soluble particles in the grease through the interlayer resin blending. When it exceeds 40% by weight, the roughness of the unevenness cannot be dissolved in the resin. Oxygen: = = = film composition JS Μ also … Q month b is difficult to pass through the insulation between the conductors and circuits of the short-circuited ^ edge layer of resin, and it will be ΪΓ: ϊϊ In addition to the above-mentioned soluble particles, the above-mentioned insoluble resin Bu Yijia has 3 hardeners and other ingredients.

Examples of the hardener include a saliva-based hardener, an amine-based hardener, a guanidine-based hardener, an epoxy adduct (addUCt) of the hardener, and a microcapsule of the hardener. Organophosphine-based compounds such as tnphenolephosphine, tetraphenol, and tetrarate borate. The content of the above-mentioned hardener is preferably from 0.5 to 0.5 weight of the resin film.

546999 V. Description of invention (39)%. When it is less than 0.5% by weight, the resin film is not sufficiently hardened, so that the degree of penetration of acids and oxidants into the resin film increases, and the insulation of the resin film is damaged. On the other hand, if it exceeds 10% by weight, an excessive amount of the hardener component will deteriorate the composition of the resin 'and cause a decrease in reliability. The other components mentioned above include, for example, fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. Examples of the inorganic compound include silicon, aluminum, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyimide resin, polyphenylene resin, melanin resin, and olefin-based resins. Resin, etc. By including the filler ′ described above, it is possible to achieve integration of thermal expansion coefficients and increase in heat resistance and chemical resistance, etc., thereby improving the performance of printed circuit boards. The resin filler may contain a solvent. Examples of the solvent include acetone, methylethyl, cyclohexanone, and the like, ethyl acetate, butylhexanoic acid, cellosolve acetate, and aromatic hydrocarbons such as toluene and dimethylbenzyl. Compound. These solvents can be used alone or in combination of two or more types. However, such interlayer resin insulation layers will completely dissolve and carbonize when added to a temperature of 35 ° C or higher. [First Modification of Embodiment 1]

Next, a multilayer e-brush wiring board according to a first modification of the first embodiment will be described with reference to FIG. 16. P In the above embodiment 1 ', the case where B G A is provided is explained. The first modified example is substantially the same as that in the first embodiment, but it is configured by a PGA method for obtaining a connection via a conductive connection bolt 96 as shown in FIG. 16. In the first embodiment described above, the interlayer window is formed by a laser, but the first modification is a photo-etching step.

546999

Into the interlayer window. Manufacturing of wiring boards

A multilayer printing method according to the first modification will be described with reference to FIG. 15. 9 U (4) · As in Example 1, a thermosetting epoxy resin 50 with a thickness of 50 was applied to the beauty board that had undergone the above steps (1) to (3) (Fig. 15)) ^ ) Next, 'the photomask sheet 49 with the black dots 4 9 a corresponding to the position where the interlayer window is formed is placed on the interlayer resin insulating layer 50 and exposed (Fig. 15 (B)). (6) • Developed by spraying with DMTG liquid, and heat-treated to provide an interlayer resin insulation layer 50 with a via hole opening 48 with a diameter of 85 (Figure 15 (C (7)). The surface of the acid roughened interlayer resin is insulated to form a roughened surface 50α (Fig. 15 (D)). The subsequent steps are the same as those in the first embodiment, so the description is omitted. The roughened surface is preferably 0 · 〇 5 to 5 / zm 0 The semiconductor elements of the above examples and the semiconductor elements of the comparative examples are housed in the multilayer printed wiring board of Example 1 and the first modification. The evaluation results are shown in the graphs of FIGS. 17 and 18. [Comparative Example] The comparative example is the same as the semiconductor element of Example 1. However, Comparative Example 1 did not form a transition layer, and the die pad was directly buried in the multilayer printed wiring board 0 [Comparative Example 2]

2160-3798-pf.ptd Page 43 546999 V. Description of the invention (41)-In Comparative Example 2, a bolt bump of No. 9-3 21 4 0 8 was formed and buried in a multilayer printed wiring board. The evaluation items were: ① The discoloration and dissolution of the remaining grains were visually judged. ② Investigate whether it is possible to form the opening for the interlayer window, use the example! The method of manufacturing a multilayer printed wiring board of the present invention is whether a laser can form an opening with a diameter of 60 μm, and whether the method of manufacturing a multilayer printed wiring board using the first modification example can form an opening with a diameter of 85em by light. ③ Measure the contact resistance between the crystal grains and the interlayer window. The semiconductor device according to the third modified example can obtain an appropriate result. However, in Comparative Examples 1 and 2, problems such as defective formation and connection failure of the interposer window, and increased resistance values have occurred. With the structure of the first embodiment, the connection between the IC chip and the printed wiring board can be obtained without the lead components. Therefore, no resin encapsulation is required. In addition, since Yu does not cause the incompatibility caused by the pin parts and the shock-sealing resin, the reliability is continued. x 'Since the pad of the IC chip and the conductive layer 疋 of the printed wiring board are directly connected', the electrical characteristics can be improved. The method of constructing IC chips known from Waiqiu, IC chip ~ substrate ~ fruit. It can also be equipped with BGA, PGA, etc., and the effect of Hi to reduce the inductance of the loop [Embodiment 2] "The degree of freedom in the formation of the mouth wiring. The following description will explain the" h "of the present invention < Embodiment 2. Sheet 20) Multi-layered description of the semiconductor element of Example 2/70 pieces (I "the structure of a printed wiring board. Θθ

546999 V. Description of the invention (42) The multilayer printed wiring board 10 shown in FIG. 24 is a heat sink 30D for placing the ic chip 20 of the first embodiment described above with reference to FIG. 3 (B), and accommodates The core substrate 3 i of the 1C wafer 20 is composed of an interlayer resin insulation layer 50 ′ and an interlayer resin insulation layer 150 on the 1C wafer 20. An interlayer window 60 and a conductor circuit 58 are formed on the interlayer resin insulation layer 50, and an interlayer window 160 and a conductor circuit 158 are formed on the interlayer resin insulation layer 150. A solder photoresist layer 70 is provided on the interlayer resin insulating layer 150. The conductor circuit 158 under the opening 71 of the fresh tin photoresist layer 70 is provided with a solder bump for connecting to an external substrate such as a daughter board or a mother board (not shown). 7 6 °

The heat sink 30D is composed of aluminum nitride, aluminum oxide, mullite (ceramics such as mulUte, etc.), or aluminum alloy, copper, or adjacent bronze. Metals are used in high-conductivity aluminum alloys or on both sides. Pre-roughened copper preparation 2 In this embodiment, 'the female radiator 50D is cracked inside the 1c wafer 2 buried in the core substrate 31, so as to make the wafer 2 5: " Γ5 1 ^ ^ ^ ^ ^ / 160, The conductor thunder, the interlayer window 60 on the interlayer resin insulation layer, Γ Laisi Road 58,1 58 did not break. This improves the installation .: Infrared heater_ is a conductive adhesive Due to its high thermal conductivity, the metal meal of Lu'an is dissipated from the heat sink 30D. The 1C chip 20 is efficiently mounted with a conductive adhesive, and the 1C chip 20 is mounted. It is to make W Ren, and to have high thermal conductivity.

546999

All can be used. In the multilayer printed wiring board 10 of this embodiment, a core substrate 31 is embedded with a wafer 20, and a transition layer 38 is disposed on a pad 22 of the IC wafer 20. So, no, you can get it with pin parts and sealing resin! c. Electrical connection between the wafer and the multilayer printed wiring board (construction substrate). Further, since the transition layer 38 is formed in the IC wafer portion, the 1C wafer portion is flattened, and the upper interlayer resin insulating layer 50 is also flattened, and the film thickness becomes uniform. In addition, #from transition layer 'can also maintain the stability of the shape when forming the upper via window.

Moreover, a copper transition layer 38 is provided on the die pad 22, which can prevent resin residue on the pad 22, and is immersed in an acid and an oxidant or an etching solution in the subsequent steps. Even after various tempering steps, the pad 22's Discoloration does not occur. Thereby, the continuity of the IC chip and the interlayer window can be improved. In addition, on the 22-m-diameter pad 22, the interlayer window of β0νπ! Diameter can be surely connected through the transition layer 37 with a diameter of 6Mm. Continuing, a method for manufacturing the multilayer printed wiring board according to the second embodiment described above with reference to Fig. 24 will be described with reference to Figs. 19 to 23.

(ο On a plate-shaped heat sink 30D (FIG. 19 (A)) composed of ceramics such as aluminum nitride, alumina, mullite, or bronze, etc., an electrically conductive adhesive 29 (FIG. 19 ( (B)). The conductive adhesive is a paste in which copper particles having an average particle diameter of 2 to 5 / zm are introduced to form a thickness of 10 to 20 m. (2) The above-mentioned Example 1 and implementation are placed. Example! The 1C chip 20 of the i-th modified example, the second modified example, or the third modified example (Fig. 19 (c)). Turn (3) Next, place a heat sink 30 with 10 chips 20 mounted thereon. Stainless steel

546999

Pressure plate 100A. Therefore, the core material such as glass cloth is impregnated with a thickness of "tree-moon, laminating, and other resins of uncured prepregs." ^ «N prepreg laminate 31α is placed on the heat sink Device 30D (Fig. 20 (A)). A through hole 32 is provided on the prepreg laminated body 31α at a position where an IC wafer 20 is provided in advance. Here, a prepreg impregnated with resin in a core material is used. However, it is also possible to use a resin substrate without a core material, or a sheet impregnated with a thermosetting resin and a thermoplastic resin. (4) The stainless steel (SUS) pressing plates 100A and 10OB are used to press the laminate from above and below. At this time, the resin 31 stone is extruded from the prepreg 31 α to fill the space between the through hole 32 and the 1C wafer 20 while covering the upper surface of the IC wafer 20. Thereby, the 1C wafer 20 and the prepreg The upper surface of the multilayer body 31 α is completely flat (Figure 20 (B)). Therefore, when forming a laminated layer in the subsequent steps, an interlayer window and wiring can be appropriately formed, and the reliability of the wiring of the multilayer printed wiring board can be improved. (5) After that, the epoxy resin of the prepreg is hardened to form a 1C wafer Core substrate 31 of 20 (Fig. 20 (0)). (6) On the substrate that has undergone the above steps, it is heated at a temperature of 50 to 150, and is laminated under a pressure of 5 kg / cm under vacuum to a thickness of 50 am. An interlayer resin insulating layer 50 composed of an epoxy resin is provided as a thermosetting epoxy resin (see FIG. 21 (A)). The degree of vacuum for vacuum compaction is 丨 0 mmHg. Co2 gas laser with a wavelength of 10.4 / zm and a beam diameter of 5mm, top hot mode, pulse 5 · 0 // second, aperture of the photomask 0.5 ·, ; [Range conditions, openings for interlayer windows with a diameter of 6 〇ν m are provided on the interlayer resin insulating layer 50 0 & β

V. Description of the invention (45) 546999

(Refer to FIG. 21: Chromic acid and perbellic acid are used to remove the resin residue in the opening.) A steel transition layer 3 is provided on the die pad 22. This can improve the die pad 22 and an interlayer window 6 described later. In addition, the 60 / m-diameter interlayer window can be reliably connected through a 60 / m transition layer 38 on a 40-diameter die pad 22 with a diameter of 48. Furthermore, here, it is Resin residue is removed using chromic acid, but desraear treatment may also be performed using osmium and corona treatment. (8) Next, the surface of the interlayer resin insulating layer 50 is roughened with permanganic acid to form a roughening. Surface 5 0 α (Fig. 21 (C)). (9) Next, an electroless plated film 52 is provided on the interlayer resin insulating layer 50 forming the roughened surface 50 α (Fig. 22 (A)). Electroless Copper and copper can be used for electroplating. Its thickness is preferably in the range of 0.3 / ζιη to 1.2 / ζπι. It is less than 0.3 m, and a metal film cannot be formed on the interlayer resin insulation layer. Exceeding 丨 · 2〆 ^ The etched metal film will remain, and it is easy to cause a short circuit between the conductors. The electromine film is formed under the same plating solution and plating conditions as in Example 1. Except Other than the ones described above, the same device as the plasma treatment can be used. Ni-Cu alloy is used as a dry material, and sputtering is performed at a pressure of 0 Pa, a temperature of 80, a power of 2000w, and a period of 5 hours. A Ni-Cu alloy 52 is formed on the surface of the resin insulating layer 50. At this time, the thickness of the Ni_Cu alloy layer 52 to be formed is 0.2 vm 〇 (10). A photosensitive dry film was placed on a photomask sheet, exposed at 10 mJ / cm2, and then treated with a sodium carbonate development of 0.8% to provide a plating resist 54 having a thickness of 20. Next, the same photoresist as in Example 1 was used. Conditions apply electrolytic plating to form a thickness of 5 # m

2160-3798-pf.ptd p. 48 546999

The electrolytic resistance film 56 (see FIG. 22 (B)). In addition, the additive in the Φ_ solution for electroplating water is 7 y / h > Manufacture, force M 5 > F HL. (11) After stripping and removing the plating photoresist 54 with 5% NaOH, the metal layer 52 under the plating photoresist is etched by using a mixed solution of krystic acid, sulfuric acid, and hafnium peroxide, and removed to form a metal layer 52 and an electrolytic capacitor. Thickness of composition 56

The conductor circuit 58 and the interlayer window 60 form a roughened surface 5 8 α, 60 0 α with an etching solution containing a second copper complex and an organic compound (refer to FIG. 22 (c)). In this embodiment ', referring to FIG. 20 (C), as described above, the upper surface of the core substrate 31 is completely formed smoothly, so that the transition layer 38 can be appropriately connected through the interlayer window 60. Therefore, the reliability of the multilayer printed wiring board can be improved. (12) Next, by repeating the above steps (6) to (11), an upper interlayer resin insulating layer 150 and a conductor circuit 158 (including the interlayer window 16) are formed again (Fig. 23 (A)). (13) Next, a resin insulating material is obtained). The same solder photoresist composition (organic (14) as in Example 1) Next, the above-mentioned solder photoresist ϊ 1 '1 1: 70 °, 20 minutes, 70 was coated on the substrate 30 at a thickness of 20 // 111. Dry in 30 minutes under conditions of ~ f to make a mask with a thickness of 5 mm traced with a pattern of solder resist openings

The male photoresist layer 70 was exposed with 1 000 mJ / cm2 of ultraviolet light and treated with = :)) image to form 200 openings with a diameter of 71 (refer to (15)). Then, a solder photoresist layer (organic resin) was formed. Insulation layer) 70 of

546999 V. Description of the invention (47) A nickel electric chain layer having a thickness of 5 mm is formed on the opening portion 71 of the substrate. A gold plating layer 74 having a thickness of 0.03 / zm is formed on the re-plating layer 72, and a solder pad 75 is formed on the conductor lightning / failure 158 (see FIG. 23 (C)). (16) After that, paste is printed on the opening 71 of the solder photoresist layer 70, and a solder bump is formed at 20 (TC by reflow), and then the heat sink 30D is divided into The block is divided into a single piece and the multi-layer 6 is the most wiring board 10 (refer to FIG. 24). Θ ^ [First Modification of Embodiment 2] Next, the change of the brush wiring of Embodiment 2 will be described with reference to FIG. 26. The second embodiment is the case where the BGA is provided. In the first modification, it is almost the same as the second embodiment, but the connection PGA is obtained through the conductive connection bolt 96 as shown in FIG. 26. In the second embodiment described above, the interlayer window is formed by laser, but in the fourth modification example, the interlayer window is formed. The i-th modification of the second embodiment will be described with reference to FIG. 25. A method for manufacturing a multilayer printed wiring board. (4) In the same manner as in Example 2, a thermosetting epoxy resin 50 having a thickness of 50 // m is applied to the substrate subjected to the above steps (1) to (3). (Figure 25 (a

) ° 5 \ Next, a photomask 4 9 with black dots 49a corresponding to the position where the interlayer window is formed is placed on the interlayer resin insulation layer $ 0, and exposed (the second figure (b)) ° (6 ) It is developed by spraying with DMTG liquid and heat treatment is performed to provide a diameter of 85

2160-3798-pf.ptd Page 50 546999 V. Description of the invention (48) -------- The interlayer resin insulation layer 50 of the opening 48 for the interlayer window (the figure (c) (7) rough In the same way as in Example 2, the surface 50α of the interlayer resin insulating layer 50 was roughened with permanganic acid or chromic acid (Fig. 25 (D)). The following steps are used, so the description is omitted. Second Modified Example of 2] Next, a multilayer printed wiring board according to a second modified example of Embodiment 2 will be described. In the first and first modified examples described above, the core substrate is formed of a prepreg. In contrast, in the first In the second modification, a resin substrate obtained by temporarily curing a prepreg is fixed to the heat sink 30D with the prepreg. The manufacturing process of the multilayer printed wiring board according to the second modification will be described with reference to FIG. 27. The conductive adhesive 29 was used to mount the IC chip 20 with copper oil roughened on both sides, to form a heat sink 30 d, and to place it on a stainless steel (sus) platen 100 A. Then, a heart material such as glass cloth was impregnated Uncured prepreg (0.2111111) 31 for resins such as BT resin and epoxy is placed on the radiator 30 d. On α, a resin substrate (0.4 ·) which is hardened by laminating the prepregs described above is placed 31 r (Fig. 27 (A)). On the prepreg 31 «, the resin substrate 31 r is placed in advance at 1C A through hole 32 is provided at the position of the wafer 20. (2) The laminated body is pressurized from above and below with stainless steel (SUS) pressing plates 100A and 100B. At this time, the resin 31 is extruded from the prepreg 31 α to fill the through hole. The space between 32 and the IC chip 20 covers the top surface of the IC chip 20 at the same time. With this, the top surface of the 1C wafer 20 and the prepreg laminated body 31 α is completely flat.

2160 > 3798-pf.ptd 546999 V. Description of the invention (49)). Therefore, when the superposed layer is formed in the subsequent steps, a via window and wiring can be appropriately formed, and the reliability of the wiring can be improved. 〇7 «I (3: after 'heating of the wiring board to harden the epoxy resin described in the prepreg = core substrate 31 of the second sheet (Figure 27 (c)). The subsequent steps are the same as in Example 2, so The explanation is omitted. Ί! 施 Γ is installed inside the 1c wafer embedded in the core substrate, and it can generate & that can disperse the 1C wafer. This can prevent the core substrate and the core substrate from being formed. The interlayer resin insulation layer on the substrate is bent without disconnecting the conductor circuit on the interlayer t on the interlayer resin insulation layer. Furthermore, with the above-mentioned structure of the present invention, the IC chip can be taken without going through the lead parts. Connection to printed wiring boards. Therefore, no resin encapsulation is required. In addition, it does not cause the misalignment of lead parts and packaging resin, so it improves connectivity and reliability. X, because the IC chip pads and printed wiring The conductive layer of the board is directly connected, so it can improve the electrical characteristics. Furthermore, compared with the conventional 1C chip mounting method, the wiring length of the IC chip to the substrate to the external substrate can be shortened, and the inductance of the circuit can be reduced. Effect [Embodiment 3] Hereinafter, Embodiment 3 of the present invention will be described with reference to the drawings. As shown in Fig. 33, the multilayer printed wiring board 10 according to Embodiment 3 is a core substrate 30 that houses a 1C wafer 20 and is insulated from the interlayer resin. The layer 50 is composed of an interlayer insulating layer 150. An interlayer resin insulating layer 50 is formed with an interlayer® 60 and a conductor circuit 58, and an interlayer resin insulating layer 5 is formed on the interlayer resin insulating layer 5

W

2160-3798-pf.ptd Page 52 546999 V. Description of the invention (50) There is a via 160 and a conductor circuit 158. A solder resist layer 70 is disposed on the interlayer resin insulating layer 150. The conductor circuit 158 under the opening 71 of the solder photoresist layer 70 is provided with a solder bump 76 ° for connection to an external substrate such as a daughter board or a mother board (not shown). The multilayer printed wiring board 1 of the third embodiment. The 1C wafer 20 is embedded in the core substrate 31, and a transition layer 38 is disposed on the pad 22 of the IC wafer 20. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (construction substrate) can be obtained without using lead parts and packaging resin. In addition, because the transition layer 38 is formed in the wafer portion, the IC wafer portion is planarized, and the upper interlayer resin insulating layer 50 is also planarized, and the film thickness becomes uniform. In addition, the transition layer 'can also maintain the stability of the shape when the upper via window is formed. And "a copper transition layer 38 is provided on the grain 22, which can prevent the resin on the pad 22 from remaining, and is immersed in an acid and an oxidant or an etching solution in subsequent steps." Even after various tempering steps, the pad 2 2 Discoloration and dissolution will not occur. This' can improve the continuity and reliability of the IC chip and the via. In addition, a 60 " diameter via window can be surely connected to the pad 22 having a diameter of 40 / zm via the transition layer 37 having a diameter of 60 or more.

Continuing 'The manufacturing method of the multilayer printed wiring board of the third embodiment described above with reference to Figures 33 to 32 will be described with reference to Figures 28 to 32. '(1) Insulating resin substrate 30A with a thickness of 0.5 mm laminated with a core material such as glass cloth and impregnated with a prepreg of BT (bismaleic anhydride imide tri-beep) resin, resin, etc. It is the starting material (Fig. 10 (A)). First, a through-hole 32 for IC chip accommodation is formed in an insulating resin substrate 30A (No.

Page 53 546999

Figure 28 (A)). Here, although a resin substrate 30 A impregnated with resin in a core material is used, a resin substrate without a core material may be used. (2) Thereafter, the through-hole 32 of the insulating resin substrate 30A houses the IC wafer 20 of the manufacturing method of the first embodiment described above (FIG. 28 (B)). (3) The thickness of the insulating resin substrate 3a that houses the IC chip 20 and the same as the core material of glass cloth impregnated with prepreg chain of resin such as BT and epoxy and laminated and cured. 2mm insulating resin substrate (core substrate)

30B is laminated with a core material such as glass cloth impregnated with an uncured prepreg 30C (thickness: 0.1 mm) in a resin such as epoxy (Fig. 28 (c)). Here, the resin substrate 30B in which the core material is impregnated with resin is used, but a resin substrate without a core material may be used. In addition, instead of the prepreg chain, a sheet in which the core material is impregnated with various thermosetting resins or thermosetting resins and thermoplastic resins may be used. (4) The laminated body is pressed with a stainless steel (SUS) platen 100A, 100B from above and below. At this time, the resin 3? Α is extruded from the prepreg 30C to fill the space between the through hole 32 and the IC wafer 20 while covering the upper surface of the IC wafer 20 at the same time. Thereby, the upper surfaces of the 1C wafer 20 and the insulating resin substrate 30A are completely flat (FIG. 29 (A)). Therefore, when forming a laminated layer in the subsequent steps,

Local opening > The formation of interlayer windows and wiring can improve the reliability of the wiring of multilayer printed wiring boards. (5) After that, the uncured epoxy resin 3 0 α is cured to form a core substrate 31 that houses the 1C wafer 20 (FIG. 29 (B)). (6) On the substrate after the above steps, heat-curing epoxy-based epoxy resin with a thickness of 50 was heated at a temperature of 50 to 150 ° C and vacuum-pressed at a pressure of 5 kg / cm2.

2160-3798-pf.ptd

546999 V. Description of the invention (52) A resin sheet, and an interlayer resin insulating layer 50 mainly composed of a thermosetting resin is provided (Fig. 29 (C)). The vacuum degree of vacuum compaction is 10mmHg.

(7) Connected by a CO2 gas laser with a wavelength of 10.4 / zm and a beam diameter of 5mm, a top hot mode, and a pulse wave (pu 1 se) 5 · 0 // second With the aperture of the photomask 0.5 mm and a range of 1, the interlayer resin insulation layer 50 is provided with an opening 48 for an interlayer window with a diameter of 60 / m (see FIG. 30 (A)). Residual resin in the openings 4 and 8 was removed using chromic acid and peracid. A copper transition layer 38 is provided on the die pad 22, whereby the connection and reliability of the die pad 22 and an interlayer window 60 described later can be improved. Furthermore, a 60 μm diameter interlayer window opening 48 can be reliably connected to a 40-diameter die pad 22 via a transition layer 38 of 60 // m or more. In addition, although "residue" is used here to remove resin residues, it is also possible to perform desmear treatment using oxygen polymerization and corona treatment. (8) Next, the surface of the interlayer resin insulating layer 50 is roughened with permanganic acid to form a roughened surface 50α (Fig. 30 (B)).

(9) Next, an electroless plated film 52 is provided on the interlayer resin insulating layer 50 forming the roughened surface 5 0 α (Fig. 30 (C)). Electroless recording can use copper and nickel. The thickness is preferably in the range of 0.3 // m to 1.2 // m. Less than 0.3 μm 'cannot form a metal film on the interlayer resin insulating layer. If it exceeds 1 · 2 ν ffl, the remaining metal film will remain, which may easily cause a short circuit between conductors. A plating film was formed under the same plating solution and plating conditions as in Example 1. In addition to the above, the same device as the plasma treatment can also be used, with Ni-Cu alloy as the target and an air pressure of 0.6 Pa, a temperature of 80, an electric power of 0, and

546999 V. Description of the invention (53) Ni-Cu alloy 52 is formed on the surface of the interlayer resin insulating layer 50 by sputtering for 5 hours. At this time, the thickness of the formed Ni-Cu alloy layer 52 is 0 2 vm 0 (10) On the substrate 30 that has been processed as described above, a commercially-available photosensitive dry film is bonded, and a photomask sheet is placed at 10 mJ / After cm2 exposure, it was developed with Q.8% sodium carbonate, and a plating resist 54 with a thickness of 20 // in was set. Next, electrolytic plating was applied under the same conditions as in Example 1 to form a thick electrolytic resistance film 56 (see FIG. 31 (A)). & (11) After stripping and removing the plating photoresist 54 with 5% NaOH, a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide is used to etch the metal layer 52 under the plating photoresist to dissolve and remove the metal layer 52 and the electrolytic plating film. The conductor circuit 58 and the interlayer window 60 with a thickness of 56 and a composition of 56 are formed with an etching solution containing a second copper complex ^ organic acid to form a roughened surface 5 8 α, 6 0 α (refer to FIG. 31 (B )). In the present embodiment, 'refer to FIG. 29 u), as described above,' the upper surface of the core substrate 31 is formed completely smoothly ', so that the transition layer 38 can be appropriately connected through the interlayer window 60. Therefore, the reliability of a multilayer printed wiring board can be improved. (12) Next, by repeating the above steps (6) to (11), an interlayer resin insulating layer 150 and a conductor circuit 158 160 are formed again (Fig. 31 (C)). Dagger 3 ′ 丨 layer * (13) and then ’# to adjust and implement the ship-like fresh (organic resin insulation material). "OR 物 (14) # 着, on the substrate 30, with; group f 物 'and take coffee minutes. ⑽minutes: piece S = thickness of the pattern with fresh tin photoresist openings after processing = Ding Guangzhi 2160-3798-pf.ptd

Page 546 999

The mask was in close contact with the solder photoresist & θ 〇 and was exposed to 1000 mJ / cm2 of ultraviolet light, and was processed with DMTG &Valley; and Figure 32 (A)). The opening 71 which is straight 200 / zm (refer to (15)) Next, a recording clock layer 72 with a thickness of 5 # m is formed on the opening 71 of the substrate on which the solder photoresist layer (organic resin insulation layer) 70 is formed. A gold plating layer 74 having a thickness of 0.03 // πm is formed on the recording plating layer 72, and a solder pad 75 is formed on the conductor circuit 158 (refer to FIG. 32 (β)). After (16), Solder paste / paste is printed on the opening 71 of the solder photoresist layer 70. The solder bumps 76 are formed by reflow at 200 ° C. Therefore, the wiring is divided into single pieces by dicing and printed in multiple layers. Board 10 (refer to # 32 (C)). In Figure 32 (C), the cheaper multilayer printed wiring board is shown in 2 divisions, but it can also be divided in 1 β and 3 2 divisions. The multilayer printed wiring board with a plurality of IC chips embedded in the wafer is manufactured in a divided manner. Example 3 manufactures a plurality of semiconductor devices with a semiconductor element by referring to FIG. 28 (A) to FIG. 32 (B). Multilayer printed wiring board. As shown in FIG. 32 (C), each multilayer printed wiring board is cut into a single piece. Therefore, it can be manufactured efficiently. The highly reliable multilayer printed wiring board 10 (refer to FIG. 33). [First Alternative Example of Embodiment 3] Next, referring to FIG. 35, the multilayer printed wiring board of another example of Embodiment 3 will be described. Example 3 illustrates a case where a BGA is provided. The first other example is substantially the same as Example 3, but is configured by a PGA method for obtaining a connection via a conductive connection bolt 96 as shown in FIG. 35. Further, the above实施 例 3, Example 3,

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= Layer window is formed by laser, but the first other example is a method of forming an interlayer by photoetching. The manufacturing of the multilayer printed wiring board of the i-th example will be described with reference to FIG. 34 (4). Same as in Example 3. On the substrate that has undergone the above steps (1) to (3), a thermosetting epoxy resin 50 with a thickness of 50 // m is applied (No. 34 ^ (A)). ° j 5): Next, a photomask sheet 49 with black dots 49a corresponding to the positions where the interlayer windows are formed is placed on the interlayer resin insulating layer 50 and exposed (Fig. 34 (B)) 〇jb) The DMTG liquid was spray-developed, and an interlayer resin insulating layer 50 having a straight f85 through-window opening 48 was provided by heat treatment (Fig. 34 (c (7)). The interlayer resin insulating layer was roughened with peracid or chromic acid. The surface of 50 is formed with a roughened surface 50 α (Fig. 34 (D)). The subsequent steps are the same as those in the third embodiment described above, and therefore the description is omitted. [First Modified Example of the Third Embodiment] Continue to the description of the above-mentioned implementation. The structure of the multilayer printed wiring board of the first modification of the third embodiment of the semiconductor element (IC wafer 20) of Example 1. Referring to the multilayer printed wiring board 10 shown in FIG. 32, the IC is embedded in the core substrate '. In contrast, in the first modification, as shown in FIG. 41, a heat sink 30d is mounted on the inside of the 1C wafer 20. The multilayer printed wiring board 10, the heat sink 30D, and the core substrate housing the IC chip 20. 31, 1C wafer 20 interlayer resin insulation layer 50, and interlayer resin insulation layer 丨 5 〇

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to make. An interlayer window 60 and a conductor circuit 58 are formed on the interlayer resin insulating layer 50, and an interlayer window 160 and a circuit 158 are formed on the interlayer resin insulating layer 150. # @ Above the interlayer resin insulation layer 150, a solder photoresist layer 70 is provided. The conductor circuit 158 under the opening 71 of the solder resist layer 70 is provided with a solder bump 76 for connection to an external substrate such as a daughter board or a mother board (not shown).

The heat sink 30D is composed of ceramics such as aluminum nitride, aluminum oxide, and mullite, or metals such as alloys, copper, and adjacent bronze. Here, it is appropriate to use an aluminum alloy having a high thermal conductivity or a copper foil subjected to roughening on both sides. In this embodiment, a heat sink 3 0D is installed inside the c-wafer 20 embedded in the core substrate 3 to dissipate the heat generated by the ic wafer 20 and prevent the core substrate 31 from forming an interlayer resin formed on the core substrate. The bending of the insulating layer 50, 5 ′, the interlayer window 6 0, 6 ′ on the interlayer resin insulating layer, and the conductor circuit 5 8 ′ 1 58 did not break. This improves the reliability of the wiring.

Furthermore, the IC chip 20 and the heat sink 30 D are mounted with a conductive adhesive 29. The conductive adhesive 29 is a metal powder containing copper, silver, gold, aluminum, etc. in the resin. Because of its high thermal conductivity, it can efficiently dissipate the heat generated in the c-chip 2 0 from the heat sink 30D. Here, the 1C wafer 20 is mounted using a conductive adhesive, but as long as it is a thermally conductive adhesive, various materials can be used. In the multilayer printed wiring board of this embodiment, the core substrate 31 has an IC chip 20 'built therein, and a transition layer 38 is provided on the pad 22 of the IC chip 20. Therefore, instead of using lead parts and packaging resin, it is possible to obtain c-chips and multilayer printing.

546999 V. Description of the invention (57) '' Electrical connection of wiring board (construction substrate). Further, because the transition layer 38 is formed in the j c wafer portion, the IC wafer portion is planarized, and the upper interlayer resin insulating layer 50 is also planarized, and the film thickness becomes uniform. In addition, the transition layer can also maintain the shape stability when forming an upper via window.

In addition, a steel transition layer 38 is provided on the die pad 22, which can prevent resin residue on the pad 22, and is immersed in an acid and an oxidizing agent or an etching solution in subsequent steps. Even after various tempering steps, the pad 22 Discoloration and dissolution will not occur. With this, it is possible to improve the continuity and reliability of the IC chip and the interlayer window. Through the transition layer 37 having a diameter of 60 // Π1 or more on the diameter 22, the interlayer window of 60 diameter can be reliably connected. Continuing, a method for manufacturing a multilayer printed wiring board according to the first modification of the third embodiment described above with reference to FIG. 41 will be described with reference to FIGS. 36 to 40. (1) A plate-shaped heat sink 30D (Fig. 36 (A)) composed of ceramics such as aluminum nitride, aluminum oxide, mullite, or aluminum, or bronze, is coated with an electrical adhesive 29 ( Figure 36 (B)). Conductive adhesive is used

There is a paste with copper particles with an average particle diameter of 2 to 5 / zm to form a thickness of 10 to 2 (m). The thickness is as described above with reference to Figure 3 (B) (Figure 36 (C)) . J "Yue 20

(5) Next, the heat sink 30 on which the 1C chip 20 is mounted is placed on a stainless steel plate 100A. Then, a 5-color prepreg laminated body 31 α formed by laminating a core material such as glass cloth and impregnating uncured prepreg chains of resins such as BT resin and epoxy is placed on a radiator 30 d. (Figure 37 ·)). The position of the IC chip 20 is set in advance on the prepreg laminated body 31 α.

546999

A through hole 32 is provided. Here, a resin-impregnated prepreg is used, but a resin substrate without a core material may be used. Instead of the prepreg, various thermosetting resins, or a sheet in which a thermosetting resin and a thermoplastic resin are impregnated, can be used. (4) The laminated body is pressed with a stainless steel (SUS) platen 100A, 100B from above and below. At this time, the resin 31々 is extruded from the prepreg 3? Α to fill the space between the through-hole 32 and the 1C wafer 20 while covering the upper surface of the IC wafer 20. Thereby, the top surface of the '1C wafer 20 and the prepreg laminated body 3ΐα is completely flat (Fig. 37 (B)). Therefore, when the superposition layer is formed in the subsequent steps,

By properly forming vias and wirings, the reliability of the wiring of the multilayer printed wiring board can be improved. (5) Then, the epoxy resin of the prepreg is hardened by heating to form the core substrate 31 containing the 1C wafer 20 (Fig. 37 (C)). (6) A thermosetting epoxy-based resin having a thickness of 50 // m is laminated on the substrate which has been heated at a temperature of 50 to 150 ° C. under a pressure of 5 kg / cm 2 and a ring is provided on the substrate after the above steps. An interlayer resin insulating layer 50 composed of an oxygen-based resin (Fig. 38 (A)). The degree of vacuum for vacuum compaction was 10 mmHg.

(7) Next, use a CO2 gas laser with a wavelength of 10.4 // π and a beam diameter of 5mm, a top hot mode, and a pulse of 5.0. With the aperture and the aperture of 0.5 mm and a range of 1 second, an interlayer window opening 60 & 8 is provided on the 'interlayer resin insulation layer 50' (see FIG. 38 (B)). Use chromic acid and permanganic acid to remove resin residues in the openings. A copper transition layer 38 is provided on the die pad 22, whereby the connection between the die pad 22 and an interlayer window 60 described later can be improved, and three 1 s

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Property: The grains 塾 22 and 巧 22 pass through the transition layer 38 on 60㈣, and they are connected to the 60-diameter interlayer window with a certain opening 48. Here, the resin residue is removed using chromic acid, but desmear treatment may also be performed by pulp and corona treatment. (8) Next, the surface of the interlayer resin insulating layer 50 is roughened with permanganic acid to form a roughened surface 50α (Fig. 38 (c)). (9) Next, an electroless plated film 52 is provided on the interlayer resin insulating layer 50 forming the roughened surface 50α (Fig. 39 (A)). For electroless plating, copper and nickel can be used. The thickness is preferably in the range of 0.3 / zm. Less than 0/3 // in, a metal film cannot be formed on the interlayer resin insulating layer. If it exceeds 2 # m, the etched metal film will remain, which may easily cause a short circuit between conductors. A plating film was formed under the same plating solution and plating conditions as in Example 1. In addition to the above, it is also possible to use the same device as the plasma treatment, and use Ni-Cu alloy as the dry material, and perform sputtering under the conditions of air pressure 0.6pa, temperature, and power 200mm for 5 hours, and interlayer A Ni-Cu alloy 52 is formed on the surface of the resin insulating layer 50. At this time, the thickness of the formed Cu alloy layer 52 is 0 · 2 // m 〇 (10) On the substrate 30 where the above-mentioned processing is completed, a commercially available photosensitive dry film is bonded, and a photomask sheet is placed thereon. After the exposure at 10 mj / cm2, the plating resist 54 was set to a thickness of 0.8% sodium carbonate development treatment. Next, electrolytic plating was applied to form an electrolytic resistive film 56 having a thickness of 15 / ZΠ1 (see Fig. 39 (B)). (11) After removing the photoresist 54 with 5 yNaOH, the nitric acid and sulfuric acid were used together with The mixed solution of hydrogen peroxide etches the metal layer 5 2 under the plating photoresist and dissolves it.

546999 V. Description of the invention (60) The conductor circuit 5 8 and the interlayer window 60 composed of the metal layer 52 and the electrolytic plating film 5 6 with a thickness of 16 6 are formed, and the second copper complex and the organic acid are etched. Liquid to form a roughened surface 5 8 α, 60 0 α (see FIG. 39 (C)). In the first modification of the third embodiment, referring to FIG. 37 (c), as described above, the upper surface of the core substrate 31 is completely formed smoothly, so that the transition layer 38 can be appropriately connected through the interlayer window 60. Therefore, the reliability of the multilayer printed wiring board can be improved. 0 (12) Next, by repeating the steps (6) to (丨 丨) above, an upper interlayer resin insulation layer 150 and a conductor circuit 158 (including a via window) are formed. 16 〇) (Figure 40 (A)). (13) Next, the above-mentioned solder resist composition is coated on the substrate 30 at a thickness of 20, and dried under the conditions of 7 (TC20 minutes, 7 (rc30 minutes), f, so that a solder resist opening is drawn. The thickness of the pattern of the part is 5 mm, which is in close contact with the solder photoresist layer 70 and exposed to ultraviolet light at 100 mJ / cm2, and processed with a DMTG solution to form a state_diameter 40 figure (B)). Step 04) Next, a thickness of 5 ㈣ on the ore layer 72 of the recording money layer 7 is formed on the opening 71 of the solder photoresist layer (organic resin insulation base: .03 _ gold plating layer 74, and A solder pad 75 is formed on the conductive nickel circuit 158 (refer to FIG. 4 (c)). • After (15), the opening (rte) of the solder resist layer 70 / borrowed * soft solution (μΜ) ) Formation of solder bumps \ tin 76 paste material Mang 4 'Zheng Zhengzhai 30D' divided into single pieces and the wiring board 10 (refer to Figure 41). Yu Xi layer printing

546999 V. Description of the invention (61) [First alternative of the first modification of the third embodiment] Next, a multilayer printed wiring board according to the first modification of the first modification of the third embodiment will be described with reference to FIG. 43. The first modification example described above is for the case where a BGA is provided. The first other example is substantially the same as the first modified example, but is configured by a PGA method in which a connection is obtained via a conductive connection bolt 96 as shown in Figs. In the first modified example described above, the interlayer window is formed by a laser. However, in the first alternative example, the interlayer window is formed by a light beam. A manufacturing method of the multilayer printed wiring board according to the first alternative example will be described with reference to Figs. (4) As in Example 1, on the substrate subjected to the above steps (丨) ~ ^), a thermosetting epoxy resin 50 with a thickness of 50 // m was applied (Fig. 42 (A)) 〇) · Next, a photomask sheet 49 with black dots 49a corresponding to the positions where the interstitial windows are formed is placed on the interlayer resin insulation layer 50, and exposed (Fig. ^ (B)) 〇)) The TG liquid spray development image is heat-treated to provide an interlayer resin insulating layer 5 having a straight window opening 48 for layer windows. (Figure 42 (c

Γ 成) The surface of the interlayer resin insulating layer 50 is roughened by the second series or chromic acid. (D)} ° The example 1 is different, so the description is omitted. [Second Alternative Example of the First Modified Example of Embodiment 3] Multilayer Printing of the Second Modified Example of the First Modified Example of Tsukisushi Yoke Example 3

2160-3798-pf.ptd Page 64 546999 V. Description of the invention (62) '~ Manufacturing method of wiring board. In the first modified example and the first other example described above, a core substrate is formed by using a prepreg. On the other hand, in a second example, a resin substrate obtained by temporarily curing a prepreg is fixed to the heat sink 30D with the prepreg. A method for manufacturing a multilayer printed wiring board according to the second alternative example will be described with reference to Fig. 44. (9) A heat sink 30D composed of a copper foil roughened on both sides of the IC chip 20 through the conductive adhesive 29 is mounted and placed on a stainless steel (SUS) plate 100A. Then, a non-hardened prepreg (0.2 mm) 31α of a core material such as glass cloth impregnated with a resin such as BT resin or epoxy is placed on the heat sink 30D. In addition, a resin substrate (0.4 mm) 31 r (see FIG. 44 (A)) was placed on the prepreg chain 31 α to harden the prepregs. In the prepreg chain 31 α 'resin substrate 31 τ, a through hole 32 is provided in advance at a position of the IC wafer 20. " (10) Stainless steel (SUS) pressure plates 100A and 10OB are used to press the above-mentioned laminated body from above and below. At this time, 31 points of the resin are extruded from the prepreg 31 α to fill the space between the through-hole 32 and the 1C wafer 20 while covering the upper surface of the IC wafer 20. Thereby, the upper surfaces of the 1C wafer 20 and the prepreg laminated body 31α are completely flat (Fig. 44 (B)). Therefore, interlayer windows and wirings can be appropriately formed when forming the laminated layer in the subsequent steps, and the reliability of the * wiring of the multilayer printed wiring board can be improved. (11) After that, the epoxy resin described in the prepreg is hardened by heating to form a core substrate 31 containing a 1C wafer 20 (Fig. 44 (C)). The subsequent steps are the same as those in the second embodiment, and therefore the description is omitted. 546999 V. Description of the Invention (63) [Second Modification of Embodiment 3] The structure of the multilayer printed wiring board according to the second modification will be described with reference to Fig. 50 showing a cross section of the multilayer printed wiring board. In the first and first modification examples described above, one 1C chip is housed. In contrast, the multilayer printed wiring board 10 of the second modified example shown in FIG. 50 contains a 1C chip (CPU) 20A and a 1C chip (a cache memory) 20B in a core substrate 30. At this time, as in Example 3, an interlayer resin insulation layer 50 and an interlayer resin insulation layer 150 are formed on the core substrate 30. An interlayer window 60 and a conductor circuit 58 are formed on the interlayer resin insulation layer 50, and the interlayer resin insulation On the layer 150, a via window 160 and a conductor circuit 158 are formed. On the 1C wafers 20A and 20B, a passivation film 24 is covered, and a die pad 22 constituting an output terminal is arranged in the opening of the passivation film 24. Over the fabricated die pad 22, a transition layer 38 is formed. The transition layer 38 has a three-layer structure including a first thin film layer 33, a second thin film layer 36, and a thickness-providing film 37. A solder photoresist layer 70 is provided on the interlayer resin insulating layer 150. The conductor circuit 58 under the opening 71 of the solder resist layer 70 is provided.

Solder bumps 76, which are connected to external substrates such as a daughter board and a mother board, which are not shown in the drawing. The multilayer printed wiring board of the second modification of the third embodiment is a 1C chip 20A, 20β embedded in the core substrate 30 in advance. A transition layer 38 is provided on 塾 22 of the IC chip 20. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (construction substrate) can be obtained without using lead parts and packaging resin.

2160-3798-pf.ptd 546999

Because the transition layer 38,1 (is formed in the IC chip portion, the upper interlayer resin insulating layer 50 is also flattened, and the @film thickness becomes uniform. Also, the transition layer can also be used to secure the pull. In addition, the stability of the shape of the interlayer window is guaranteed, and a copper transition layer 38 is provided on the die pad 22, which can prevent the resin on the pad 22 from remaining. Collapsed in acid and oxidant 戋 etching solution, discoloration and dissolution of pad 22 will not occur even after various tempering steps. This can improve the connection and reliability of wafers and interlayer windows. A 60-diameter interlayer window can be surely connected to the pad 22 having a diameter of about 40 / zm via a transition layer 37 having a diameter of 60 or more. The second modification of the third embodiment is to change two (^ 1 | Use IC chip 20A and fast, buffer storage memory. IC chip 20B is embedded in the printed wiring board. The IC chip is "individual manufacturing method is cheap, because each jc chip is nearby." It is not easy to cause transmission. Delays and malfunctions. Also, even if the printed wiring board is not changed In this case, the design of the IC chip itself does not need to be changed, and the degree of freedom of formation is high. The recessed portion 32 of the printed wiring board according to the second modification of the third embodiment is filled with an adhesive layer 34. The recessed portion 32 can be joined 1C wafers 20A and 20B can suppress the behavior of 丨 c wafers A and 2 0β and maintain smoothness even after the thermal history during thermal cycling and formation of the interlayer window. Therefore, it will not cause a connection with the interlayer_ Partial peeling and disconnection, or cracks in the interlayer insulation layers 50 and 150. And it improves reliability. Continue to 'Refer to Figure 45 to Figure 49 and explain the above-mentioned example 3 with reference to Figure 50. A multilayer printed wiring board according to a second modified example. Here, the first

2160-3798-pf.ptd Page 67 546999 V. Description of the Invention (65) 1 'First modified example' is formed on the IC substrate and then stored in the core substrate. On the other hand, in the second modified example, I (;; the transition layer 38 is formed after the wafer is housed in the core substrate.) (1) First, the core material such as glass cloth is impregnated with a resin such as epoxy resin and the prepreg is described as a laminate. An insulating resin substrate (core substrate) 30 is a starting material (FIG. 45 (A)). Next, one side of the core substrate 30 is processed with a recess (zagul i) to form a recessed portion 32 for ic wafer storage (FIG. 45 (B )). Here, although the recessed portion is processed by the recessed portion, an insulating tree provided with an opening will be provided.

The substrate is bonded to a resin-insulated substrate without an opening, and a core substrate having a receiving portion can be formed. (2) After that, the adhesive material 34 is applied to the recessed portion 32 by a printer. In this case, infusion can be used in addition to the cloth. Next, 1 (: wafers 20A and 20b are placed on the bonding material 34 (FIG. 45 (C)). (3) Then, the tops of the IC wafers 20A and 20B are pressed or knocked. And it is completely contained in the recessed part 32 (FIG. 45 (D)). Thereby, the core substrate 30 can be made to slide.

(j) Thereafter, the core substrate 30, which contains the wafers 20A and 20b, is subjected to vapor deposition, low-grade ore, and the like to form a conductive first thin film layer 33 (Fig. 45 (E). The metal is preferably nickel, lead, chromium, cobalt, titanium, gold, tin, or copper. The metal, chromium, and titanium are particularly suitable for film formation and electrical characteristics. The thickness is 0.002. 2 It is better to form between them. The combination of chromium is preferably a thickness of 0.1 Am. By covering the die pad 22 with the first thin film layer, the adhesion between the transition layer and the interface on the a wafer and the die pad 22 can be improved. In addition, by covering these metals with 546999, the invention description (66) is covered with the grain pad 22, the energy level L, solution, rotten name, and can be improved by: invading the interface and preventing grains The solution of rhenium can be made without using a lead; =. Also, with the first thin film layer 铬, chromium is used ... because 2 = the connection with the IC chip is obtained. μ It is better to stop water from invading the interface. Form the second thinner =; Second borrowed ^, Figure 46 (A)). The metal is nickel, copper, electrical characteristics, economy and stacks formed in the subsequent Guide of alu The layer is mainly copper, so copper is preferred. One layer: the reason for the thin film layer is that in the first thin film layer, the lead for electrolytic power mining cannot be obtained after the thick additional layer is formed. The second thin film layer 36 It is a pin with a given thickness. The thickness is preferably in the range of 0 01 to 5_. If it is less than 0.01, the effect as a pin cannot be obtained. If it exceeds, the lower layer of the first layer will be removed during etching. There are voids in the layer, and moisture becomes easy to penetrate, which reduces reliability. The most appropriate value is 0.3 / zm. (6) After that, a photoresist layer is applied, and exposed and developed to the die pad of the IC chip. The upper part is provided with an electroplating photoresist 35 without openings, and an electrolytic plated film (thick additional layer) 37 is provided by applying electrolytic power ore (Fig. 46 (B)). The thickness of the film can be recorded, copper, gold, silver, Sub-errors, iron, etc. are formed. After the plating photoresist 35 is removed, the second thin film layer 36 and metal film 33 under the photoresist photoresist 35 are removed in a short time, and a transition layer 38 is formed on the die pad 22 of the 1C wafer. (Fig. 46 (C)). Although the transition layer is formed by electroplating photoresist, the non-electrolytic second film can also be formed here. The thickness of the electrolytic plating film is uniformly formed on the layer 36 to form an etching photoresist, and the image is exposed to expose parts other than the transition layer.

546999 Fifth, the invention describes (67) the metal and carries out #engraving, and the layer is on the die pad of the 1C wafer. The thickness of the electrolytic plated film is preferably 20 // m. A thicker dagger than this will cause an undercut in the rest of the time, resulting in a ~ # 'gap in the transition layer. The layer-solid interface will occur (7). Next, a rough screen 38 will be formed by spraying an etching solution on the surface of the etching etching transition layer 38 with a spray (see Fig. 46 &). Electroless plating and redox treatment form a roughened surface. ° 38 is composed of the first thin film layer 33, the second thin film layer 36, and the thick additional layer. (8) The temperature of the heat-curable fat sheet with a thickness of 50 / zm is raised on the substrate after the above steps. An interlayer resin insulation layer 50 (Fig. 47 (A)) is provided at a pressure of 5 kg / cm2 to 50 to 150 ° C under vacuum pressure lamination. The degree of vacuum during vacuum pressure is 10 mmHg. (9) Next, With a CO2 gas laser with a wavelength of ΐ0.4, and a beam diameter of 5mm, a top hot mode, a pulse wave of 5.00 seconds, Aperture: 0.5mm; [range conditions, openings for interlayer windows with a diameter of 800m are provided on the interlayer resin insulating layer 50

(Refer to Figure 47 (B)). Residual resin in the opening 48 was removed using chromic acid. By providing a transition layer 38 made of copper on the die pad 22, the resin on the die pad 24 can be prevented from remaining, and the connection and reliability of the die pad 24 and an interposer window 60 described later can be improved. In addition, a 60 μm diameter window 48 can be reliably connected to a 40 μm diameter die pad 22 through a transition layer 38 of 60 // m or more. Here, the resin residue is removed using permanganic acid ’, but the residue may be removed using an oxygen plasma and a corona treatment.

Page 70 546999 V. Description of Invention (68) (desmear) processing. Here, although the opening 48 is formed by a laser, it may be formed by exposure and development processing. (1 0) A roughened surface 5 0 α is formed on the interlayer resin insulating layer 50 using an acid or an oxidizing agent (see FIG. 47 (c)). The rough surface is preferably formed in a range of an average thickness of 卜 5. (11) An electroless mineral film 52 is provided on the interlayer resin insulating layer 50 forming the roughened surface (Fig. 48 (A)). For electroless plating, copper and nickel can be used. The thickness is preferably in the range of 0 · 3 to 1 · 2. Below 0.3, a metal film cannot be formed on the interlayer resin insulating layer. If it exceeds 1.2, the metal film will remain after etching, which is easy.

Cause short circuit between conductors. A plating film was formed using the same plating solution and plating conditions as in Example 1. (12) After the above-mentioned substrate 30 is completed, a commercially-available photosensitive dry film is laminated, a photomask sheet is placed, and after exposure at 40 mJ / cm2, the thickness is set with 0.8% sodium carbonate imaging treatment. 25 # m 的 铜 光 54。 54. Next, electrolytic plating is applied to form an electrolytic resistance film 56 having a thickness of 18 / zm (see FIG. 48 (B)).

(13) After stripping and removing the plating photoresist 54 with 5% NaOH, the metal layer 52 under the plating photoresist is etched by using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide to dissolve and remove the metal layer 52 and the electrolytic plating film 5 The conductor circuit 58 and the interlayer window 60 with a thickness of 6 // m and a thickness of 6 are formed by etching with a second copper complex and an organic acid. The etching solution forms a roughened surface 5 8 α, 6 0 α (refer to Section 4 8 (C)). The roughened surface can also be formed using electroless plating and redox treatment. 04) Then, by repeating the above steps (9) to (13), the interlayer 150 and the conductor circuit 158 (including the interlayer window 16) of the upper layer are formed again (refer to page 49).

2160-3798-pf.ptd p. 71 546999

Figure (A)) 〇 (15) Next, the same solder photoresist composition was coated on the substrate 30 at a thickness of 30 Å, and dried under a condition of 7 (rc 20 minutes, tillering conditions), and then drawn. The outer line with the solder ^ is exposed, and the DMTG solution is used to develop the opening s to form an opening 71 (refer to Figure 49 (B)). (16) Next, a solder photoresist layer (organic resin insulation layer) will be formed. The substrate was immersed in the same electroless plating solution as in Example 丨, and a nickel plating layer 72 having a thickness of 5 // m was formed in the opening 71. The substrate was immersed in the same electroless plating as in Example 1. In the liquid, a gold plating layer 74 having a thickness of 0.03 is formed on the nickel plating layer 72, and a solder pad 7 5 is formed on the conductor circuit 158 (refer to FIG. 4 9 (C)). (1 7) After the soldering A solder paste is printed on the opening 7 丨 of the resist layer 7 and the solder bump 76 is formed by reflow at 200 ° C. Then, it is divided into squares to obtain a single piece of printing. Wiring board 丨 〇 (Refer to Fig. 50). [First alternative of the second modification of the third embodiment] Continue to 'Explain actual conditions with reference to Figs. 5 1 to 5 2 The printed wiring board of the first other example of Embodiment 3. Fig. 52 shows the printed wiring board of the first other example. The printed wiring board of the first other example and the second modification described above with reference to Fig. 50 The printed wiring board is the same. However, in the second modification described above, the transition layer 38 is formed after the core substrate 30 receives the IC chip. In contrast, the first modification is the same as the first embodiment.

2160-3798-pf.ptd Page 72 546999 V. Description of the invention (70) After the transition layer 38 is formed on the IC chip, it is housed in the core substrate. Continuing, a method of manufacturing a multilayer printed wiring board according to a first alternative shown in FIG. 52 of the semiconductor device (1C wafer) 20A and 20B in the through hole of the core substrate will be described with reference to FIG. 51. Here, the transition layer 38 is provided on the 1C wafers 20A and 20B in the same manner as in the manufacturing method of the first embodiment. (1) First, an insulating resin substrate (core substrate) 30 laminated with a core material such as glass cloth impregnated with a resin such as epoxy is used as a starting material (Fig. 51 (A)). Next, on one side of the core substrate 30, a recessed portion 32 for ic wafer storage is formed as a recessed portion (FIG. 51 (B)).

). Here, although the recessed portion is formed by processing the recessed portion, an insulating resin substrate provided with an opening and a resin insulating substrate provided without an opening may be bonded to form a core substrate having a receiving portion. (2) After that, the adhesive material 34 is applied to the recessed portion 32 by a printer. In this case, infusion can be used in addition to the cloth. The 1C wafer 20 is then placed on the bonding material 34 (FIG. 51 (C)). (3) Then, the upper surface of the IC wafer 20 is squeezed or knocked to be completely contained in the recessed portion 32 (Fig. 51 (D)). Thereby, the core substrate 30 can be smoothed. The subsequent steps are the same as those in the second modification described above with reference to Figs. 47 to 49, and description thereof will be omitted. In Embodiment 3, a transition layer is provided on the die pad, which can prevent resin residue on the die, and improve the continuity and reliability of the die pad and the interlayer window. Furthermore, it is manufactured by using a plurality of multilayer printed wiring boards including semiconductor elements. Then, each multilayer printed wiring board was obtained by cutting into a single piece. Therefore, a highly reliable multilayer printed wiring board can be manufactured efficiently. ^ 546999 V. Description of the invention (71) In addition, compared with the conventional IC chip's & method, it can shorten the wiring length of the IC chip ~ substrate ~ external substrate, and also ^ ^ ^ ^. 4 has the effect of reducing loop inductance [Embodiment 4] The following describes Embodiment 4 of the present invention with reference to the drawings. The multilayer printed wiring board 10 of Embodiment 4 as shown in Fig. 57 is composed of The core substrate 30 of the Shigu C wafer 20 is composed of an interlayer resin insulation layer 50 and an interlayer resin insulation layer 150. An interlayer window 60 and a conductor circuit 58 are formed on the interlayer resin insulation layer 50, and the interlayer resin insulation Formed on layer 15

There are via windows 160 and conductor circuits 158. A heat radiation plate 44 is mounted inside the ic wafer 20. A fresh tin photoresist layer 70 is arranged on the interlayer tree-known insulating layer 150. The conductor circuit 58 under the opening 71 of the tin photoresist layer 70 is provided with a solder bump 76 for connecting to an external substrate such as a daughter board or a mother board (not shown). '

A die pad 22 and wiring (not shown) are arranged on the same multilayer printed wiring board as in Example 1, and a passivation film is coated on the die pad 22 and the wiring. An opening of the tunable film 24 is formed in the die pad. On the die pad 22, a transition layer 38 mainly composed of copper is formed. The transition layer 38 is composed of a thin film layer 33 and an electrolytic plated film 37. In the multilayer printed wiring board of the fourth embodiment, a 1C wafer 20 is embedded in the core substrate 31, and a transition layer 38 is disposed on the pad 22 of the 1C wafer 20. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (construction substrate) can be obtained without using lead parts and packaging resin. Also, because in the IC chip part

2160-3798-pf.ptd p. 74 546999

The y-k layer 38 is flattened, and the IC wafer portion is flattened. The upper interlayer resin insulation layer 50 is also flattened, and the film thickness becomes uniform. In addition, the transition layer can also maintain the shape stability when forming an upper via window. In addition, a copper transition layer 38 is provided on the anode 22 to prevent resin residue on the pad 22, and in the subsequent steps, it is immersed in acid and oxidant or etching solution. Even after various tempering steps, the pad 22 Discoloration does not occur. This' can improve the continuity and reliability of the IC chip and the interlayer window. In addition, through a transition layer 37 having a diameter of 60 / zm or more on a // 22 having a diameter of 40 // in, a via window having a diameter of 60 can be surely connected. Continuing, a manufacturing method of the multilayer printed wiring board of Example 4 will be described with reference to Figs. 5 3 to 56.

(1) A core substrate 30 having a thickness of 0.5 mm is laminated with a core material such as glass cloth impregnated with a prepreg of BT (bismaleic anhydride imine triazine) resin, epoxy resin, or the like, and hardened. . First, a through hole 32 for 1C wafer accommodation is formed in the core substrate 30 (Fig. 53 (A)). Here, a resin substrate 30 in which a core material is impregnated with a resin is used, but a resin substrate without a core material may be used. Furthermore, it is preferable that the lower end opening portion of the through hole 32 is provided with the adhesive tape 32a. The tape 32a is pressurized as described later, and no bubbles remain between the 1C wafer 20, the filling resin 41, and the substrate 30, which can improve the reliability of the multilayer printed wiring board. (2) Thereafter, a UV tape 40 is attached to the bottom surface of the through hole 32 of the core substrate 30 (Fig. 53 (B)). This UV tape 40 can be used with // Yu Xi: / Adwill D-201, D-203, D2303DF, D-204,

2160-3798-pf.ptd Page 75 546999 V. Description of the invention (73) D210, D218, etc. i. The detached adhesive tape repairs the spleen belt which loses the adhesive force of the adhesive surface. Here, even though Gu Zhi Xuan You 4 > tape with a temperature of 80 ° c or higher is applied, it is also possible to use 冋 on temporarily hard ^ ^ ^, and various adhesives that do not reduce the adhesion ▼ For example, poly Imidic tape, etc. y ZOοΐί is placed on the through-hole 32_v tape 40 at 3 ° of the core substrate, and ϋν, ί # τ Γ μ is in contact with the die pad 38 and is placed with reference to FIG. 3 (B). ○ (Fig. 53 (C)) 〇 (4) Filler 41 is filled in the through-hole 32 formed in the core substrate 30 (Fig. 53 / Fig. (D)). Filling is performed by printing, mask printing, infusion, and the like. This filler uses an epoxy resin, a polyimide resin, and the like to mix an imidazole-based, amine-based, acid-anhydride-based hardener and a filler (organic particles, organic solvents, metal particles, and the like), and mixes the solvent as desired Resin with a viscosity of 0.1 to 50,000 Pa · s (C-series, 曱 本 糸 f). The filler may be a thermosetting resin, a thermoplastic resin, or a composite thereof. (5) After the filling of the filler 41, the pressure is reduced in a decompression chamber of about 10 minutes to remove bubbles in the filler 41. Thereby, no bubbles remain in the filler 41 'can improve the reliability of the multilayer printed wiring board. (6) Stainless steel (SUS) pressure plates 100A and 100B are pressurized from the up and down direction 10 as a bell (Fig. 53 (E)). After that, it is heated at 70 to 120 ° C for about 30 minutes while being pressurized to temporarily harden the filler 41. It is appropriate that pressurization, 'pressurization, and / or temporary hardening is performed under reduced pressure. By reducing the pressure, no air bubbles remain between the IC chip 20, the core substrate 30, the filler 41, and the filler 41, and the reliability of the multilayer printed wiring board can be improved. At the time of this pressing, the die pad 38 has the UV tape 40 as a cushioning material.

2160-3798-pf.ptd p. 76 546999

It will not damage the die pad 38. (7) Irradiate the u V tape 40 U V of the core substrate 30 temporarily filled with the filler 41 and peel it off after the adhesive force is lost (Fig. 54 (A)). In Example 4, since a UV tape is used, there is no adhesive residue on the die pad 38 of the IC wafer, and it can be completely peeled off without damaging the die pad 39. Therefore, the interlayer window 60 can be connected to the die pad 38 in the subsequent steps. (8) Thereafter, the filler 41 and the core substrate 30 on the inner side of the IC wafer 20 are polished using a belt grinder (be It sander) of a belt-shaped abrasive paper (manufactured by Sankyo Rika Co., Ltd.) to make the 1C wafer Inside side exposed (p. 54

(B)). In Example 4, the polishing can be easily performed because the polishing is performed while the filler 41 is temporarily hardened. "(9) After heating, the filler is really hardened to form the core substrate 30 containing the c-wafer 20. The true hardening is suitable to be performed under reduced pressure. By reducing the pressure, there is no air bubble remaining in the filler 41 No groove will be formed. In addition, the reliability and flatness of the multilayer printed wiring board can be improved. (10) A heat radiation plate is mounted on the inner side of the IC chip 20 via a heat conductive adhesive (containing, for example, metal particles) 42. 44 (Figure 54 (C)).

The exothermic plate can use metal plates and ceramic plates such as aluminum and copper. In Example 4, the bottom side of the core substrate 30 was polished and exposed! At the bottom of the c-chip 20, it is possible to install a heat radiation plate 44 at the bottom of the 1C-chip, which can improve the stability of the operation of the ic-chip 20. (11) On the substrate that has undergone the above steps, it is heated at a temperature of 50 ° to 150 ° C, and a thermosetting ring 1 with a thickness of 50 v ^ is laminated under a pressure of 5 kg / cm2 to form a resin sheet. Interlayer resin insulation layer 5 (Fig. 54 (D)

546999 V. Description of Invention (75)). The degree of vacuum for vacuum compaction was 10 mmHg. (12) ’followed by a CO2 gas laser with a wavelength of 10.4 // m, and a radio wave

(beam) diameter 5mm, top hot mode, pulse 5 · 0 // second, aperture of the mask 0 · 5mm, [condition of range, set on interlayer resin insulation layer 50 Openings for vias with a diameter of 6 0 // m 4 8 (refer to Figure 54 (B)). Residual resin in the opening 48 was removed using chromic acid and permanganic acid. By providing a copper transition layer 38 on the die pad 22, the connection between the die pad 22 and an interlayer window 60 described later can be improved. Furthermore, the 60 / zm diameter interlayer window can be reliably connected to the 40 // m diameter die pad 22 via a transition layer 38 'of 60 or more. Here, although the resin residue is removed using an oxidizing agent, a desmear treatment may be performed using an oxygen plasma and a corona treatment. (13) Next, the roughened surface 50 0 α of the interlayer resin insulating layer 50 is set by immersing in an oxidizing agent such as chromic acid or peracid (Fig. 55 (A)). The roughened surface 5 0 α is preferably formed in a range of 0 ·; 1 to 5 // m. An example of this is to set a roughened surface 50α of 2 to 3 // m by immersing it in a sodium permanganate solution at 50 g / l and a temperature of 60 ° C for 5 to 25 minutes. In addition to the above, it is also possible to perform an electrical equipment treatment to provide a roughened surface 50 α on the surface of the interlayer resin insulating layer 50.

(14) An electroless plated film 52 is provided on the interlayer resin insulating layer 50 forming the roughened surface 50 ck (Fig. 55 (B)). The metal layer 52 is formed by electroless plating. Catalysts such as pal lidium) were applied to the surface of the interlayer resin insulating layer 50 in advance, and immersed in an electroless plating solution for 5 to 60 minutes in the same manner as in Example 1 to set 0 ·; [~ 5 // m-plated metal reed 52. , 9

546999 Description of the invention (76) In addition to the above, a Ni-Cu alloy 52 may be formed on the surface of the interlayer resin insulating layer 50 by using the same device as the above-mentioned plasma treatment. (15) A commercially-available photosensitive dry film is attached to the substrate 30 that has undergone the above-mentioned processing, and a photomask sheet is placed, exposed at 10 mJ / cm2, and then developed with 0.8% sodium carbonate. Set the plating photoresist 5 4 with thickness 1 5 // m. Next, electrolytic plating was applied under the same conditions as in Example 1 to form an electrolytic resistance film 56 having a thickness of 5 ”m (see FIG. 55 (C)).

(16) After stripping and removing the plating photoresist 54 with 5% NaOH, the metal layer 52 under the plating photoresist is etched by using a mixed solution of nitric acid, sulfuric acid, and hydrogen peroxide to dissolve and remove the metal layer 52 and the electrolytic plating film 56. The conductor circuit 58 and the interlayer window 60 with a thickness of 16 are composed of a second copper complex and an organic acid to form a roughened surface 5 8 α, 6 0 α (refer to FIG. 5 (D)) ). Embodiment 4 'Referring to FIG. 53 (E), as described above, the upper surface of the core substrate 31 is completely formed smoothly, so that the transition layer 38 can be obtained through the interlayer window 60 and connected appropriately. Therefore, 'the reliability of two multilayer printed wiring boards can be improved. (17) Next, by repeating the above steps (11) to (16), an upper interlayer resin insulating layer 15 and a conductor circuit 158 (including the interlayer window 160) are formed again (Fig. 56 (A)). Say

(18) Next, a solder resist composition (organic resin insulating material) adjusted in the same manner as in Example 1 was obtained. (19) Next, the above-mentioned solder photoresist composition is coated on the substrate 30 at a thickness of 20 # m, and dried at 70 ° C for 20 minutes and at 70 ° C for 30 minutes. A 5 mm-thick reticle with a pattern of the photoresist openings was in close contact with the solder photoresist layer and exposed to ultraviolet light at 100 mj / cm2.

546999 V. Description of the invention (77) DMTG solution is developed, and 56 (B)). $ 成 200 in diameter of the opening 71 (refer to the jth connection, second, the opening 71 of the substrate forming the tinned photoresist layer (organic resin insulation layer) 70 is formed with a diarrhea & e, and the towel is formed into a thickness of 5 // m of nickel plating layer 72. A nickel plating layer 74 having a thickness of 0.03 // m is then formed on nickel, and fresh tin 塾 75 is formed on the conductor circuit 158 (see section 56¾ (C)). After that, a solder paste (^ paste) is printed on the opening portion 7 丨 of the solder resist layer 70, and a solder bump 76 is formed by softening (reflow) at 200 ° C. Then use dci ng is divided into a single piece and a multi-layer printed wiring board 1 (see FIG. 57). In Example 4, the die pad 38 is brought into contact with the UV tape 4 and placed 1 (wafer 20 'after the UV tape is peeled off) A superposition layer is formed on the IC chip 20. Therefore, it is possible to electrically connect the interlayer window 6 of the IC chip and the superposition layer, and it is possible to manufacture a multilayer printed wiring board embedded in a highly reliable semiconductor element. As above Example 4 described, a thin plate on the bottom of a through hole of a core substrate, a semiconductor element is placed with the thin plate in contact with a terminal, and the through hole is filled with resin to be peeled off That is, a laminated layer is formed. That is, a semiconductor element is placed with a terminal in contact with a thin plate, and after the thin plate is peeled off, a laminated layer is formed on the semiconductor element. Therefore, when the wiring of the terminal and the laminated layer is electrically connected, manufacturing is possible. Multilayer printed wiring board with a highly reliable semiconductor element. [Embodiment 5] Hereinafter, Embodiment 5 of the present invention will be described. Referring to Fig. 63 showing a cross section of the multilayer printed wiring board 10, the description of Embodiment 5 will be described. The structure of a multilayer printed wiring board.

2160-3798-pf.ptd p. 80 546999

For example, the multilayer printed wiring board 10 shown in FIG. 63 is composed of a housing 1 (: wafer 20 to substrate 30, an interlayer resin insulation layer 50, an interlayer resin insulation layer 150, and an interlayer tree insulation layer. It is composed of 2 5 0. On the interlayer resin insulating layer μ, //, layer solid 60 and conductor circuit 58 are formed, and on the interlayer resin insulation layer 5 0, interlayer window 1 60 and conductor circuit 58 are formed. On the interlayer resin insulation layer 250, a via window 260 and a conductor circuit 258 are formed. Above the interlayer resin insulation layer 250, a solder photoresist layer 70 is provided. Below the opening 71 of the solder photoresist layer 70 The conductive circuit 258 is provided with a BGA76 connected to an external substrate such as a daughter board or a motherboard, which is not shown. The BGA76 is disposed on a region R2 other than the region ri above the 1C chip 20. On the 1C chip 20, A passivation film 24 covering the IC chip 20 is covered, and a die pad constituting an output terminal is arranged in the opening of the passivation film 24. On the pad 22, a transition layer 38 mainly composed of copper is formed. At 1C Between the wafer 20 and the recessed portion 32 of the substrate 30 is a bonding material 34 filled with a resin material. The material 34 is fixed to the recess of the substrate—the resin filling material 34 can reduce the stress caused by thermal expansion and prevent cracks in the core substrate 30. The interlayer resin insulation layers 50, 150, The curvature of 250 and the solder resist layer 70. Therefore, it can prevent peeling and cracks that occur around the BGA76. Therefore, it can prevent the solder bump 76 from falling off and the position shift, and can improve electrical continuity and reliability. Fig. 65 shows a £? Ε cross section of the multilayer printed wiring board 10 in Fig. 63. The area inside indicated by the dotted line in Fig. 65 is the area R1 in which the c-chip 2 is built. The area inside the solid line outside the dotted line in Fig. 65 is the area R2 without the 1C chip 20. The conductor circuit 258 is from the area to the area.

2160-3798-pf.ptd Page 81 546999 V. Description of the invention (79) The domain R2 is widely formed in a radial pattern. The solder bumps 75 for connecting with the BGA 76 are arranged in a grid pattern in the region R2. Fig. 66 (A) is a plan view showing the multilayer printed wiring board 10 in Fig. 63. The BGA76 is arranged in a grid pattern in the region R2 and is connected to an external substrate such as a daughter board or a mother board (not shown). In addition, BGA76 may be formed in the region R2 in the shape of a thousand birds as shown in FIG. 66 (B). In the multilayer printed wiring board of Example 5, BGA76 is arranged in the region R2 on the substrate without the IC chip 20 embedded therein.

In short, 'BGA76 is provided in the area R2 other than the IC chip 20', which can reduce the IC chip 20 with a small thermal expansion coefficient of the ceramic composition and the interlayer insulating layer 5 with a large thermal expansion coefficient with the resin composition. 〇, 2 〇 and the thermal expansion of the solder resist layer 70, and can prevent peeling and cracks around the BGA76. Therefore, it is possible to prevent the solder bump 76 from falling off and its position being shifted, and it is possible to improve electrical continuity and reliability. * Also, the multilayer printed wiring board of the present embodiment includes a 1C wafer 20 in the core substrate 30, and a transition layer 38 is provided on the pad 22 of the IC wafer 20. Therefore, the transition layer 3 8 is formed without using the pin parts and the package printed wiring board (construction substrate), and the IC wafer grease insulation layer 50 is also flattened, and the film transition layer can also maintain the formation of the upper layer. Residual resin on the pad 22 is provided. In the subsequent etching solution, even if various tempered resins are passed, the IC chip and the multilayer electrical connection can be obtained. In addition, since the IC chip portion is flattened, the thickness of the upper interlayer tree becomes uniform. And, the stability of the shape when passing through the dielectric window. The copper transition layer 38 can prevent the pad 22 from being immersed in acid and oxidant during the step or discoloration and dissolution of the pad 22

546999

V. Invention Description (80) will happen. This can improve the continuity and reliability of the IC chip and the via. Furthermore, a 60 // m-diameter interlayer window can be read and solidly connected to the pad 22 having a diameter of about 40 through a transition layer 37 having a diameter of 60 / zm or more. Continuing, the multilayer printed wiring board of the fifth embodiment described above with reference to Fig. 63 will be described with reference to Figs. 58 to 62. _ (1) First of all, an insulating resin substrate (core substrate) 30 laminated with a core material such as glass cloth impregnated with a resin such as epoxy resin is used as a starting material (Fig. 58 (A)). Next, on the side of the core substrate 30, a recessed portion 32 for the 1C wafer accommodation is formed by a recessed portion (zagul i) (Fig. 58 (B)). Here, although the recessed portion is provided by the recessed portion processing, the insulation provided with the opening is provided. The resin substrate is bonded to a resin insulating substrate without an opening, so that a core substrate having a container can be formed. 'How to prepare: + is a resin substrate that contains electronic components such as IC chips. Can it be used? · Strong materials and heartwood are impregnated with epoxy resin, BT resin, or prepreg impregnated with epoxy resin with 2 resin ’s layers, but used for printed wiring boards. In addition, m: s board, sheet board, and resin board without metal film can also be used. However, when the temperature above 35 ° C is applied, the resin will completely dissolve, and the carbon

(Cloth 2): Can be πη! Machine-coated adhesive material 34. At this time, it is coated (Fig. 58 tc). The IC chip 20 is placed on a resin having a large expansion coefficient of the bonding material 34. //, the material 'uses a thermal expansion difference worse than that of the core substrate 30. 9 and 1C wafer 20 and core substrate 30

546999 V. Description of the invention (81) (3) Then, the upper surface of the IC wafer 20 is squeezed or knocked to be completely contained in the recess 32 (Fig. 58 (D)). Thereby, the core substrate 30 can be smoothed. At this time, 'the material 34 follows, there is such a material on the 1C wafer 20, because a resin layer is provided on the 1C wafer 20 as described later, and an opening for dielectric sound is provided by laser' will not affect the transition layer and the dielectric. The connection of landing windows has an impact. (4) On the substrate 30 that has undergone the above steps, the thermosetting resin sheet having a thickness of 50 // ιη is heated to 50 to 150 ° C, and laminated with a pressure of 5 kg / cm2 under vacuum, and interlayer resin insulation is provided. Layer 50 (Fig. 59 (A)). The vacuum degree at the time of Ou Yiyi was 10 mmHg. In addition, as described above, the interlayer resin insulating layer 50 can also be used instead of heating and pressing the resin in a semi-hardened state in a thin film shape. The resin composition whose viscosity is adjusted in advance can be coated by a roller and curtain (curtain ) Coating to form. (5) Then 'at a wavelength of ιo 4; / miC〇2 gas laser, and with a beam diameter of 5mm, top hot mode, pulse wave (pu 1 se) 5 · 0 // Second, the aperture of the photomask is 0.5 mm, [the conditions of the range, an interlayer window opening 8 of 8 0 // m in diameter is provided on the interlayer resin insulating layer 50 (refer to FIG. 59 (B)). Use 60 ° C permanganic acid to remove the resin residue in the opening 48. By providing a copper transition layer 38 on the die pad 22, the resin on the die pad 24 is prevented from remaining, and the connection and reliability of the die pad 24 and an interlayer window 60 described later can be improved. Furthermore, a 60 / zm diameter interlayer window opening 48 can be reliably connected to the 40 ° -diameter die pad 22 via a transition layer 38 of 60 // m or more. Here, the resin residue is removed using permanganic acid, but a desmear treatment may be performed using an oxygen plasma and a corona treatment.

546999 V. Description of the invention (82) (6) Then, by immersing in an oxidizing agent such as chromic acid, permanganate, and the like, a rough surface 5 0α of the interlayer tree month insulation layer 50 (refer to Fig. 59 (C). The roughened surface 5 Ο α 'is preferably formed in the range of 0 ·; [~ 5 // m. An example is > 1. 5 to 25 minutes at a temperature of 60 °, and a roughened surface of 50 ° to 2 ° / zm is provided. In addition to the above, a plasma treatment may be performed to form a rough surface on the surface of the interlayer resin insulation layer 50. Metalized surface 5 0 a 〇 (7) A metal layer 52 is provided on the interlayer resin insulating layer 50 forming the roughened surface 50 0 α (see FIG. 60 (A)). The metal layer 52 is formed by electroless plating Catalysts such as palladium; pal 1 idium) are preliminarily provided on the surface of the interlayer resin insulating layer 50, and immersed in an electroless plating solution for 5 to 60 minutes, and set to 0 · !! ~ 5 // The metal layer 52 of the plating film in the range of m. In addition to the above, a Ni / Cll metal layer 52 may be formed on the surface of the interlayer resin insulating layer 50 using Ni and Cu as targets using the same device as the plasma treatment. In addition, instead of sputtering, a metal film may be formed by vapor deposition or electric writing. It is also possible to apply electroless plating after forming a thin additional layer by physical methods such as sputtering, evaporation, and electrodeposition. (8) After the above-mentioned substrate 30 is completed, a commercially-available photosensitive dry film is bonded, a photomask sheet is placed thereon, and the film is exposed at 10 mJ / cm2, and then developed with 0.8% sodium carbonate to develop a thickness. 15 μιη plated photoresist 54. (Refer to FIG. 60 ('FIG. (B)) Next') Electrolytic plating was applied under the same conditions as in Example 1 to form an electrolytic resistance film 56 having a thickness of 15 μm (refer to FIG. 60 (C)). (9) After stripping and removing the photoresist 54 with 5% NaOH, the mixed solution of nitric acid, sulfuric acid and hydrogen peroxide is used to etch the metal layer 52 under the photoresist to dissolve.

Hi 2160-3798-pf.ptd Page 85 546999 V. Description of the invention (83) The second it interposer window 60 with a thickness of 16 组成 consisting of the G1 L1 metal layer 52 and the electrolytic power ore film 56 (refer to section 61 ® (A )). Gasification j, fluorinated second iron, peracids, hydrogen peroxide / sulfuric acid, etc. are used as the remaining liquid. Continue to form a roughened surface 58a, 6Qa (see No. U5) with a second copper distorted spot and a wide range of liquid, and then repeat the steps (7) to (12) above. Then, the upper interlayer 150 and the conductor circuit 158 (including the interlayer window 16) are formed (refer to No. 6; (11). Next, a solder resist composition adjusted to the same as in Example 丨 is obtained. D2) Next, on the substrate 30 Then, the solder resist composition is applied at a thickness of 20 / zm, and after the drying process, the mask is adhered to the solder resist layer 70 to form an opening 71 having a diameter of 20 ° (refer to FIG. 62 (A)). ). (1 3) Next, a nickel plating layer 72 having a thickness of 5 // 111 is formed in the opening portion 71 of the substrate on which the solder photoresist layer (organic resin insulating layer) is formed. Then, a gold plating layer 74 having a thickness of 0.03αm is formed on the nickel plating layer 72, and a solder pad 7 5 is formed on the conductor circuit 258 (see FIG. 62 (B)). 0 4) After that, a solder paste is printed on the opening 71 of the solder photoresist layer 70. The solder paste can be Sn / pt), Sn / Sl), Sn / Ag,

Sn / Ag / Cu, etc. Of course, a radiation low-α-type solder paste can also be used. Continuing ’BGA 76 (Fig. 63, Fig. 63) is arranged in a grid (or a thousand bird shape) in a region R2 that does not contain 丨 c wafer 2 〇 at 200 ℃ by soft solution (re f 1 ow).

Page 86 2160-3798-pf.ptd 546999

The insulating resin substrate (core substrate) 30 laminated on the blank is shown in Fig. 68). Next, on one side of the core substrate 30, a recessed portion 32 for 1C wafer storage is formed by a recessed material (Zaguli) (Fig. 68 (b (2)), and then the adhesive material 34 is applied to the recessed portion 32 by a printer. .Infusion can also be used in addition to this cloth. Then 1 (: wafer 20 is placed on material 1 (Figure 68 (C)). (3) Then, the IC wafer 20A, 2 is squeezed or knocked. The upper surface of 〇B is completely inside the recessed portion 32 (FIG. 69 (A)). As a result, the core substrate 30 can be slipped. (4) Thereafter, the core substrate 30, which houses the IC chip 20, is vaporized. Physical evaporation, such as sputtering, forms a conductive metal film 33 (Figure 69 and (B)). The metal is preferably made of more than one layer of tin, chromium, titanium, zinc, lead, cobalt, and gold. Metals such as copper and copper. The thickness is preferably formed between 0.00 and 2.0 m. Particularly preferred is a thickness of 0.001 to 1.0. The metal film 33 can also be formed by Electroless plating is used to form a plating film 36 (Fig. 69 (C)). The types of electroplating are copper, nickel, gold, silver, meta, iron, etc. Because of electrical characteristics, economy, and superposition in subsequent formations Layer guide The electrical layer is mainly copper, so it is preferable to use copper. The thickness is preferably in the range of 1 to 20 // m. (5) After that, a photoresist layer is coated, and exposed and developed. An opening is provided at the upper portion of the pad 22 to provide a plating photoresist 35, and electroless plating is applied to provide an electroless plating film 37 (FIG. 70 (A)). After removing the plating photoresist 35, the plating resist 35 is removed. Electroless plating film 36, metal film

2160-3798.pf.ptd Page 88 546999 V. Description of the invention (86) 33, and a transition layer 38 is formed on the die pad 22 of the 1C wafer (Fig. 70 (B)). Here, although the transition layer is formed by electroplating photoresist, it is also possible to uniformly form an electrolytic plating film thickness on the electroless electrostrip film 36 to form an etching photoresist, and expose the image to expose the metal other than the transition layer. Etching is performed to form a transition layer on the die pad of the IC wafer. In this case, the thickness of the electrolytic plating film is preferably 1 to 2 0 // ra. If it is thicker than this thickness, undercutting will cause an undercut at the interface between the formed transition layer and the interlayer window during etching. (6) · Next, the surface of the transition layer 38 is etched to form a rough day surface 38α by spraying an etching solution on the substrate with a spray (Fig. 70 (c)). The subsequent steps are the same as those in the fifth embodiment, and therefore descriptions thereof are omitted. [Comparative Example 3] A multilayer printed wiring board of Comparative Example 3 will be described. In the fifth embodiment described above, the BGA 76 is arranged in the region R2 above and outside the 1C wafer. In contrast, in Comparative Example 3, the BGA 76 is uniformly arranged on the solder photoresist layer as shown in FIG. 6 (C). In short, the area ri is no different from the area R2, and the BGA 76 is formed in a full grid shape on the entire surface of the solder resist layer. The multilayer printed wiring board of Example 5 and the multilayer printed wiring board of Comparative Example were each connected to an external substrate, and then the electrical connection was performed. The following items were evaluated. ① Whether there is crack or peeling after mounting with external substrate t② Whether there is no crack or peeling after mounting BGA ③ Whether there is crack or peeling after mounting with outer substrate after reliability test ④ Whether there is no BGA after reliability test or not ⑤ Measurement of contact resistance 546999 5. Description of the invention (87) In the multilayer printed wiring board of Example 5, suitable results were obtained, but in Comparative Example 3, cracks and peeling were found around the BGA. Also, an increase in contact resistance was confirmed. As shown in Figure 64, the same results were obtained when PGA was used instead of BGA. As in the fifth embodiment described above, a region on a substrate included in a semiconductor element of a multilayer printed wiring board is distinguished from a region on a substrate without a semiconductor element embedded therein. Therefore, external connection terminals (BGA / PGA) are provided on the substrates without built-in semiconductor elements. In short, by reducing the influence of thermal expansion in the non-internal domain, it is possible to prevent the occurrence of peeling and cracks in the periphery of the daughter (BG Gu) '. Therefore, the detachment of the π terminal (BGA / PGA) and the position deviation of the π terminal (BGA / PGA) depend on the external connection terminals. Improve electrical continuity and reliability

2160-3798-pf.ptd

Claims (1)

546999 Two '-Ά 90108562 This year and last month, the following month is said to be ^. Here, the patent application ^ --- Layer I A multilayer printed wiring board that repeatedly forms interlayer insulation ^ and conductor layers on the substrate. An interlayer window is formed on the interlayer insulating layer, and is electrically connected through the interlayer. The electronic component is embedded in the substrate, and the bump portion of the electric component forms an interlayer for interfacing with the lowest interlayer insulating layer. Window connected transition layer. 2 The multilayer printed wiring board according to item 1 of the scope of patent application, wherein the aforementioned substrate is a mounting substrate. "3 · The multilayer printed wiring board according to item 1 or 2 of the scope of patent application,-wherein the aforementioned transition layer is at least two or more layers. 4 · The multilayer printed wiring board according to item 2 of the scope of patent application, in which the ribs The lowest layer of the transition layer is a laminate of at least one or more members selected from the group consisting of tin, chromium, titanium, nickel, lead, cobalt, gold, and copper. 5. The multilayer printed wiring board according to item 4 of the scope of patent application, wherein The uppermost layer of the transition layer is a group selected from the group consisting of nickel, copper, gold, silver, lead, and iron. "6. A kind of semiconductor element, which is formed on the wafer of the semiconductor element." A transition layer is formed on the pad, and the transition layer is formed of a first thin film layer, a second thin film layer, and a thick additional layer. 7. The semiconductor device according to item 6 of the scope of patent application, wherein the first thin film layer of the aforementioned transition layer is at least one selected from the group consisting of tin, chromium, titanium, 8 · The semiconductor device according to item 6 or 7 of the scope of patent application, wherein the second thin film layer is selected from the group consisting of nickel, silver, lead, and iron. ^ 546999 VI. The scope of application for patents shall contain and store the child number 90sRft for 9 years or be buried as in the scope of application for patents 6, 7 or 8 -1-P: / 7 > 丄 上 », l > i ting m X The aforementioned semiconductor element is formed by: ;;;; solid: b, 7 or 8 items. 'The manufacturing method of forming a 1-layer semiconductor device by the step of adding layers on the provincial and physical components, at least through ⑷ ~ ⑴ and (a) forming wirings and grains on Japanese-Japanese chips; layers; (2) "The fully formed thin film forming portion on the wafer obtained in step (a) is formed to form a thick S :: layer i 'to form a photoresist layer, and the photoresist layer is peeled off (d) at the non- (d) portion of the photoresist layer; The thin film layer is removed by etching; and (:) 7 the aforementioned wafer is formed to form a semiconductor. 11. A semiconductor element, a semiconductor layer _ forming a transition layer: a w /, at least through (a) ~ (f) to form wiring, crystal Granules; (b) in the aforementioned (a) step a layer, the second thin film layer; and said that the first film (C) is formed on the entire surface of the film (C) in the aforementioned film > ^ ^, forming a thick additional layer; 'Forming a photoresist layer' and peeling off the photoresist layer in the non- (d) photoresist layer; the first thin film layer and the second thin film layer are described; and the wafer is formed by a single cutting operation to form a semiconductor element. Method to form a transition layer: by kaj Cf) and 546999 Case No. 901085fi? ^ VI. Patent application scope-u) Forming wiring and crystal grains on the wafer. It is described in step u) that a thin wafer (C) is formed on the wafer. A photoresist layer is formed on the entire, additional layer; the additional layer, π the thickness 3: a non- (e) stripped photoresist layer to remove the photoresist by etching; and " sub-additional layer; the aforementioned wafer is divided to form a semiconductor element. 13. A method of manufacturing a semiconductor device to form a transition layer: (a (a) forming wiring and die pads on a wafer; first film (b) on the wafer obtained in step (a) above) Full-layer, second thin-film layer; W chemical formation (c) on the other thin-film layer, a thick additional layer is formed on the whole, and a photoresist layer is formed on the additional layer; and the thick non-formed portion of the photoresist is removed by etching. The i-th and thick additional layers; the barrier film layer is peeled with (e) the photoresist layer; and (f) the aforementioned wafer is divided to form a semiconductor element. 14. The method for manufacturing a semiconductor device according to item 10 or 12 of the scope of patent application, wherein the thin film layer is formed by any of sputtering and vapor deposition. 0 1 5 · As item 11 or 13 of the scope of patent application In the method for manufacturing a semiconductor device, the first thin film layer is formed by any of sputtering and stripping. 2160-3798-pf2. Page 93 546999 ------ 篆 9090562 --_ year and month VI. Patent application scope 16. The method for manufacturing a semiconductor device according to item (1) or (13) of the scope of application for a patent, wherein the second thin film layer is formed by any one of sputtering and evaporation. 1 7 · The method for manufacturing a semiconductor device according to any one of claims i 0, Π, 12 or 13 in the scope of the patent application, wherein the thick additional layer is selected from the group consisting of nickel, copper, gold, silver, and lead , Iron Group. 1 8 · The method for manufacturing a semiconductor device according to item 10 or 12 of the scope of patent application, wherein the thin film layer is at least one selected from the group consisting of tin, aluminum, titanium, nickel, lead, cobalt, gold, and copper. Build up. • 19 · The method for manufacturing a semiconductor device according to item 11 or 13 of the scope of patent application ', wherein the first thin film layer is at least one selected from the group consisting of tin, aluminum, titanium, nickel, lead, cobalt, gold, and copper And laminated. , 2 0 · A multilayer printed wiring board, characterized in that the interlayer insulation layer and the conductor layer are repeatedly formed on the substrate, and are electrically connected through the interlayer window, which is ^ K-based; and is contained, stored or buried For semiconductor components, a metal or ceramic heat sink is arranged inside the aforementioned half-piece, and a die pad of a semiconductor component is provided with a _cross layer * ^ the aforementioned interlayer: then complex 2 ^. If the scope of patent application is the 20th The multilayer printed wiring board according to the item, wherein the bulk conductive element is used as described above via a conductive adhesive) 2) A method for manufacturing a multilayer printed wiring board, steps from (a) to (e): The following is to form a transition layer on the die pad of a semiconductor element; on /) Place the aforementioned semiconductor element on a metal or ceramic radiator 546999 ---- ^ i〇L〇8562_year month n amendment ... Fibre '-(C) A sheet having a through hole corresponding to the semiconductor element and a core material impregnated with uncured resin is placed on the heat sink; (d) the sheet is pressed to form a core substrate; and (e) ) A superimposed layer is formed on the core board. 23. · A method for manufacturing a multilayer printed wiring board, comprising at least the following steps (a) to (f): (a) forming a transition layer on a die pad of a semiconductor element; (b) forming a transition layer on a core substrate A plurality of through holes receiving a plurality of semiconductor elements; (c) Laminating the core substrate and resin plate containing the semiconductor element through the core material impregnated with a sheet of uncured resin; (d) Pressurizing the core substrate and resin plate; (e) Forming on the core machine plate Laminated layers; and (f) cutting the core substrate to obtain a single-piece multilayer printed wiring board. 2 4 · A method for manufacturing a multilayer printed wiring board, which has at least the following steps (a) to (f) ... (a) forming a transition layer on a die pad of a semiconductor element; (b) placing the aforementioned semiconductor element On radiators made of metal or talman; (c) a core material having a through hole corresponding to the semiconductor element and impregnated with an unhardened resin is placed on the heat sink; (d) the core sheet is pressed to form a core substrate; (e) the core substrate A laminated layer is formed thereon, and (f) a single-layer multilayer printed wiring board is obtained by cutting the core substrate. 2 5 · —A method for manufacturing a multilayer printed wiring board, which has at least the following 2160-3798-pf2.ptc Page 95 546999 A_E Amend the steps of (a) ~ (d) in the scope of patent application: C aj / any number of through-holes formed in the core substrate to accommodate multiple semiconductor elements; ( b) forming a transition layer on a die pad of a semiconductor element; (c) forming a laminated layer on the core substrate; and (d) cutting the core substrate to obtain a single-piece multilayer printed wiring board. 26. The method for manufacturing an evening-layer printed circuit wiring board according to any one of claims 23, 24, or 25, wherein the single-layer multilayer printed wiring board includes a plurality of semiconductor elements. 2 7 · —A method for manufacturing a multilayer printed wiring board, which has at least the following steps (a) to (f): (a) coating a sheet on the bottom of a through hole formed in a core substrate; ^ (b) in 蝻On the aforementioned sheet at the bottom of the through hole, a terminal is bonded to the aforementioned sheet to mount a semiconductor element forming a transition layer on the aforementioned terminal; (c) filling the via with a resin; (d) pressing and hardening the resin; (e) peeling the sheet; and (f) forming a laminated layer on the semiconductor element. 28 · —A method for manufacturing a multilayer printed wiring board, the steps of (a) to (i) are as follows: (a) A sheet is coated on the bottom of a through hole formed in a core substrate. On the aforementioned sheet at the bottom of the hole, the terminals are bonded; L is mounted with a semiconductor element forming a transition layer on another terminal; (c) the resin is filled in the aforementioned through hole; (i) the resin is pressurized and temporarily hardened; 2160-3798-pf2.ptc p. 96 546999 case number 90108562 6. Scope of patent application (e) Peel off the aforementioned sheet; (f) Polish the bottom side of the core substrate and expose the bottom; (g) Temporarily harden the aforementioned resin; Install a heat sink on the bottom of the aforementioned semiconductor element (h) Mount the aforementioned semiconductor A superposed layer is formed on the element. 2 9 · The method for manufacturing a multilayer printed wiring board according to item 27 or 28 of the patent application claim, wherein a UV adhesive tape for reducing adhesion by UV irradiation is used as the aforementioned sheet. 30. The method for manufacturing a multilayer printed wiring board according to any one of claims 27, 28, and 29, wherein the resin is pressurized under reduced pressure. 3 1 · The method for manufacturing a gas-multilayer printed wiring board according to item 30 of the scope of patent application ', wherein the aforementioned through hole formed on the aforementioned core substrate is provided with an adhesive tape. 3 2 · — A multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate on which a semiconductor element is embedded, accommodated, or housed, a via window is formed in the aforementioned interlayer insulating layer, and an electrical connection is made through the aforementioned interlayer window, Among them, external connection terminals are formed only in areas other than directly above the semiconductor elements in the Li substrate; in the pad portion of the 70 semiconductor devices described above, the aforementioned interlayer windows for forming the aforementioned interlayer insulating layer formed on the lowest layer are formed. Connected transition layer. 33. The multilayer printed wiring board according to Item 32 of the declared patent scope, wherein a resin filling material is filled between the recessed portion or through hole 'of the aforementioned substrate embedded in the valley or the semiconductor element and the rigid semiconductor element. Make the aforementioned semiconductor element and # 2160-3798-pf2.ptc Chapter 97