JP4248157B2 - Multilayer printed wiring board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention incorporates an electronic component such as an IC chip.multilayerIt also relates to printed wiring boards.
[0002]
[Prior art]
The IC chip has been electrically connected to the printed wiring board by a mounting method such as wire bonding, TAB, or flip chip.
In wire bonding, an IC chip is die-bonded to a printed wiring board with an adhesive, and the pad of the printed wiring board and the IC chip pad are connected with a wire such as a gold wire, and then the IC chip and the wire are protected. An encapsulating resin such as a thermosetting resin or a thermoplastic resin has been applied.
In TAB, the bumps of the IC chip and the pads of the printed wiring board are collectively connected with wires called leads by solder or the like, and then sealed with resin.
The flip chip is performed by connecting the IC chip and the pad portion of the printed wiring board via bumps and filling a resin in the gap between the bumps.
[0003]
[Problems to be solved by the invention]
However, in each mounting method, electrical connection is performed between the IC chip and the printed wiring board via connecting lead parts (wires, leads, bumps). Each of these lead parts is likely to be cut and corroded, which may cause the connection with the IC chip to be lost or cause a malfunction.
[0004]
The inventor has devised that the IC chip and the multilayer printed wiring board can be electrically connected without using lead parts by incorporating the IC chip in the multilayer printed wiring board. That is, an opening, a through-hole, or a counterbore is provided in a resin insulating substrate, an electronic component such as an IC chip is built in in advance, an interlayer insulating layer is laminated, and a photoetching or laser is applied on the pad of the IC chip. A structure was devised in which a via hole was provided to form a conductive circuit as a conductive layer, and then a multilayer printed wiring board was provided by repeating the interlayer insulating layer and the conductive layer.
[0005]
However, it has been clarified that in the structure incorporating the IC chip, the interlayer insulating layer disposed on the upper layer of the IC chip is peeled and cracked, and the reliability is lowered.
[0006]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multilayer print that can be directly electrically connected to an IC chip without a lead component and has high reliability. The purpose is to propose a wiring board.
[0007]
[Means for Solving the Problems]
It is clear that the above-mentioned peeling and cracking of the interlayer insulating layer are caused by the difference in thermal expansion between the IC chip made of silicon with a small coefficient of thermal expansion and other members made of resin with a large coefficient of thermal expansion. The specific response was unknown.
The inventor has the idea that stress caused by the difference in thermal expansion of the IC chip can be relieved by adjusting the elastic modulus of the filling resin when the IC chip is accommodated in the recess of the core substrate, and the durability test is performed. As a result, it was found that no peeling or cracking occurred in the interlayer insulating layer.
[0008]
The filled resin has an elastic modulus of 250 kgf / mm.²Hereinafter, more preferably 0.1 to 100 kgf / mm²By lowering to a minimum, the thermal expansion difference between the IC chip and the core substrate can be absorbed, and peeling of the interlayer insulating layer and generation of cracks can be prevented. The filling resin desirably contains an olefin resin. This is because an olefin resin has a low elastic modulus and can absorb a difference in thermal expansion.
[0009]
It is preferable to provide a transition layer on the pad of the IC chip. The reason for this is as follows. IC pad pads are generally made of aluminum or the like. When the via hole of the interlayer insulating layer was formed by photoetching with the die pad on which the transition layer was not formed, the resin was likely to remain on the surface layer of the pad after exposure and development if the die pad remained. Moreover, discoloration of the pad was caused by the adhesion of the developer. On the other hand, even when the via hole was formed by the laser, if the die pad was not burned out, a resin residue was generated on the pad. Further, when the substrate was immersed in an acid, an oxidant, or an etchant in the subsequent process, or after various annealing processes, discoloration and dissolution of the IC chip pad occurred. Further, the pads of the IC chip are made with a diameter of about 40 μm, and the via hole is larger than that, and therefore unconnected is likely to occur at the time of displacement.
[0010]
On the other hand, by providing a transition layer made of copper or the like on the die pad, it is possible to use a solvent and prevent resin residue on the pad. Further, even when the substrate is immersed in an acid, an oxidant, or an etching solution in the post-process, or through various annealing processes, the pad is not discolored or dissolved. This improves the connectivity and reliability between the pad and the via hole. Furthermore, via holes can be reliably connected by interposing a transition layer having a diameter larger than 40 μm on the pads of the IC chip. Desirably, the transition layer should be equal to or larger than the via hole diameter.
[0011]
Each of them may function only with a multilayer printed wiring board, but in some cases, in order to function as a package substrate as a semiconductor device, BGA, solder bump or PGA for connection with a mother board or daughter board as an external substrate (Conductive connection pins) may be provided. In addition, with this configuration, the wiring length can be shortened and the loop inductance can be reduced as compared with the case of connection by the conventional mounting method.
[0012]
As a resin-made substrate incorporating an electronic component such as an IC chip used in the present invention, epoxy resin, BT resin, phenol resin or the like impregnated with a reinforcing material such as glass epoxy resin or a core material, or an epoxy resin. A laminate of prepregs or the like is used, and those generally used for printed wiring boards can be used. In addition, a double-sided copper-clad laminate, a single-sided plate, a resin plate without a metal film, and a resin sheet can be used. However, if a temperature of 350 ° C. or higher is applied, the resin will dissolve and carbonize.
[0013]
An electronic component such as a core substrate or the like in which a cavity for accommodating an electronic component such as an IC chip is previously formed in a counterbore, a through hole, and an opening is bonded with an adhesive or the like. Physical vapor deposition such as vapor deposition and sputtering is performed on the entire surface of the core substrate incorporating the IC chip to form a conductive metal film on the entire surface. As the metal, one that forms one or more layers of metals such as tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferable. As thickness, it is good to form between 0.001-2.0 micrometers. In particular, a thickness of 0.01 to 1.0 μm is desirable. In particular, it is good to form with nickel, chromium, and titanium. This is because moisture does not enter from the interface and the metal adhesion is excellent.
[0014]
The metal film is thickened by electroless or electrolytic plating. The types of plating formed include copper, nickel, gold, silver, zinc, and iron. Since the conductor layer, which is a build-up formed later, is mainly copper, it is preferable to use copper. The thickness is preferably in the range of 1 to 20 μm. If it is thicker, undercutting may occur during etching, and a gap may be generated at the interface between the formed transition layer and via hole. Thereafter, an etching resist is formed, exposed and developed to expose portions of the metal other than the transition layer, and etched to form a transition layer on the pad of the IC chip.
[0015]
The transition layer defined in the present invention will be described.
The transition layer means an intermediate intermediary layer provided to directly connect an IC chip as a semiconductor element and a printed wiring board without using a conventional IC chip mounting technique. A feature is that it is formed of two or more metal layers and is larger than a die pad of an IC chip which is a semiconductor element. This improves electrical connection and alignment, and enables via hole processing by laser or photoetching without damaging the die pad. For this reason, the IC chip can be securely embedded, accommodated, accommodated, and connected to the printed wiring board. Further, it is possible to directly form a metal which is a conductor layer of the printed wiring board on the transition layer. Examples of the conductor layer include a via hole in an interlayer resin insulating layer and a through hole on a substrate.
[0016]
In addition to the above method of manufacturing the transition layer, a dry film resist is formed on the metal film formed on the IC chip and the core substrate, and the portion corresponding to the transition layer is removed and thickened by electrolytic plating. Thereafter, the resist is peeled off, and a transition layer can be similarly formed on the pad of the IC chip by an etching solution.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the multilayer printed wiring board according to the first embodiment of the present invention will be described with reference to FIG. 7 showing a cross section of the multilayer printed wiring board 10.
[0018]
As shown in FIG. 7, the multilayer printed wiring board 10 includes a core substrate 30 that houses the IC chip 20, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150. Via hole 60 and conductor circuit 58 are formed in interlayer resin insulation layer 50, and via hole 160 and conductor circuit 158 are formed in interlayer resin insulation layer 150.
[0019]
The IC chip 20 is covered with a passivation film 24, and a die pad 22 constituting an input / output terminal is disposed in the opening of the passivation film 24. A transition layer 38 mainly made of copper is formed on the pad 22.
[0020]
A solder resist layer 70 is disposed on the interlayer resin insulating layer 150. The conductor circuit 158 under the opening 71 of the solder resist layer 70 is provided with solder bumps 76 for connection to an external substrate (not shown) such as a daughter board or a mother board.
[0021]
In the multilayer printed wiring board 10 of the first embodiment, the IC chip 20 is built in the core substrate 30 in advance, and the transition layer 38 is disposed on the pad 22 of the IC chip 20. For this reason, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using lead parts or sealing resin.
[0022]
The IC chip 20 is accommodated in a recess 32 formed in the core substrate 30 via a filling resin 34. Filling resin 34 has an elastic modulus of 100 kgf / mm.²It is set as follows. In the first embodiment, by reducing the elastic modulus of the filling resin 34, the stress caused by the difference in thermal expansion between the IC chip 20 and the core substrate 30 is alleviated, and the interlayer resin insulation layer 50 is separated and cracks are generated. prevent.
[0023]
In the multilayer printed wiring board of the first embodiment, the IC chip 20 has a coefficient of thermal expansion (CTE) of 3.5 ppm, and the core substrate 30 having a glass cloth as a core material has a coefficient of thermal expansion (CTE) of 15 ppm. In the first embodiment, the thermal expansion coefficient (CTE) of the filling resin 34 is adjusted so that the difference from the thermal expansion coefficient (CTE) of the core substrate 30 is 55 ppm or less, which is 40 or less. That is, by reducing the thermal expansion coefficient of the filling resin 34 and bringing it closer to the core substrate 30 having a relatively small thermal expansion coefficient using a glass cloth as a core material, it is generated between the IC chip 20 and the core substrate 30 due to a difference in thermal expansion. The stress to be absorbed is absorbed by the filling resin 34 to affect the thin and fragile interlayer resin insulation layer 50 without having a core material, thereby preventing peeling and cracking.
[0024]
In the multilayer printed wiring board 10 according to the first embodiment, the thickness H of the built-in IC chip 20 is set to 50 to 250 μm. That is, while the existing IC chip has a thickness of about 700 μm, in the first embodiment, the thickness direction of the IC chip 20, the interlayer resin insulating layer 50, and the core substrate 30 is less than half of the thickness of less than 250 μm. The difference in the amount of thermal expansion is reduced, and the interlayer resin insulation layer 50 is prevented from peeling and cracking.
[0025]
As described above, the IC chip 20 has a coefficient of thermal expansion (CTE) of 3.5 ppm, the interlayer resin insulation layer 50 having a configuration described later has a coefficient of thermal expansion (CTE) of 80 ppm, and the core substrate 30 having a glass cloth as a core material has a coefficient of thermal expansion ( CTE) 15 ppm. Since the thermal expansion coefficient of the interlayer resin insulation layer 50 greatly exceeds the thermal expansion coefficient of the IC chip 20, stress that cannot be absorbed in the heat cycle causes peeling of the interlayer resin insulation layer 50 and generation of cracks. For this reason, in the first embodiment, by reducing the thickness of the IC chip 20 as described above, the difference in thermal expansion amounts of the IC chip, the interlayer resin insulating layer, and the core substrate in the thickness direction of the IC chip is reduced. Further, peeling of the interlayer resin insulation layer 50 and generation of cracks are prevented.
[0026]
If the thickness of the IC chip 20 exceeds 250 μm, peeling and cracking occur in the interlayer resin insulation layer 50, while if it is less than 50 μm, it is difficult to manufacture the IC chip and the IC chip itself is broken during handling. There are things to do. Here, it is particularly desirable that the IC chip has a thickness of 100 to 200 μm. By setting the thickness to 200 μm or less, peeling and cracking in the interlayer resin insulating layer 50 can be completely prevented, and by setting the thickness to 100 μm or more, manufacturing is facilitated and the IC chip is not broken.
[0027]
A plan view of the IC chip 20 incorporated in the multilayer printed wiring board 10 is shown in FIG. 1 (B), and a side view thereof is shown in FIG. 1 (C). The corners 20a on the four sides of the IC chip 20 may be chamfered and formed in a semicircular shape. By cutting off the corners, it is difficult to crack the thin IC chip. Further, by chamfering, stress is not concentrated on the corner portion 20a of the IC chip 20 even when the multilayer printed wiring board 10 is subjected to a heat cycle. Therefore, in the vicinity of the corner portion 20a, the core substrate 30 and the interlayer resin insulation layer 50, the IC chip and the interlayer resin insulation layer 50 are prevented from peeling off, and the generation of cracks in the interlayer resin insulation layer 50 is prevented. The reliability of the plate 10 can be improved.
[0028]
In the multilayer printed wiring board of the first embodiment, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened. Therefore, the upper interlayer insulating layer 50 is also flattened to form a film. The thickness is also uniform. Furthermore, the shape stability can be maintained even when the upper via hole 60 is formed by the transition layer.
[0029]
Furthermore, by providing the copper transition layer 38 on the die pad 22, it is possible to prevent the resin residue on the pad 22 from being immersed in an acid, an oxidant, or an etching solution in various subsequent processes, and various annealing. Even after the process, discoloration and dissolution of the pad 22 do not occur. This improves the connectivity and reliability between the IC chip pads and via holes. Furthermore, a via hole having a diameter of 60 μm can be reliably connected by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm.
[0030]
Next, a method for manufacturing the multilayer printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.
[0031]
(1) First, the multi-chip IC chip shown in FIG. 1 (A) is cut into individual pieces by dicing as shown in FIG. 1 (B), and the corner portion 20a is chamfered into a semicircular shape by polishing. .
(2) On the other hand, an insulating resin substrate (core substrate) 30 in which a prepreg in which a core material such as glass cloth is impregnated with a resin such as epoxy is laminated is prepared as a starting material (see FIG. 2A). Next, a recess 32 for accommodating an IC chip is formed on one surface of the core substrate 30 by counterboring (see FIG. 2B). Here, the concave portion is provided by counterbore processing, but a core substrate including an accommodation portion can be formed by bonding an insulating resin substrate provided with an opening and a resin insulating substrate not provided with an opening.
[0032]
(3) Thereafter, the filling resin 34 is applied to the recesses 32 using a printing machine. At this time, potting or the like may be performed in addition to the application. Next, the IC chip 20 is placed on the filling resin 34 (see FIG. 2C).
[0033]
As described above, the filling resin 34 has an elastic modulus of 100 kgf / mm.²It is set as follows. By lowering the elastic modulus, the filling resin 34 relieves the stress caused by the difference in thermal expansion between the IC chip 20 and the core substrate 30 and prevents the interlayer resin insulating layer 50 from peeling and cracking. The filling resin 34 desirably contains an olefin resin. This is because an olefin resin has a low elastic modulus and can absorb a difference in thermal expansion. Here, an olefin resin is used, but a polyimide resin and an epoxy resin are combined, and the elastic modulus is 250 kgf / mm.²By setting to the following, peeling of the interlayer resin insulation layer 50 and generation of cracks can be prevented. As the filling resin, a thermosetting resin, a thermoplastic resin, or a composite thereof can be used.
[0034]
The filling resin 34 is adjusted to have a thermal expansion coefficient of 55 ppm or less so that the difference from the thermal expansion coefficient (15 ppm) of the core substrate 30 is 40 ppm or less. For this reason, the thermal expansion coefficient is adjusted by including at least one of inorganic particles, metal particles, and resin particles in the resin in an amount of 10 wt% or more. Note that when the amount of particles increases, the adhesive strength decreases, and the role as a filler is not achieved, and the brittleness increases and the filling resin 34 is easily cracked. Therefore, the amount is suppressed to 80 wt% or less.
[0035]
(4) Then, the upper surface of the IC chip 20 is pushed or hit to be completely accommodated in the recess 32 (see FIG. 2D). Thereby, the core substrate 30 can be smoothed.
[0036]
(5) After that, physical vapor deposition such as vapor deposition and sputtering is performed on the entire surface of the core substrate 30 in which the IC chip 20 is accommodated, and a conductive metal film 33 is formed on the entire surface (FIG. 3A). As the metal, one that forms one or more layers of metals such as tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferable. The thickness is preferably between 0.001 and 2 μm. In particular, 0.01 to 1.0 μm is desirable.
[0037]
A plating film 36 may be formed on the metal film 33 by electroless plating (FIG. 3B). The types of plating formed include copper, nickel, gold, silver, zinc, and iron. Since the conductor layer, which is a build-up formed later, is mainly copper, it is preferable to use copper. The thickness is preferably in the range of 1 to 20 μm.
[0038]
In the configuration of the present embodiment, the transition layer 38 has a two-layer structure including a metal layer (first thin film layer) 33 and an electrolytic plating film 36. However, the transition layer is a thin film layer (first thin film layer). And a three-layer structure comprising an electroless plating film (second thin film layer) and an electrolytic plating film (thickening layer). In the case of a three-layer structure, the second thin film layer is laminated on the first thin film layer 33 by sputtering, vapor deposition, or electroless plating. The thickness is preferably 0.01 to 5 μm, and particularly preferably 0.1 to 3.0 μm. In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver.
[0039]
(6) Thereafter, a resist is applied, exposed and developed to provide a plating resist 35 so as to provide an opening above the pad of the IC chip, and electroless plating is performed to provide an electroless plating film 37 (FIG. 3 ( C)). After removing the plating resist 35, the electroless plating film 36 and the metal film 33 under the plating resist 35 are removed, thereby forming a transition layer 38 on the pad 22 of the IC chip (FIG. 3D). Here, the transition layer is formed of a plating resist. However, after the electrolytic plating film is uniformly formed on the electroless plating film 36, an etching resist is formed, exposed and developed, and the metal other than the transition layer is formed. It is also possible to form a transition layer on the pad of the IC chip by exposing and etching. In this case, the thickness of the electrolytic plating film is preferably in the range of 1 to 20 μm. If it is thicker, undercutting occurs during etching, and a gap may be generated at the interface between the formed transition layer and via hole.
Desirable combinations are chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel.
It is superior to other combinations in terms of metal bondability and electrical conductivity.
[0040]
(7) Next, an etching solution is sprayed on the substrate to etch the surface of the transition layer 38 to form a roughened surface 38α (see FIG. 4A). The roughened surface can also be formed using electroless plating or oxidation-reduction treatment.
[0041]
(8) A pressure of 5 kg / cm while heating a thermosetting resin sheet having a thickness of 50 μm to a temperature of 50 to 150 ° C. on the substrate subjected to the above steps.²Then, an interlayer resin insulation layer 50 is provided by vacuum compression lamination (see FIG. 4B). The degree of vacuum at the time of vacuum bonding is 10 mmHg.
[0042]
(9) Next, CO with a wavelength of 10.4 μm₂A via hole opening 48 having a diameter of 80 μm is provided in the interlayer resin insulating layer 50 with a gas laser under conditions of a beam diameter of 5 mm, a top hat mode, a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot ( (See FIG. 4C). The residual resin in the opening 48 is removed using chromic acid. By providing the copper transition layer 38 on the die pad 22, it is possible to prevent the resin residue on the pad 22, thereby improving the connectivity and reliability between the pad 22 and a via hole 60 described later. Further, by providing the transition layer 38 having a diameter of 60 μm or more on the 40 μm diameter pad 22, the via hole opening 48 having a diameter of 60 μm can be reliably connected. Although the resin residue is removed here using chromic acid, desmear treatment can also be performed using oxygen plasma.
[0043]
(10) Next, the roughened surface 50α of the interlayer resin insulation layer 50 is provided by dipping in an oxidizing agent such as chromic acid or permanganate (see FIG. 4D). The roughened surface 50α is preferably formed in the range of 0.1 to 5 μm. As an example, a roughened surface 50α of 2 to 3 μm is provided by dipping in a sodium permanganate solution 50 g / l at a temperature of 60 ° C. for 5 to 25 minutes. In addition to the above, the roughened surface 50α can be formed on the surface of the interlayer resin insulation layer 50 by performing plasma treatment using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. At this time, argon gas is used as the inert gas, and plasma treatment is performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C.
[0044]
(9) A metal layer 52 is provided on the interlayer resin insulating layer 50 on which the roughened surface 50α is formed (see FIG. 5A). The metal layer 52 is formed by electroless plating. A metal layer 52 that is a plating film is provided in the range of 0.1 to 5 μm by preliminarily applying a catalyst such as palladium to the surface layer of the interlayer resin insulation layer 50 and immersing it in an electroless plating solution for 5 to 60 minutes. As an example,
[Electroless plating aqueous solution]
NiSO_Four                  0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
It was immersed for 40 minutes at a liquid temperature of 34 ° C.
Other than the above, using the same apparatus as the plasma treatment described above, after replacing the argon gas inside, sputtering with Ni and Cu as targets was performed under conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, time 5 minutes. The Ni / Cu metal layer 52 can also be formed on the surface of the interlayer resin insulation layer 50. At this time, the thickness of the formed Ni / Cu metal layer 52 is 0.2 μm.
[0045]
(12) A commercially available photosensitive dry film is pasted on the substrate 30 that has been subjected to the above-described treatment, and a photomask film is placed thereon, and 100 mJ / cm.²After the exposure, the development process is performed with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 5B). The additive in the electrolytic plating aqueous solution is Kaparaside HL manufactured by Atotech Japan.
[0046]
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive (manufactured by Atotech Japan, Kaparaside HL)
19.5 ml / l
[Electrolytic plating conditions]
Current density 1A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0047]
(13) After stripping and removing the plating resist 54 with 5% NaOH, the metal layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 52 and the electrolytic plating are removed. A conductor circuit 58 and a via hole 60 having a thickness of 16 μm formed of the film 56 are formed, and roughened surfaces 58α and 60α are formed by an etching solution containing a cupric complex and an organic acid (see FIG. 5C). ).
[0048]
(14) Next, the above steps (8) to (13) are repeated to further form the upper interlayer resin insulation layer 150 and the conductor circuit 158 (including the via hole 160) (see FIG. 6A). ).
[0049]
(15) Next, the photosensitizing property obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd.) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 A weight part is put into a container, and a mixed composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator and Michler's ketone as a photosensitizer for the mixed composition. (Kanto Chemical Co., Ltd.) 0.2 part by weight is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured with a B type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3. In addition, a commercially available solder resist can also be used as a solder resist.
[0050]
(16) Next, the solder resist composition is applied to the substrate 30 to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the solder resist resist opening is formed. A photomask having a thickness of 5 mm on which a pattern of 10 mm is drawn is brought into close contact with the solder resist layer 70 to 1000 mJ / cm²Then, an opening 71 having a diameter of 200 μm is formed (see FIG. 6B).
[0051]
(17) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 was formed was treated with nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphate (2.8 × 10 6)^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1mol / l) is immersed in an electroless plating solution at 80 ° C. for 7.5 minutes to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72. Solder pads 75 are formed (see FIG. 6C).
[0052]
(18) Thereafter, a solder paste is printed on the opening 71 of the solder resist layer 70 and reflowed at 200 ° C. to form solder bumps 76. As a result, it is possible to obtain the multilayer printed wiring board 10 including the IC chip 20 and having the solder bumps 76 (see FIG. 7).
[0053]
In the above-described embodiment, thermosetting resin sheets are used for the interlayer resin insulation layers 50 and 150. This thermosetting resin sheet resin contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.
[0054]
The thermosetting resin sheet used in the manufacturing method of the first embodiment is a resin in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are hardly soluble in an acid or oxidizing agent (hereinafter referred to as a hardly soluble resin). It is dispersed inside.
Note that the terms “sparingly soluble” and “soluble” used in the first embodiment are “soluble” for convenience in terms of relatively fast dissolution rates when immersed in a solution comprising the same acid or oxidizing agent for the same time. A material having a relatively low dissolution rate is referred to as “slightly soluble” for convenience.
[0055]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0056]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0057]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the first embodiment, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0058]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. And it may consist of a mixture of two or more kinds of resins.
[0059]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified and other modified polybutadiene rubbers, carboxyl group-containing (meth) acrylonitrile / butadiene rubbers, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0060]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0061]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate and the like. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0062]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0063]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin sheet can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack is generated in the interlayer resin insulation layer made of the resin sheet. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.
[0064]
The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via hole opening can be formed in the interlayer resin insulating layer by exposure and development.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0065]
Specific examples of the hardly soluble resin include, for example, epoxy resins, phenol resins, phenoxy resins, polyimide resins, polyphenylene resins, polyolefin resins, fluororesins and the like. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0066]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0067]
In the resin sheet used in the first embodiment, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface having unevenness with a uniform roughness can be formed, and even if a via hole or a through hole is formed in a resin sheet, the adhesion of the metal layer of the conductor circuit formed thereon can be secured. Because it can. Moreover, you may use the resin sheet which contains a soluble particle only in the surface layer part which forms a roughening surface. Thereby, since the portions other than the surface layer portion of the resin sheet are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits through the interlayer resin insulating layer is reliably maintained.
[0068]
In the resin sheet, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin sheet. If the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. If the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin sheet is melted to the deep part of the resin sheet, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin sheet cannot be maintained, which may cause a short circuit.
[0069]
The resin sheet preferably contains a curing agent, other components, etc. in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0070]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin sheet. If it is less than 0.05% by weight, the resin sheet is not sufficiently cured, so that the degree of penetration of acid or oxidant into the resin sheet increases, and the insulation of the resin sheet may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0071]
Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, dolomite, and the like. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By including these fillers, it is possible to improve the performance of the multilayer printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0072]
Moreover, the said resin sheet may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers melt and carbonize when a temperature of 350 ° C. or higher is applied.
[0073]
Next, a multilayer printed wiring board according to a first modification of the first embodiment will be described with reference to FIG. In 1st Embodiment mentioned above, the case where BGA was arrange | positioned demonstrated. The first modified example is substantially the same as that of the first embodiment, but is configured in a PGA system in which connection is established via conductive connection pins 96 as shown in FIG.
[0074]
Next, a multilayer printed wiring board according to a second modification of the first embodiment will be described with reference to FIG.
In the first embodiment described above, the IC chip is accommodated in the recess 32 provided in the core substrate 30 with counterbore. On the other hand, in the second modified example, the IC chip 20 is accommodated in the through hole 32 formed in the core substrate 30. In the second modified example, since the heat sink can be directly attached to the back side of the IC chip 20, there is an advantage that the IC chip 20 can be efficiently cooled.
[0075]
In the second modification, the IC chip 20 is accommodated in the through hole 32 formed in the core substrate 30 via the filling resin 34. Here, the filling resin 34 has an elastic modulus of 100 kgf / mm as in the first embodiment.²It is set as follows. By lowering the elastic modulus, the filling resin 34 relieves the stress caused by the difference in thermal expansion between the IC chip 20 and the core substrate 30 and prevents the interlayer resin insulating layer 50 from peeling and cracking.
[0076]
Next, a multilayer printed wiring board according to a third modification of the first embodiment will be described with reference to FIG.
In the first embodiment described above, the transition layer 38 is formed on the pad 22 of the IC chip 20, and the via hole 60 of the interlayer resin insulating layer 50 is connected to the transition layer 38. On the other hand, in the third modified example, the via hole 60 is directly connected to the pad 22 without providing a transition layer. Since this third modified example can reduce the number of steps compared to the first embodiment, there is an advantage that it can be configured at a low cost.
[0077]
Next, a multilayer printed wiring board according to a fourth modification of the first embodiment will be described with reference to FIG.
In the first embodiment described above, the IC chip is accommodated in the multilayer printed wiring board. On the other hand, in the fourth modified example, the IC chip 20 is accommodated in the multilayer printed wiring board, and the IC chip 120 is placed on the surface. As the built-in IC chip 20, a cache memory having a relatively small calorific value is used, and as the IC chip 120 on the surface, an arithmetic CPU is mounted.
[0078]
The pads 22 of the IC chip 20 and the pads 124 of the IC chip 120 are connected via a transition layer 38 -via hole 60 -conductor circuit 58 -via hole 160 -conductor circuit 158 -solder bump 76U. On the other hand, the pad 124 of the IC chip 120 and the pad 92 of the daughter board 90 are composed of the solder bump 76U-conductor circuit 158-via hole 160-conductor circuit 58-via hole 60-through hole 136-via hole 60-conductor circuit 58-. Via hole 160 is connected to conductor circuit 158 via solder bump 76U.
[0079]
In the fourth modified example, it is possible to arrange the IC chip 120 and the cache memory 20 close to each other while manufacturing the cache memory 20 having a low yield separately from the IC chip 120 for the CPU. Is possible. In the fourth modified example, by incorporating an IC chip and placing it on the surface, it is possible to mount electronic components such as IC chips having different functions, and to obtain a higher-performance multilayer printed wiring board. Can do.
[0080]
[First comparative example]
As a first comparative example, a multilayer printed wiring board was formed in the same manner as in the first embodiment. However, the elastic modulus of the filling resin 34 is 300 kgf / mm.²Set to.
[0081]
[Second comparative example]
As a second comparative example, a multilayer printed wiring board was formed in the same manner as the second modified example. However, the elastic modulus of the filling resin 34 is 300 kgf / mm.²Set to.
[0082]
Existence of peeling of interlayer resin insulation layer and occurrence of cracks after heat cycle of multilayer printed wiring board of first embodiment and second modified example and multilayer printed wiring boards of first and second comparative examples The results of the evaluation are shown in the chart of FIG. In the first embodiment and the second modified example, peeling and cracks were not generated in the interlayer resin insulating layer, and no crack was generated in the filling resin. In the first and second comparative examples, peeling and cracks were generated in the interlayer resin insulating layer. Occurred.
[0083]
【The invention's effect】
As described above, in the present invention, in a printed wiring board in which an IC chip is accommodated in a through hole or a recess formed in a core substrate, the elastic modulus of the filling resin interposed between the through hole or the recess and the IC chip. 250Kgf / mm²By lowering to the following, it is possible to absorb the difference in thermal expansion between the IC chip and the core substrate, and to prevent peeling of the interlayer insulating layer and generation of cracks.
[Brief description of the drawings]
FIG. 1A is a plan view of a multi-chip IC chip before cutting, FIG. 1B is a plan view of a chamfered IC chip, and FIG. It is a side view of B).
FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention. FIGS.
3A, 3B, 3C, and 3D are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention.
4A, 4B, 4C, and 4D are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention.
5A, 5B, and 5C are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention.
6A, 6B, and 6C are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention.
FIG. 7 is a sectional view of the multilayer printed wiring board according to the first embodiment.
FIG. 8 is a cross-sectional view of a multilayer printed wiring board according to a first modification of the first embodiment of the first embodiment.
FIG. 9 is a cross-sectional view of a multilayer printed wiring board according to a second modification of the first embodiment.
FIG. 10 is a cross-sectional view of a multilayer printed wiring board according to a third modification of the first embodiment.
FIG. 11 is a cross-sectional view of a multilayer printed wiring board according to a fourth modification of the first embodiment.
FIG. 12 is a chart showing evaluation results of the first embodiment, the second modified example, and the comparative example.
[Explanation of symbols]
20 IC chip
20a Corner
22 pads
24 Passivation film
30 core substrate
30D heat sink
32 recess
34 Filling resin
36 Resin layer
38 Transition layer
50 Interlayer resin insulation layer
58 Conductor circuit
60 Bahia Hall
70 Solder resist layer
76 Solder bump
90 daughter board
96 Conductive connection pins
97 Conductive adhesive
150 Interlayer resin insulation layer
158 Conductor circuit
160 Viahole

Claims (6)

An interlayer insulating layer and a conductor layer are repeatedly formed on a substrate containing an IC chip in a through hole or a recess, and a via hole is formed in the interlayer insulating layer, and the pad of the IC chip and the conductor layer are formed. In a multilayer printed wiring board electrically connected through the via hole,
A multilayer printed wiring board, wherein an elastic modulus of a filling resin interposed between the through hole or recess and the IC chip is 250 kgf / mm ² or less. ^2. The multilayer printed wiring board according to claim 1, wherein the elastic modulus of the filled resin is 0.1 to 100 kgf / mm < ² >. The multilayer printed wiring board according to claim 1, wherein the filling resin contains an olefin-based resin. 4. The multilayer print according to claim 1, wherein an intermediary layer is formed on the pad of the IC chip, and the pad and the via hole are connected via the intermediary layer. Wiring board. The multilayer printed wiring board according to claim 4, wherein a diameter of the intermediate layer is larger than a diameter of the pad. 6. The multilayer printed wiring board according to claim 1, wherein a surface of the via hole opening reaching the pad is roughened.

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