JP4931283B2 - Printed wiring board and printed wiring board manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention particularly relates to a semiconductor element such as an IC chip.TheBuilt-in multilayerPrinted wiring board and theThe present invention also relates to a method for manufacturing a printed wiring board.
[0002]
[Prior art]
The IC chip has been electrically connected to the printed wiring board by a mounting method such as wire bonding, TAB, or flip chip.
In wire bonding, an IC chip is die-bonded to a printed wiring board with an adhesive, and the pad of the printed wiring board and the IC chip pad are connected with a wire such as a gold wire, and then the IC chip and the wire are protected. An encapsulating resin such as a thermosetting resin or a thermoplastic resin has been applied.
[0003]
In TAB, the bumps of the IC chip and the pads of the printed wiring board are collectively connected with wires called leads by solder or the like, and then sealed with resin.
The flip chip is performed by connecting the IC chip and the pad portion of the printed wiring board via bumps and filling a resin in the gap between the bumps.
[0004]
However, in each mounting method, electrical connection is performed between the IC chip and the printed wiring board via connecting lead parts (wires, leads, bumps). Each of these lead parts is likely to be cut and corroded, which may cause the connection with the IC chip to be lost or cause a malfunction.
In addition, each mounting method is sealed with a thermoplastic resin such as an epoxy resin to protect the IC chip, but if bubbles are included when filling the resin, the bubbles become the starting point, Lead components are destroyed, IC pads are corroded, and reliability is reduced. For sealing with thermoplastic resin, it is necessary to create a plunger and mold for resin loading according to each part. In addition, even for thermosetting resin, the materials such as lead parts and solder resist are considered. Since it was necessary to select the resin, it was also a cause of high cost in each.
[0005]
On the other hand, instead of attaching an IC chip to the outside of a printed wiring board (package substrate) as described above, a conventional semiconductor device is embedded in a substrate, and a buildup layer is formed on the upper layer to establish electrical connection. As a technique, Japanese Patent Laid-Open No. 9-321408 (USP 5875100), Japanese Patent Laid-Open No. 10-256429, Japanese Patent Laid-Open No. 11-126978, and the like have been proposed.
[0006]
In JP-A-9-321408 (US Pat. No. 5,875,100), a semiconductor element in which stud bumps are formed on a die pad is embedded in a printed wiring board, and wiring is formed on the stud bumps for electrical connection. However, since the stud bump is onion-like and has a large variation in height, when the interlayer insulating layer is formed, the smoothness is lowered, and even if a via hole is formed, it is easily disconnected. In addition, stud bumps are planted one by one by bonding, and cannot be arranged in a lump, and there is a problem in terms of productivity.
[0007]
Japanese Patent Application Laid-Open No. 10-256429 shows a structure in which a semiconductor element is accommodated in a ceramic substrate and electrically connected in a flip chip form. However, ceramics have poor outer formability and do not fit in semiconductor elements. In addition, the bumps also had large height variations. For this reason, the smoothness of the interlayer insulating layer is impaired, and the connection is lowered.
[0008]
Japanese Patent Application Laid-Open No. 11-126978 discloses a multilayer printed wiring board in which an electronic component such as a semiconductor element is embedded in a space accommodating portion, connected to a conductor circuit, and stored via a via hole. However, since the accommodating portion is a gap, misalignment is likely to occur, and disconnection from the pads of the semiconductor element is likely to occur. Further, since the die pad and the conductor circuit are directly connected, there is a problem that an oxide film is easily formed on the die pad and the insulation resistance is increased.
[0009]
[Problems to be solved by the invention]
  The present invention has been made to solve the above-described problems, and the object of the present invention is to be able to directly connect to a printed wiring board without using a lead component.RuPrinted wiring board with built-in semiconductor elementsAnd printed wiring boardIt aims at proposing the manufacturing method of this.
[0010]
[Means for Solving the Problems]
As a result of diligent research, the present inventor has created that a transition layer is formed on a die pad of a semiconductor element. A semiconductor element having the transition layer can be obtained in a desired size or shape even if embedded in a printed wiring board, housed, or accommodated, or an interlayer insulating layer is formed thereon to form a via hole. It is done.
[0011]
The reason why the transition layer is provided on the die pad of the IC chip will be described. The die pad of the IC chip is generally made of aluminum or the like. When the via hole of the interlayer insulating layer was formed by photoetching with the die pad on which the transition layer was not formed, the resin was likely to remain on the surface layer of the pad after exposure and development if the die pad remained. Moreover, discoloration of the pad was caused by the adhesion of the developer. On the other hand, when a via hole is formed by a laser, there is a risk of burning the aluminum pad. Moreover, when it performed on the conditions which do not burn out, the resin residue generate | occur | produced on the pad. Further, when the substrate was immersed in an acid, an oxidant, or an etchant in the subsequent process, or after various annealing processes, discoloration and dissolution of the IC chip pad occurred. Furthermore, the pads of the IC chip are made with a diameter of about 40 μm, and the via hole is larger than that, and a positional tolerance is required. Therefore, misalignment or the like easily occurs.
[0012]
On the other hand, by providing a transition layer made of copper or the like on the die pad, the inconvenience of forming the via hole can be solved, and the use of a solvent can be achieved, so that the resin residue on the pad can be prevented. Further, even when the substrate is immersed in an acid, an oxidant, or an etching solution in the post-process, or through various annealing processes, the pad is not discolored or dissolved. This improves the connectivity and reliability between the pad and the via hole. Furthermore, via holes can be reliably connected by interposing a transition layer having a larger diameter than that on the die pad of the IC chip. Desirably, the transition layer should be equal to or greater than the via hole diameter and position tolerance.
[0013]
Furthermore, since the transition layer is formed, the semiconductor device can be easily operated and electrically inspected before or after the IC chip, which is a semiconductor device, is embedded in the printed wiring board. . This is because the inspection probe pin is easily contacted because a transition layer larger than the die pad is formed. As a result, whether or not the product is available can be determined in advance, and productivity and cost can be improved. In addition, the pad is not lost or scratched by the probe.
[0014]
Therefore, by forming the transition, it is possible to suitably embed, house, and house the IC chip, which is a semiconductor element, in the printed wiring. That is, it can be said that a semiconductor element having a transition layer is a semiconductor element for embedding, accommodating, and accommodating a printed wiring board.
The transition layer is formed by forming a thin film layer on a die pad and forming a thickening layer thereon. It can be formed of at least two layers.
[0015]
Each of them may function only with a multilayer printed wiring board, but in some cases, in order to function as a package substrate as a semiconductor device, BGA, solder bump or PGA for connection with a mother board or daughter board as an external substrate (Conductive connection pins) may be provided. In addition, with this configuration, the wiring length can be shortened and the loop inductance can be reduced as compared with the case of connection by the conventional mounting method.
[0016]
The transition layer defined in the present invention will be described.
The transition layer means an intermediate intermediate layer provided to directly connect an IC chip as a semiconductor element and a printed wiring board without using a conventional IC chip mounting technique. As its feature, it is formed of two or more metal layers. Or it is to make it larger than the die pad of the IC chip which is a semiconductor element. This improves electrical connection and alignment, and enables via hole processing by laser or photoetching without damaging the die pad. Therefore, the IC chip can be securely embedded, accommodated, accommodated and connected to the printed wiring board. Further, it is possible to directly form a metal which is a conductor layer of the printed wiring board on the transition layer. Examples of the conductor layer include a via hole in an interlayer resin insulating layer and a through hole on a substrate.
[0017]
As a resin-made substrate incorporating an electronic component such as an IC chip used in the present invention, epoxy resin, BT resin, phenol resin or the like impregnated with a reinforcing material such as glass epoxy resin or a core material, or an epoxy resin. A laminate of prepregs or the like is used, and those generally used for printed wiring boards can be used. In addition, a double-sided copper-clad laminate, a single-sided plate, a resin plate without a metal film, and a resin film can be used. However, if a temperature of 350 ° C. or higher is applied, the resin will dissolve and carbonize.
[0018]
Physical vapor deposition such as vapor deposition and sputtering is performed on the entire surface of the IC chip to form a conductive metal film on the entire surface. As the metal, one that forms one or more layers of metals such as tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferable. As thickness, it is good to form between 0.001-2.0 micrometers. In particular, 0.01 to 1.0 μm is desirable.
[0019]
A metal film can be further provided on the metal film by electroless plating or the like. The upper metal film preferably has one or more layers of metals such as nickel, copper, gold, and silver. The thickness is preferably 0.01 to 5 μm, and particularly preferably 0.1 to 3.0 μm.
[0020]
The metal film is thickened by electroless or electrolytic plating. The types of plating formed include nickel, copper, gold, silver, zinc, and iron. Since the conductor layer, which is a build-up formed later, is mainly copper, it is preferable to use copper. The thickness is preferably in the range of 1 to 20 μm. If it is thicker, undercutting may occur during etching, and a gap may be generated at the interface between the formed transition layer and via hole. Thereafter, an etching resist is formed, exposed and developed to expose portions of the metal other than the transition layer, and then etched to form a transition layer on the pad of the IC chip.
[0021]
In addition to the above method of manufacturing the transition layer, a dry film resist is formed on the metal film formed on the IC chip and the core substrate, and the portion corresponding to the transition layer is removed and thickened by electrolytic plating. Thereafter, the resist is peeled off, and a transition layer can be similarly formed on the pad of the IC chip by an etching solution.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
A. Semiconductor element
First, the configuration of the semiconductor element (IC chip) according to the first embodiment of the present invention will be described with reference to FIG. 3A showing a cross section of the semiconductor element 20 and FIG. 4B showing a plan view. To do.
[0023]
[First embodiment]
As shown in FIG. 3B, a die pad 22 and wiring (not shown) are disposed on the upper surface of the semiconductor element 20, and a protective film 24 is coated on the die pad 22 and wiring. The die pad 22 has an opening for the protective film 24. On the die pad 22, a transition layer 38 mainly made of copper is formed. The transition layer 38 includes a thin film layer 33 and a thickening layer 37. In other words, it is formed of two or more metal layers.
[0024]
Next, a method for manufacturing the semiconductor element described above with reference to FIG. 3B will be described with reference to FIGS.
[0025]
(1) First, the wiring 21 and the die pad 22 are formed by the usual method on the silicon wafer 20A shown in FIG. 1A (see FIG. 4A showing the plan views of FIG. 1B and FIG. 1B). Note that FIG. 1B shows a BB cross section of FIG.
(2) Next, a protective film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (FIG. 1C).
[0026]
(3) Physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A to form a conductive metal film (thin film layer) 33 on the entire surface (FIG. 2A). The thickness is preferably formed in the range of 0.001 to 2.0 μm. If it is below that range, a thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is 0.01 to 1.0 μm. As a metal to be formed, a material selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the first embodiment, the thin film layer 33 is made of chromium by sputtering. Chromium has good adhesion to metal and can suppress moisture intrusion. Moreover, you may sputter | spatter copper on a chromium layer. Two layers of chromium and copper may be continuously formed in a vacuum chamber. At this time, the thickness is about 0.05 to 0.1 μm of chromium and about 0.5 μm of copper.
[0027]
(4) Thereafter, a resist layer of any one of a liquid resist, a photosensitive resist, and a dry film is formed on the thin film layer 33. A mask (not shown) on which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and exposure and development are performed to form a non-formed portion 35a in the resist 35. Electrolytic plating is performed to provide a thickening layer (electrolytic plating film) 37 on the resist layer non-forming portion 35a (FIG. 2B). The types of plating formed include nickel, copper, gold, silver, zinc, and iron. Electrical characteristics, economic efficiency, and the conductor layer, which is a build-up formed later, is mainly copper, so copper is preferably used. In the first embodiment, copper is used. The thickness is preferably in the range of 1 to 20 μm.
[0028]
(5) After removing the plating resist 35 with an alkaline solution or the like, the metal film 33 under the plating resist 35 is subjected to sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt, etc. Then, the transition layer 38 is formed on the pad 22 of the IC chip (FIG. 2C).
[0029]
(6) Next, an etching solution is sprayed onto the substrate to etch the surface of the transition layer 38 to form a roughened surface 38α (see FIG. 3A). The roughened surface can also be formed using electroless plating or oxidation-reduction treatment.
[0030]
(7) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into pieces by dicing or the like to form the semiconductor element 20 (FIGS. 3B and 3B are plan views). (See FIG. 4B). Thereafter, if necessary, operation check and electrical inspection of the divided semiconductor element 20 may be performed. Since the semiconductor element 20 has the transition layer 38 larger than the die pad 22, the probe pin can be easily applied, and the inspection accuracy is high.
[0031]
[First modification of the first embodiment]
In the first embodiment described above, the thin film layer 33 is formed of chromium. On the other hand, in the first modified example, the thin film layer 33 is formed of titanium. Titanium is applied by vapor deposition or sputtering. Titanium has good adhesion to metal and can suppress the intrusion of moisture.
[0032]
[Second modification of the first embodiment]
In the first embodiment described above, the thin film layer 33 is formed of chromium. On the other hand, in the second modified example, the thin film layer is formed of tin.
[0033]
[Third modification of the first embodiment]
In the first embodiment described above, the thin film layer 33 is formed of chromium. On the other hand, in the third modified example, the thin film layer is formed of zinc.
[0034]
[Fourth modification of the first embodiment]
In the first embodiment described above, the thin film layer 33 is formed of chromium. On the other hand, in the fourth modified example, the thin film layer is formed of nickel. Nickel is formed by sputtering. Nickel has good adhesion to metal and can suppress the intrusion of moisture.
[0035]
[Fifth modification of the first embodiment]
In the first embodiment described above, the thin film layer 33 is formed of chromium. On the other hand, in the fifth modified example, the thin film layer is formed of cobalt.
In each modified example, copper may be further laminated on the thin film layer.
[0036]
[Second Embodiment]
A semiconductor element 20 according to the second embodiment will be described with reference to FIG. In the semiconductor device according to the first embodiment described above with reference to FIG. 3B, the transition layer 38 has a two-layer structure including the thin film layer 33 and the thickening layer 37. In contrast, in the second embodiment, as shown in FIG. 7B, the transition layer 38 has a three-layer structure including a first thin film layer 33, a second thin film layer 36, and a thickening layer 37. It is configured as.
[0037]
Subsequently, a method of manufacturing the semiconductor device according to the second embodiment described above with reference to FIG. 7B will be described with reference to FIGS.
[0038]
(1) First, the wiring 21 and the die pad 22 are formed on the silicon wafer 20A shown in FIG. 5A (FIG. 5B).
(2) Next, a protective film 24 is formed on the die pad 22 and the wiring (FIG. 5C).
[0039]
(3) Physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A to form a conductive metal film (first thin film layer) 33 on the entire surface (FIG. 5D). The thickness is preferably in the range of 0.001 to 2 μm. If it is below that range, a thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is 0.01 to 1.0 μm. As a metal to be formed, a material selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the second embodiment, the first thin film layer 33 is made of chromium. Chromium, nickel, and titanium have good adhesion to metal and can suppress moisture intrusion.
[0040]
(4) The second thin film layer 36 is laminated on the first thin film layer 33 by any one of sputtering, vapor deposition, and electroless plating. In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it may be formed of either copper or nickel. This is because copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and hardly causes peeling or cracking. In the second embodiment, the second thin film layer 36 is formed by electroless copper plating. A desirable combination of the first thin film layer and the second thin film layer is chromium-copper, chromium-nickel, titanium-copper, titanium-nickel, or the like. It is superior to other combinations in terms of metal bondability and electrical conductivity.
[0041]
(5) Thereafter, a resist layer is formed on the second thin film layer 36. A mask (not shown) is placed on the resist layer, and after exposure and development, a non-formed portion 35a is formed in the resist 35. Electrolytic plating is performed to provide a thickening layer (electrolytic plating film) 37 on the resist layer non-forming portion 35a (FIG. 6B). The types of plating formed include copper, nickel, gold, silver, zinc, and iron. Electrical characteristics, economic efficiency, and the conductor layer, which is a build-up formed later, is mainly copper. Therefore, copper is preferably used. In the second embodiment, copper is used. The thickness is preferably in the range of 1 to 20 μm.
[0042]
(6) After removing the plating resist 35 with an alkaline solution or the like, the second thin film layer 36 and the first thin film layer 33 under the plating resist 35 are mixed with sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, second The transition layer 38 is formed on the pad 22 of the IC chip by removing with an etching solution such as a dicopper complex-organic acid salt (FIG. 6C).
[0043]
(7) Next, an etching solution is sprayed on the substrate to etch the surface of the transition layer 38, thereby forming a roughened surface 38α (see FIG. 7A). The roughened surface can also be formed using electroless plating or oxidation-reduction treatment.
[0044]
(8) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like to form the semiconductor element 20 (FIG. 7B).
[0045]
[First modification of the second embodiment]
In the second embodiment described above, the first thin film layer 33 is formed of chromium, the second thin film layer 36 is formed of electroless plated copper, and the thickening layer 37 is formed of electrolytic copper plating. In contrast, in the first modified example, the first thin film layer 33 is formed of chromium, the second thin film layer 36 is formed of sputtered copper, and the thickening layer 37 is formed of electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 0.5 μm copper, and 15 μm electrolytic copper.
[0046]
[Second modification of the second embodiment]
In the second modified example, the first thin film layer 33 is formed of titanium, the second thin film layer 36 is formed of electroless copper, and the thickening layer 37 is formed of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 1.0 μm plated copper, and 17 μm electrolytic copper.
[0047]
[Third modification of the second embodiment]
In the third modified example, the first thin film layer 33 is formed of titanium, the second thin film layer 36 is formed of sputtered copper, and the thickening layer 37 is formed of electrolytic copper plating. The thickness of each layer is 0.06 μm titanium, 0.5 μm copper, and 15 μm electrolytic copper.
[0048]
[Fourth modification of the second embodiment]
In the fourth modified example, the first thin film layer 33 is formed of chromium, the second thin film layer 36 is formed of electroless plating nickel, and the thickening layer 37 is formed of electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 1.0 μm plated copper, and 15 μm electrolytic copper.
[0049]
[Fifth modification of the second embodiment]
In the fifth modified example, the first thin film layer 33 is formed of titanium, the second thin film layer 36 is formed of electroless plating nickel, and the thickening layer 37 is formed of electrolytic copper plating. The thickness of each layer is 0.05 μm titanium, 1.2 μm plated nickel, and 15 μm electrolytic copper.
[0050]
[Third embodiment]
A method for manufacturing the semiconductor element 20 according to the third embodiment will be described with reference to FIG. The configuration of the semiconductor device of the third embodiment is substantially the same as that of the first embodiment described above with reference to FIG. However, in the first embodiment, the transition layer 38 is formed by forming the thickening layer 37 in the resist non-forming portion using a semi-additive process. On the other hand, in the third embodiment, an additive process is used to form the thick layer 37 uniformly, and then a resist is provided, and the non-resist formation portion is removed by etching to form the transition layer 38.
[0051]
A manufacturing method of the third embodiment will be described with reference to FIG.
(1) As described above with reference to FIG. 2B in the first embodiment, physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form the conductive first thin film layer 33 on the entire surface. (FIG. 2A). The thickness is preferably in the range of 0.001 to 2.0 μm. If it is below that range, a thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is preferably 0.01 to 1.0 μm. As a metal to be formed, a material selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals provide die pad protection and do not degrade electrical properties. In the third embodiment, the first thin film layer 33 is formed by sputtering chromium. The thickness of chromium is 0.05 μm.
[0052]
(2) A thickening layer (electrolytic plating film) 37 is uniformly provided on the first thin film layer 33 by electrolytic plating (FIG. 8B). The types of plating formed include copper, nickel, gold, silver, zinc, and iron. Electrical characteristics, economic efficiency, and the conductor layer, which is a build-up formed later, is mainly copper. Therefore, copper is preferably used. In the third embodiment, copper is used. The thickness is preferably in the range of 1 to 20 μm. If it is thicker than that, undercut occurs during the etching described later, and a gap may be generated at the interface between the formed transition layer and via hole.
[0053]
(3) Thereafter, a resist layer 35 is formed on the thickening layer 37 (FIG. 8C).
[0054]
(4) The metal film 33 and the thickening layer 37 in the non-formed portion of the resist 35 are removed with an etching solution such as sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt. After that, the resist 35 is peeled off to form a transition layer 38 on the pad 22 of the IC chip (FIG. 8D). Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.
[0055]
[First modification of the third embodiment]
In the third embodiment described above, the thin film layer 33 is made of chromium. On the other hand, in the first modified example, the thin film layer 33 is formed of titanium.
[0056]
[Fourth embodiment]
A method for manufacturing the semiconductor element 20 according to the fourth embodiment will be described with reference to FIG. In the semiconductor device according to the third embodiment described above with reference to FIG. 8, the transition layer 38 has a two-layer structure including the thin film layer 33 and the thickening layer 37. In contrast, in the fourth embodiment, as shown in FIG. 9D, the transition layer 38 has a three-layer structure including a first thin film layer 33, a second thin film layer 36, and a thickening layer 37. It is configured as.
[0057]
The manufacturing method of the fourth embodiment will be described with reference to FIG.
(1) In the first embodiment, as in the second embodiment described above with reference to FIG. 6A, the second thin film layer 36 is formed on the first thin film layer 33 by sputtering, vapor deposition, or electroless plating. They are stacked (FIG. 9A). In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it may be formed of either copper or nickel. This is because copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and hardly causes peeling or cracking. In the fourth embodiment, the second thin film layer 36 is formed by electroless copper plating.
Desirable combinations of the first thin film layer and the second thin film layer are chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of metal bondability and electrical conductivity.
[0058]
(2) Electroplating is performed to uniformly provide a thick film 37 on the second thin film layer 36 (FIG. 9B).
[0059]
(3) Thereafter, a resist layer 35 is formed on the thickening layer 37 (FIG. 9C).
[0060]
(4) The first thin film layer 33, the second thin film layer 36, and the thickening layer 37 in the portion where the resist 35 is not formed are made of sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic. After removing with an etching solution such as an acid salt, the resist 35 is peeled off to form a transition layer 38 on the pad 22 of the IC chip (FIG. 9D). Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.
[0061]
[First modification of the fourth embodiment]
In the fourth embodiment described above, the first thin film layer 33 is made of chromium, the second thin film layer 36 is made of electroless plated copper, and the thickening layer 37 is made of electrolytic copper plating. In contrast, in the first modified example, the first thin film layer 33 is formed of chromium, the second thin film layer 36 is formed of sputtered copper, and the thickening layer 37 is formed of electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 0.5 μm copper, and 15 μm electrolytic copper.
[0062]
[Second modification of the fourth embodiment]
In the second modified example, the first thin film layer 33 is formed of titanium, the second thin film layer 36 is formed of electroless copper, and the thickening layer 37 is formed of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 1.0 μm copper, and 15 μm electrolytic copper.
[0063]
[Third Modification of Fourth Embodiment]
In the third modified example, the first thin film layer 33 is formed of titanium, the second thin film layer 36 is formed of sputtered copper, and the thickening layer 37 is formed of electrolytic copper plating. The thickness of each layer is titanium 0.07 μm, copper 0.5 μm, and electrolytic copper 18 μm.
[0064]
[Fourth modification of the fourth embodiment]
In the fourth modified example, the first thin film layer 33 is formed of chromium, the second thin film layer 36 is formed of electroless plating nickel, and the thickening layer 37 is formed of electrolytic copper plating. The thickness of each layer is
Chrome 0.06 μm, nickel 1.2 μm, and electrolytic copper 16 μm.
[0065]
[Fifth modification of the fourth embodiment]
In the fifth modified example, the first thin film layer 33 is formed of titanium, the second thin film layer 36 is formed of electroless plating nickel, and the thickening layer 37 is formed of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 1.1 μm nickel, and 15 μm electrolytic copper.
[0066]
B. Multilayer printed wiring board with built-in semiconductor elements
Next, the configuration of the multilayer printed wiring board in which the semiconductor elements (IC chips) 20 of the first to fourth embodiments described above are embedded, accommodated, and accommodated in the recesses, gaps, and openings of the core substrate will be described.
[First embodiment]
As shown in FIG. 14, the multilayer printed wiring board 10 includes a core substrate 30 that accommodates the IC chip 20 of the first embodiment described above with reference to FIG. 3B, an interlayer resin insulation layer 50, and an interlayer resin insulation layer. 150. Via hole 60 and conductor circuit 58 are formed in interlayer resin insulation layer 50, and via hole 160 and conductor circuit 158 are formed in interlayer resin insulation layer 150.
[0067]
A solder resist layer 70 is disposed on the interlayer resin insulating layer 150. The conductor circuit 158 under the opening 71 of the solder resist layer 70 is provided with solder bumps 76 for connection to an external substrate (not shown) such as a daughter board or a mother board.
[0068]
In the multilayer printed wiring board 10 of this embodiment, the IC chip 20 is built in the core substrate 30, and a transition layer 38 is disposed on the pad 22 of the IC chip 20. For this reason, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using lead parts or sealing resin. In addition, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened. Therefore, the upper interlayer insulating layer 50 is also flattened, and the film thickness becomes uniform. Furthermore, the shape stability can be maintained even when the upper via hole 60 is formed by the transition layer.
[0069]
Furthermore, by providing the copper transition layer 38 on the die pad 22, it is possible to prevent the resin residue on the pad 22 from being immersed in an acid, an oxidant, or an etching solution in various subsequent processes, and various annealing. Even after the process, discoloration and dissolution of the pad 22 do not occur. This improves the connectivity and reliability between the IC chip pads and via holes. Furthermore, a via hole having a diameter of 60 μm can be reliably connected by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm.
[0070]
Next, a method for manufacturing the multilayer printed wiring board described above with reference to FIG. 14 will be described with reference to FIGS.
[0071]
(1) First, an insulating resin substrate (core substrate) 30 in which a prepreg impregnated with a resin such as epoxy is laminated on a core material such as glass cloth is used as a starting material (see FIG. 10A). Next, a recess 32 for accommodating an IC chip is formed on one surface of the core substrate 30 by counterboring (see FIG. 10B). Here, the concave portion is provided by counterbore processing, but a core substrate including an accommodation portion can be formed by bonding an insulating resin substrate provided with an opening and a resin insulating substrate not provided with an opening.
[0072]
(2) Thereafter, the adhesive material 34 is applied to the recesses 32 using a printing machine. At this time, potting or the like may be performed in addition to the application. Next, the IC chip 20 is placed on the adhesive material 34 (see FIG. 10C).
[0073]
(3) Then, the upper surface of the IC chip 20 is pushed or hit to be completely accommodated in the recess 32 (see FIG. 10D). Thereby, the core substrate 30 can be smoothed. At this time, the adhesive material 34 may be applied to the upper surface of the IC chip 20. However, as described later, since a resin layer is provided on the upper surface of the IC chip 20 and an opening for a via hole is provided by a laser, a transition layer is formed. 38 does not affect the connection between the via hole and the via hole.
[0074]
(4) A pressure of 5 kg / cm while heating a thermosetting resin sheet having a thickness of 50 μm to a temperature of 50 to 150 ° C. on the substrate subjected to the above steps.²Then, an interlayer resin insulation layer 50 is provided (see FIG. 11A). The degree of vacuum at the time of vacuum bonding is 10 mmHg.
[0075]
(5) Next, CO with a wavelength of 10.4 μm²A via hole opening 48 having a diameter of 60 μm is provided in the interlayer resin insulating layer 50 with a gas laser under the conditions of a beam diameter of 5 mm, a top hat mode, a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot ( (See FIG. 11B). The resin residue in the opening 48 is removed using permanganic acid having a liquid temperature of 60 ° C. By providing the copper transition layer 38 on the die pad 22, it is possible to prevent resin residue on the pad 22, thereby improving the connectivity and reliability between the pad 22 and a via hole 60 described later. Further, by providing the transition layer 38 having a diameter of 60 μm or more on the 40 μm diameter pad 22, the via hole opening 48 having a diameter of 60 μm can be reliably connected. Here, the resin residue is removed using an oxidizing agent such as permanganic acid, but it is also possible to perform desmear treatment using oxygen plasma or the like or corona treatment.
[0076]
(6) Next, the surface of the interlayer resin insulation layer 50 is roughened with permanganic acid to form a roughened surface 50α (see FIG. 11C). The roughened surface is desirably between 0.05 and 5 μm.
[0077]
(7) The metal layer 52 was provided on the interlayer resin insulation layer 50 on which the roughened surface 50α was formed. The metal layer 52 was formed by electroless plating. A metal layer 52 as a plating film was provided in the range of 0.1 to 5 μm by previously applying a catalyst such as palladium on the surface layer of the interlayer resin insulation layer 50 and immersing it in an electroless plating solution for 5 to 60 minutes. (See FIG. 12A). As an example,
[Electroless plating aqueous solution]
NiSO_Four                  0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
It was immersed for 40 minutes at a liquid temperature of 34 ° C.
[0078]
Instead of plating, using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd., sputtering using Ni—Cu alloy as a target was performed under the conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, and time 5 minutes. The Cu alloy 52 can also be formed on the surface of the epoxy-based interlayer resin insulation layer 50. At this time, the formed Ni—Cu alloy layer 52 has a thickness of 0.2 μm.
[0079]
(8) A commercially available photosensitive dry film is pasted on the substrate 30 that has been subjected to the above-described treatment, and a photomask film is placed thereon, and 100 mJ / cm.²After the exposure, the development process is performed with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 12B). The additive in the electrolytic plating aqueous solution is Kaparaside HL manufactured by Atotech Japan.
[0080]
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive (manufactured by Atotech Japan, Kaparaside HL) 19.5 ml / l
[Electrolytic plating conditions]
Current density 1A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0081]
(9) After stripping and removing the plating resist 54 with 5% NaOH, the metal layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 52 and the electrolytic plating are removed. A conductor circuit 58 and a via hole 60 each having a thickness of 16 μm formed of the film 56 are formed, and roughened surfaces 58α and 60α are formed by an etching solution containing a cupric complex and an organic acid (see FIG. 12C). ).
[0082]
(10) Next, the above steps (4) to (9) are repeated to further form an upper interlayer resin insulation layer 150 and a conductor circuit 158 (including via holes 160) (see FIG. 13A). ).
[0083]
(11) Next, a photosensitizing agent obtained by acrylating 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 A weight part is put into a container, and a mixed composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator and Michler's ketone as a photosensitizer for the mixed composition. (Kanto Chemical Co., Ltd.) 0.2 part by weight is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured with a B type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3.
[0084]
(12) Next, the solder resist composition is applied to the substrate 30 in a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the solder resist resist opening is formed. A photomask having a thickness of 5 mm on which a pattern of 10 mm is drawn is brought into close contact with the solder resist layer 70 to 1000 mJ / cm²Then, an opening 71 having a diameter of 200 μm is formed (see FIG. 13B). A commercially available solder resist may also be used.
[0085]
(13) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed is nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphate (2.8 × 10 6)^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1mol / l) is immersed in an electroless plating solution at 80 ° C. for 7.5 minutes to form a 0.03 μm thick gold plating layer 74 on the nickel plating layer 72. Solder pads 75 are formed (see FIG. 13C).
[0086]
(14) Thereafter, a solder paste is printed on the opening 71 of the solder resist layer 70 and reflowed at 200 ° C. to form solder bumps 76. Thereby, the multilayer printed wiring board 10 including the IC chip 20 and having the solder bumps 76 can be obtained (see FIG. 14).
[0087]
For the solder paste, Sn / Pb, Sn / Sb, Sn / Ag, Sn / Ag / Cu, or the like can be used. Of course, a radiation low α-ray type solder paste may be used.
[0088]
In the embodiment described above, thermosetting resin sheets are used for the interlayer resin insulation layers 50 and 150. This resin sheet contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.
[0089]
The resin used in the production method of the present invention is a resin in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are dispersed in a resin that is hardly soluble in an acid or oxidizing agent (hereinafter referred to as a hardly soluble resin). is there.
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively fast dissolution rate as “soluble” for convenience when immersed in a solution of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.
[0090]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0091]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0092]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0093]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.
[0094]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified various modified polybutadiene rubber, carboxyl group-containing (meth) acrylonitrile-butadiene rubber, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0095]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0096]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0097]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0098]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.
[0099]
The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via hole opening can be formed in the interlayer resin insulating layer by exposure and development.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0100]
Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin, polyimide resin, polyphenylene resin, polyolefin resin, polyethersulfone, and fluorine resin. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0101]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0102]
In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface with unevenness of uniform roughness can be formed, and even if a via hole or a through hole is formed in a resin film, the adhesion of the metal layer of the conductor circuit formed thereon can be secured. Because it can. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. As a result, since the portion other than the surface layer portion of the resin film is not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is reliably maintained.
[0103]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film is melted to the deep part of the resin film, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.
[0104]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0105]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0106]
Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By including these fillers, it is possible to improve the performance of the multilayer printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0107]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers melt and carbonize when a temperature of 350 ° C. or higher is applied.
[0108]
[Second Embodiment]
Next, a multilayer printed wiring board according to a second embodiment of the present invention will be described with reference to FIG.
In the first embodiment described above, the case where the BGA is provided has been described. The second embodiment is substantially the same as the first embodiment, but is configured in a PGA system in which connection is made via conductive connection pins 96 as shown in FIG. In the first embodiment described above, the via hole is formed by a laser. In the second embodiment, the via hole is formed by photoetching.
[0109]
A method for manufacturing a multilayer printed wiring board according to the second embodiment will be described with reference to FIG.
(4) Similar to the first embodiment, the thermosetting epoxy resin 50 having a thickness of 50 μm is applied to the substrate that has undergone the above steps (1) to (3) (see FIG. 15A).
[0110]
(5) Next, the photomask film 49 on which the black circle 49a corresponding to the via hole forming position is drawn is placed on the interlayer resin insulating layer 50 and exposed (FIG. 15B).
[0111]
(6) An interlayer resin insulation layer 50 having a via hole opening 48 having a diameter of 85 μm is provided by spray development with a DMTG solution and heat treatment (see FIG. 15C).
[0112]
(7) The surface of the interlayer resin insulation layer 50 is roughened with permanganic acid or chromic acid to form a roughened surface 50α (see FIG. 15D). Since the subsequent steps are the same as those in the first embodiment described above, description thereof is omitted. The roughened surface is desirably between 0.05 and 5 μm.
[0113]
The results of the evaluation of the semiconductor elements of the above-described examples and the comparative example of the semiconductor elements accommodated in the multilayer printed wiring boards of the first and second examples are shown in the charts of FIGS.
[Comparative Example 1]
The comparative example is the same as the semiconductor element of the first embodiment. However, in Comparative Example 1, the transition layer was not formed, and the die pad was embedded as it was in the multilayer printed wiring board.
[Comparative Example 2]
In Comparative Example 2, stud bumps disclosed in JP-A-9-321408 were formed and embedded in a multilayer printed wiring board.
[0114]
As an evaluation item,
(1) The presence or absence of discoloration / dissolution of the die pad was determined visually.
(2) Whether or not the via hole opening can be formed by using the manufacturing method of the multilayer printed wiring board of the first embodiment, whether or not an opening having a diameter of 60 μm can be formed by a laser, Using a plate manufacturing method, it was investigated whether an opening having a diameter of 85 μm could be formed if it was a photo.
(3) The contact resistance between the die pad and the via hole was measured.
In the semiconductor elements of the first to fourth examples, favorable results were obtained, but in Comparative Examples 1 and 2, problems such as poor formation of via holes, poor connection, or increased resistance values occurred.
[0115]
【The invention's effect】
With the structure of the present invention, the IC chip and the printed wiring board can be connected without using lead components. Therefore, resin sealing is also unnecessary. Furthermore, since troubles due to lead parts and sealing resin do not occur, connectivity and reliability are improved. In addition, since the IC chip pad and the conductive layer of the printed wiring board are directly connected, the electrical characteristics can be improved.
Furthermore, compared with the conventional IC chip mounting method, the wiring length from the IC chip to the substrate to the external substrate can be shortened, and the loop inductance can be reduced. In addition, the degree of freedom of wiring formation increased as BGA, PGA, and the like were arranged.
[Brief description of the drawings]
FIGS. 1A, 1B, and 1C are manufacturing process diagrams of a semiconductor device according to a first embodiment of the present invention. FIGS.
FIGS. 2A, 2B, and 2C are manufacturing process diagrams of a semiconductor device according to a first embodiment of the present invention. FIGS.
FIGS. 3A and 3B are manufacturing process diagrams of a semiconductor device according to the first embodiment of the present invention. FIGS.
FIG. 4A is a plan view of a silicon wafer 20A according to the first embodiment of the present invention, and FIG. 4B is a plan view of a separated semiconductor element.
5A, 5B, 5C, and 5D are manufacturing process diagrams of a semiconductor device according to a second embodiment of the present invention.
FIGS. 6A, 6B, and 6C are process diagrams of manufacturing a semiconductor device according to a second embodiment of the present invention. FIGS.
FIGS. 7A and 7B are manufacturing process diagrams of a semiconductor device according to a second embodiment of the present invention. FIGS.
8A, 8B, 8C, and 8D are manufacturing process diagrams of a semiconductor device according to a third embodiment of the present invention.
FIGS. 9A, 9B, 9C, 9D, 9D and 9D are manufacturing process diagrams of a semiconductor device according to a second embodiment of the present invention.
10A, 10B, 10C, and 10D are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention.
11A, 11B, and 11C are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention.
12A, 12B, and 12C are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention.
13A, 13B, and 13C are manufacturing process diagrams of a multilayer printed wiring board according to the first embodiment of the present invention.
FIG. 14 is a cross-sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.
15A, 15B, 15C, and 15D are manufacturing process diagrams of a multilayer printed wiring board according to a second embodiment of the present invention.
FIG. 16 is a cross-sectional view of a multilayer printed wiring board according to a second embodiment of the present invention.
FIG. 17 is a chart showing the results of evaluating the semiconductor elements of the first and second examples.
FIG. 18 is a chart showing the results of evaluating the semiconductor elements of the third and fourth examples as comparative examples.
[Explanation of symbols]
20 IC chip (semiconductor element)
22 die pad
24 Protective film
30 core substrate
32 recess
36 Resin layer
38 Transition layer
50 Interlayer resin insulation layer
58 Conductor circuit
60 Bahia Hall
70 Solder resist layer
76 Solder bump
90 daughter board
96 Conductive connection pins
97 Conductive adhesive
120 IC chip
150 Interlayer resin insulation layer
158 Conductor circuit
160 Viahole

Claims (3)

Prints in which interlayer insulating layers and conductor layers are alternately stacked on a substrate having an IC chip embedded in a recess or through hole, and a conductor circuit is connected via via holes formed in the interlayer insulating layer In the wiring board,
On the pads of the IC chip, intermediary layer formed Ri by the electrolytic copper plating a larger diameter than the pad is formed,
Inside the interlayer insulating layer on the surface of the substrate, an opening reaching the mediating layer is formed by a laser,
A printed wiring board in which a pad of the IC chip and the conductor layer are connected by a via hole formed inside the opening. Prints in which interlayer insulating layers and conductor layers are alternately stacked on a substrate having an IC chip embedded in a recess or through hole, and a conductor circuit is connected via via holes formed in the interlayer insulating layer A method for manufacturing a wiring board comprising:
On the pad, the IC chip having an intermediary layer formed Ri by the electrolytic copper plating a larger diameter than the pad, and received in the recess or through hole of the substrate;
Laminating an interlayer insulating layer on the substrate;
Forming an opening in the interlayer insulating layer by laser to reach the mediating layer;
A via hole connected to the conductor layer on the interlayer insulating layer is formed inside the opening; a method for manufacturing a printed wiring board.   The method of manufacturing a printed wiring board according to claim 2, wherein the via hole is formed by filling the opening with copper plating.

Images