JPH11126978A - Multilayered wiring board - Google Patents

Multilayered wiring board

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Publication number
JPH11126978A
JPH11126978A JP9292766A JP29276697A JPH11126978A JP H11126978 A JPH11126978 A JP H11126978A JP 9292766 A JP9292766 A JP 9292766A JP 29276697 A JP29276697 A JP 29276697A JP H11126978 A JPH11126978 A JP H11126978A
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JP
Japan
Prior art keywords
wiring
layer
formed
wiring circuit
insulating
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP9292766A
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Japanese (ja)
Inventor
Akiya Fujisaki
Katsura Hayashi
桂 林
昭哉 藤崎
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Kyocera Corp
京セラ株式会社
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Application filed by Kyocera Corp, 京セラ株式会社 filed Critical Kyocera Corp
Priority to JP9292766A priority Critical patent/JPH11126978A/en
Publication of JPH11126978A publication Critical patent/JPH11126978A/en
Application status is Pending legal-status Critical

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Abstract

PROBLEM TO BE SOLVED: To provide a multilayered wiring board, wherein an electrical element such as a semiconductor element, a capacitor element, and a resistor element, etc., is mounted for reduced size and enhanced mounting density of the electrical element, while making higher density of wiring circuit layer possible.
SOLUTION: An insulating substrate 50 in which a plurality of insulating layers consisting of at least a thermosetting resin are laminated, a plurality of wiring circuit layers 51 formed on the surface and inside of the insulating substrate 50, an insulating layer 56, wherein preferably a via hole conductor 52 which filled with metal powder, connects between the wiring circuit layers 51 is provided, a void part 53 is formed inside the insulating substrate 50, and having a photosensitive resin, based on build-up method, on the surface of a wiring core substrate 55 wherein an electric element 54 is mounted/housed in the void part 53, and a wiring circuit layer 58 formed by thin-film formation method are sequentially laminated to form a multilayered wiring layer 60.
COPYRIGHT: (C)1999,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、例えば、多層配線基板及び半導体素子収納用パッケージなどに適し、特に絶縁基板内部に電気素子が内蔵されてなる多層配線基板に関するものである。 The present invention relates to, for example, suitable such multilayer wiring board and the semiconductor device package for housing, to a multilayer wiring board comprising a built-in particular an insulating substrate inside the electric element.

【0002】 [0002]

【従来技術】近年、通信機器の普及に伴い、高速動作が求められる電子機器が広く使用されるようになり、さらにこれに伴って高速動作が可能なプリント配線基板が求められている。 BACKGROUND ART In recent years, with the spread of communication devices, become the electronic equipment speed operation is required are widely used, and a printed wiring board capable of high speed operation sought further accordingly. このような高速動作を行うためには、配線の高密度化が必要とされている。 In order to perform such a high-speed operation, high-density wiring is needed.

【0003】このような高密度化を達成するための1つの手法として、ビルドアップ法が知られている。 [0003] One approach to achieve such densification, the build-up method is known. この方法は、例えば、銅箔のエッチング等の手段により配線が形成された両面銅張ガラスエポキシ等からなるコア基板の表面に、感光性樹脂を塗布して、露光現像してバイアホールを具備する絶縁層を形成した後、その表面に無電解銅メッキを施して、これをレジスト塗布、エッチング、レジスト除去によりバイアホール導体および配線回路層を形成する。 This method, for example, on the core surface of a substrate made of double-sided copper-clad glass epoxy on which wiring is formed by means of etching of the copper foil, a photosensitive resin is applied, comprises a via hole is exposed and developed after forming the insulating layer is subjected to electroless copper plating on the surface, which resist coating, etching, forming the via-hole conductor and the wiring circuit layers by resist removal. そして、上記の感光性樹脂による絶縁層の形成と、バイアホール導体および配線回路層の形成を繰り返すことにより、微細化、多層化した後、さらに、ドリル等によりスルーホールを形成して、ホール内にメッキ層を形成して層間の配線回路層を接続するようにしたものである。 Then, the formation of the insulating layer by a photosensitive resin described above, by repeating the formation of the via-hole conductor and the wiring circuit layer, miniaturization, after multilayered, further, forming a through hole by a drill or the like, the hole forming a plating layer on is obtained so as to connect the wiring circuit layer interlayer.

【0004】なお、この時に用いられる両面銅張ガラスエポキシ基板としては、ガラス織布または不織布内にエポキシ樹脂を含浸させたものが最も一般的に使用されている。 [0004] As the double-sided copper-clad glass epoxy substrate used at this time, impregnated with the epoxy resin to the glass woven fabric or a nonwoven fabric is most commonly used.

【0005】一方、電子機器は小型化が進んでいるが、 [0005] On the other hand, the electronic apparatus is progressing miniaturization,
近年携帯情報端末の発達や、コンピューターを持ち運んで操作する、いわゆるモバイルコンピューティングの普及によってさらに小型、薄型且つ高精細の多層配線基板が求められる傾向にある。 Development and the recent portable information terminals, operated carrying your computer, even smaller the spread of so-called mobile computing tends to thin and high definition of the multilayer wiring board is obtained.

【0006】従来のプリント配線基板では、プリプレグと呼ばれる有機樹脂を含む平板の表面に銅箔を接着した後、これをエッチングして微細な回路を形成し、これを積層した後、所望位置にマイクロドリルでスルーホールの穴明けを行い、そのホール内壁にメッキ法により金属を付着させてスルーホール導体を形成して各層間の電気的な接続を行っている。 [0006] In the conventional printed wiring board, after bonding the copper foil on the surface of plates containing organic resin called prepreg, after which is etched to form a fine circuit, a laminate of this micro the desired position perform drilling of through holes by drilling, by attaching metal to form through-hole conductors are made electrical connection between layers by plating on the hole inner wall. また最近では、絶縁層に対して形成したバイアホール内に金属粉末を充填してバイアホール導体を形成した後、他の絶縁層を積層して多層化した配線基板も提案されている。 Recently also after the formation of the via-hole conductor by filling a metal powder into the via holes formed on the insulating layer, has been proposed wiring board multilayered by stacking another insulating layer.

【0007】また、従来のプリント配線基板に対して、 [0007] In addition, for the conventional printed wiring board,
半導体素子やコンデンサ素子、抵抗素子などを実装する場合には、配線基板の表面に形成された配線回路層に対してこれらの電気素子を半田等により実装し、実装した素子を樹脂によってモールドする方法、絶縁基板の表面に凹部を形成して、その凹部内に素子を収納して樹脂モールドしたり、蓋体によって凹部を気密に封止する方法がある。 Semiconductor devices and the capacitor element, when implementing such resistance elements, how these electrical elements mounted by soldering or the like to the wiring circuit layer formed on the surface of the wiring board, molding the mounting the device by resin , by forming a concave portion on the surface of the insulating substrate, or a resin mold accommodating the element in its recess, there is a method of sealing a recess hermetically by the lid.

【0008】 [0008]

【発明が解決しようとする課題】しかしながら、バイアホール導体を金属粉末の充填によって形成する方法は、 [SUMMARY OF THE INVENTION However, the method of forming a via hole conductor by filling the metal powder,
バイアホール導体の小径化が可能であるとともに、任意の位置にバイアホール導体を形成できる点で有利であり、また、ビルドアップ法により形成された多層配線層を具備した配線基板においても、薄い絶縁層と配線回路層により形成されることから、いずれも高密度配線が可能ではあっても、その配線基板に種々の電気素子を搭載する場合には、その多層配線基板の表面に実装するしかために、電気素子を搭載した配線基板の小型化には、自ずと限界があった。 As well as a possible diameter of the via-hole conductors, is advantageous in that it can form a via-hole conductor in any position, also in the wiring substrate provided with the multilayer wiring layer formed by buildup method, a thin insulating from being formed by a layer and the wiring circuit layer, even if are both capable of high-density wiring, when mounting the various electrical devices on the wiring board, reservoir only be mounted on the surface of the multilayer wiring board to, the miniaturization of the wiring substrate mounted with electrical devices, there is a limit.

【0009】従って、本発明は、半導体素子や電子部品(コンデンサ素子、抵抗素子、フィルター素子、発振素子など)の電気素子を搭載し、小型化と、電気素子の実装密度を高めるとともに、配線回路層の高密度化が可能な多層配線基板を提供することを目的とするものである。 Accordingly, the present invention relates to a semiconductor device and electronic component (a capacitor element, a resistor element, a filter element, such as an oscillation element) mounted electrical device, and downsizing, to increase the mounting density of the electric element, the wiring circuit it is an object of the present invention that densification of the layer to provide a multilayer wiring board as possible.

【0010】 [0010]

【課題を解決するための手段】本発明者等は、電気素子を搭載した配線基板の小型化と高密度配線化について検討を重ねた結果、ビルドアップ法により高密度配線層を形成するにあたり、そのコア基板中に、電気素子を実装収納するための空隙部を形成し、その空隙部に電気素子を実装収納することにより、配線基板のより多くの電気素子を搭載した小型の配線基板を提供できることを知見し、本発明に至った。 The present inventors have SUMMARY OF THE INVENTION The miniaturization of the wiring board having electric elements and a result of studying on high-density wiring of, when forming a high-density wiring layers by a build-up method, in its core substrate, forming a space portion for mounting accommodating the electric element, by implementing housing the electrical element in its gap portion, provide a compact wiring board having more electrical elements of the wiring substrate can the knowledge that has led to the present invention.

【0011】即ち、本発明の多層配線基板は、少なくとも熱硬化性樹脂を含む複数の絶縁層を積層してなる絶縁基板と、該絶縁基板の表面および内部に形成された複数の配線回路層と、前記配線回路層間を接続するためのバイアホール導体を具備するとともに、前記絶縁基板内部に空隙部が形成され、該空隙部内に電気素子を実装収納してなる配線コア基板の表面に、感光性樹脂を含有する絶縁層と、配線回路層とを順次積層してなる多層配線層を形成したことを特徴とするものであり、前記空隙部内にて、前記電気素子を金属箔からなる配線回路層に半田実装してなること、前記配線コア基板におけるバイアホール導体を金属粉末の充填によって形成してなることを特徴とするものである。 [0011] That is, the multilayer wiring board of the present invention includes an insulating substrate formed by laminating a plurality of insulating layers containing at least a thermosetting resin, and a plurality of wiring circuit layer formed on the surface and inside of the insulating substrate , together comprising a via hole conductors for connecting the wiring circuit layers, the insulating substrate internal void portion is formed on the surface of the wiring core substrate formed by mounting housing the electrical element in the airspace, photosensitive an insulating layer containing a resin, which is characterized in that a multilayer wiring layer formed by sequentially stacking a wiring circuit layer, at the said gap portion, the wiring circuit layer made of the electrical device from a metal foil that formed by soldering, the via hole conductors in the wiring core substrate is characterized in that become formed by filling metal powder.

【0012】 [0012]

【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION

(配線コア基板の形成)図1は、本発明の多層配線基板における配線コア基板を作製するための第1の製造工程を説明するための図である。 (Wire core formed of a substrate) 1 is a diagram for explaining a first manufacturing process for producing a wiring core substrate in a multilayer wiring board of the present invention. 図1によれば、まず、図1 According to FIG. 1, FIG. 1
(a)に示すように、熱硬化性樹脂を含む軟質(Bステージ状態)の第1の絶縁シート1を作製する。 (A), the making of the first insulation sheet 1 a soft (B stage state) containing a thermosetting resin. また、この絶縁シート1には、所望により厚み方向に貫通するスルーホールを形成し、そのスルーホール内に金属粉末を含む導体ペーストをスクリーン印刷や吸引処理しながら充填して、バイアホール導体2を形成する。 Moreover, this insulation sheet 1, optionally forming a through hole penetrating in the thickness direction, a conductive paste containing a metal powder and filled with screen printing or suction process within the through hole, the via hole conductors 2 Form. また、この絶縁シート1の所定箇所に電気素子を収納するための空隙部3を形成する。 Further, to form an air gap 3 for accommodating an electric element in a predetermined position of the insulating sheet 1.

【0013】次に、図1(b)に示すように、絶縁シート1の表面に配線回路層4を形成するとともに、絶縁シート1の空隙部3に電気素子5を実装収納する。 [0013] Next, as shown in FIG. 1 (b), to form the wiring circuit layers 4 on the surface of the insulating sheet 1, to implement housing the electric element 5 in the gap portion 3 of the insulation sheet 1. 配線回路層4を形成する方法としては、1)絶縁シート1の表面に金属箔を貼り付けるか、メッキにより全面に金属層を形成した後、エッチング処理して回路パターンを形成する方法、2)絶縁シート1表面にレジストを形成して、メッキにより形成する方法、3)転写シート表面に金属箔を貼り付け、金属箔をエッチング処理して回路パターンを形成した後、この金属箔からなる回路パターンを絶縁シート1表面に転写させる方法。 As a method for forming the wiring circuit layers 4, 1) paste or a metal foil on the surface of the insulating sheet 1, after forming a metal layer on the entire surface by plating, a method of forming a circuit pattern by etching, 2) forming a resist on the insulating sheet 1 surface, a method of forming by plating, 3) adhered to a metal foil on the transfer sheet surface, after forming a circuit pattern of the metal foil by etching, the circuit composed of the metal foil pattern how to transfer the insulating sheet 1 surface. 4)導体ペーストをスクリーン印刷法などにより回路パターンに印刷する方法等が挙げられる。 4) How to print a conductive paste to the circuit pattern by a screen printing method and the like.

【0014】本第1の製造方法においては、配線回路層4と、配線回路層4に電気素子5を実装した構造物を転写フィルムから絶縁シート1に転写させる。 In the present first manufacturing method, the wiring circuit layers 4, to the structure to the wiring circuit layers 4 mounting the electric element 5 is transferred from the transfer film to the insulating sheet 1. その具体的な方法を図1(b1)〜(b3)に示す。 The specific method is shown in FIG. 1 (b1) ~ (b3). この方法によれば、例えば、樹脂や金属からなる転写フィルム6の表面に金属箔を接着した後、エッチングして配線回路層4 According to this method, for example, after bonding the metal foil to the surface of the transfer film 6 made of resin or metal, etched and the wiring circuit layers 4
を形成する(図1(b1))。 The formed (FIG. 1 (b1)). その後、その配線回路層4に、電気素子5を半田、TAB、ワイヤーボンディング等により実装する(図1(b2))。 Thereafter, the wiring circuit layers 4, the electric element 5 soldering, TAB, implemented by wire bonding or the like (FIG. 1 (b2)).

【0015】その後、電気素子5が実装された転写フィルム6を絶縁シート1に対して、電気素子5が絶縁シート1の空隙部3に収納されるように積層して圧着した後(図1(b3))、転写フィルム6を剥がして、配線回路層4と電気素子5とを絶縁シート1に転写させて、図1(b)に示すような電気素子5が空隙部3に実装収納された単層の配線層を形成することができる。 [0015] Then, the insulating transfer film 6 to the electric element 5 is mounted sheet 1, after the electric element 5 is crimped stacked so is accommodated in the gap portion 3 of the insulation sheet 1 (FIG. 1 ( b3)), peel off the transfer film 6, and a wiring circuit layer 4 and the electric element 5 is transferred to the insulating sheet 1, the electrical device 5, as shown in FIG. 1 (b) implemented housed in the gap portion 3 it is possible to form a wiring layer of a single layer. この時、 At this time,
絶縁シート1は、未硬化または半硬化状態であり軟質であることから、配線回路層4を圧着することにより、絶縁シート1の表面に埋め込むことができるとともに、絶縁シート1に形成されたバイアホール導体2を緻密化することができる。 Insulation sheet 1, since it is uncured or semi-cured state soft, by crimping the wiring circuit layers 4, it is possible to embed the surface of the insulating sheet 1, the via holes formed in the insulating sheet 1 it is possible to densify the conductor 2.

【0016】また、上記の例では、基本的には、電気素子5を実装する配線回路層4は、電気素子5とともに、 Further, in the above example, basically, the wiring circuit layers 4 to implement the electrical element 5, together with the electric element 5,
同時に転写させるものであるが、電気素子5の実装に関与しない配線回路層(図示せず)は、電気素子5と配線回路層4とともに同時するか、または個別に前述した1)〜4)のいずれの方法で形成してもよい。 But it is intended to be simultaneously transferred, the wiring circuit layer that is not involved in the implementation of the electric element 5 (not shown), either simultaneously with the electric element 5 with the wiring circuit layers 4, or separately described above 1) to 4) of it may be formed by any method.

【0017】また、空隙部3内に収納された電気素子5 [0017] The electric element 5 housed in the gap portion 3
は、配線回路層4に実装された状態でエポキシ樹脂等により封止してもよい。 It may be sealed by epoxy resin or the like in a state of being mounted on the wiring circuit layers 4.

【0018】次に、上記のように空隙部3内に電気素子5が実装収納された絶縁シート1の上下面に、軟化状態(Bステージ状態)の第2および第3の絶縁シート7、 Next, the upper and lower surfaces of the insulation sheet 1 is electric element 5 into the gap portion 3 mounted housing as described above, the second and third insulating sheet 7 of softened (B stage state),
8を積層圧着して、絶縁シート1、7、8中の熱硬化性樹脂が硬化するに十分な温度に加熱して一括して完全硬化させる。 8 are laminated crimped to completely cure collectively by heating to a temperature sufficient to cure the thermosetting resin in the insulating sheet 1,7,8. なお、絶縁シート7、8には、配線回路層9、10やバイアホール導体11、12を前述した方法により適宜形成してもよい。 Note that the insulating sheet 7 and 8 may be suitably formed by the method of the wiring circuit layers 9 and 10 and via-hole conductors 11 and 12 described above. このようにして、図1 Thus, as shown in FIG. 1
(c)に示すように、絶縁基板13内に電気素子5を内蔵する多層配線コア基板14を形成することができる。 As shown in (c), it is possible to form a multilayer wiring core substrate 14 having a built-in electrical element 5 in the insulating substrate 13.

【0019】次に、本発明の第2の製造方法によれば、 Next, according to the second manufacturing method of the present invention,
図2(a)に示すように、熱硬化性樹脂を含有する絶縁シート20に、適宜バイアホールを形成してそのホール内に金属粉末を含有する導体ペーストを充填してバイアホール導体21を形成し、さらにその表面又は裏面に配線回路層22を形成する。 As shown in FIG. 2 (a), the insulating sheet 20 containing a thermosetting resin, forming the via hole conductor 21 is filled with a conductive paste containing a metal powder into the hole to form a suitably via hole and further forming a wiring circuit layer 22 on the front surface or back surface. 配線回路層22の形成は、前述した1)〜4)のいずれの方法でもよい。 Formation of the wiring circuit layer 22 may be any method described above 1) to 4).

【0020】次に、図2(b)に示すように、配線回路層22の表面に、電気素子23を半田、フリップチップ、ワイヤーボンディングなどの方法で実装する。 Next, as shown in FIG. 2 (b), on the surface of the wiring circuit layers 22, implementing the electrical element 23 solder flip chip, a method such as wire bonding.

【0021】その後、図2(c)に示すように、電気素子23が実装された絶縁シート20の表面に、空隙部2 [0021] Thereafter, as shown in FIG. 2 (c), the surface of the insulating sheet 20 electric element 23 is mounted, the void portion 2
4が形成された絶縁シート25を電気素子23が空隙部24に収納されるように位置合わせして積層する。 4 electric element 23 are stacked by aligning to be received in the gap portion 24 insulating sheet 25 is formed. なお、絶縁シート25には、前述した方法に基づき配線回路層26、バイアホール導体27が形成されていてもよい。 Note that the insulating sheet 25, the wiring circuit layers 26 on the basis of the method described above, may be via hole conductors 27 are formed.

【0022】そして、図2(d)に示すように、空隙部24が形成された絶縁シート25を積層したその上に、 [0022] Then, as shown in FIG. 2 (d), on the laminated insulating sheet 25 gap 24 are formed,
空隙部24を密封するように、絶縁シート28を積層する。 To seal the gap portion 24, laminating the insulating sheet 28.

【0023】また、この絶縁シート28には、前述した方法に基づき配線回路層29、バイアホール導体30が形成されていてもよい。 Further, the insulating sheet 28, the wiring circuit layers 29 on the basis of the method described above, it may be via hole conductors 30 are formed.

【0024】そして、最終的にこれらの積層物を絶縁シート20、25、28中の熱硬化性樹脂が硬化するに十分な温度に加熱して一括して完全硬化させることにより、絶縁基板31内に電気素子23を内蔵する多層配線コア基板32を形成することができる。 [0024] Then, finally by complete curing in bulk by heating to a temperature sufficient to these laminates thermosetting resin in the insulating sheet 20,25,28 cured, insulating substrate 31 it is possible to form the multilayer wiring core substrate 32 having a built-in electric device 23.

【0025】また、本発明によれば、上記第1および第2の電気素子の空隙部内への実装収納構造を基礎として、あらゆる形態の多層配線コア基板を作製することができる。 Further, according to the present invention, it is possible on the basis of the mounting housing structure into the gap portion of the first and second electrical element, to produce a multilayer wiring core substrate of any form. 例えば、図3に示すように、多層配線コア基板33の絶縁基板34内において、IC素子35やコンデンサ36等のなどの電気素子を収納する空隙部37、3 For example, as shown in FIG. 3, in the insulating substrate 34 of the multilayer wiring core substrate 33, the gap portion for accommodating the electric element such as an IC element 35 and the capacitor 36 37,3
8を同一面内、または異なる層内に空隙部39を複数箇所形成して、これら複数の電気素子を実装収納させることができる。 8 the same plane, or in different layers with an air gap portion 39 and a plurality of locations forming, it is possible to implement housing the plurality of electrical elements.

【0026】上記の第1および第2の製造方法によって作製される配線コア基板によれば、後述するビルドアップ法により多層配線層を形成するにあたり、その多層配線層形成面におけるコア基板の配線回路層は、コア基板の絶縁基板の表面に埋設されており、その表面が平坦であることが望ましい。 According to the wiring core substrate made by the first and second manufacturing methods described above, when forming a multilayer wiring layer by a build-up method described later, the wiring circuit of the core board at the multilayer wiring layer formed surface layer is embedded in the insulating surface of the substrate of the core substrate, it is desirable that the surface is flat. これは、多層配線層を形成するコア基板表面に配線回路層が突出(載置)した構造では、 This is, in the structure in which the wiring circuit layer on the core substrate surface to form a multilayer wiring layer is projected (placed),
コア基板表面の凹凸が多層配線層の平坦度を低下させてしまう結果、多層配線層における微細な配線回路層の形成を阻害する要因となるためである。 Results irregularities of the core substrate surface will reduce the flatness of the wiring layer is to become a factor that inhibits the formation of fine wiring circuit layers in a multilayer wiring layer. また、コア基板の多層配線層形成面における配線回路層の表面粗さ(R The surface roughness of the wiring circuit layer in the multilayer wiring layer formed surface of the core substrate (R
a)はAFM法による測定で0.01μm以上、特に0.02μm以上であることが多層配線層との密着性および電気的接続の信頼性を高める上で望ましい。 a) the above 0.01μm as measured by AFM method, it is desirable in increasing the adhesion and reliability of the electrical connection between the wiring layer particularly 0.02μm or more.

【0027】このような配線回路層が絶縁基板表面に埋設された構造は、例えば、未硬化状態の絶縁シート表面に金属箔からなる配線回路層を重ねて圧力を印加することにより、強制的に配線回路層を埋設することができる。 The buried structure such wiring circuit layer insulating substrate surface, for example, by applying pressure on top of the wiring circuit layer made of a metal foil on the insulating sheet surface of the uncured, forced it is possible to embed the wiring circuit layer. 上記の第1および第2の製造方法において、用いられる熱硬化性樹脂を含有する絶縁シートは、熱硬化性有機樹脂、または熱硬化性有機樹脂とフィラーなどの組成物を混練機や3本ロールなどの手段によって十分に混合し、これを圧延法、押し出し法、射出法、ドクターブレード法などによってシート状に成形する。 In the first and second manufacturing methods described above, the insulating sheet containing a thermosetting resin to be used is, kneader or three-roll compositions, such as thermosetting organic resin or a thermosetting organic resin, and a filler thoroughly mixed by means such as rolling method which, extrusion method, an injection method and formed into a sheet by a doctor blade method. そして、所望により熱処理して熱硬化性樹脂を半硬化させる。 The semi-curing the desired heat treated thermosetting resin. 半硬化には、樹脂が完全硬化するに十分な温度よりもやや低い温度に加熱する。 The semi-cured, the resin is heated to a temperature slightly lower than the temperature sufficient to complete cure.

【0028】そして、この状態の絶縁層に対するスルーホール(バイアホール)および空隙部の形成は、ドリル、パンチング、サンドブラスト、あるいは炭酸ガスレーザ、YAGレーザ、及びエキシマレーザ等の照射による加工など公知の方法が採用される。 [0028] Then, formation of the through hole (via hole) and the void portion is to the insulating layer in this state, drilling, punching, sandblast, or carbon dioxide gas laser, YAG laser, and a known method such as processing by the irradiation of an excimer laser or the like It is adopted.

【0029】なお、絶縁シートを形成する熱硬化性樹脂としては、絶縁材料としての電気的特性、耐熱性、および機械的強度を有する熱硬化性樹脂であれば特に限定されるものでなく、例えば、アラミド樹脂、フェノール樹脂、エポキシ樹脂、イミド樹脂、フッ素樹脂、フェニレンエーテル樹脂、ビスマイレイドトリアジン樹脂、ユリア樹脂、メラミン樹脂、シリコーン樹脂、ウレタン樹脂、不飽和ポリエステル樹脂、アリル樹脂等が、単独または組み合わせて使用できる。 [0029] As the thermosetting resin constituting the insulating sheet, electric properties as an insulating material, heat resistance, and not limited in particular as long as the thermosetting resin having mechanical strength, e.g. , aramid resin, phenol resin, epoxy resin, imide resin, fluororesin, polyphenylene ether resin, bis Mai laid triazine resins, urea resins, melamine resins, silicone resins, urethane resins, unsaturated polyester resins, allyl resins, and, alone or in in combination it can be used.

【0030】また、上記の絶縁シート1中には、絶縁基板あるいは配線基板全体の強度を高めるために、有機樹脂に対してフィラーを複合化させることもできる。 Further, during the above-mentioned insulating sheet 1, in order to increase the strength of the entire insulating substrate or wiring board, fillers may also be conjugated to an organic resin. 有機樹脂と複合化されるフィラーとしては、SiO 2 、Al The filler with an organic resin is complexed, SiO 2, Al
23 、ZrO 2 、TiO 2 、AlN、SiC、BaT 2 O 3, ZrO 2, TiO 2, AlN, SiC, BaT
iO 3 、SrTiO 3 、ゼオライト、CaTiO 3 、ほう酸アルミニウム等の無機質フィラーが好適に用いられる。 iO 3, SrTiO 3, zeolite, CaTiO 3, inorganic fillers such as aluminum borate is suitably used. また、ガラスやアラミド樹脂からなる不織布、織布などに上記樹脂を含浸させて用いてもよい。 It may also be used in non-woven fabric made of glass or aramid resin, such as woven fabric impregnated with the resin. なお、有機樹脂とフィラーとは、体積比率で15:85〜50:5 Note that the organic resin and a filler, 15 in volume ratio: 85 to 50: 5
0の比率で複合化されるのが適当である。 It is suitable for being complexed in a ratio of 0.

【0031】これらの電気素子を収納するための空隙部を形成する絶縁シートは、上記の種々の材質の中でも空隙部をパンチング又はレーザーで容易に加工できる点から、エポキシ樹脂、イミド樹脂、フェニレンエーテル樹脂と、シリカまたはアラミド不織布との混合物であることが最も望ましい。 The insulating sheet forming the void portion for accommodating these electrical devices, the air gap among various materials of the terms that can be readily processed by punching or laser, epoxy resin, imide resin, polyphenylene ether a resin, and most preferably a mixture of silica or aramide nonwoven fabric.

【0032】一方、バイアホール導体2に充填される金属ペーストは、銅粉末、銀粉末、銀被覆銅粉末、銅銀合金などの、平均粒径が0.5〜50μmの金属粉末を含む。 On the other hand, the metal paste filled in the via-hole conductor 2 includes copper powder, silver powder, silver-coated copper powder, such as copper-silver alloy, an average particle size of the metal powder 0.5 to 50 [mu] m.

【0033】金属粉末の平均粒径が0.5μmよりも小さいと、金属粉末同士の接触抵抗が増加してスルーホール導体の抵抗が高くなる傾向にあり、50μmを越えるとスルーホール導体の低抵抗化が難しくなる傾向にある。 [0033] If the average particle size of the metal powder is less than 0.5 [mu] m, there is a tendency that the resistance is high in the through-hole conductors contact resistance of the metal powder particles is increased, the low resistance of the through-hole conductors exceeds 50μm there is a tendency that reduction becomes difficult.

【0034】また、導体ペーストは、前述したような金属粉末に対して、前述したような結合用有機樹脂や溶剤を添加混合して調製される。 Further, the conductive paste, the metal powder as described above, is prepared by adding and mixing a binding organic resins and solvents as described above. ペースト中に添加される溶剤としては、用いる結合用有機樹脂が溶解可能な溶剤であればよく、例えば、イソプロピルアルコール、テルピネオール、2−オクタノール、ブチルカルビトールアセテート等が用いられる。 The solvent added in the paste may be a solvent capable of bonding an organic resin is dissolved using, for example, isopropyl alcohol, terpineol, 2-octanol, butyl carbitol acetate or the like is used.

【0035】上記の導体ペースト中の結合用有機樹脂としては、前述した種々の絶縁シートを構成する有機樹脂の他、セルロースなども使用される。 [0035] As binding organic resin in the above conductive paste, other organic resin constituting the various insulating sheet described above are also used, such as cellulose. この有機樹脂は、 The organic resin,
前記金属粉末同士を互いに接触させた状態で結合するとともに、金属粉末を絶縁シートに接着させる作用をなしている。 With bound being in contact with said metal powder particles to one another, and has a function of adhering the metal powder to the insulating sheet. この有機樹脂は、金属ペースト中において、 The organic resin is in a metal paste,
0.1乃至40体積%、特に0.3乃至30体積%の割合で含有されることが望ましい。 0.1 to 40 vol%, it is desirable that the content at a rate of preferably 0.3 to 30 vol%. これは、樹脂量が0. This is, the amount of resin is 0.
1体積%よりも少ないと、金属粉末同士を強固に結合することが難しく、低抵抗金属を絶縁層に強固に接着させることが困難となり、逆に40体積%を越えると、金属粉末間に樹脂が介在することになり粉末同士を十分に接触させることが難しくなり、スルーホール導体の抵抗が大きくなるためである。 When the amount is less than 1 vol%, it is difficult to strongly bond the metal powder particles, it is difficult to firmly bond the low-resistance metal in the insulating layer, exceeds 40 volume percent Conversely, the resin between the metal powder There it becomes difficult to sufficiently contact the powder particles will be interposed, because the resistance of the through-hole conductors increases.

【0036】配線回路層としては、銅、アルミニウム、 [0036] As the wiring circuit layer, copper, aluminum,
金、銀の群から選ばれる少なくとも1種、または2種以上の合金からなることが望ましく、特に、銅、または銅を含む合金が最も望ましい。 Gold, at least one selected from the group consisting of silver, or desirably composed of two or more alloys, in particular, an alloy containing copper or copper, is most preferable. また、場合によっては、導体組成物として回路の抵抗調整のためにNi−Cr合金などの高抵抗の金属を混合、または合金化してもよい。 In some cases, the high resistance metal, such as Ni-Cr alloy mixture, or may be alloyed for resistance adjustment circuit as a conductor composition.
さらには、配線層の低抵抗化のために、前記低抵抗金属よりも低融点の金属、例えば、半田、錫などの低融点金属を導体組成物中の金属成分中に2〜20重量%の割合で含んでもよい。 Furthermore, in order to reduce the resistance of the wiring layers, than said low resistance metal having a low melting point metal, for example, solder, a low-melting-point metal such as tin in a metal component in the conductor composition of 2-20 wt% including at the rate may be.

【0037】上記配線回路層と絶縁シートとの密着強度を高める上では、絶縁シートの配線回路層の形成箇所及び/又は転写フィルム表面の配線回路層表面の表面を0.1μm以上、特に0.3μm〜3μm、最適には0.3〜1.5μmに粗面加工することが望ましい。 [0037] The in increasing the adhesion strength between the wiring circuit layer and the insulating sheet, the area where the wiring circuit layer of the insulating sheet and / or the surface of the wiring circuit layer surface of the transfer film surface 0.1μm or more, especially 0. 3Myuemu~3myuemu, optimally it is desirable to roughening to 0.3 to 1.5 .mu.m. また、バイアホール導体の両端を金属箔からなる配線回路層によって封止する上では、配線回路層の厚みは、5〜 Further, in order to seal by the wiring circuit layer formed at both ends of the via-hole conductors from the metal foil, the thickness of the wiring circuit layer, 5
40μmが適当である。 40μm is appropriate.

【0038】また、本発明によれば、電気素子を内蔵する上記配線コア基板40には、図4に示すように、電気素子41を収納する空隙部42近傍の絶縁層43中に、 Further, according to the present invention, in the wiring core substrate 40 having a built-in electric device, as shown in FIG. 4, in the gap portion 42 near the insulating layer 43 for housing the electric element 41,
熱伝導性に優れた金属部材や無機質部材からなる放熱体44を介装し、その少なくとも一端をコア基板40の側面から突出させることにより、電気素子41から発生して熱を放熱体44を経由して、コア基板40の系外に放出させることも可能である。 The heat dissipating member 44 made of a metal excellent member or inorganic member in thermal conductivity is interposed, by projecting the at least one end from the side of the core substrate 40, via the heat dissipation body 44 to the heat generated from the electric element 41 and, it is also possible to discharge to the outside of the core substrate 40.

【0039】(多層配線層の形成)次に、本発明によれば、上記のようにして作製した配線コア基板の表面に、 [0039] (formation of the wiring layer) Next, according to the present invention, the surface of the wiring core substrate prepared as described above,
ビルドアップ法により感光性樹脂を含有する絶縁層と、 An insulating layer containing a photosensitive resin by a build-up method,
配線回路層とを順次積層して多層配線層を形成する。 Sequentially laminating the wiring circuit layer to form a multilayer wiring layer. そこで、具体的な多層配線層の形成方法について図5をもとに説明する。 Therefore, a method for forming a specific multi-layered wiring layers on the basis of FIG.

【0040】まず、図5(a)に示すように、上述したようにして作製され、少なくとも熱硬化性樹脂を含む複数の絶縁層を積層してなる絶縁基板50と、絶縁基板5 [0040] First, as shown in FIG. 5 (a), is manufactured as described above, an insulating substrate 50 formed by laminating a plurality of insulating layers containing at least a thermosetting resin, the insulating substrate 5
0の表面および内部に形成された複数の配線回路層51 0 a plurality formed surface and the interior of the wiring circuit layer 51
と、配線回路層51間を接続するためのバイアホール導体52を具備するとともに、絶縁基板50内部に空隙部53が形成され、空隙部53内に電気素子54を実装収納してなる配線コア基板55の表面に、感光性樹脂からなる絶縁層56を一面に形成する。 When, with comprises a via hole conductor 52 for connecting the wiring circuit layers 51, the wiring core substrate void portion 53 is formed inside the insulating substrate 50, formed by mounting housing the electric element 54 into the gap portion 53 55 the surface of, the insulating layer 56 made of a photosensitive resin on one surface.

【0041】なお、配線コア基板55の表面に配線回路層51が形成されていない場合には、絶縁層56を形成する前に、コア基板55表面に、周知の方法で配線回路層51を形成する。 [0041] In the case where the wiring circuit layer 51 on the surface of the wiring core substrate 55 is not formed, formed before forming the insulating layer 56, the core substrate 55 surface, a wiring circuit layer 51 by a known method to. コア基板55表面に配線回路層51 Wiring on the core substrate 55 surface circuit layer 51
を形成するには、前述したような1)〜4)の方法がなどが採用される。 To form the the method and is employed in a 1) to 4) as described above.

【0042】なお、絶縁層56の形成にあたっては感光性樹脂をカーテンコート法やスピンコート法により塗布する方法が、均一な厚さで簡易に形成できることから好適に採用される。 [0042] Incidentally, in forming the insulating layer 56 is a method of coating by a photosensitive resin curtain coating or spin coating is preferably employed since it can be formed easily with a uniform thickness. 絶縁層を形成する樹脂としては、周知の感光性樹脂が用いられ、例えば、感光性を有するポリイミド樹脂、エポキシ樹脂、エポキシアクリレート樹脂、ポリエステル樹脂、ウレタンアクリレート樹脂、ビスマレイドトリアジン(BT)樹脂などが用いられ、絶縁層56の厚みとしては、40〜100μmが好適である。 The resin for forming the insulating layer, known photosensitive resin is used, for example, a polyimide resin having photosensitivity, epoxy resins, epoxy acrylate resins, polyester resins, urethane acrylate resins, bismaleimide triazine (BT) resin used, the thickness of the insulating layer 56, 40 to 100 [mu] m is preferred.

【0043】次に、図5(b)に示すように、絶縁層5 Next, as shown in FIG. 5 (b), the insulating layer 5
6に対して、露光、現像を施し、バイアホールを形成する部分の絶縁層56を除去する。 Against 6, exposed, subjected to development to remove the portion of the insulating layer 56 to form the via hole. このように露光、現像工程で形成することにより、微細なバイアホール57を得ることができる。 Thus exposed, by forming in the development step, it is possible to obtain a fine via holes 57.

【0044】次に、図5(c)のように、絶縁層56上に無電解メッキ、電解メッキ、蒸着法、スパッタリング法、イオンプレーティング法などの薄膜形成法によって一面に金属層を形成した後、フォトレジスト等を塗布し、露光、現像し、不要な金属層をエッチングするなどの、周知の方法によって配線回路層58およびバイアホール導体59を形成する。 Next, as shown in FIG. 5 (c), the electroless plating on the insulating layer 56, electrolytic plating, vapor deposition method, sputtering method to form a metal layer on one side by a thin film forming method such as ion plating after, applying a photoresist or the like, exposed and developed, such as etching the unnecessary metal layer to form a wiring circuit layer 58 and via-hole conductors 59 by known methods. なお、エッチングによる配線回路層58およびバイアホール導体59の形成は、サブトラクティブ法及びアディティブ法のいずれでもよい。 The formation of the wiring circuit layers 58 and the via-hole conductor 59 by etching may be either a subtractive method or additive method.
この配線回路層は、銅、銀、金、アルミニウム、ニッケルなどの低抵抗金属またはそれらを含む合金により形成することが望ましい。 The wiring circuit layer, copper, silver, gold, aluminum, it is formed by a low-resistance metal or alloy containing these, such as nickel desirable.

【0045】そして、この配線回路層58が形成された絶縁層56の表面に、上記図5(a)、図5(b)および図5(c)で説明したのと同様な方法により、感光性樹脂からなる絶縁層形成、絶縁層形成の露光、現像によるバイアホール形成、薄膜形成法による配線回路層およびバイアホール導体形成を、繰り返し施すことにより、 [0045] Then, the surface of the insulating layer 56 which the wiring circuit layer 58 is formed, FIG 5 (a), by the same method as that described in FIGS. 5 (b) and 5 (c), the photosensitive insulating layer formed consisting rESIN, exposure of the insulating layer formed, via holes formed by development, the wiring circuit layers and via-hole conductors formed by thin film forming method, by performing repeatedly,
図5(d)に示すような、任意の層数からなる多層配線層60を形成することができる。 As shown in FIG. 5 (d), it is possible to form a wiring layer 60 made of any number of layers. そして、必要に応じて、多層配線層60の最表面にコンデンサ、半導体素子、抵抗素子などの電気素子61を実装する。 Then, if necessary, to implement a capacitor, a semiconductor element, an electric device 61 such as a resistance element on the outermost surface of the multilayer wiring layer 60.

【0046】また、適宜、多層配線層60における最表面の配線回路層を薄膜形成法により形成する前、または形成後に、配線コア基板55の表面に多層配線層60が形成された多層配線基板に対して、レーザー照射やマイクロドリル等により、多層配線層60から配線コア基板55を貫通するスルーホール用の貫通孔を形成し、その貫通孔内壁に、最表面の配線回路層の形成と同時、または後工程として、前記薄膜形成法により導体を被着形成してスルーホール導体を形成してもよい。 [0046] Also, as appropriate, before forming the thin film forming method wiring circuit layer on the outermost surface of the multilayer wiring layer 60, or after formation, the multilayer wiring board multi-layer wiring layer 60 is formed on the surface of the wiring core substrate 55 in contrast, by laser irradiation or micro drill or the like, to form a through hole for a through hole penetrating the wiring core substrate 55 from the multilayer wiring layer 60, on the inner wall of the through hole, simultaneously with the formation of the wiring circuit layer on the outermost surface, or as a post-process, it may be formed through-hole conductors by conductors deposited formed by the thin film forming method. その場合、スルーホール導体は配線回路層やバイアホール導体による高密度配線形成の障害とならないためには、できる限り小さい孔径であることが望ましい。 In that case, through-hole conductors for not a failure of the high-density wiring formed by the wiring circuit layer and the via hole conductor, it is small pore diameter as possible is desirable.

【0047】なお、上記の多層配線層60は、配線コア基板55の片面のみならず、配線コア基板55の両面に形成しても何ら差し支えない。 [0047] Incidentally, the multilayer wiring layer 60 described above, not only one side of the wiring core substrate 55, no problem be formed on both surfaces of the wiring core substrate 55.

【0048】このようにして、本発明によれば、従来の積層方法を用いて、複数の絶縁層が積層されてなる配線基板内部に電気素子を実装収納することができ、且つその配線基板をコア基板とし、ビルドアップ法により多層配線層を形成することにより、電気素子を高密度に実装することができ、且つ高密度の多層配線化を図ることができる。 [0048] In this way, according to the present invention, using conventional lamination methods, can be a plurality of insulating layers implement housing the electric element on the wiring board inside obtained by laminating, and the wiring substrate a core substrate, by forming a multi-wiring layer by a build-up method, the electrical device can be mounted at a high density, can and increasing the density of the multilayer wiring of.

【0049】 [0049]

【実施例】 【Example】

実施例1 (配線コア基板の作製) (1)アラミド樹脂の不織布に対してイミド樹脂を50 Example 1 (wiring Preparation of the core substrate) (1) imide resin relative aramid resin of the nonwoven fabric 50
体積%の割合で含浸した厚さ100μmのプリプレグに、炭酸ガスレーザーで直径0.1mmのバイアホールを形成し、そのホール内に銀をメッキした銅粉末を含む銅ペーストを充填してバイアホール導体を形成した。 Volume% thickness 100μm prepreg impregnated at a rate of, forming a via hole having a diameter of 0.1mm at a carbon dioxide gas laser, via-hole conductor is filled with a copper paste containing copper powder plated with silver to the hole It was formed. また、このプリプレグにレーザーを用いて半導体素子や電子部品を設置するための12mm×12mmの大きさの空隙部を形成し、それらを収納する電子部品の厚さ相当以上となる厚みに積層した。 Further, the prepreg using a laser to form a size of the gap portion of 12 mm × 12 mm for mounting the semiconductor devices and electronic parts, was laminated to a thickness which becomes them more substantial thickness of the electronic component accommodating.

【0050】(2)一方、イミド樹脂50体積%、シリカ粉末50体積%の割合となるように、ワニス状態の樹脂と粉末を混合しドクターブレード法により、厚さ75 [0050] (2) On the other hand, imide resin 50% by volume, as a percentage of the silica powder 50% by volume, by a doctor blade method by mixing the resin and powder varnish state, 75 thickness
μmの絶縁シートを作製し、その絶縁シートにパンチングで直径0.1mmのバイアホールを形成し、そのホール内に銀をメッキした銅粉末を含む銅ペーストを充填してバイアホール導体を形成した。 To produce μm of the insulating sheet, the insulating sheet punching by forming a via hole having a diameter of 0.1mm to and form a via hole conductor is filled with a copper paste containing copper powder plated with silver in its hole.

【0051】(3)また、ポリエチレンテレフタレート(PET)樹脂からなる転写シートの表面に接着剤を用いて、厚さ12μm、表面粗さ0.8μmの銅箔を一面に接着した。 [0051] (3) Further, by using an adhesive to the surface of the transfer sheet made of polyethylene terephthalate (PET) resin was adhered thickness 12 [mu] m, a copper foil surface roughness 0.8μm on one side. そして、フォトレジスト(ドライフィルム)を塗布し露光現像を行った後、これを塩化第二鉄溶液中に浸漬して非パターン部をエッチング除去して配線回路層を形成した。 Then, after the coating is exposed and developed photoresist (dry film) was formed the wiring circuit layers which the pattern portion is immersed in a ferric chloride solution is removed by etching. なお、作製した配線回路層は、線幅が20μm、配線と配線との間隔が20μmの微細なパターンである。 The wiring circuit layer prepared in a line width of 20 [mu] m, distance between the wiring and the wiring is a fine pattern of 20 [mu] m. その後、この配線回路層にIC素子をT Thereafter, the IC element to the wiring circuit layer T
AB実装し、実装したIC素子をポリイミド樹脂で封止した。 And AB implement, the implement the IC element is sealed with a polyimide resin.

【0052】(4)そして、(1)で作製した空隙部を有するプリプレグに対して、(2)でIC素子を実装した転写シートを、プリプレグの空隙部にIC素子が収納されるように位置決めして50kg/cm 2の圧力を加えて圧着した後、転写フィルムを剥離して、配線回路層とIC素子をプリプレグに転写した。 [0052] (4) Then, positioned such relative to the prepreg having a gap portion produced, transfer sheet obtained by mounting an IC element (2), the IC element in the gap portion of the prepreg is housed in (1) after crimping by applying a pressure of 50 kg / cm 2 and, by peeling off the transfer film, the wiring circuit layer and the IC element and transferred to the prepreg.

【0053】(5)その後、(2)で作製した絶縁シートの表面にも(3)と同様にして、金属箔からなる配線回路層を形成したPET樹脂フィルムから、配線回路層を転写させた。 [0053] (5) Thereafter, in the same manner as in the surface of the insulating sheet prepared in (2) (3), a PET resin film wiring forming a circuit layer made of a metal foil, was transferred to the wiring circuit layer .

【0054】(6)空隙部にIC素子が収納されたプリプレグを中心に、上下に配線回路層およびバイアホール導体が形成されたプリプレグを1層づつ積層し、さらにその上下面に(5)のようにして配線回路層が転写された絶縁シートを上下各2層づつ積層した。 [0054] (6) around a prepreg IC element is accommodated in the gap portion, a prepreg vertical wiring circuit layers and via hole conductors are formed one layer at a time by stacking further on the upper and lower surfaces (5) way wiring circuit layer has upper and lower laminated 2 layers each one by an insulating sheet that has been transferred. なお空隙部に対峙する下層のプリプレグの一部に銅からなる放熱板を介装するための溝を形成し、この溝内に放熱体を設置した。 Note a groove for interposing the heat radiation plate made of copper to a portion of the lower layer of the prepreg facing the gap portion was placed heat radiator into the groove. そしてこれらの積層物を50kg/cm 2の圧力で圧着し、200℃で1時間加熱して完全硬化させて多層配線コア基板を作製した。 And these laminates were pressed at a pressure of 50 kg / cm 2, to produce a multilayer wiring core substrate by completely cured by heating 1 hour at 200 ° C..

【0055】(多層配線層の形成) (7)上記のようにして作製した多層配線コア基板の両面に感光性エポキシ樹脂からなる絶縁材料を一面に塗布し、100℃で加熱して予備硬化した後、露光、現像により絶縁層の一部を除去して、コア基板表裏の絶縁層にバイアホールを形成した。 [0055] The insulating material consisting of (multi-layer formation of the wiring layer) (7) a photosensitive epoxy resin on both surfaces of the multilayer wiring core substrate prepared as described above was coated on one side, was precured by heating at 100 ° C. after exposure, by removing a part of the insulating layer by development, thereby forming a via hole in the insulating layer of the core substrate sides.

【0056】(8)次いで、絶縁層の配線回路層形成箇所およびバイアホール導体形成箇所の絶縁層表面を触媒化処理した後、無電解メッキ法により銅を析出させて、 [0056] (8) Next, after the insulating layer surface of the wiring circuit layer formed portions and via-hole conductors formed portion of the insulating layer was treated catalyzed and copper to precipitate by electroless plating,
フォトレジストを全面に塗布し、露光、現像し、不要部分の銅をエッチング除去して絶縁層の表面に配線回路層およびバイアホール導体を形成した。 A photoresist is applied to the entire surface, exposed and developed to form a wiring circuit layer and via holes conductors on the surface of the copper unnecessary portion is removed by etching the insulating layer.

【0057】(9)さらに、上記(7)〜(8)の工程を繰り返して施し、配線回路層6層の多層配線層を形成した。 [0057] (9) Further, subjected by repeating the steps (7) - (8), to form a multilayer wiring layer of the wiring circuit layer 6 layers.

【0058】(10)そして、多層配線層の表面に、コンデンサ素子および抵抗素子を半田実装して、本発明の多層配線基板を作製した。 [0058] (10) Then, the surface of the multilayer wiring layer, and soldering the capacitor element and the resistor element, to produce a multilayer wiring board of the present invention.

【0059】得られた多層配線基板に対して、多層配線コア基板における配線回路層やバイアホール導体の形成付近およびIC素子と配線回路層との接続部分を観察した結果、IC素子と配線回路層、バイアホール導体と配線回路層とは良好な接続状態であり、各配線間の導通テストを行った結果、配線の断線も認められなかった。 [0059] the obtained multilayer wiring board, result of observation of the connection portion between the multilayered wiring core wiring circuit layer on the substrate and the via-hole conductors formed around and IC element and the wiring circuit layer, IC element and the wiring circuit layer , the via-hole conductor and the wiring circuit layer is a good connection state, as a result of the continuity test between the wires, was not observed disconnection of the wiring.

【0060】また、コア基板表面に形成した多層配線層とIC素子との接続も良好であり、IC素子の動作においても何ら問題はなかった。 [0060] The connection between the wiring layer and the IC element formed on the core substrate surface is also good, there was no no problem in the operation of the IC element. 得られた多層配線基板を湿度85%、温度85℃の高温多湿雰囲気に100時間放置したが、目視で判別できる程度の変化は生じていなかった。 The resulting multi-layer wiring board humidity of 85%, was allowed to stand for 100 hours in hot and humid atmosphere at 85 ° C., to the extent that can be distinguished visually change did not occur.

【0061】実施例2 (1)アラミド樹脂の不織布に対してポリアミノビスマレイミド樹脂55体積%の割合で含浸した厚さ100μ [0061] The thickness 100μ impregnated at a rate of Example 2 (1) 55 vol% polyaminobismaleimide resin relative aramid resin of the nonwoven fabric
mのプリプレグAに炭酸ガスレーザーにより直径0.1 Diameter by carbon dioxide laser prepreg A of m 0.1
mmのバイアホールを形成しそのホール内に粒径約5μ Forming a mm via holes having a diameter of approximately 5μ to the hole
mの銀をメッキした銅粉末からなる銅ペーストを充填した。 Silver m was filled with a copper paste comprising plated copper powder.

【0062】(2)また、ポリエチレンテレフタレート(PET)樹脂からなる転写シートの表面に接着剤を用いて、厚さ18μm、表面粗さ0.7μmの銅箔を一面に接着した。 [0062] The (2), using an adhesive on the surface of the transfer sheet made of polyethylene terephthalate (PET) resin was adhered thickness 18 [mu] m, a copper foil surface roughness 0.7μm on one side. そして、フォトレジスト(ドライフィルム)を塗布し露光現像を行った後、これを塩化第二鉄溶液中に浸漬して非パターン部をエッチング除去して配線回路層を形成した。 Then, after the coating is exposed and developed photoresist (dry film) was formed the wiring circuit layers which the pattern portion is immersed in a ferric chloride solution is removed by etching. なお、作製した配線回路層は、線幅が40μm、配線と配線との間隔が40μmの微細なパターンである。 The wiring circuit layer prepared in a line width of 40 [mu] m, distance between the wiring and the wiring is a fine pattern of 40 [mu] m.

【0063】(3)そして、上記プリプレグAの表面に、(2)で配線回路層が形成された転写シートを、位置決めして50kg/cm 2の圧力を加えて圧着した後、転写フィルムを剥離して、配線回路層をプリプレグA表面に転写した。 [0063] (3) Then, the peeling on the surface of the prepreg A, the transfer sheet wiring circuit layer is formed, after crimping by applying a pressure of 50 kg / cm 2 by positioning the transfer film (2) to the wiring circuit layer has been transferred to the prepreg a surface.

【0064】(4)そして、プリプレグAの表面の配線回路層にチップ抵抗素子を半田実装した。 [0064] (4) Then, the chip resistor elements were soldered to the wiring circuit layer on the surface of the prepreg A.

【0065】(5)その後、チップ抵抗素子を実装したプリプレグAの表面に、(1)と同様にして作製したプリプレグBに対して、(1)(2)と同様にしてバイアホール導体および配線回路層を形成するとともに、チップ抵抗素子を収納するための空隙部をレーザー加工により形成し、これをチップ抵抗素子が搭載されたプリプレグAのIC素子実装面にて、プリプレグBの空隙部にチップ抵抗素子が収納される位置にて積層し、30kg/ [0065] (5) Then, on the surface of the prepreg A mounting the chip resistor elements, (1) and against the prepreg B was prepared in the same manner, (1) (2) and the via hole conductor and the wiring in the same manner chip to form a circuit layer, a gap portion for accommodating a chip resistor element is formed by laser processing, which in IC element mounting face of the prepreg a chip resistor element is mounted, the gap portion of the prepreg B laminated at a position where the resistance element is accommodated, 30kg /
cm 2の圧力で積層圧着した。 It was laminated crimped at a pressure of cm 2.

【0066】(6)さらに、(1)と同様にして作製したプリプレグCに対して、(1)(2)と同様にしてバイアホール導体および配線回路層を形成し、プリプレグBの空隙部に対向する面に銅からなる放熱板を収納するための溝をレーザー加工し、その溝内に一端がプリプレグの端面から突出するように、放熱板を設置した。 [0066] (6) In addition, with respect to prepreg C was prepared in the same manner as (1), (1) (2) In the same manner as to form a via-hole conductor and the wiring circuit layer, the gap portion of the prepreg B a groove for accommodating a heat radiating plate made of copper on opposite sides by laser processing, one end of the groove is so as to protrude from the end surface of the prepreg was placed radiator plate. そして、このプリプレグCをプリプレグBの表面に30kg Then, 30kg of prepreg C on the surface of the prepreg B
/cm 2の圧力をもって積層圧着した。 / Were stacked crimped with the pressure of cm 2.

【0067】(7)一方、ポリアミノビスマレイミド樹脂50体積%、シリカ粉末50体積%の割合となるように、ワニス状態の樹脂と粉末を混合しドクターブレード法により、厚さ75μmの絶縁シートを作製し、その絶縁シートにパンチングで直径0.1mmのバイアホールを形成し、そのホール内に銀をメッキした銅粉末を含む銅ペーストを充填してバイアホール導体を形成し、さらに(2)(3)と同様にして絶縁シートの表面に配線回路層を形成した。 [0067] (7) On the other hand, polyamino bismaleimide resin 50 vol%, such that the ratio of the silica powder 50% by volume, by a doctor blade method by mixing the resin and powder varnish state, making the insulating sheet having a thickness of 75μm and, the insulation sheet punching in forming a via hole having a diameter of 0.1mm to form a via-hole conductor is filled with a copper paste containing copper powder plated with silver in its hole, and (2) (3 ) and to form a wiring circuit layer on the surface of the insulating sheet in the same manner.

【0068】(8)(7)により形成した4層の絶縁シートを上記プリプレグA、B,Cからなる積層体の上下面にそれぞれ2層づつ積層した後、50kg/cm 2の圧力で圧着し、200℃で1時間加熱して完全硬化させてコア基板を作製した。 [0068] (8) (7) by forming the four layers of the insulating sheet of the above prepreg A, B, after each two layers one by stacking the upper and lower surfaces of the stacked body consisting of C, and pressed at a pressure of 50 kg / cm 2 , to prepare a core substrate by completely cured by heating 1 hour at 200 ° C..

【0069】・多層配線層の形成 (9)上記のようにして作製した多層配線コア基板の両面に対して、実施例1の(7)〜(9)に従ってビルドアップ法により、配線回路層6層の多層配線層を形成した。 [0069] - with respect to both surfaces of the multilayer wiring core substrate was prepared in the form (9) above the wiring layer, the build-up method according to (7) to (9) of Example 1, the wiring circuit layer 6 to form a multilayer wiring layer of the layer.

【0070】(10)そして、多層配線層の表面に、コンデンサ素子およびIC素子を半田実装して、本発明の多層配線基板を作製した。 [0070] (10) Then, the surface of the multilayer wiring layer, and soldering the capacitor element and the IC element, to produce a multilayer wiring board of the present invention.

【0071】得られた多層配線基板に対して、多層配線コア基板における配線回路層やバイアホール導体の形成付近およびチップ抵抗素子と配線回路層との接続部分を観察した結果、抵抗素子と配線回路層、バイアホール導体と配線回路層とは良好な接続状態であり、各配線間の導通テストを行った結果、配線の断線も認められなかった。 [0071] the obtained multilayer wiring board, result of observation of the connection portion between the multilayer interconnection wiring in the core substrate circuit layer and the via-hole conductors formed around and chip resistance element and the wiring circuit layer, and the resistance element wiring circuit layer, a good connection is established between the via-hole conductor and the wiring circuit layer, as a result of the continuity test between the wires, was not observed disconnection of the wiring.

【0072】また、コア基板表面に形成した多層配線層とチップ抵抗素子との接続も良好であり、チップ抵抗素子の動作においても何ら問題はなかった。 [0072] The connection of the multilayer wiring layer and the chip resistor element formed on the core substrate surface is also good, there was no no problem in the operation of the chip resistor elements. 得られた多層配線基板を湿度85%、温度85℃の高温多湿雰囲気に100時間放置したが、目視で判別できる程度の変化は生じていなかった。 The resulting multi-layer wiring board humidity of 85%, was allowed to stand for 100 hours in hot and humid atmosphere at 85 ° C., to the extent that can be distinguished visually change did not occur.

【0073】 [0073]

【発明の効果】以上詳述した通り、本発明の多層配線基板は、ビルドアップ法により高密度配線層を形成するためのコア基板内に、半導体素子、コンデンサ素子、抵抗素子などの電気素子を収納することから、多層配線基板表面のみならず、基板内部まで電気素子を実装することができる結果、配線基板における電気素子の高密度実装と同時に、高密度配線化、さらには配線基板の小型化を図ることができる。 As described above in detail, the multilayer wiring board of the present invention, the core substrate for forming a high-density wiring layers by a build-up method, the semiconductor element, a capacitor element, an electrical element such as a resistance element since the housing, not only the multilayer wiring substrate surface, since it is possible to implement an electrical element to the internal substrate, simultaneously with the high density packaging of the electric element in the wiring board, high-density wiring of further miniaturization of the wiring substrate it can be achieved.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の多層配線基板における配線コア基板を製造するための一方法を説明するための工程図である。 1 is a process diagram for explaining one method for manufacturing a wiring core substrate in a multilayer wiring board of the present invention.

【図2】本発明の多層配線基板における配線コア基板を製造するための他の方法を説明するための工程図である。 2 is a process diagram for explaining another method for manufacturing a wiring core substrate in a multilayer wiring board of the present invention.

【図3】本発明の多層配線基板における配線コア基板の他の構造を説明するための概略断面図である。 3 is a schematic sectional view for illustrating another structure of the wiring core substrate in a multilayer wiring board of the present invention.

【図4】本発明の多層配線基板における配線コア基板のさらに他の構造を説明するための概略断面図である。 4 is a schematic cross-sectional view for explaining still another structure of the wiring core substrate in a multilayer wiring board of the present invention.

【図5】本発明の多層配線基板における多層配線層を形成するための方法を説明するための工程図である。 5 is a process diagram for explaining a method for forming a multilayer wiring layer in a multilayer wiring board of the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

50 絶縁基板 51 配線回路層 52 バイアホール導体 53 空隙部 54 電気素子 55 配線コア基板 56 絶縁層 57 バイアホール 58 配線回路層 59 バイアホール導体 60 多層配線層 61 電気素子 50 insulating substrate 51 wiring circuit layer 52 via hole conductor 53 gap portion 54 electric element 55 wiring core substrate 56 insulating layer 57 via holes 58 wiring circuit layer 59 via-hole conductors 60 wiring layer 61 electrical element

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】少なくとも熱硬化性樹脂を含む複数の絶縁層を積層してなる絶縁基板と、該絶縁基板の表面および内部に形成された複数の配線回路層と、前記配線回路層間を接続するためのバイアホール導体を具備するとともに、前記絶縁基板内部に空隙部が形成され、該空隙部内に電気素子を実装収納してなる配線コア基板の表面に、 And 1. A formed by laminating a plurality of insulating layers containing at least a thermosetting resin insulating substrate, a plurality of the wiring circuit layer formed on the surface and inside of the insulating substrate, for connecting the wiring circuit layers as well as including a via-hole conductors for, on the insulating substrate internal void portion is formed on the surface of the wiring core substrate formed by mounting accommodating the electric element into the void portion,
    感光性樹脂を含有する絶縁層と、配線回路層とを順次積層してなる多層配線層を形成し、且つ前記電気素子と前記多層配線層における配線回路層とを電気的に接続されてなることを特徴とする多層配線基板。 An insulating layer containing a photosensitive resin, to form a multilayer wiring layer formed by sequentially stacking a wiring circuit layer, and be electrically connected to the wiring circuit layer in the multilayered wiring layer and the electrical element multilayer wiring substrate according to claim.
  2. 【請求項2】前記空隙部内にて、前記電気素子を金属箔からなる配線回路層に半田実装してなることを特徴とする請求項1記載の多層配線基板。 Wherein in the said gap portion, the multilayer wiring board according to claim 1, wherein said electrical device is characterized by being soldered to the wiring circuit layer made of a metal foil.
  3. 【請求項3】前記配線コア基板におけるバイアホール導体を金属粉末の充填によって形成してなることを特徴とする請求項1記載の多層配線基板。 3. A multilayer wiring board according to claim 1, wherein the via hole conductors in the wiring core substrate is characterized by being formed by filling metal powder.
JP9292766A 1997-10-24 1997-10-24 Multilayered wiring board Pending JPH11126978A (en)

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Cited By (47)

* Cited by examiner, † Cited by third party
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WO2001019149A1 (en) * 1999-09-02 2001-03-15 Ibiden Co., Ltd. Printed wiring board and method of producing the same and capacitor to be contained in printed wiring board
WO2001019148A1 (en) * 1999-09-02 2001-03-15 Ibiden Co., Ltd. Printed wiring board and method of producing the same
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