JP2785444B2 - Semiconductor device, manufacturing method thereof, and electronic circuit device using semiconductor device - Google Patents

Semiconductor device, manufacturing method thereof, and electronic circuit device using semiconductor device

Info

Publication number
JP2785444B2
JP2785444B2 JP2127317A JP12731790A JP2785444B2 JP 2785444 B2 JP2785444 B2 JP 2785444B2 JP 2127317 A JP2127317 A JP 2127317A JP 12731790 A JP12731790 A JP 12731790A JP 2785444 B2 JP2785444 B2 JP 2785444B2
Authority
JP
Japan
Prior art keywords
layer
semiconductor
chip
connection terminal
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2127317A
Other languages
Japanese (ja)
Other versions
JPH0425038A (en
Inventor
恒 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2127317A priority Critical patent/JP2785444B2/en
Publication of JPH0425038A publication Critical patent/JPH0425038A/en
Application granted granted Critical
Publication of JP2785444B2 publication Critical patent/JP2785444B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は広範な電子機器に用いられる半導体装置およ
びその製造方法ならびに半導体装置を用いた電子回路装
置に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for a wide variety of electronic devices, a method for manufacturing the same, and an electronic circuit device using the semiconductor device.

従来の技術 近年、電子機器の小型化や、高性能化,高機能化に対
する要求が増大するに伴い、半導体素子の高密度実装技
術の重要性が益々高まっている。
2. Description of the Related Art In recent years, as the demands for miniaturization, higher performance, and higher functionality of electronic devices have increased, the importance of high-density packaging technology for semiconductor devices has been increasing.

このような中にあって、昨今半導体素子の高密度化を
指向した実装方法としてTAB方式やフリップチップ方式
による実装技術が多く使われるようになってきた。
Under such circumstances, recently, as a mounting method aimed at increasing the density of semiconductor elements, a mounting technique based on a TAB method or a flip chip method has been increasingly used.

一般に、TAB方式はポリイミドフィルムに設けたフィ
ンガー状の銅箔パターン(スズめっきした)と外部接続
端子に金バンプを設けた半導体ICチップを熱圧着してAu
−Snの共晶を形成することによって電気的に接続したも
のである。
In general, the TAB method uses thermocompression bonding between a finger-like copper foil pattern (tin-plated) provided on a polyimide film and a semiconductor IC chip provided with gold bumps on external connection terminals.
It is electrically connected by forming a eutectic of -Sn.

これに対して、フリップチップ法は第4図に示すよう
に、半導体ICチップ21のアルミからなる外部接続端子層
22にTAB法と同様に金やはんだによるバンプ(突起電極
層)23を形成して、この半導体ICチップ21をフェースダ
ウン方式により接続用の回路導体層24を設けた回路基板
25にはんだ26を用いてはんだリフロー法等によって直接
接続したものである。
On the other hand, in the flip chip method, as shown in FIG. 4, the external connection terminal layer made of aluminum of the semiconductor IC chip 21 is formed.
A circuit board 22 on which bumps (projection electrode layers) 23 of gold or solder are formed in the same manner as the TAB method, and the semiconductor IC chip 21 is provided with a circuit conductor layer 24 for connection by a face-down method.
25, a solder 26 is directly connected by solder reflow method or the like.

発明が解決しようとする課題 このような従来の半導体装置およびその製造方法で
は、前者のTAB方式はポリイミドフィルムに形成するイ
ンナーリード用のフィンガー状の銅箔パターンやアウタ
ーリード用の銅箔パターンのピッチ精度が得にくいこと
や、半導体ICチップ21の外部接続端子層22がチップの四
周の端部に沿って構成されなければならないため、接続
端子の数が増大する程チップサイズが大きくなり、高密
度実装化がはかりにくい課題がある。
SUMMARY OF THE INVENTION In such a conventional semiconductor device and a method of manufacturing the same, in the former TAB method, a pitch of a finger-shaped copper foil pattern for an inner lead or a copper foil pattern for an outer lead is formed on a polyimide film. Since the accuracy is difficult to obtain and the external connection terminal layer 22 of the semiconductor IC chip 21 must be formed along the four peripheral edges of the chip, the chip size increases as the number of connection terminals increases, resulting in higher density. There is a problem that it is difficult to implement.

また一方、後者のフリップチップ方式による実装方法
は、半導体ICチップ21の外部接続端子層22が半導体ICチ
ップ21上の任意の位置に構成できるので半導体の回路設
計の自由度が増大し、その外部接続端子層22と実装する
回路基板25の回路導体層24とが直接1対1で接続される
ので、回路の高密度化には好都合であるが、反面実装す
る回路基板25の材料は半導体ICチップ(シリコン)21と
同等の熱膨張係数を有さないと熱衝撃等による電気的接
続の信頼性が確保されにくく、したがってガラスエポキ
シ等の通常のプリント配線板を回路基板材料に使用する
フリップチップ方式では実装できないという課題があっ
た。
On the other hand, the latter flip-chip mounting method increases the degree of freedom in semiconductor circuit design because the external connection terminal layer 22 of the semiconductor IC chip 21 can be configured at an arbitrary position on the semiconductor IC chip 21. Since the connection terminal layer 22 and the circuit conductor layer 24 of the circuit board 25 to be mounted are directly connected one-to-one, it is convenient for increasing the density of the circuit, but the material of the circuit board 25 to be mounted is a semiconductor IC. If the chip (silicon) 21 does not have the same coefficient of thermal expansion, it is difficult to ensure the reliability of electrical connection due to thermal shock and the like. Therefore, a flip chip using a normal printed wiring board such as glass epoxy as a circuit board material There is a problem that it cannot be implemented by the method.

さらに、このフリップチップ方式はフェースダウン方
式により回路基板25に実装されるために実装状態で半導
体ICチップ21と回路基板25の隙間に耐湿性の樹脂を充填
することが極めて困難であり、半導体装置の信頼性、特
に耐湿性を確保することが難しいという課題を有してい
た。
Further, since the flip-chip method is mounted on the circuit board 25 by the face-down method, it is extremely difficult to fill a gap between the semiconductor IC chip 21 and the circuit board 25 with a moisture-resistant resin in a mounted state. Has a problem that it is difficult to secure the reliability, especially the moisture resistance.

本発明は上記課題を解決するもので、一般的に最も広
く用いられているガラスエポキシ等の樹脂系のプリント
配線板に高密度に実装でき、かつ耐湿性や接続の信頼性
に優れた半導体装置およびその製造方法ならびに半導体
装置を用いた電子回路装置を提供することを目的として
いる。
The present invention solves the above-mentioned problems, and is a semiconductor device that can be mounted at high density on a resin-based printed wiring board such as glass epoxy, which is generally most widely used, and has excellent moisture resistance and connection reliability. And an electronic circuit device using the semiconductor device.

課題を解決するための手段 本発明は上記目的を達成するために、凹部を有する硬
質性基板と、その凹部に、表面が同一面になるように埋
め込まれた表面所定部に少なくとも外部接続端子層を設
けた半導体ICチップと、その半導体ICチップの表面およ
び硬質性基板の表面に形成された外部接続端子層に開口
部を有する絶縁樹脂層と、開口部の外部接続端子層を含
む絶縁樹脂層上にパターン形成された回路導体層と、そ
の回路導体層上に形成された所定部に開口部を有する絶
縁性のソルダーレジスト層と、そのソルダーレジスト層
の開口部の回路導体層に形成された突起状の外部電極層
とを有する構成よりなる。
Means for Solving the Problems In order to achieve the above object, the present invention provides a rigid substrate having a concave portion and at least an external connection terminal layer provided on a predetermined surface portion embedded in the concave portion so that the surface is flush with the rigid substrate. A semiconductor IC chip provided with an insulating resin layer having an opening in an external connection terminal layer formed on the surface of the semiconductor IC chip and the surface of the rigid substrate, and an insulating resin layer including the external connection terminal layer in the opening A circuit conductor layer having a pattern formed thereon, an insulating solder resist layer having an opening in a predetermined portion formed on the circuit conductor layer, and a circuit conductor layer formed on the opening of the solder resist layer. It has a configuration having a protruding external electrode layer.

作用 本発明は上記した構成により、半導体ICチップおよび
硬質性基板上に被覆された絶縁樹脂層上の任意の位置に
外部接続端子層を設けることができ、湿度の影響を受け
難くなるとともに、プリント配線板とはんだ層をはさん
で接続しても、熱衝撃による影響を受け難くなる。
Function The present invention can provide an external connection terminal layer at an arbitrary position on an insulating resin layer coated on a semiconductor IC chip and a rigid substrate by the above-described configuration, and is not easily affected by humidity, and can be printed. Even if the wiring board and the solder layer are connected to each other, the connection is hardly affected by the thermal shock.

実施例 以下、本発明の一実施例について第1図,第2図およ
び第3図を参照しながら説明する。
Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3. FIG.

第1図において、1は半導体ICチップ、2は半導体IC
チップ1の外部接続端子層、3は硬質性基板、4は絶縁
樹脂層、5は回路導体層、6は絶縁性のソルダーレジス
ト層、7は突起状の外部電極層である。
In FIG. 1, 1 is a semiconductor IC chip, and 2 is a semiconductor IC.
The external connection terminal layer 3 of the chip 1 is a hard substrate, 4 is an insulating resin layer, 5 is a circuit conductor layer, 6 is an insulating solder resist layer, and 7 is a protruding external electrode layer.

以上のように構成された半導体装置について以下その
製造方法の詳細を説明する。
The manufacturing method of the semiconductor device configured as described above will be described in detail below.

本実施例では、先ず第2図に示すように硬質性基板3
のほぼ中央部に第1図の半導体ICチップ1とほぼ同一の
外形寸法を有する凹部3aを形成し、この凹部3aの中にす
でにダイシング加工により精度良く所定の寸法に切断加
工した半導体ICチップ1をはめ込み表面が硬質性基板3
の表面と同一面になるように接着剤等で固定した。
In the present embodiment, first, as shown in FIG.
A recess 3a having substantially the same outer dimensions as the semiconductor IC chip 1 of FIG. 1 is formed at a substantially central portion of the semiconductor IC chip 1 already cut into a predetermined size by dicing in the recess 3a. With a rigid substrate 3
Was fixed with an adhesive or the like so as to be flush with the surface.

この場合、半導体ICチップ1はその外部接続端子層2
を構成するためアルミニウム電極パッド部分に予めバリ
ヤー金属層としてクロム,チタン,ニッケル,パラジウ
ム等の金属層を真空蒸着法や無電解めっき法等によって
被覆したものや、これらのバリヤー金属層の表面に銅,
金等の金属をめっき法によって突起状に形成したもの、
さらにはパッド上にボールボンディング法によって金や
銅のバンプを直接形成したもの等いろいろな電極構造の
ものを使用した。
In this case, the semiconductor IC chip 1 has its external connection terminal layer 2
In order to compose the aluminum electrode pad portion, a metal layer of chromium, titanium, nickel, palladium or the like is coated as a barrier metal layer in advance by a vacuum deposition method or an electroless plating method, or the surface of the barrier metal layer is coated with copper. ,
A metal such as gold formed into a projection by plating,
Furthermore, various electrode structures such as those in which gold or copper bumps were directly formed on the pads by a ball bonding method were used.

また、この半導体ICチップ1に接する硬質性基板3は
目的に応じていろいろな材質のものを使用した。すなわ
ち熱放散性のよい半導体装置を作る場合には、アルミニ
ウムや銅,ニッケル等の金属を使用してエッチング法や
機械的切削法によりその中央部に半導体ICチップ1をは
めこむ凹部3aを設け、この凹部3aに熱伝導性に優れた接
着剤により半導体ICチップ1を固定した。
The rigid substrate 3 in contact with the semiconductor IC chip 1 was made of various materials depending on the purpose. That is, when manufacturing a semiconductor device having good heat dissipation, a concave portion 3a into which the semiconductor IC chip 1 is to be fitted is provided at the center by etching or mechanical cutting using a metal such as aluminum, copper, or nickel. The semiconductor IC chip 1 was fixed to the recess 3a with an adhesive having excellent thermal conductivity.

さらに熱放散性を考慮しなくてもよい半導体装置の場
合には、高耐熱性を有する熱硬化性樹脂として例えばエ
ポキシ樹脂,トリアジン樹脂等を使用して機械的な切削
法によって部分的に凹部3aを備えた硬質性基板3を作る
か、高耐熱性を有する熱可望性樹脂として、例えばポリ
サルホン樹脂,ポリエーテルサルホン樹脂,ポリフェニ
レンサルファイド樹脂,ポリアミドイミド樹脂,ポリエ
ーテルイミド樹脂,ポリエーテルエーテルケトン樹脂,
ポリイミド樹脂,フッ素樹脂,液晶ポリエステル樹脂等
を使用し、射出成形法によって部分的に凹部3aを備えた
硬質性基板3を作った。
Further, in the case of a semiconductor device which does not need to consider heat dissipation, the concave portion 3a is partially cut by a mechanical cutting method using, for example, an epoxy resin or a triazine resin as a thermosetting resin having high heat resistance. Or a heat-resisting resin having high heat resistance such as polysulfone resin, polyethersulfone resin, polyphenylene sulfide resin, polyamideimide resin, polyetherimide resin, polyetheretherketone. resin,
Using a polyimide resin, a fluorine resin, a liquid crystal polyester resin, or the like, a rigid substrate 3 partially provided with a concave portion 3a was formed by an injection molding method.

そして、これらの部分的に凹部3aを備えた硬質性基板
3に半導体ICチップ1を上向きにして凹部3aに接着した
後で、第1図に示すようにその表面全体に絶縁樹脂層4
をコーティングして硬化させ、半導体ICチップ1の外部
接続端子層2に相当した部分の絶縁樹脂層4を除去し
て、半導体ICチップ1のバリヤー金属層で覆われた外部
接続端子層2を露出させた。
After bonding the semiconductor IC chip 1 to the recess 3a with the semiconductor IC chip 1 facing upward on the rigid substrate 3 partially provided with the recess 3a, as shown in FIG.
Is coated and cured, and the portion of the insulating resin layer 4 corresponding to the external connection terminal layer 2 of the semiconductor IC chip 1 is removed to expose the external connection terminal layer 2 covered with the barrier metal layer of the semiconductor IC chip 1. I let it.

この場合、絶縁樹脂層4は高純度で感光性を有し、か
つ耐熱性と電気絶縁性に優れた樹脂が好ましく、本実施
例ではこの目的に合致した絶縁樹脂として感光性ポリイ
ミド樹脂やエポキシ樹脂,アクリル樹脂等を使用した。
In this case, the insulating resin layer 4 is preferably made of a resin having high purity and photosensitivity, and excellent in heat resistance and electrical insulation. In this embodiment, a photosensitive polyimide resin or epoxy resin is used as an insulating resin meeting this purpose. And acrylic resin.

ついで、この絶縁樹脂層4の表面に真空蒸着法やイオ
ンプレーティング法、さらには無電解めっき法等によっ
て銅やニッケル金属からなる導電金属層を半導体ICチッ
プ1の外部接続端子層2を含む絶縁樹脂層4の全面に成
膜し、ついでフォトエッチング法等によって不要に導電
金属層を溶解除去し、所望とするパターン状に回路導体
層5を形成した後で、このパターン状の回路導体層5の
突起状の外部電極層を形成する部分以外に絶縁性のソル
ダーレジスト層6を被覆し、露出した回路導体層5に選
択的にに銅やニッケル等の金属層を厚付けし、突起状の
外部電極層7を形成して半導体装置を完成させた。
Then, a conductive metal layer made of copper or nickel metal is formed on the surface of the insulating resin layer 4 by vacuum evaporation, ion plating, electroless plating, or the like, including the external connection terminal layer 2 of the semiconductor IC chip 1. After forming a film on the entire surface of the resin layer 4 and then dissolving and removing the conductive metal layer unnecessarily by a photo-etching method or the like to form the circuit conductor layer 5 in a desired pattern, the circuit conductor layer 5 having the pattern Is covered with an insulating solder resist layer 6 except for the portion where the projecting external electrode layer is formed, and a metal layer such as copper or nickel is selectively thickened on the exposed circuit conductor layer 5. The external electrode layer 7 was formed to complete the semiconductor device.

この方法により得られた半導体装置は、その外部電極
層7をソルダーレジスト層6の任意の位置に構成するこ
とができるので、装置の小型化が可能であり、さらには
半導体ICチップ1の表面には絶縁性のソルダーレジスト
層6が被覆された構成になるので特に耐湿信頼性にすぐ
れた半導体装置が得られた。
In the semiconductor device obtained by this method, the external electrode layer 7 can be formed at an arbitrary position on the solder resist layer 6, so that the device can be downsized. Has a configuration in which the insulating solder resist layer 6 is covered, so that a semiconductor device having particularly excellent humidity resistance is obtained.

また、この方法により得られた半導体装置の複数個を
プリント配線板に実装して電子回路装置を構成したもの
の要部断面図を第3図に示した。
FIG. 3 is a sectional view of a main part of an electronic circuit device in which a plurality of semiconductor devices obtained by this method are mounted on a printed wiring board to constitute an electronic circuit device.

第3図において、第1図と同一部分には同一番号を付
し、説明を省略する。すなわち8は電子回路装置、9は
プリント配線板、10はプリント配線板9の回路導体層、
11ははんだ層である。
In FIG. 3, the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. That is, 8 is an electronic circuit device, 9 is a printed wiring board, 10 is a circuit conductor layer of the printed wiring board 9,
11 is a solder layer.

この電子回路装置8は、ガラスエポキシ等の合成樹脂
系基板からなるプリント配線板9と半導体ICチップ1の
表面に被覆した絶縁性のソルダーレジスト層6の開口部
に構成された突起状の外部電極層7がはんだ層11によっ
て接続されたものであるので電子回路装置8の小型,高
密度化とともに熱衝撃等を加えた場合のプリント配線板
9と熱膨張係数の違いによるはんだ接続の信頼性の劣化
がなくなる。
The electronic circuit device 8 includes a printed wiring board 9 made of a synthetic resin-based substrate such as glass epoxy and a protruding external electrode formed in an opening of an insulating solder resist layer 6 covering the surface of the semiconductor IC chip 1. Since the layer 7 is connected by the solder layer 11, the reliability of the solder connection due to the difference in thermal expansion coefficient between the printed circuit board 9 and the thermal expansion coefficient when the electronic circuit device 8 is miniaturized and increased in density and subjected to thermal shock, etc. Deterioration is eliminated.

発明の効果 以上の実施例から明らかなように本発明によれば、凹
部を有する硬質性基板と、その凹部に表面が同一面にな
るように埋め込まれた表面所定部に少なくとも外部接続
端子層等を設けた半導体ICチップと、その半導体ICチッ
プの表面および硬質性基板の表面に形成された上記外部
接続端子層に開口部を有する絶縁樹脂層と、上記開口部
の外部接続端子層を含む上記絶縁樹脂層上にパターン形
成された回路導体層と、その回路導体層上に形成された
所定部に開口部を有する絶縁性のソルダーレジスト層
と、そのソルダーレジスト層の開口部の上記回路導体層
に形成された突起状の外部電極層とを有する構成による
ので、絶縁樹脂層の表面の任意の位置に外部接続端子層
が構成でき、半導体ICチップの表面が絶縁樹脂層で覆わ
れた構造になり、小型で高耐湿の半導体装置を提供でき
る。
Advantages of the Invention As is apparent from the above embodiments, according to the present invention, at least an external connection terminal layer and the like are provided on a hard substrate having a concave portion and a predetermined surface embedded in the concave portion so that the surface is flush with the rigid substrate. A semiconductor IC chip provided with: an insulating resin layer having an opening in the external connection terminal layer formed on the surface of the semiconductor IC chip and the surface of the rigid substrate; and an external connection terminal layer having the opening. A circuit conductor layer having a pattern formed on an insulating resin layer, an insulating solder resist layer having an opening in a predetermined portion formed on the circuit conductor layer, and the circuit conductor layer having an opening in the solder resist layer The external connection terminal layer can be configured at any position on the surface of the insulating resin layer, and the surface of the semiconductor IC chip is covered with the insulating resin layer. What Thus, a small and highly moisture-resistant semiconductor device can be provided.

さらに外部接続端子層が絶縁樹脂層の表面に構成され
るので、この半導体装置をフェースダウン方式によりガ
ラスエポキシ等の樹脂系のプリント配線板に直接はんだ
付け実装して電子回路装置を構成してもプリント配線板
と半導体装置の熱膨張係数が同一であるため熱衝撃試験
で接続の信頼性を損なうことがない電子回路装置を提供
できる。
Further, since the external connection terminal layer is formed on the surface of the insulating resin layer, the semiconductor device can be directly soldered and mounted on a resin-based printed wiring board such as glass epoxy by a face-down method to form an electronic circuit device. Since the printed wiring board and the semiconductor device have the same thermal expansion coefficient, it is possible to provide an electronic circuit device that does not impair the reliability of connection in a thermal shock test.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の一実施例の半導体装置の要部断面図、
第2図は同装置に使用する硬質性基板の斜視図、第3図
は本発明による半導体装置をプリント配線板に実装した
電子回路装置の要部断面図、第4図は従来の半導体装置
の要部断面図である。 1……半導体ICチップ、2……半導体ICチップの外部接
続端子層、3……硬質性基板、3a……硬貸性基板の凹
部、4……絶縁樹脂層、5……回路導体層、6……絶縁
性のソルダーレジスト層、7……突起状の外部電極層。
FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention,
FIG. 2 is a perspective view of a rigid substrate used in the device, FIG. 3 is a sectional view of a main part of an electronic circuit device in which the semiconductor device according to the present invention is mounted on a printed wiring board, and FIG. It is principal part sectional drawing. DESCRIPTION OF SYMBOLS 1 ... Semiconductor IC chip, 2 ... External connection terminal layer of semiconductor IC chip, 3 ... Hard board, 3a ... Recess of hard lending board, 4 ... Insulating resin layer, 5 ... Circuit conductor layer, 6: an insulating solder resist layer; 7: a protruding external electrode layer.

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】凹部を有する硬質性基板と、 前記凹部に表面が同一面になるように埋め込まれた表面
所定部に少なくとも外部接続端子層等を設けた半導体IC
チップと、 その半導体ICチップの表面および前記硬質性基板の表面
に形成された前記外部接続端子層に開口部を有する絶縁
樹脂層と、 前記開口部の外部接続端子層を含む前記絶縁樹脂層上に
パターン形成された回路導体層と、 その回路導体層上に形成された所定部に開口部を有する
絶縁性のソルダーレジスト層と、 そのソルダーレジスト層の開口部の前記回路導体層に形
成された突起状の外部電極層とを有する半導体装置。
1. A semiconductor IC having a hard substrate having a concave portion, and at least an external connection terminal layer provided at a predetermined surface portion embedded in the concave portion so as to have the same surface.
A chip, an insulating resin layer having an opening in the external connection terminal layer formed on the surface of the semiconductor IC chip and the surface of the hard substrate, and on the insulating resin layer including the external connection terminal layer in the opening A circuit conductor layer patterned on the circuit conductor layer, an insulating solder resist layer having an opening in a predetermined portion formed on the circuit conductor layer, and an insulating solder resist layer formed on the circuit conductor layer in the opening of the solder resist layer. A semiconductor device having a protruding external electrode layer.
【請求項2】一主面の所定部に少なくとも外部接続端子
層を設けた半導体ICチップを前記一主面を上向きにし
て、その一主面と凹部を有する硬質性基板の表面が同一
面になるように、前記凹部に埋め込み固着する工程と、 前記同一面の半導体ICチップの表面および硬質性基板の
表面に前記外部接続端子層上の開口部を除いて絶縁樹脂
層をパターン形成する工程と、 前記開口部の外部接続端子層を含む前記絶縁樹脂層上に
回路導体層をパターン形成する工程と、 その回路導体層上の所定部に開口部を有する絶縁性のソ
ルダーレジスト層をパターン形成する工程と、 そのソルダーレジスト層の開口部の前記回路導体層上に
突起状の外部電極層を形成する工程とを有する半導体装
置の製造方法。
2. A semiconductor IC chip having at least an external connection terminal layer provided on a predetermined portion of one main surface with the one main surface facing upward, and the one main surface and the surface of a hard substrate having a concave portion are flush with each other. A step of embedding and fixing in the recess, and a step of patterning an insulating resin layer on the surface of the semiconductor IC chip on the same surface and the surface of the hard substrate except for an opening on the external connection terminal layer. Patterning a circuit conductor layer on the insulating resin layer including the external connection terminal layer in the opening; and patterning an insulating solder resist layer having an opening in a predetermined portion on the circuit conductor layer. A method for manufacturing a semiconductor device, comprising: a step of forming a protruding external electrode layer on the circuit conductor layer in an opening of the solder resist layer.
【請求項3】請求項(1)記載の半導体装置の突起状の
外部電極層をプリント配線板上にパターン形成された回
路導体層にはんだ層を介して接続した電子回路装置。
3. An electronic circuit device according to claim 1, wherein the protruding external electrode layer of the semiconductor device is connected to a circuit conductor layer patterned on a printed wiring board via a solder layer.
JP2127317A 1990-05-16 1990-05-16 Semiconductor device, manufacturing method thereof, and electronic circuit device using semiconductor device Expired - Fee Related JP2785444B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2127317A JP2785444B2 (en) 1990-05-16 1990-05-16 Semiconductor device, manufacturing method thereof, and electronic circuit device using semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2127317A JP2785444B2 (en) 1990-05-16 1990-05-16 Semiconductor device, manufacturing method thereof, and electronic circuit device using semiconductor device

Publications (2)

Publication Number Publication Date
JPH0425038A JPH0425038A (en) 1992-01-28
JP2785444B2 true JP2785444B2 (en) 1998-08-13

Family

ID=14956948

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2785444B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878472A (en) * 1994-09-05 1996-03-22 Hitachi Cable Ltd Semiconductor device and base body therefor
JP3196758B2 (en) * 1999-03-08 2001-08-06 ソニー株式会社 Lead frame, method of manufacturing lead frame, semiconductor device, and method of manufacturing semiconductor device
EP1990833A3 (en) 2000-02-25 2010-09-29 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
JP4931283B2 (en) * 2000-09-25 2012-05-16 イビデン株式会社 Printed wiring board and printed wiring board manufacturing method
EP1321980A4 (en) 2000-09-25 2007-04-04 Ibiden Co Ltd Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
JP4785268B2 (en) * 2000-12-15 2011-10-05 イビデン株式会社 Multilayer printed wiring board with built-in semiconductor elements
JP4771608B2 (en) * 2000-12-15 2011-09-14 イビデン株式会社 Printed wiring board
JP4480710B2 (en) * 2006-12-04 2010-06-16 Okiセミコンダクタ株式会社 Semiconductor device embedded substrate
JP5089660B2 (en) * 2009-07-27 2012-12-05 ラピスセミコンダクタ株式会社 Manufacturing method of semiconductor device embedded substrate

Also Published As

Publication number Publication date
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