JPH0425038A - Semiconductor device and manufacture of the same and electronic circuit utilizing the semiconductor device - Google Patents
Semiconductor device and manufacture of the same and electronic circuit utilizing the semiconductor deviceInfo
- Publication number
- JPH0425038A JPH0425038A JP2127317A JP12731790A JPH0425038A JP H0425038 A JPH0425038 A JP H0425038A JP 2127317 A JP2127317 A JP 2127317A JP 12731790 A JP12731790 A JP 12731790A JP H0425038 A JPH0425038 A JP H0425038A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- circuit conductor
- chip
- solder resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title description 5
- 239000011347 resin Substances 0.000 claims abstract description 40
- 229920005989 resin Polymers 0.000 claims abstract description 40
- 229910000679 solder Inorganic materials 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 18
- 238000000059 patterning Methods 0.000 claims 3
- 229910052751 metal Inorganic materials 0.000 abstract description 12
- 239000002184 metal Substances 0.000 abstract description 12
- 238000000034 method Methods 0.000 description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 230000035939 shock Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- -1 polyphenylene sulfite Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000004696 Poly ether ether ketone Substances 0.000 description 1
- 239000004962 Polyamide-imide Substances 0.000 description 1
- 239000004695 Polyether sulfone Substances 0.000 description 1
- 239000004697 Polyetherimide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920002492 poly(sulfone) Polymers 0.000 description 1
- 229920002312 polyamide-imide Polymers 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920006393 polyether sulfone Polymers 0.000 description 1
- 229920002530 polyetherether ketone Polymers 0.000 description 1
- 229920001601 polyetherimide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は広範な電子機器に用いられる半導体装置および
その製造方法ならびに半導体装置を用いた電子回路装置
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device used in a wide variety of electronic devices, a method for manufacturing the same, and an electronic circuit device using the semiconductor device.
従来の技術
近年、電子機器の小型化や、高性能化、高機能化に対す
る要求が増大するに伴い、半導体素子の高密度実装技術
の重要性が益々高まっている。BACKGROUND OF THE INVENTION In recent years, as demands for smaller electronic devices, higher performance, and higher functionality have increased, high-density packaging technology for semiconductor elements has become increasingly important.
このような中にあって、昨今半導体素子の高密度化を指
向した実装方法としてＴＡＢ方式やフリップチップ方式
による実装技術が多く使われるようになってきた。Under these circumstances, mounting techniques such as the TAB method and the flip-chip method have recently come into widespread use as mounting methods aimed at increasing the density of semiconductor elements.
一般に、ＴＡＢ方式はポリイミドフィルムに設けたフィ
ンガー状の銅箔パターン（スズめっきした〉と外部接続
端子に金バンプを設けた半導体ＩＣチップを熱圧着して
Ａｕ−３ｎの共晶を形成することによって電気的に接続
したものである。In general, the TAB method uses a finger-shaped copper foil pattern (tin-plated) provided on a polyimide film and a semiconductor IC chip with gold bumps provided on external connection terminals to be thermocompressed to form an Au-3n eutectic. It is electrically connected.
これに対して、フリップチップ法は第４図に示すように
、半導体ＩＣチップ２］のアルミからなる外部接続端子
層２２にＴＡＢ法と同様に金やはんだによるバンブ（突
起電極層）２３を形成して、この半導体ＩＣチップ２１
をフェースダウン方式により接続用の回路導体層２４を
設けた回路基板２５にはんだ２６を用いてはんだリフロ
ー法等によって直接接続したものである。On the other hand, in the flip-chip method, as shown in FIG. 4, bumps (protruding electrode layers) 23 made of gold or solder are formed on the external connection terminal layer 22 made of aluminum of the semiconductor IC chip 2, similar to the TAB method. Then, this semiconductor IC chip 21
is directly connected face-down to a circuit board 25 provided with a circuit conductor layer 24 for connection using a solder 26 by a solder reflow method or the like.
発明が解決しようとする課題
このような従来の半導体装置およびその製造方法では、
前者のＴＡＢ方式はポリイミドフィルムに形成するイン
ナーリード用のフィンカー状の銅箔パターンやアウター
リード用の銅箔パターンのピッチ精度が得にくいことや
、半導体ＩＣチップ２１の外部接続端子層２２がチップ
の四周の端部に沿って構成されなければならないため、
接続端子の数が増大する程チップサイズが大きくなり、
高密度実装化がはかりに（い課題がある。Problems to be Solved by the Invention In such a conventional semiconductor device and its manufacturing method,
In the former TAB method, it is difficult to obtain the pitch accuracy of the finker-like copper foil pattern for the inner lead and the copper foil pattern for the outer lead formed on the polyimide film, and the external connection terminal layer 22 of the semiconductor IC chip 21 is Because it must be constructed along the edges of the four circumferences,
As the number of connection terminals increases, the chip size increases.
High-density packaging poses challenges.
また一方、後者のフリップチップ方式による実装方法は
、半導体ＩＣチップ２１の外部接続端子層２２が半導体
ＩＣチップ２１上の任意の位置に構成できるので半導体
の回路設計の自由度が増大し、その外部接続端子層２２
と実装する回路基板２５の回路導体層２４とが直接１対
１で接続されるので、回路の高密度化には好都合である
が、反面実装する回路基板２５の材料は半導体ＩＣチッ
プ（シリコン）２１と同等の熱膨張係数を有さないと熱
衝撃等による電気的接続の信頼性が確保されにくく、し
たがってガラスエポキシ等の通常のプリント配線板を回
路基板材料に使用するフリップチップ方式では実装でき
ないという課題があった。On the other hand, in the latter flip-chip mounting method, the external connection terminal layer 22 of the semiconductor IC chip 21 can be configured at any position on the semiconductor IC chip 21, which increases the degree of freedom in semiconductor circuit design. Connection terminal layer 22
Since there is a direct one-to-one connection between the circuit board 25 and the circuit conductor layer 24 of the circuit board 25 to be mounted, it is convenient for increasing the density of the circuit, but on the other hand, the material of the circuit board 25 to be mounted is a semiconductor IC chip (silicon). If it does not have a coefficient of thermal expansion equivalent to that of 21, it will be difficult to ensure the reliability of electrical connections due to thermal shock, etc., and therefore it cannot be mounted using the flip-chip method, which uses ordinary printed wiring boards such as glass epoxy as the circuit board material. There was a problem.
さらに、このフリップチップ方式はフェースダウン方式
により回路基板２５に実装されるために実装状態で半導
体ＩＣチップ２１と回路基板２５の隙間に耐湿性の樹脂
を充填することが極めて困難であり、半導体装置の信頼
性、特に耐湿性を確保することが難しいという課題を有
していた。Furthermore, since this flip-chip method is mounted on the circuit board 25 by a face-down method, it is extremely difficult to fill the gap between the semiconductor IC chip 21 and the circuit board 25 with moisture-resistant resin in the mounted state, and the semiconductor device The problem was that it was difficult to ensure reliability, especially moisture resistance.
本発明は上記課題を解決するもので、一般的に最も広く
用いられているカラスエポキシ等の樹脂系のプリント配
線板に高密度に実装でき、かつ耐湿性や接続の信頼性に
優れた半導体装置およびその製造方法ならびに半導体装
置を用いた電子回路装置を提供することを目的としてい
る。The present invention solves the above problems, and is a semiconductor device that can be mounted at high density on printed wiring boards made of resin such as glass epoxy, which is the most widely used semiconductor device, and has excellent moisture resistance and connection reliability. It is an object of the present invention to provide a method for manufacturing the same, and an electronic circuit device using the semiconductor device.
課題を解決するための手段
本発明は上記目的を達成するために、凹部を有する硬質
性基板と、その凹部に、表面が同一面になるように埋め
込まれた表面所定部に少なくとも外部接続端子層を設け
た半導体ＩＣチップと、その半導体ＩＣチップの表面お
よび硬質性基板の表面に形成された外部接続端子層に開
口部を有する絶縁樹脂層と、開口部の外部接続端子層を
含む絶縁樹脂層上にパターン形成された回路導体層と、
その回路導体層上に形成された所定部に開口部を有する
絶縁性のソルダーレジスト層と、そのソルダーレジスト
層の開口部の回路導体層に形成された突起状の外部電極
層とを有する構成よりなる。Means for Solving the Problems In order to achieve the above object, the present invention provides a rigid substrate having a recess, and at least an external connection terminal layer embedded in the recess so that the surfaces thereof are flush with each other in a predetermined portion of the surface. an insulating resin layer having an opening in an external connection terminal layer formed on the surface of the semiconductor IC chip and a surface of a rigid substrate, and an insulating resin layer including the external connection terminal layer in the opening. a circuit conductor layer patterned thereon;
A structure including an insulating solder resist layer formed on the circuit conductor layer and having an opening at a predetermined portion, and a protruding external electrode layer formed on the circuit conductor layer at the opening of the solder resist layer. Become.
作用
本発明は」１記した構成により、半導体ＩＣチップおよ
び硬質性基板」−に被覆された絶縁樹脂層上の任意の位
置に外部接続端子層を設けることができ、湿度の影響を
受は難くなるとともに、プリント配線板とはんだ層をは
さんで接続しても、熱衝撃による影響を受は難（なる。Effect of the present invention With the configuration described in 1., an external connection terminal layer can be provided at any position on an insulating resin layer coated on a semiconductor IC chip and a rigid substrate, and is hardly affected by humidity. At the same time, it is difficult to be affected by thermal shock even if the printed wiring board and the solder layer are connected together.
実施例
以下、本発明の一実施例について第１図、第２図および
第３図を参照しながら説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1, 2, and 3.
第１図において、１は半導体ＩＣチップ、２は半導体Ｉ
Ｃデツプｌの外部接続端子層、３は硬質性基板、４は絶
縁樹脂層、５は回路導体層、６は絶縁性のソルダーレジ
スト層、７は突起状の外部電極層である。In FIG. 1, 1 is a semiconductor IC chip, 2 is a semiconductor I
The external connection terminal layer of the C depth l, 3 is a rigid substrate, 4 is an insulating resin layer, 5 is a circuit conductor layer, 6 is an insulating solder resist layer, and 7 is a protruding external electrode layer.
以上のように構成された半導体装置について以下その製
造方法の詳細を説明する。The details of the manufacturing method for the semiconductor device configured as described above will be explained below.
本実施例では、先ず第２図に示すように硬質性基板３の
ほぼ中央部に第１図の半導体ＩＣチップ１とほぼ同一の
外形寸法を有する凹部３ａを形成し、この凹部３ａの中
にすてにダイシング加工により精度良く所定の寸法に切
断加工した半導体ＩＣチップ１をはめ込み表面が硬質性
基板３の表面と同一面になるように接着剤等で固定した
。In this embodiment, first, as shown in FIG. 2, a recess 3a having approximately the same external dimensions as the semiconductor IC chip 1 shown in FIG. The semiconductor IC chip 1, which had been cut to a predetermined size with high precision by dicing, was fitted and fixed with an adhesive or the like so that its surface was flush with the surface of the hard substrate 3.
この場合、半導体ＩＣチップ１はその外部接続端子層２
を構成するめアルミニウム電極パッド部分に予めバリヤ
ー金属層としてクロム、チタン。In this case, the semiconductor IC chip 1 has its external connection terminal layer 2
The aluminum electrode pad part is pre-coated with chromium and titanium as a barrier metal layer.
ニッケル、パラジウム等の金属層を真空蒸着法や無電解
めっき法等によって被覆したものや、これらのバリヤー
金属層の表面に銅、金等の金属をめっき法によって突起
状に形成したもの、さらにはパッド上にポールボンディ
ング法によって金や銅のバンプを直接形成したもの等い
ろいろな電極構造のものを使用した。Those coated with a metal layer such as nickel or palladium by vacuum evaporation or electroless plating, or those in which metal such as copper or gold is formed into protrusions on the surface of these barrier metal layers by plating, and Various electrode structures were used, including those in which gold or copper bumps were directly formed on pads by pole bonding.
また、この半導体ＩＣチップ１に接する硬質性基板３は
目的に応じているいろな材質のものを使用した。すなわ
ち熱放散性のよい半導体装置を作る場合には、アルミニ
ウムや銅、ニッケル等の金属を使用してエツチング法や
機械的切削法によりその中央部に半導体ＩＣチップ１を
はめこむ凹部３ａを設け、この凹部３ａに熱伝導性に優
れた接着剤により半導体ＩＣチップ１を固定した。Furthermore, the rigid substrate 3 in contact with the semiconductor IC chip 1 was made of various materials depending on the purpose. That is, when making a semiconductor device with good heat dissipation, a recess 3a into which the semiconductor IC chip 1 is fitted is formed in the center of a metal such as aluminum, copper, or nickel by etching or mechanical cutting. The semiconductor IC chip 1 was fixed to this recess 3a with an adhesive having excellent thermal conductivity.
さらに熱放散性を考慮しなくてもよい半導体装置の場合
には、高耐熱性を有する熱硬化性樹脂として例えばエポ
キシ樹脂、トリアジン樹脂等を使用して機械的な切削法
によって部分的に凹部３ａを備えた硬質性基板３を作る
か、高耐熱性を有する熱硬化性樹脂として、例えばポリ
ザルホン樹脂、ポリエーテルサルホン樹脂、ポリフェニ
レンザルファイト樹脂、ポリアミドイミド樹脂、ポリエ
ーテルイミド樹脂、ポリエーテルエーテルケトン樹脂、
ポリイミド樹脂、フッ素樹脂、液晶ポリエステル樹脂等
を使用し、射出成形法によって部分的に凹部３ａを備え
た硬質性基板３を作った。Furthermore, in the case of a semiconductor device that does not require consideration of heat dissipation, a thermosetting resin having high heat resistance such as epoxy resin or triazine resin is used to partially form the recess 3a by mechanical cutting. or use a thermosetting resin with high heat resistance, such as polysulfone resin, polyethersulfone resin, polyphenylene sulfite resin, polyamideimide resin, polyetherimide resin, polyetheretherketone. resin,
A rigid substrate 3 partially provided with recesses 3a was made by injection molding using polyimide resin, fluororesin, liquid crystal polyester resin, or the like.
そして、これらの部分的に凹部３ａを備えた硬質性基板
３に半導体ＩＣチップ１を上向きにして凹部３ａに接着
した後で、第１図に示すようにその表面全体に絶縁樹脂
層４をコーティングして硬化させ、半導体ＩＣチップ１
の外部接続端子層２に相当した部分の絶縁樹脂層４を除
去して、半導体ＩＣチップ１のバリヤー金属層で覆われ
た外部接続端子層２を露出させた。After adhering the semiconductor IC chip 1 upward to the hard substrate 3 partially provided with the recesses 3a, the entire surface is coated with an insulating resin layer 4 as shown in FIG. and harden the semiconductor IC chip 1.
A portion of the insulating resin layer 4 corresponding to the external connection terminal layer 2 was removed to expose the external connection terminal layer 2 covered with the barrier metal layer of the semiconductor IC chip 1.
この場合、絶縁樹脂層４は高純度で感光性を有し、かつ
耐熱性と電気絶縁性に優れた樹脂が好ましく、本実施例
ではこの目的に合致した絶縁樹脂として感光性ポリイミ
ド樹脂やエポキシ樹脂、アクリル樹脂等を使用した。In this case, the insulating resin layer 4 is preferably made of a resin that is highly pure, photosensitive, and has excellent heat resistance and electrical insulation.In this embodiment, photosensitive polyimide resin or epoxy resin is used as an insulating resin that meets this purpose. , acrylic resin, etc. were used.
ついで、この絶縁樹脂層４の表面に真空蒸着法やイオン
ブレーティング法、さらには無電解めっき法等によって
銅やニッケル金属からなる導電金属層を半導体ＩＣチッ
プ１の外部接続端子層２を含む絶縁樹脂層４の全面に成
膜し、ついてフォトエツチング法等によって不要に導電
金属層を溶解除去し、所望とするパターン状に回路導体
層５を形成した後で、このパターン状の回路導体層５の
突起状の外部電極層を形成する部分ν外に絶縁性のソル
ダーレジスト層６を被覆し、露出した回路導体層５に選
択的にに鋼やニッケル等の金属層を厚付けし、突起状の
外部電極層７を形成して半導体装置を完成させた。Next, a conductive metal layer made of copper or nickel metal is applied to the surface of the insulating resin layer 4 by vacuum evaporation, ion blating, electroless plating, etc. to insulate the surface of the insulating resin layer 4, including the external connection terminal layer 2 of the semiconductor IC chip 1. After forming a film on the entire surface of the resin layer 4 and removing unnecessary conductive metal layers by photoetching or the like to form a circuit conductor layer 5 in a desired pattern, this patterned circuit conductor layer 5 is formed. An insulating solder resist layer 6 is coated on the outside of the part ν where the protruding external electrode layer is formed, and a thick metal layer such as steel or nickel is selectively applied to the exposed circuit conductor layer 5. The external electrode layer 7 was formed to complete the semiconductor device.
この方法により得られた半導体装置は、その外部電極層
７をソルダーレジスト層６の任意の位置に構成すること
ができるので、装置の小型化が可能であり、さらには半
導体ＩＣチップ１の表面には絶縁性のソルダーレジスト
層６が被覆された構成になるので特に耐湿信頼性にすぐ
れた半導体装置か得られた。In the semiconductor device obtained by this method, the external electrode layer 7 can be formed at an arbitrary position on the solder resist layer 6, so that the device can be miniaturized. Since the semiconductor device is coated with an insulating solder resist layer 6, a semiconductor device having particularly excellent moisture resistance and reliability can be obtained.
また、この方法により得られた半導体装置の複数個をプ
リント配線板に実装して電子回路装置を構成したものの
要部断面図を第３図に示した。Further, FIG. 3 shows a cross-sectional view of essential parts of an electronic circuit device constructed by mounting a plurality of semiconductor devices obtained by this method on a printed wiring board.
第３図において、第１図と同一部分には同一番号を付し
、説明を省略する。すなわち８は電子回路装置、９はプ
リント配線板、１０はプリント配線板９の回路導体層、
１１ははんだ層である。In FIG. 3, parts that are the same as those in FIG. 1 are given the same numbers and their explanations will be omitted. That is, 8 is an electronic circuit device, 9 is a printed wiring board, 10 is a circuit conductor layer of the printed wiring board 9,
11 is a solder layer.
この電子回路装置８は、カラスエポキシ等の合成樹脂系
基板からなるプリント配線板９と半導体ＩＣチップ］の
表面に被覆した絶縁性のソルダーレジスト層６の開口部
に構成された突起状の外部電極層７がはんだ層１１によ
って接続されたものであるので電子回路装置８の小型、
高密度化とともに熱衝撃等を加えた場合のプリント配線
板９との熱膨張係数の違いによるはんだ接続の信頼性の
劣化がなくなる。This electronic circuit device 8 includes a printed wiring board 9 made of a synthetic resin substrate such as glass epoxy, and a semiconductor IC chip. Since the layers 7 are connected by the solder layer 11, the size of the electronic circuit device 8 can be reduced.
As the density increases, the reliability of solder connections will not deteriorate due to the difference in thermal expansion coefficient with the printed wiring board 9 when thermal shock or the like is applied.
発明の効果
以上の実施例から明らかなように本発明によれば、凹部
を有する硬質性基板と、その凹部に表面が同一面になる
ように埋め込まれた表面所定部に少なくとも外部接続端
子層を設けた半導体ＩＣチップと、その半導体ＩＣチッ
プの表面および硬質性基板の表面に形成された上記外部
接続端子層に開口部を有する絶縁樹脂層と、上記開口部
の外部接続端子層を含む上記絶縁樹脂層上にパターン形
成された回路導体層と、その回路導体層上に形成された
所定部に開口部を有する絶縁性のソルダーレジスト層と
、そのソルダーレジスト層の開口部の上記回路導体層に
形成された突起状の外部電極層とを有する構成によるの
で、絶縁樹脂層の表面の任意の位置に外部接続端子層が
構成でき、半導体ＩＣチップの表面が絶縁樹脂層で覆わ
れた構造になり、小型で高耐湿の半導体装置を提供でき
る。Effects of the Invention As is clear from the above embodiments, the present invention includes a rigid substrate having a recess, and at least an external connection terminal layer on a predetermined portion of the surface embedded in the recess so that the surfaces thereof are flush with each other. the provided semiconductor IC chip, an insulating resin layer having an opening in the external connection terminal layer formed on the surface of the semiconductor IC chip and the surface of the rigid substrate, and the insulation resin layer including the external connection terminal layer in the opening. A circuit conductor layer patterned on the resin layer, an insulating solder resist layer formed on the circuit conductor layer and having openings at predetermined portions, and the circuit conductor layer in the openings of the solder resist layer. Since the structure includes a protruding external electrode layer, an external connection terminal layer can be formed at any position on the surface of the insulating resin layer, and the surface of the semiconductor IC chip is covered with the insulating resin layer. , it is possible to provide a small and highly moisture resistant semiconductor device.
さらに外部接続端子層が絶縁樹脂層の表面に構成される
ので、この半導体装置をフェースダウン方式によりガラ
スエポキシ等の樹脂系のプリント配線板に直接はんだ付
は実装して電子回路装置を構成してもプリント配線板と
半導体装置の熱膨張係数か同一であるため熱衝撃試験で
接続の信頼性を損なうことがない電子回路装置を提供で
きる。Furthermore, since the external connection terminal layer is formed on the surface of the insulating resin layer, this semiconductor device can be mounted face-down on a resin-based printed wiring board such as glass epoxy by direct soldering to form an electronic circuit device. Since the thermal expansion coefficients of the printed wiring board and the semiconductor device are the same, it is possible to provide an electronic circuit device that does not impair connection reliability in a thermal shock test.
第１図は本発明の一実施例の半導体装置の要部断面図、
第２図は同装置に使用する硬質性基板の斜視図、第３図
は本発明による半導体装置をプリント配線板に実装した
電子回路装置の要部断面図、第４図は従来の半導体装置
の要部断面図である。
１・・・・・・半導体ＩＣデツプ、２・・・・・・半導
体ＩＣチップの外部接続端子層、３・・・・・・硬質性
基板、３ａ・・・・・・硬貨性基板の凹部、４・・・・
・・絶縁樹脂層、５・・・・・・回路導体層、６・・・
・・・絶縁性のソルダーレジスト層、７・・・・・・突
起状の外部電極層。FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention;
Fig. 2 is a perspective view of a rigid substrate used in the device, Fig. 3 is a sectional view of main parts of an electronic circuit device in which a semiconductor device according to the present invention is mounted on a printed wiring board, and Fig. 4 is a diagram of a conventional semiconductor device. It is a sectional view of the main part. 1... Semiconductor IC depth, 2... External connection terminal layer of semiconductor IC chip, 3... Rigid substrate, 3a... Recessed portion of coin substrate. , 4...
...Insulating resin layer, 5...Circuit conductor layer, 6...
...Insulating solder resist layer, 7...Protruding external electrode layer.
Claims (3)
所定部に少なくとも外部接続端子層等を設けた半導体Ｉ
Ｃチップと、 その半導体ＩＣチップの表面および前記硬質性基板の表
面に形成された前記外部接続端子層に開口部を有する絶
縁樹脂層と、 前記開口部の外部接続端子層を含む前記絶縁樹脂層上に
パターン形成された回路導体層と、その回路導体層上に
形成された所定部に開口部を有する絶縁性のソルダーレ
ジスト層と、そのソルダーレジスト層の開口部の前記回
路導体層に形成された突起状の外部電極層とを有する半
導体装置。(1) A hard substrate having a concave portion, and a semiconductor I having at least an external connection terminal layer, etc. on a predetermined portion of the surface embedded in the concave portion so that the surfaces thereof are flush with each other.
C chip; an insulating resin layer having an opening in the external connection terminal layer formed on the surface of the semiconductor IC chip and the surface of the rigid substrate; and the insulating resin layer including the external connection terminal layer in the opening. A circuit conductor layer with a pattern formed thereon, an insulating solder resist layer formed on the circuit conductor layer and having an opening at a predetermined portion, and a circuit conductor layer formed in the opening of the solder resist layer. A semiconductor device having a protruding external electrode layer.
けた半導体ＩＣチップを前記一主面を上向きにして、そ
の一主面と凹部を有する硬質性基板の表面が同一面にな
るように、前記凹部に埋め込み固着する工程と、 前記同一面の半導体ＩＣチップの表面および硬質性基板
の表面に前記外部接続端子層上の開口部を除いて絶縁樹
脂層をパターン形成する工程と、 前記開口部の外部接続端子層を含む前記絶縁樹脂層上に
回路導体層をパターン形成する工程と、 その回路導体層上の所定部に開口部を有する絶縁性のソ
ルダーレジスト層をパターン形成する工程と、 そのソルダーレジスト層の開口部の前記回路導体層上に
突起状の外部電極層を形成する工程とを有する半導体装
置の製造方法。(2) A semiconductor IC chip with at least an external connection terminal layer provided on a predetermined portion of one principal surface is placed with the one principal surface facing upward, and the one principal surface and the surface of the hard substrate having the recess are flush with each other. a step of embedding and fixing in the concave portion; a step of patterning an insulating resin layer on the surface of the semiconductor IC chip and the surface of the rigid substrate on the same surface except for the openings above the external connection terminal layer; a step of patterning a circuit conductor layer on the insulating resin layer including an external connection terminal layer at an opening; a step of patterning an insulating solder resist layer having an opening at a predetermined portion on the circuit conductor layer; and forming a protruding external electrode layer on the circuit conductor layer in the opening of the solder resist layer.
極層をプリント配線板上にパターン形成された回路導体
層にはんだ層を介して接続した電子回路装置。(3) An electronic circuit device in which the protruding external electrode layer of the semiconductor device according to claim (1) is connected to a circuit conductor layer patterned on a printed wiring board via a solder layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2127317A JP2785444B2 (en) | 1990-05-16 | 1990-05-16 | Semiconductor device, manufacturing method thereof, and electronic circuit device using semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2127317A JP2785444B2 (en) | 1990-05-16 | 1990-05-16 | Semiconductor device, manufacturing method thereof, and electronic circuit device using semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0425038A true JPH0425038A (en) | 1992-01-28 |
| JP2785444B2 JP2785444B2 (en) | 1998-08-13 |
Family
ID=14956948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2127317A Expired - Fee Related JP2785444B2 (en) | 1990-05-16 | 1990-05-16 | Semiconductor device, manufacturing method thereof, and electronic circuit device using semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2785444B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0878472A (en) * | 1994-09-05 | 1996-03-22 | Hitachi Cable Ltd | Semiconductor device and base body therefor |
| JPH11288983A (en) * | 1999-03-08 | 1999-10-19 | Sony Corp | Lead frame, manufacture of the lead frame, semiconductor device and manufacture of the semiconductor device |
| JP2002170840A (en) * | 2000-09-25 | 2002-06-14 | Ibiden Co Ltd | Manufacturing method of semiconductor device and multi-layer printed circuit board including the same |
| JP2002246761A (en) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | Multilayer printed circuit board containing semiconductor elements |
| JP2002246758A (en) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | Printed-wiring board |
| JP2007059950A (en) * | 2006-12-04 | 2007-03-08 | Oki Electric Ind Co Ltd | Substrate with built-in semiconductor device, and method for manufacturing the same |
| JP2009246397A (en) * | 2009-07-27 | 2009-10-22 | Oki Semiconductor Co Ltd | Method for manufacturing substrate with built-in semiconductor device |
| US7842887B2 (en) | 2000-02-25 | 2010-11-30 | Ibiden Co., Ltd. | Multilayer printed circuit board |
| US7852634B2 (en) | 2000-09-25 | 2010-12-14 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
-
1990
- 1990-05-16 JP JP2127317A patent/JP2785444B2/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0878472A (en) * | 1994-09-05 | 1996-03-22 | Hitachi Cable Ltd | Semiconductor device and base body therefor |
| JPH11288983A (en) * | 1999-03-08 | 1999-10-19 | Sony Corp | Lead frame, manufacture of the lead frame, semiconductor device and manufacture of the semiconductor device |
| US8438727B2 (en) | 2000-02-25 | 2013-05-14 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
| US8186045B2 (en) | 2000-02-25 | 2012-05-29 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
| US7842887B2 (en) | 2000-02-25 | 2010-11-30 | Ibiden Co., Ltd. | Multilayer printed circuit board |
| US7908745B2 (en) | 2000-09-25 | 2011-03-22 | Ibiden Co., Ltd. | Method of manufacturing multi-layer printed circuit board |
| JP2002170840A (en) * | 2000-09-25 | 2002-06-14 | Ibiden Co Ltd | Manufacturing method of semiconductor device and multi-layer printed circuit board including the same |
| US7999387B2 (en) | 2000-09-25 | 2011-08-16 | Ibiden Co., Ltd. | Semiconductor element connected to printed circuit board |
| US7852634B2 (en) | 2000-09-25 | 2010-12-14 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
| US7855342B2 (en) | 2000-09-25 | 2010-12-21 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
| US7893360B2 (en) | 2000-09-25 | 2011-02-22 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
| JP2002246761A (en) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | Multilayer printed circuit board containing semiconductor elements |
| JP2002246758A (en) * | 2000-12-15 | 2002-08-30 | Ibiden Co Ltd | Printed-wiring board |
| JP2007059950A (en) * | 2006-12-04 | 2007-03-08 | Oki Electric Ind Co Ltd | Substrate with built-in semiconductor device, and method for manufacturing the same |
| JP2009246397A (en) * | 2009-07-27 | 2009-10-22 | Oki Semiconductor Co Ltd | Method for manufacturing substrate with built-in semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2785444B2 (en) | 1998-08-13 |
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