JP3639514B2 - Circuit device manufacturing method - Google Patents

Circuit device manufacturing method Download PDF

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Publication number
JP3639514B2
JP3639514B2 JP2000266685A JP2000266685A JP3639514B2 JP 3639514 B2 JP3639514 B2 JP 3639514B2 JP 2000266685 A JP2000266685 A JP 2000266685A JP 2000266685 A JP2000266685 A JP 2000266685A JP 3639514 B2 JP3639514 B2 JP 3639514B2
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Prior art keywords
conductive
conductive path
conductive foil
separation groove
insulating resin
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JP2002076245A (en
Inventor
則明 坂本
義幸 小林
純次 阪本
茂明 真下
克実 大川
栄寿 前原
幸嗣 高橋
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority to JP2000266685A priority Critical patent/JP3639514B2/en
Priority to CNB011123885A priority patent/CN1244258C/en
Priority to TW090103348A priority patent/TW486920B/en
Priority to KR10-2001-0007482A priority patent/KR100400629B1/en
Priority to US09/810,110 priority patent/US6545364B2/en
Priority to EP01302580A priority patent/EP1187204A3/en
Publication of JP2002076245A publication Critical patent/JP2002076245A/en
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

PURPOSE: To solve the problem of a circuit device mounting a circuit element using a printed board, a ceramic board or a flexible board as a supporting board, where the supporting board is an essentially unnecessary and extra material, and the size of the circuit device is increased by the thickness of the supporting board. CONSTITUTION: After an isolation trench 54 is made in a conductive foil 60, a circuit device is flip-chip mounted and applied with insulating resin 50 using the conductive foil 60 as a support board. It is then turned over and the conductive, foil is polished using the insulating resin 50 as a supporting board and isolated as a conductive path. A circuit device, where the conductive path 51 and a circuit element 52 are supported by the insulating resin 50, can be implemented without having to adopt a supporting board.

Description

【0001】
【発明の属する技術分野】
本発明は、回路装置およびその製造方法に関し、特に支持基板を不要にした薄型の回路装置およびその製造方法に関するものである。
【0002】
【従来の技術】
従来、電子機器にセットされる回路装置は、携帯電話、携帯用のコンピューター等に採用されるため、小型化、薄型化、軽量化が求められている。
【0003】
例えば、回路装置として半導体装置を例にして述べると、一般的な半導体装置として、従来通常のトランスファーモールドで封止されたパッケージ型半導体装置がある。この半導体装置は、図15のように、プリント基板PSに実装される。
【0004】
またこのパッケージ型半導体装置は、半導体チップ2の周囲を樹脂層3で被覆し、この樹脂層3の側部から外部接続用のリード端子4が導出されたものである。
【0005】
しかしこのパッケージ型半導体装置1は、リード端子4が樹脂層3から外に出ており、全体のサイズが大きく、小型化、薄型化および軽量化を満足するものではなかった。
【0006】
そのため、各社が競って小型化、薄型化および軽量化を実現すべく、色々な構造を開発し、最近ではCSP(チップサイズパッケージ)と呼ばれる、チップのサイズと同等のウェハスケールCSP、またはチップサイズよりも若干大きいサイズのCSPが開発されている。
【0007】
図16は、支持基板としてガラスエポキシ基板5を採用した、チップサイズよりも若干大きいCSP6を示すものである。ここではガラスエポキシ基板5にトランジスタチップTが実装されたものとして説明していく。
【0008】
このガラスエポキシ基板5の表面には、第1の電極7、第2の電極8およびダイパッド9が形成され、裏面には第1の裏面電極10と第2の裏面電極11が形成されている。そしてスルーホールTHを介して、前記第1の電極7と第1の裏面電極10が、第2の電極8と第2の裏面電極11が電気的に接続されている。またダイパッド9には前記ベアのトランジスタチップTが固着され、トランジスタのエミッタ電極と第1の電極7が金属細線12を介して接続され、トランジスタのベース電極と第2の電極8が金属細線12を介して接続されている。更にトランジスタチップTを覆うようにガラスエポキシ基板5に樹脂層13が設けられている。
【0009】
前記CSP6は、ガラスエポキシ基板5を採用するが、ウェハスケールCSPと違い、チップTから外部接続用の裏面電極10、11までの延在構造が簡単であり、安価に製造できるメリットを有する。
【0010】
また上述したCSP6は、図15のように、プリント基板PSに実装される。プリント基板PSには、電気回路を構成する電極、配線が設けられ、前記CSP6、パッケージ型半導体装置1、チップ抵抗CRまたはチップコンデンサCC等が電気的に接続されて固着される。
【0011】
そしてこのプリント基板で構成された回路は、色々なセットの中に取り付けられる。
【0012】
つぎに、このCSPの製造方法を図17および図18を参照しながら説明する。尚、図18では、中央のガラエポ/フレキ基板と題するフロー図を参照する。
【0013】
まず基材(支持基板)としてガラスエポキシ基板5を用意し、この両面に絶縁性接着剤を介してCu箔20、21を圧着する。(以上図17Aを参照)
続いて、第1の電極7,第2の電極8、ダイパッド9、第1の裏面電極10および第2の裏面電極11対応するCu箔20、21に耐エッチング性のレジスト22を被覆し、Cu箔20、21をパターニングする。尚、パターニングは、表と裏で別々にしても良い(以上図17Bを参照)
続いて、ドリルやレーザを利用してスルーホールTHのための孔を前記ガラスエポキシ基板に形成し、この孔にメッキを施し、スルーホールTHを形成する。このスルーホールTHにより第1の電極7と第1の裏面電極10、第2の電極8と第2の裏面電極10が電気的に接続される。(以上図17Cを参照)
更に、図面では省略をしたが、ボンデイングポストと成る第1の電極7,第2の電極8にAuメッキを施すと共に、ダイボンディングポストとなるダイパッド9にAuメッキを施し、トランジスタチップTをダイボンディングする。
【0014】
最後に、トランジスタチップTのエミッタ電極と第1の電極7、トランジスタチップTのベース電極と第2の電極8を金属細線12を介して接続し、樹脂層13で被覆している。(以上図17Dを参照)
そして必要により、ダイシングして個々の電気素子として分離している。図17では、ガラスエポキシ基板5に、トランジスタチップTが一つしか設けられていないが、実際は、トランジスタチップTがマトリックス状に多数個設けられている。そのため、最後にダイシング装置により個別分離されている。
【0015】
以上の製造方法により、支持基板5を採用したCSP型の電気素子が完成する。この製造方法は、支持基板としてフレキシブルシートを採用しても同様である。
【0016】
一方、セラミック基板を採用した製造方法を図18左側のフローに示す。支持基板であるセラミック基板を用意した後、スルーホールを形成し、その後、導電ペーストを使い、表と裏の電極を印刷し、焼結している。その後、前製造方法の樹脂層を被覆するまでは図17の製造方法と同じであるが、セラミック基板は、非常にもろく、フレキシブルシートやガラスエポキシ基板と異なり、直ぐに欠けてしまうため金型を用いたモールドができない問題がある。そのため、封止樹脂をポッティングし、硬化した後、封止樹脂を平らにする研磨を施し、最後にダイシング装置を使って個別分離している。
【0017】
【発明が解決しようとする課題】
図16に於いて、トランジスタチップT、接続手段7〜12および樹脂層13は、外部との電気的接続、トランジスタの保護をする上で、必要な構成要素であるが、これだけの構成要素で小型化、薄型化、軽量化を実現する電気回路素子を提供するのは難しかった。
【0018】
また、支持基板となるガラスエポキシ基板5は、前述したように本来不要なものである。しかし製造方法上、電極を貼り合わせるため、支持基板として採用しており、このガラスエポキシ基板5を無くすことができなかった。
【0019】
そのため、このガラスエポキシ基板5を採用することによって、コストが上昇し、更にはガラスエポキシ基板5が厚いために、回路素子として厚くなり、小型化、薄型化、軽量化に限界があった。
【0020】
更に、ガラスエポキシ基板やセラミック基板では必ず両面の電極を接続するスルーホール形成工程が不可欠であり、製造工程も長くなる問題もあった。
【0021】
更に、金属細線12はループを描いて接続されるので、これも薄型化の大きな障害となっていた。
【0025】
【課題を解決するための手段】
本発明は、前述した多くの課題に鑑みて成され、第1に、導電箔を用意し、少なくとも導電路と成る領域を除いた前記導電箔に、前記導電箔の厚みよりも浅い分離溝を形成して導電路を形成する工程と、所望の前記導電路上に回路素子の表面電極を固着する工程と、該回路素子の裏面電極と所望の前記導電路を金属接続板で接続する工程と、前記回路素子を被覆し、前記分離溝に充填されるように絶縁性樹脂でモールドする工程と、前記分離溝を設けていない厚み部分の前記導電箔を除去する工程とを具備する回路装置の製造方法を提供することで、導電路を形成する導電箔がスタートの材料であり、絶縁性樹脂がモールドされるまでは導電箔が支持機能を有し、モールド後は絶縁性樹脂が支持機能を有することで支持基板を不要にでき、従来の課題を解決することができる。
【0026】
に、導電箔を用意し、少なくとも導電路と成る領域を除いた前記導電箔に、前記導電箔の厚みよりも浅い分離溝を形成して導電路を形成する工程と、所望の前記導電路上に複数の回路素子の表面電極を固着する工程と、前記回路素子の裏面電極と所望の前記導電路を金属接続板で接続する工程と、前記複数の回路素子を被覆し、前記分離溝に充填されるように絶縁性樹脂でモールドする工程と、前記分離溝を設けていない厚み部分の前記導電箔を除去する工程と、前記絶縁性樹脂を切断して個別の回路装置に分離する工程とを具備する回路装置の製造方法を提供することで、多数個の回路装置を量産でき、従来の課題を解決することができる。
【0027】
【発明の実施の形態】
回路装置を説明する第1の実施の形態
まず本発明の回路装置について図1を参照しながらその構造について説明する。
【0028】
図1には、絶縁性樹脂50に埋め込まれた導電路51を有し、前記導電路51上には回路素子52が固着され、前記絶縁性樹脂50で導電路51を支持して成る回路装置53が示されている。
【0029】
本構造は、回路素子52A、52B、複数の導電路51A、51B、51C、51Dと、この導電路51A、51B、51C、51Dを埋め込む絶縁性樹脂50の3つの材料で構成され、導電路51間には、この絶縁性樹脂50で充填された分離溝54が設けられる。そして絶縁性樹脂50により前記導電路51が支持されている。
【0030】
絶縁性樹脂50としては、エポキシ樹脂等の熱硬化性樹脂、ポリイミド樹脂、ポリフェニレンサルファイド等の熱可塑性樹脂を用いることができる。また絶縁性樹脂は、金型を用いて固める樹脂、ディップ、塗布をして被覆できる樹脂であれば、全ての樹脂が採用できる。
【0031】
また、導電路51としては、Cuを主材料とした導電箔、Alを主材料とした導電箔、またはFe−Ni等の合金から成る導電箔等を用いることができる。もちろん、他の導電材料でも可能であり、特にエッチングできる導電材、レーザで蒸発する導電材が好ましい。
【0032】
更に、回路素子52は、表面電極521および裏面電極522を有する半導体ベアチップ52Aと、チップ抵抗、チップコンデンサ等のチップ部品52Bで構成されているが、これのみには限定されない。半導体ベアチップ52Aについては後で図8を参照して詳しく述べるので、ここでは省略する。
【0033】
更に、回路素子52の接続手段としては、金属接続板55A、ロウ材から成る導電ボール、扁平する導電ボール、半田等のロウ材55B、Agペースト等の導電ペースト55C、導電被膜または異方性導電性樹脂等がある。これら接続手段は、回路素子52の種類、回路素子52の実装形態で選択される。例えば、半導体ベアチップであれば、表面に設けた表面電極521と導電路51との接続は、半田等のロウ材55B、Agペースト等の導電ペースト55Cが選択され、また裏面電極522と導電路51との接続は、半田等のロウ材55Bを用いて金属接続板55Aで行う。表面電極521としては金バンプ等で形成した突起電極を用いると良い。更に、チップ抵抗、チップコンデンサは、半田55Bが選択される。
【0034】
本回路装置は、導電路51を封止樹脂である絶縁性樹脂50で支持しているため、支持基板が不要となり、導電路51、回路素子52および絶縁性樹脂50で構成される。この構成は、本発明の特徴である。従来の技術の欄でも説明したように、従来の回路装置の導電路は、支持基板で支持されていたり、リードフレームで支持されているため、本来不要にしても良い構成が付加されている。しかし、本回路装置は、必要最小限の構成要素で構成され、支持基板を不要としているため、薄型で安価となる特徴を有する。
【0035】
また前記構成の他に、回路素子52を被覆し且つ前記導電路52間の前記分離溝54に充填されて一体に支持する絶縁性樹脂50を有している。
【0036】
この導電路51間は、分離溝54となり、ここに絶縁性樹脂50が充填されることで、お互いの絶縁がはかれるメリットを有する。
【0037】
また、回路素子52を被覆し且つ導電路51間の分離溝54に充填され導電路51の裏面のみを露出して一体に支持する絶縁性樹脂50を有している。
【0038】
この導電路の裏面を露出する点は、本発明の特徴の一つである。導電路の裏面が外部との接続に供することができ、図16の如き従来構造のスルーホールTHを不要にできる特徴を有する。
【0039】
また本回路装置は、分離溝54の表面と導電路51の表面は、実質一致している構造となっている。本構造は、本発明の特徴であり、図16に示す裏面電極10、11の段差が設けられないため、回路装置53をそのまま水平に移動できる特徴を有する。
【0040】
更に本回路装置は、半導体ベアチップ52Aを表面電極521を下側に向けてフリップチップ方式で導電路51A、51Bに固着するので、従来の様にボンディングワイヤのループを不要とでき、極めて薄型の構造を実現できる特徴も有する。
【0041】
回路装置を説明する第2の実施の形態
次に図9に示された回路装置56を説明する。
【0042】
本構造は、導電路51の表面に導電被膜57が形成されており、それ以外は、図1の構造と実質同一である。よってこの導電被膜57について説明する。
【0043】
第1の特徴は、導電路や回路装置の反りを防止するするために導電被膜57を設ける点である。
【0044】
一般に、絶縁性樹脂と導電路材料(以下第1の材料と呼ぶ。)の熱膨張係数の差により、回路装置自身が反ったり、また導電路が湾曲したり剥がれたりする。また導電路51の熱伝導率が絶縁性樹脂の熱伝導率よりも優れているため、導電路51の方が先に温度上昇して膨張する。そのため、第1の材料よりも熱膨張係数の小さい第2の材料を被覆することにより、導電路の反り、剥がれ、回路装置の反りを防止することができる。特に第1の材料としてCuを採用した場合、第2の材料としてはAu、NiまたはPt等が良い。Cuの膨張率は、16.7×10−6(10のマイナス6乗)で、Auは、14×10−6、Niは、12.8×10−6、Ptは、8.9×10−6である。
【0045】
第2の特徴は、第2の材料によりアンカー効果を持たせている点である。第2の材料によりひさし58が形成され、しかも導電路51と被着したひさし58が絶縁性樹脂50に埋め込まれているため、アンカー効果を発生し、導電路51の抜けを防止できる構造となる。
【0046】
回路装置の製造方法を説明する第1の実施の形態
次に図2〜図8および図1を参照して回路装置53の製造方法について説明する。
【0047】
まず図2の如く、シート状の導電箔60を用意する。この導電箔60は、ロウ材の付着性、ボンディング性、メッキ性が考慮されてその材料が選択され、材料としては、Cuを主材料とした導電箔、Alを主材料とした導電箔またはFe−Ni等の合金から成る導電箔等が採用される。
【0048】
導電箔の厚さは、後のエッチングを考慮すると10μm〜300μm程度が好ましく、ここでは70μm(2オンス)の銅箔を採用した。しかし300μm以上でも10μm以下でも基本的には良い。後述するように、導電箔60の厚みよりも浅い分離溝61が形成できればよい。
【0049】
尚、シート状の導電箔60は、所定の幅でロール状に巻かれて用意され、これが後述する各工程に搬送されても良いし、所定の大きさにカットされた導電箔が用意され、後述する各工程に搬送されても良い。
【0050】
続いて、少なくとも導電路51となる領域を除いた導電箔60を、導電箔60の厚みよりも薄く除去する工程がある。そしてこの除去工程により形成された分離溝61および導電箔60に絶縁性樹脂50を被覆する工程がある。
【0051】
まず、Cu箔60の上に、ホトレジスト(耐エッチングマスク)PRを形成し、導電路51となる領域を除いた導電箔60が露出するようにホトレジストPRをパターニングする(以上図3を参照)。そして、前記ホトレジストPRを介してエッチングすればよい(以上図4を参照)。
【0052】
エッチングにより形成された分離溝61の深さは、例えば50μmであり、その側面は、粗面となるため絶縁性樹脂50との接着性が向上される。
【0053】
またこの分離溝61の側壁は、模式的にストレートで図示しているが、除去方法により異なる構造となる。この除去工程は、ウェットエッチング、ドライエッチング、レーザによる蒸発、ダイシングが採用できる。ウェットエッチングの場合、エッチャントは、塩化第二鉄または塩化第二銅が主に採用され、前記導電箔は、このエッチャントの中にディッピングされるか、このエッチャントでシャワーリングされる。ここでウェットエッチングは、一般に非異方性にエッチングされるため、側面は湾曲構造になる。
【0054】
またドライエッチングの場合は、異方性、非異方性でエッチングが可能である。現在では、Cuを反応性イオンエッチングで取り除くことは不可能といわれているが、スパッタリングで除去できる。またスパッタリングの条件によって異方性、非異方性でエッチングできる。
【0055】
またレーザでは、直接レーザ光を当てて分離溝を形成でき、この場合は、どちらかといえば分離溝61の側面はストレートに形成される。
【0056】
またダイシングでは、曲折した複雑なパターンを形成することは不可能であるが、格子状の分離溝を形成することは可能である。
【0057】
尚、図3に於いて、ホトレジストの代わりにエッチング液に対して耐食性のある導電被膜を選択的に被覆しても良い。導電路と成る部分に選択的に被着すれば、この導電被膜がエッチング保護膜となり、レジストを採用することなく分離溝をエッチングできる。この導電被膜として考えられる材料は、Ag、Au、PtまたはPd等である。しかもこれら耐食性の導電被膜は、ダイパッド、ボンディングパッドとしてそのまま活用できる特徴を有する。
【0058】
続いて、図5の如く、分離溝61が形成された導電箔60に回路素子52を電気的に接続して実装する工程がある。
【0059】
回路素子52としては、トランジスタ、ダイオード、ICチップ等の半導体素子、チップコンデンサ、チップ抵抗等の受動素子である。
【0060】
ここでは、ベアのトランジスタチップ52Aのベース電極となる表面電極521が導電路51Aに、エミッタ電極となる表面電極521が導電路51Bに半田等のロウ材または導電ペースト55Bでフリップチップ方式で固着される。またトランジスタチップ52Aのコレクタ電極となる裏面電極522はL字型に曲折した銅より成る金属接続板55Aの一端を半田等のロウ材または導電ペースト55Bで接続し、他端は導電路51Cに同様に接続される。この金属接続板55Aはトランジスタチップ52Aの裏側はすべて裏面電極522のみしかないので、異形部品マウンターを用いてラフな位置合わせで容易にマウント可能である。更に、52Bはチップ抵抗等の受動素子であり、半田等のロウ材または導電ペースト55Bで固着される。
【0061】
更に、図6に示すように、前記導電箔60および分離溝61に絶縁性樹脂50を付着する工程がある。これは、トランスファーモールド、インジェクションモールド、またはディッピングにより実現できる。樹脂材料としては、エポキシ樹脂等の熱硬化性樹脂がトランスファーモールドで実現でき、ポリイミド樹脂、ポリフェニレンサルファイド等の熱可塑性樹脂はインジェクションモールドで実現できる。
【0062】
本実施の形態では、導電箔60表面に被覆された絶縁性樹脂の厚さは、回路素子の最頂部から約100μm程度が被覆されるように調整されている。この厚みは、強度を考慮して厚くすることも、薄くすることも可能である。
【0063】
本工程の特徴は、絶縁性樹脂50を被覆するまでは、導電路51となる導電箔60が支持基板となることである。従来では、図17の様に、本来必要としない支持基板5を採用して導電路7〜11を形成しているが、本発明では、支持基板となる導電箔60は、電極材料として必要な材料である。そのため、構成材料を極力省いて作業できるメリットを有し、コストの低下も実現できる。
【0064】
また分離溝61は、導電箔の厚みよりも浅く形成されているため、導電箔60が導電路51として個々に分離されていない。従ってシート状の導電箔60として一体で取り扱え、絶縁性樹脂をモールドする際、金型への搬送、金型への実装の作業が非常に楽になる特徴を有する。
【0065】
続いて、導電箔60の裏面を化学的および/または物理的に除き、導電路51として分離する工程がある。ここでこの除く工程は、研磨、研削、エッチング、レーザの金属蒸発等により施される。
【0066】
実験では研磨装置または研削装置により全面を30μm程度削り、分離溝61から絶縁性樹脂50を露出させている。この露出される面を図6では点線で示している。その結果、約40μmの厚さの導電路51となって分離される。また絶縁性樹脂50が露出する手前まで、導電箔60を全面ウェトエッチングし、その後、研磨または研削装置により全面を削り、絶縁性樹脂50を露出させても良い。更に絶縁性樹脂50が露出するまで、導電箔60を全面ウェトエッチングして、絶縁性樹脂50を露出させても良い。
【0067】
この結果、絶縁性樹脂50に導電路51の表面が露出する構造となる。そして分離溝61が削られ、図1の分離溝54となる。(以上図6参照)
最後に、必要によって露出した導電路51に半田等の導電材を被着し、回路装置として完成する。
【0068】
尚、導電路51の裏面に導電被膜を被着する場合、図2の導電箔の裏面に、前もって導電被膜を形成しても良い。この場合、導電路に対応する部分を選択的に被着すれば良い。被着方法は、例えばメッキである。またこの導電被膜は、エッチングに対して耐性がある材料がよい。またこの導電被膜を採用した場合、研磨をせずにエッチングだけで導電路51として分離できる。
【0069】
尚、本製造方法では、導電箔60にトランジスタとチップ抵抗が実装されているだけであるが、これを1単位としてマトリックス状に配置しても良いし、どちらか一方の回路素子を1単位としてマトリックス状に配置しても良い。この場合は、後述するようにダイシング装置で個々に分離される。
【0070】
以上の製造方法によって、絶縁性樹脂50に導電路51が埋め込まれ、絶縁性樹脂50の裏面と導電路51の裏面が一致する平坦な回路装置56が実現できる。
【0071】
本製造方法の特徴は、絶縁性樹脂50を支持基板として活用し導電路51の分離作業ができることにある。絶縁性樹脂50は、導電路51を埋め込む材料として必要な材料であり、図17の従来の製造方法のように、不要な支持基板5を必要としない。従って、最小限の材料で製造でき、コストの低減が実現できる特徴を有する。
【0072】
尚、導電路51表面からの絶縁性樹脂の厚さは、前工程の絶縁性樹脂の付着の時に調整できる。本発明では半導体ベアチップ52Aをフリップチップ方式で導電路51に固着するので、ボンディングワイヤを排除できた。従って実装される半導体ベアチップ52Aの厚みにより違ってくるが、回路装置56としての厚さは、極めて薄くできる特徴を有する。ここでは、400μm厚の絶縁性樹脂50に40μmの導電路51と回路素子が埋め込まれた回路装置になる。(以上図1を参照)
図7に、分離溝61を形成した後の導電箔60の基板の平面図を示す。この基板は大きさが45mm×60mmであり、黒い部分が導電路51を形成しており、白い部分は分離溝61を形成している。従って、回路装置53、56と成る部分は5列17行にマトリックス状に配列され、周辺には位置合わせマーク611や、製造中に使用するインデックス孔612等が設けられている。
【0073】
図8に、半導体ベアチップ52Aの具体的な構造を断面図で示す。半導体ベアチップ52AはN型半導体基板523にP型ベース領域524、N型エミッタ領域525が設けられ、半導体基板523の絶縁膜526上にはP型ベース領域524およびN型エミッタ領域525とコンタクトしたアルミニウムのスパッタで形成された下地ベース電極527と下地エミッタ電極528が設けられる。この下地ベース電極527と下地エミッタ電極528上にはPd/TiあるいはAu/TiWのバリアメタル層529を設け、この上に約25μmの高さに金メッキ層で形成したベース表面電極521とエミッタ表面電極521を設けられる。また、半導体基板523の裏面全体にはAu/Cr等の蒸着で裏面電極522が設けられている。
【0074】
回路装置の製造方法を説明する第2の実施の形態
次に図10〜図14、図9を参照してひさし58を有する回路装置56の製造方法について説明する。尚、ひさしとなる第2の材料70が被着される以外は、第1の実施の形態と実質同一であるため、詳細な説明は省略する。
【0075】
まず図10の如く、第1の材料から成る導電箔60の上にエッチングレートの小さい第2の材料70が被覆された導電箔60を用意する。
【0076】
例えばCu箔の上にNiを被着すると、塩化第二鉄または塩化第二銅でCuとNiが一度にエッチングでき、エッチングレートの差によりNiがひさし58と成って形成されるため好適である。太い実線がNiから成る導電被膜70であり、その膜厚は1〜10μm程度が好ましい。またNiの膜厚が厚い程、ひさし58が形成されやすい。
【0077】
また第2の材料は、第1の材料と選択エッチングできる材料を被覆しても良い。この場合、まず第2の材料から成る被膜を導電路51の形成領域に被覆するようにパターニングし、この被膜をマスクにして第1の材料から成る被膜をエッチングすればひさし58が形成できるからである。第2の材料としては、Al、Ag、Au等が考えられる。(以上図10を参照)
続いて、少なくとも導電路51となる領域を除いた導電箔60を、導電箔60の厚みよりも薄く取り除く工程がある。
【0078】
Ni70の上に、ホトレジストPRを形成し、導電路51となる領域を除いたNi70が露出するようにホトレジストPRをパターニングし、前記ホトレジストを介してエッチングすればよい。
【0079】
前述したように塩化第二鉄、塩化第二銅のエッチャント等を採用しエッチングすると、Ni70のエッチングレートがCu60のエッチングレートよりも小さいため、エッチングが進むにつれてひさし58がでてくる。
【0080】
尚、前記分離溝61が形成された導電箔60に回路素子52を実装する工程(図13)、前記導電箔60および分離溝61に絶縁性樹脂50を被覆し、導電箔60の裏面を化学的および/または物理的に除き、導電路51として分離する工程(図14)、および導電路裏面に導電被膜を形成して完成までの工程(図9)は、前述した製造方法と同一であるためその説明は省略する。
【0081】
【発明の効果】
以上の説明から明らかなように、本発明では、回路装置、導電路および絶縁性樹脂の必要最小限で構成され、資源に無駄のない回路装置となる。よって完成するまで余分な構成要素が無く、コストを大幅に低減できる回路装置を実現できる。
【0082】
また半導体ベアチップをフリップチップ方式で導電路に固着するので、ボンディングワイヤを不要にでき、絶縁性樹脂の被覆膜厚、導電箔の厚みを最適値にすることにより、高さが0.5mm以下の非常に薄型化が図れ、同時に小型軽量化された回路装置を実現できる。
【0083】
また導電路の裏面のみを絶縁性樹脂から露出しているため、導電路の裏面が直ちに外部との接続に供することができ、図16の如き従来構造の裏面電極およびスルーホールを不要にできる利点を有する。
【0084】
また本回路装置は、分離溝の表面と導電路の表面は、実質一致している平坦な表面を有する構造となっており、狭ピッチQFP実装時には回路装置自身を半田の表面張力でそのまま水平に移動できるので、電極ずれの修正が極めて容易となる。
【0085】
また導電路の表側に第2の材料を形成しているため、熱膨張係数の違いにより実装基板の反り、特に細長い配線の反りまたは剥離を抑制することができる。
【0086】
また導電路の表面に第2の材料から成る被膜を形成することにより、導電路に被着されたひさしが形成できる。よってアンカー効果を発生させることができ、導電路の反り、抜けを防止することができる。
【0087】
また本発明の回路装置の製造方法では、導電路の材料となる導電箔自体を支持基板として機能させ、分離溝の形成時あるいは回路素子の実装、絶縁性樹脂の被着時までは導電箔で全体を支持し、また導電箔を各導電路として分離する時は、絶縁性樹脂を支持基板にして機能させている。従って、回路素子、導電箔、絶縁性樹脂の必要最小限で製造できる。従来例で説明した如く、本来回路装置を構成する上で支持基板が要らなくなり、コスト的にも安価にできる。また支持基板が不要であること、導電路が絶縁性樹脂に埋め込まれていること、更には絶縁性樹脂と導電箔の厚みの調整が可能で且つボンディングワイヤを不要とすることにより、非常に薄い回路装置が形成できるメリットもある。
【0088】
また図18から明白なように、スルーホールの形成工程、導体の印刷工程(セラミック基板の場合)等を省略できるので、従来より従来より製造工程を大幅に短縮でき、全行程を内作できる利点を有する。またフレーム金型も一切不要であり、極めて短納期となる製造方法である。
【0089】
次に導電箔の厚みよりも薄く取り除く工程(例えばハーフエッチング)までは、導電路を個々に分離せずに取り扱えるため、極めて小さい基板に多くの回路装置を集積して製造するので、作業性が向上する特徴も有する。
【0090】
また導電路と絶縁性樹脂で同一面を形成するため、実装された回路装置は、実装基板上の導電路側面に当たることなくずらすことができる。特に位置ずれして実装された回路装置を水平方向にずらして配置し直すことができる。また回路装置の実装後、ロウ材が溶けていれば、ずれて実装された回路装置は、溶けたロウ材の表面張力により、導電路上部に自ら戻ろうとし、回路装置自身による再配置が可能となる。
【図面の簡単な説明】
【図1】本発明の回路装置を説明する断面図である。
【図2】本発明の回路装置の製造方法を説明する断面図である。
【図3】本発明の回路装置の製造方法を説明する断面図である。
【図4】本発明の回路装置の製造方法を説明する断面図である。
【図5】本発明の回路装置の製造方法を説明する断面図である。
【図6】本発明の回路装置の製造方法を説明する断面図である。
【図7】本発明の回路装置の製造方法を説明する平面図である。
【図8】本発明の回路装置の製造方法を説明する断面図である。
【図9】本発明の回路装置を説明する断面図である。
【図10】本発明の回路装置の製造方法を説明する断面図である。
【図11】本発明の回路装置の製造方法を説明する断面図である。
【図12】本発明の回路装置の製造方法を説明する断面図である。
【図13】本発明の回路装置の製造方法を説明する断面図である。
【図14】本発明の回路装置の製造方法を説明する断面図である。
【図15】従来の回路装置の実装構造を説明する断面図である。
【図16】従来の回路装置を説明する断面図である。
【図17】従来の回路装置の製造方法を説明する断面図である。
【図18】従来と本発明の回路装置の製造方法を説明する図である。
【符号の説明】
50 絶縁性樹脂
51 導電路
52 回路素子
53 回路装置
54 分離溝
58 ひさし
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit device and a manufacturing method thereof, and more particularly to a thin circuit device that does not require a support substrate and a manufacturing method thereof.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a circuit device set in an electronic device is employed in a mobile phone, a portable computer, and the like, and thus, a reduction in size, thickness, and weight are required.
[0003]
For example, a semiconductor device as an example of a circuit device will be described. As a general semiconductor device, there is a package type semiconductor device sealed by a conventional transfer mold. This semiconductor device is mounted on a printed circuit board PS as shown in FIG.
[0004]
In this package type semiconductor device, the periphery of the semiconductor chip 2 is covered with a resin layer 3, and lead terminals 4 for external connection are led out from the side of the resin layer 3.
[0005]
However, the package type semiconductor device 1 has lead terminals 4 protruding from the resin layer 3 and has a large overall size, which does not satisfy the miniaturization, thickness reduction, and weight reduction.
[0006]
Therefore, various companies have competed to develop various structures to achieve miniaturization, thinning, and weight reduction, and recently called CSP (chip size package), wafer scale CSP equivalent to chip size, or chip size A slightly larger CSP has been developed.
[0007]
FIG. 16 shows a CSP 6 that employs a glass epoxy substrate 5 as a support substrate and is slightly larger than the chip size. Here, description will be made assuming that the transistor chip T is mounted on the glass epoxy substrate 5.
[0008]
A first electrode 7, a second electrode 8 and a die pad 9 are formed on the surface of the glass epoxy substrate 5, and a first back electrode 10 and a second back electrode 11 are formed on the back surface. The first electrode 7 and the first back electrode 10 are electrically connected to the second electrode 8 and the second back electrode 11 through the through hole TH. Further, the bare transistor chip T is fixed to the die pad 9, the emitter electrode of the transistor and the first electrode 7 are connected via the fine metal wire 12, and the base electrode of the transistor and the second electrode 8 are connected to the fine metal wire 12. Connected through. Further, a resin layer 13 is provided on the glass epoxy substrate 5 so as to cover the transistor chip T.
[0009]
The CSP 6 employs the glass epoxy substrate 5, but unlike the wafer scale CSP, the extending structure from the chip T to the backside electrodes 10 and 11 for external connection is simple, and has an advantage that it can be manufactured at low cost.
[0010]
The CSP 6 described above is mounted on a printed circuit board PS as shown in FIG. The printed circuit board PS is provided with electrodes and wirings constituting an electric circuit, and the CSP 6, the package type semiconductor device 1, the chip resistor CR, the chip capacitor CC, and the like are electrically connected and fixed.
[0011]
And the circuit comprised with this printed circuit board is attached in various sets.
[0012]
Next, a method for manufacturing the CSP will be described with reference to FIGS. In FIG. 18, reference is made to a flow diagram entitled the central glass epoxy / flexible substrate.
[0013]
First, a glass epoxy substrate 5 is prepared as a base material (support substrate), and Cu foils 20 and 21 are pressure-bonded to both surfaces via an insulating adhesive. (See FIG. 17A above)
Subsequently, the Cu foils 20, 21 corresponding to the first electrode 7, the second electrode 8, the die pad 9, the first back electrode 10, and the second back electrode 11 are covered with an etching resistant resist 22, and Cu The foils 20 and 21 are patterned. Patterning may be performed separately for the front and back sides (see FIG. 17B above).
Subsequently, a hole for the through hole TH is formed in the glass epoxy substrate by using a drill or a laser, and the hole is plated to form the through hole TH. The first electrode 7 and the first back electrode 10, and the second electrode 8 and the second back electrode 10 are electrically connected through the through hole TH. (See FIG. 17C above)
Further, although omitted in the drawings, the first electrode 7 and the second electrode 8 which are bonding posts are plated with Au, and the die pad 9 which is a die bonding post is plated with Au, so that the transistor chip T is die bonded. To do.
[0014]
Finally, the emitter electrode of the transistor chip T and the first electrode 7, the base electrode of the transistor chip T and the second electrode 8 are connected via the metal thin wire 12 and covered with the resin layer 13. (See FIG. 17D above)
If necessary, it is diced and separated as individual electric elements. In FIG. 17, only one transistor chip T is provided on the glass epoxy substrate 5, but actually, a large number of transistor chips T are provided in a matrix. Therefore, it is finally separated by a dicing device.
[0015]
With the above manufacturing method, a CSP type electric element employing the support substrate 5 is completed. This manufacturing method is the same even if a flexible sheet is adopted as the support substrate.
[0016]
On the other hand, a manufacturing method employing a ceramic substrate is shown in the flow on the left side of FIG. After preparing the ceramic substrate as the support substrate, through holes are formed, and then the front and back electrodes are printed and sintered using a conductive paste. After that, until the resin layer of the pre-manufacturing method is coated, the manufacturing method is the same as the manufacturing method of FIG. 17, but the ceramic substrate is very brittle, and unlike a flexible sheet or glass epoxy substrate, it will be chipped immediately. There is a problem that can not be molded. Therefore, the potting resin is potted and cured, and then polishing for flattening the sealing resin is performed, and finally, the dicing apparatus is used for individual separation.
[0017]
[Problems to be solved by the invention]
In FIG. 16, the transistor chip T, the connecting means 7 to 12 and the resin layer 13 are necessary components for electrical connection with the outside and protection of the transistor. It has been difficult to provide an electric circuit element that can be made thinner, thinner, and lighter.
[0018]
Moreover, the glass epoxy board | substrate 5 used as a support substrate is an essentially unnecessary thing as mentioned above. However, since the electrodes are bonded together in the manufacturing method, it is adopted as a support substrate, and the glass epoxy substrate 5 cannot be eliminated.
[0019]
For this reason, the use of the glass epoxy substrate 5 increases the cost. Further, since the glass epoxy substrate 5 is thick, it becomes thick as a circuit element, and there is a limit to miniaturization, thickness reduction, and weight reduction.
[0020]
Furthermore, a glass epoxy substrate or a ceramic substrate always requires a through-hole forming process for connecting electrodes on both sides, and there is a problem that the manufacturing process becomes long.
[0021]
Furthermore, since the fine metal wires 12 are connected in a loop, this is also a major obstacle to thinning.
[0025]
[Means for Solving the Problems]
The present invention is made in view of the many problems described above. First , a conductive foil is prepared, and a separation groove shallower than the thickness of the conductive foil is formed on the conductive foil except at least a region that becomes a conductive path. Forming a conductive path, fixing the surface electrode of the circuit element on the desired conductive path, connecting the back electrode of the circuit element and the desired conductive path with a metal connection plate, Production of a circuit device comprising: a step of covering the circuit element and molding with an insulating resin so as to fill the separation groove; and a step of removing the conductive foil in a thickness portion where the separation groove is not provided. By providing a method, the conductive foil forming the conductive path is a starting material, and the conductive foil has a supporting function until the insulating resin is molded, and after the molding, the insulating resin has a supporting function. This eliminates the need for a support substrate. It is possible to solve the problem.
[0026]
Second , preparing a conductive foil and forming a conductive path by forming a separation groove shallower than the thickness of the conductive foil on the conductive foil excluding at least a region to be a conductive path; Fixing the surface electrodes of the plurality of circuit elements on the road, connecting the back electrode of the circuit elements and the desired conductive path with a metal connection plate, covering the plurality of circuit elements, and forming the separation grooves A step of molding with an insulating resin so as to be filled, a step of removing the conductive foil in a thickness portion where the separation groove is not provided, and a step of cutting the insulating resin and separating it into individual circuit devices. By providing a method for manufacturing a circuit device including the above, a large number of circuit devices can be mass-produced, and the conventional problems can be solved.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
First Embodiment Explaining the Circuit Device First, the structure of the circuit device of the present invention will be described with reference to FIG.
[0028]
In FIG. 1, a circuit device has a conductive path 51 embedded in an insulating resin 50, a circuit element 52 is fixed on the conductive path 51, and the conductive path 51 is supported by the insulating resin 50. 53 is shown.
[0029]
This structure is composed of three materials: circuit elements 52A, 52B, a plurality of conductive paths 51A, 51B, 51C, 51D, and an insulating resin 50 that embeds the conductive paths 51A, 51B, 51C, 51D. A separation groove 54 filled with the insulating resin 50 is provided therebetween. The conductive path 51 is supported by the insulating resin 50.
[0030]
As the insulating resin 50, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin or polyphenylene sulfide can be used. As the insulating resin, any resin can be adopted as long as it is a resin that can be hardened using a mold, a resin that can be coated by dipping or coating.
[0031]
Further, as the conductive path 51, a conductive foil mainly made of Cu, a conductive foil mainly made of Al, a conductive foil made of an alloy such as Fe-Ni, or the like can be used. Of course, other conductive materials are possible, and a conductive material that can be etched and a conductive material that evaporates with a laser are particularly preferable.
[0032]
Further, the circuit element 52 includes a semiconductor bare chip 52A having a front surface electrode 521 and a back surface electrode 522, and a chip component 52B such as a chip resistor and a chip capacitor, but is not limited thereto. The semiconductor bare chip 52A will be described later in detail with reference to FIG.
[0033]
Further, as the connection means of the circuit element 52, a metal connection plate 55A, a conductive ball made of a brazing material, a flat conductive ball, a brazing material 55B such as solder, a conductive paste 55C such as an Ag paste, a conductive film or an anisotropic conductive material. For example. These connection means are selected depending on the type of the circuit element 52 and the mounting form of the circuit element 52. For example, in the case of a semiconductor bare chip, for the connection between the surface electrode 521 provided on the surface and the conductive path 51, a brazing material 55B such as solder or a conductive paste 55C such as Ag paste is selected, and the back electrode 522 and the conductive path 51 are selected. Is connected to the metal connection plate 55A using a brazing material 55B such as solder. As the surface electrode 521, a protruding electrode formed with a gold bump or the like may be used. Further, the solder 55B is selected as the chip resistor and the chip capacitor.
[0034]
In this circuit device, since the conductive path 51 is supported by the insulating resin 50 that is a sealing resin, a support substrate is not required, and the conductive path 51, the circuit element 52, and the insulating resin 50 are included. This configuration is a feature of the present invention. As described in the section of the prior art, since the conductive path of the conventional circuit device is supported by the support substrate or supported by the lead frame, a configuration that may be unnecessary is added. However, since this circuit device is composed of the minimum necessary components and does not require a support substrate, it is characterized by being thin and inexpensive.
[0035]
In addition to the above-described configuration, the insulating resin 50 that covers the circuit element 52 and is filled in the separation groove 54 between the conductive paths 52 and is integrally supported is provided.
[0036]
The space between the conductive paths 51 becomes a separation groove 54, and the insulating resin 50 is filled therewith, so that there is an advantage that mutual insulation can be achieved.
[0037]
In addition, the insulating resin 50 that covers the circuit element 52 and is filled in the separation groove 54 between the conductive paths 51 and that supports only the back surface of the conductive path 51 is exposed.
[0038]
The point that the back surface of the conductive path is exposed is one of the features of the present invention. The back surface of the conductive path can be used for connection to the outside, and the through hole TH having the conventional structure as shown in FIG. 16 can be eliminated.
[0039]
In the circuit device, the surface of the separation groove 54 and the surface of the conductive path 51 are substantially coincident with each other. This structure is a feature of the present invention and has a feature that the circuit device 53 can be moved horizontally as it is because the steps of the back electrodes 10 and 11 shown in FIG. 16 are not provided.
[0040]
Furthermore, since this circuit device is fixed to the conductive paths 51A and 51B by the flip chip method with the front surface electrode 521 facing downward, the circuit device can eliminate the bonding wire loop as in the prior art, and has an extremely thin structure. It has the feature which can realize.
[0041]
Second Embodiment Explaining Circuit Device Next, the circuit device 56 shown in FIG. 9 will be explained.
[0042]
In this structure, a conductive film 57 is formed on the surface of the conductive path 51, and the other structure is substantially the same as the structure in FIG. Therefore, the conductive film 57 will be described.
[0043]
The first feature is that a conductive film 57 is provided to prevent warping of the conductive path and the circuit device.
[0044]
Generally, the circuit device itself is warped or the conductive path is curved or peeled off due to the difference in thermal expansion coefficient between the insulating resin and the conductive path material (hereinafter referred to as the first material). Further, since the thermal conductivity of the conductive path 51 is superior to that of the insulating resin, the conductive path 51 first rises in temperature and expands. Therefore, by covering the second material having a smaller thermal expansion coefficient than that of the first material, warping and peeling of the conductive path and warping of the circuit device can be prevented. In particular, when Cu is employed as the first material, Au, Ni, Pt, or the like is preferable as the second material. The expansion coefficient of Cu is 16.7 × 10 −6 (minus the sixth power of 10), Au is 14 × 10 −6, Ni is 12.8 × 10 −6, and Pt is 8.9 × 10 6 -6.
[0045]
The second feature is that the anchor effect is provided by the second material. Since the eaves 58 are formed of the second material, and the eaves 58 attached to the conductive path 51 are embedded in the insulating resin 50, an anchor effect is generated, and the conductive path 51 can be prevented from coming off. .
[0046]
First Embodiment Explaining Method of Manufacturing Circuit Device Next, a method of manufacturing the circuit device 53 will be described with reference to FIGS. 2 to 8 and FIG.
[0047]
First, as shown in FIG. 2, a sheet-like conductive foil 60 is prepared. The conductive foil 60 is selected in consideration of the adhesiveness, bonding property, and plating property of the brazing material. As the material, a conductive foil mainly composed of Cu, a conductive foil mainly composed of Al, or Fe is used. A conductive foil made of an alloy such as Ni is employed.
[0048]
The thickness of the conductive foil is preferably about 10 μm to 300 μm in consideration of the later etching, and here, a copper foil of 70 μm (2 ounces) is employed. However, it is basically good if it is 300 μm or more and 10 μm or less. As will be described later, it is only necessary that the separation groove 61 shallower than the thickness of the conductive foil 60 can be formed.
[0049]
In addition, the sheet-like conductive foil 60 is prepared by being wound in a roll shape with a predetermined width, and this may be conveyed to each step described later, or a conductive foil cut into a predetermined size is prepared, You may convey to each process mentioned later.
[0050]
Subsequently, there is a step of removing the conductive foil 60 excluding at least the region to be the conductive path 51 thinner than the thickness of the conductive foil 60. There is a step of covering the insulating groove 50 and the conductive foil 60 formed by this removal step with the insulating resin 50.
[0051]
First, a photoresist (etching-resistant mask) PR is formed on the Cu foil 60, and the photoresist PR is patterned so that the conductive foil 60 excluding the region to be the conductive path 51 is exposed (see FIG. 3 above). Then, etching may be performed through the photoresist PR (see FIG. 4 above).
[0052]
The depth of the separation groove 61 formed by etching is, for example, 50 μm, and its side surface is a rough surface, so that the adhesiveness with the insulating resin 50 is improved.
[0053]
The side wall of the separation groove 61 is schematically illustrated as a straight line, but has a different structure depending on the removal method. This removal process can employ wet etching, dry etching, laser evaporation, and dicing. In the case of wet etching, ferric chloride or cupric chloride is mainly used as the etchant, and the conductive foil is dipped in the etchant or showered with the etchant. Since wet etching is generally non-anisotropic, the side surface has a curved structure.
[0054]
In the case of dry etching, etching can be performed anisotropically or non-anisotropically. At present, it is said that Cu cannot be removed by reactive ion etching, but it can be removed by sputtering. Etching can be anisotropic or non-anisotropic depending on sputtering conditions.
[0055]
Further, in the laser, the separation groove can be formed by direct laser light irradiation. In this case, the side surface of the separation groove 61 is formed to be straight.
[0056]
In dicing, it is impossible to form a complicated bent pattern, but it is possible to form a lattice-like separation groove.
[0057]
In FIG. 3, instead of the photoresist, a conductive film resistant to the etching solution may be selectively coated. If the conductive film is selectively deposited on the conductive path, this conductive film becomes an etching protective film, and the separation groove can be etched without employing a resist. Possible materials for the conductive film are Ag, Au, Pt, Pd, and the like. In addition, these corrosion-resistant conductive films have the feature that they can be used as they are as die pads and bonding pads.
[0058]
Subsequently, as shown in FIG. 5, there is a step of electrically connecting the circuit element 52 to the conductive foil 60 in which the separation groove 61 is formed and mounting it.
[0059]
The circuit element 52 is a semiconductor element such as a transistor, a diode or an IC chip, or a passive element such as a chip capacitor or a chip resistor.
[0060]
Here, the surface electrode 521 serving as the base electrode of the bare transistor chip 52A is fixed to the conductive path 51A, and the surface electrode 521 serving as the emitter electrode is fixed to the conductive path 51B by a soldering material such as solder or the conductive paste 55B in a flip chip manner. The The back electrode 522 serving as the collector electrode of the transistor chip 52A has one end of a metal connection plate 55A made of copper bent in an L shape connected by a brazing material such as solder or a conductive paste 55B, and the other end similar to the conductive path 51C. Connected to. Since the metal connection plate 55A has only the back electrode 522 on the back side of the transistor chip 52A, it can be easily mounted with rough alignment using a deformed component mounter. Further, 52B is a passive element such as a chip resistor, and is fixed by a brazing material such as solder or a conductive paste 55B.
[0061]
Further, as shown in FIG. 6, there is a step of attaching an insulating resin 50 to the conductive foil 60 and the separation groove 61. This can be realized by transfer molding, injection molding, or dipping. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding, and a thermoplastic resin such as polyimide resin or polyphenylene sulfide can be realized by injection molding.
[0062]
In the present embodiment, the thickness of the insulating resin coated on the surface of the conductive foil 60 is adjusted so as to cover about 100 μm from the top of the circuit element. This thickness can be increased or decreased in consideration of strength.
[0063]
The feature of this step is that the conductive foil 60 that becomes the conductive path 51 becomes the support substrate until the insulating resin 50 is coated. Conventionally, as shown in FIG. 17, the conductive paths 7 to 11 are formed by using the support substrate 5 that is not originally required, but in the present invention, the conductive foil 60 that becomes the support substrate is necessary as an electrode material. Material. Therefore, there is a merit that the work can be performed with the constituent materials omitted as much as possible, and the cost can be reduced.
[0064]
Further, since the separation groove 61 is formed shallower than the thickness of the conductive foil, the conductive foil 60 is not individually separated as the conductive path 51. Therefore, the sheet-like conductive foil 60 can be handled as a unit, and when the insulating resin is molded, it has a feature that it is very easy to carry to the mold and mount to the mold.
[0065]
Subsequently, there is a step of chemically and / or physically removing the back surface of the conductive foil 60 and separating it as the conductive path 51. Here, this removal step is performed by polishing, grinding, etching, laser metal evaporation, or the like.
[0066]
In the experiment, the entire surface is cut by about 30 μm by a polishing apparatus or a grinding apparatus, and the insulating resin 50 is exposed from the separation groove 61. This exposed surface is indicated by a dotted line in FIG. As a result, the conductive path 51 having a thickness of about 40 μm is separated. Alternatively, wet etching may be performed on the entire surface of the conductive foil 60 until the insulating resin 50 is exposed, and then the entire surface may be shaved by a polishing or grinding apparatus to expose the insulating resin 50. Further, the conductive foil 60 may be wet etched to expose the insulating resin 50 until the insulating resin 50 is exposed.
[0067]
As a result, the surface of the conductive path 51 is exposed to the insulating resin 50. Then, the separation groove 61 is shaved to form the separation groove 54 in FIG. (See Figure 6 above)
Finally, a conductive material such as solder is applied to the exposed conductive path 51 as necessary, thereby completing the circuit device.
[0068]
When a conductive film is applied to the back surface of the conductive path 51, a conductive film may be formed in advance on the back surface of the conductive foil in FIG. In this case, a portion corresponding to the conductive path may be selectively attached. The deposition method is, for example, plating. The conductive film is preferably made of a material that is resistant to etching. Further, when this conductive film is employed, the conductive path 51 can be separated only by etching without polishing.
[0069]
In this manufacturing method, the transistor and the chip resistor are only mounted on the conductive foil 60. However, the transistor and the chip resistor may be arranged in a matrix shape as one unit, or one of the circuit elements is set as one unit. They may be arranged in a matrix. In this case, it separates with a dicing apparatus so that it may mention later.
[0070]
With the above manufacturing method, the flat circuit device 56 in which the conductive path 51 is embedded in the insulating resin 50 and the back surface of the insulating resin 50 and the back surface of the conductive path 51 coincide can be realized.
[0071]
The feature of this manufacturing method is that the insulating path 50 can be used as a support substrate to separate the conductive path 51. The insulating resin 50 is a material necessary as a material for embedding the conductive path 51, and does not require an unnecessary support substrate 5 unlike the conventional manufacturing method of FIG. Therefore, it has the characteristics that it can be manufactured with a minimum amount of material and cost can be reduced.
[0072]
The thickness of the insulating resin from the surface of the conductive path 51 can be adjusted when the insulating resin is attached in the previous step. In the present invention, since the semiconductor bare chip 52A is fixed to the conductive path 51 by the flip chip method, the bonding wire can be eliminated. Therefore, the thickness of the circuit device 56 has a feature that can be extremely reduced, although it varies depending on the thickness of the semiconductor bare chip 52A to be mounted. Here, a circuit device is obtained in which a 40 μm conductive path 51 and circuit elements are embedded in an insulating resin 50 having a thickness of 400 μm. (See Figure 1 above)
FIG. 7 shows a plan view of the substrate of the conductive foil 60 after the separation groove 61 is formed. This substrate has a size of 45 mm × 60 mm, the black part forms the conductive path 51, and the white part forms the separation groove 61. Accordingly, the portions to be the circuit devices 53 and 56 are arranged in a matrix in 5 columns and 17 rows, and are provided with alignment marks 611, index holes 612 used during manufacture, and the like in the periphery.
[0073]
FIG. 8 is a sectional view showing a specific structure of the semiconductor bare chip 52A. In the semiconductor bare chip 52A, a P-type base region 524 and an N-type emitter region 525 are provided on an N-type semiconductor substrate 523, and aluminum in contact with the P-type base region 524 and the N-type emitter region 525 is formed on the insulating film 526 of the semiconductor substrate 523. A base electrode 527 and a base emitter electrode 528 formed by sputtering are provided. A barrier metal layer 529 of Pd / Ti or Au / TiW is provided on the base electrode 527 and the base emitter electrode 528, and a base surface electrode 521 and an emitter surface electrode formed by a gold plating layer at a height of about 25 μm thereon. 521 is provided. Further, a back electrode 522 is provided on the entire back surface of the semiconductor substrate 523 by vapor deposition of Au / Cr or the like.
[0074]
Second Embodiment Explaining Method of Manufacturing Circuit Device Next, a method of manufacturing the circuit device 56 having the eaves 58 will be described with reference to FIGS. In addition, since it is substantially the same as 1st Embodiment except the 2nd material 70 used as eaves being adhere | attached, detailed description is abbreviate | omitted.
[0075]
First, as shown in FIG. 10, a conductive foil 60 in which a second material 70 having a low etching rate is coated on a conductive foil 60 made of a first material is prepared.
[0076]
For example, it is preferable to deposit Ni on a Cu foil because Cu and Ni can be etched at once with ferric chloride or cupric chloride, and Ni is formed into eaves 58 due to the difference in etching rate. . The thick solid line is the conductive film 70 made of Ni, and the film thickness is preferably about 1 to 10 μm. Further, the thicker the Ni film, the easier the eaves 58 are formed.
[0077]
The second material may be coated with a material that can be selectively etched with the first material. In this case, the eaves 58 can be formed by first patterning the coating made of the second material so as to cover the formation region of the conductive path 51 and etching the coating made of the first material using this coating as a mask. is there. As the second material, Al, Ag, Au, or the like can be considered. (See Figure 10 above)
Subsequently, there is a step of removing the conductive foil 60 excluding at least the region to be the conductive path 51 thinner than the thickness of the conductive foil 60.
[0078]
A photoresist PR is formed on the Ni 70, the photoresist PR is patterned so that the Ni 70 excluding the region to be the conductive path 51 is exposed, and etching is performed through the photoresist.
[0079]
As described above, when etching is performed using ferric chloride, cupric chloride etchant, etc., the etching rate of Ni 70 is smaller than the etching rate of Cu 60, and thus eaves 58 appears as etching progresses.
[0080]
The circuit element 52 is mounted on the conductive foil 60 in which the separation groove 61 is formed (FIG. 13), the conductive foil 60 and the separation groove 61 are covered with an insulating resin 50, and the back surface of the conductive foil 60 is chemically treated. The process of separating as the conductive path 51 (FIG. 14) and the process up to completion by forming a conductive film on the back surface of the conductive path (FIG. 9) are the same as those in the manufacturing method described above. Therefore, the description is omitted.
[0081]
【The invention's effect】
As is apparent from the above description, the present invention is a circuit device that is configured with the minimum necessary circuit devices, conductive paths, and insulating resin, and that does not waste resources. Therefore, it is possible to realize a circuit device in which there are no extra components until completion and the cost can be significantly reduced.
[0082]
In addition, since the semiconductor bare chip is fixed to the conductive path by the flip chip method, a bonding wire can be eliminated, and the height of the insulating resin coating film and the thickness of the conductive foil are optimized, and the height is 0.5 mm or less. Therefore, it is possible to realize a circuit device that can be made very thin and at the same time reduced in size and weight.
[0083]
Further, since only the back surface of the conductive path is exposed from the insulating resin, the back surface of the conductive path can be immediately used for connection to the outside, and the advantage that the back electrode and the through hole having the conventional structure as shown in FIG. 16 can be eliminated. Have
[0084]
In addition, this circuit device has a structure in which the surface of the separation groove and the surface of the conductive path have a flat surface that is substantially coincident, and when the narrow pitch QFP is mounted, the circuit device itself is leveled by the surface tension of the solder as it is. Since it can move, correction of electrode displacement becomes very easy.
[0085]
In addition, since the second material is formed on the front side of the conductive path, it is possible to suppress warping of the mounting substrate, particularly warpage or peeling of the elongated wiring due to a difference in thermal expansion coefficient.
[0086]
Further, by forming a film made of the second material on the surface of the conductive path, an eaves attached to the conductive path can be formed. Therefore, an anchor effect can be generated, and the warpage and disconnection of the conductive path can be prevented.
[0087]
In the method of manufacturing a circuit device according to the present invention, the conductive foil itself, which is a material of the conductive path, functions as a support substrate, and the conductive foil is used until the separation groove is formed, the circuit element is mounted, or the insulating resin is applied. When supporting the whole and separating the conductive foil as each conductive path, an insulating resin is used as a support substrate to function. Therefore, the circuit element, conductive foil, and insulating resin can be manufactured with the minimum necessary. As described in the conventional example, a support substrate is not necessary in constructing a circuit device originally, and the cost can be reduced. In addition, the support substrate is unnecessary, the conductive path is embedded in the insulating resin, and the thickness of the insulating resin and the conductive foil can be adjusted, and the bonding wire is unnecessary, so that it is very thin. There is also an advantage that a circuit device can be formed.
[0088]
Further, as apparent from FIG. 18, the through hole forming process, conductor printing process (in the case of a ceramic substrate), etc. can be omitted, so that the manufacturing process can be greatly shortened compared to the prior art, and the entire process can be made in-house. Have Also, a frame mold is not required at all, and this is a manufacturing method with extremely short delivery time.
[0089]
Next, until the process of removing the conductive foil thinner than the thickness of the conductive foil (for example, half-etching), since the conductive paths can be handled without being separated individually, many circuit devices are integrated and manufactured on an extremely small substrate. It also has improved characteristics.
[0090]
Further, since the same surface is formed by the conductive path and the insulating resin, the mounted circuit device can be shifted without hitting the side surface of the conductive path on the mounting substrate. In particular, it is possible to reposition the circuit devices mounted with their positions shifted in the horizontal direction. In addition, if the brazing material is melted after the circuit device is mounted, the circuit device that has been mounted out of position tries to return to the upper part of the conductive path by the surface tension of the melted brazing material and can be rearranged by the circuit device itself. It becomes.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a circuit device of the present invention.
FIG. 2 is a cross-sectional view illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 3 is a cross-sectional view illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 4 is a cross-sectional view illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 5 is a cross-sectional view illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 6 is a cross-sectional view illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 7 is a plan view illustrating the method for manufacturing the circuit device of the present invention.
FIG. 8 is a cross-sectional view illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 9 is a cross-sectional view illustrating a circuit device of the present invention.
FIG. 10 is a cross-sectional view illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 11 is a cross-sectional view illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 12 is a cross-sectional view illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 13 is a cross-sectional view illustrating a method for manufacturing a circuit device of the present invention.
FIG. 14 is a cross-sectional view illustrating a method for manufacturing a circuit device according to the present invention.
FIG. 15 is a cross-sectional view illustrating a mounting structure of a conventional circuit device.
FIG. 16 is a cross-sectional view illustrating a conventional circuit device.
FIG. 17 is a cross-sectional view illustrating a conventional method for manufacturing a circuit device.
FIG. 18 is a diagram for explaining a conventional method of manufacturing a circuit device according to the present invention.
[Explanation of symbols]
50 Insulating resin 51 Conductive path 52 Circuit element 53 Circuit device 54 Separation groove 58 Eaves

Claims (16)

導電箔を用意し、少なくとも導電路と成る領域を除いた前記導電箔に、前記導電箔の厚みよりも浅い分離溝を形成して導電路を形成する工程と、
所望の前記導電路上に回路素子の表面電極を固着する工程と、
該回路素子の裏面電極と所望の前記導電路を金属接続板で接続する工程と、
前記回路素子を被覆し、前記分離溝に充填されるように絶縁性樹脂でモールドする工程と、
前記分離溝を設けていない厚み部分の前記導電箔を除去する工程とを具備することを特徴とする回路装置の製造方法。
Preparing a conductive foil, forming a conductive path by forming a separation groove shallower than the thickness of the conductive foil on the conductive foil excluding at least a region to be a conductive path; and
Fixing a surface electrode of a circuit element on a desired conductive path;
Connecting the back electrode of the circuit element and the desired conductive path with a metal connection plate;
Covering the circuit element and molding with an insulating resin so as to fill the separation groove;
And a step of removing the conductive foil in a thickness portion where the separation groove is not provided.
導電箔を用意し、該導電箔表面の少なくとも導電路となる領域に耐食性の導電被膜を形成する工程と、
少なくとも導電路となる領域を除いた前記導電箔に、前記導電箔の厚みよりも浅い分離溝を形成して導電路を形成する工程と、
所望の前記導電路上に回路素子の表面電極を固着する工程と、
前記回路素子の裏面電極と所望の前記導電路を金属接続板で接続する工程と、
前記回路素子を被覆し、前記分離溝に充填されるように絶縁性樹脂でモールドする工程と、
前記分離溝を設けていない厚み部分の前記導電箔を除去する工程とを具備することを特徴とする回路装置の製造方法。
Preparing a conductive foil, and forming a corrosion-resistant conductive film in at least a region that becomes a conductive path on the surface of the conductive foil;
Forming a conductive path by forming a separation groove shallower than the thickness of the conductive foil in the conductive foil except at least a region to be a conductive path;
Fixing a surface electrode of a circuit element on a desired conductive path;
Connecting the back electrode of the circuit element and the desired conductive path with a metal connection plate;
Covering the circuit element and molding with an insulating resin so as to fill the separation groove;
And a step of removing the conductive foil in a thickness portion where the separation groove is not provided.
導電箔を用意し、少なくとも導電路と成る領域を除いた前記導電箔に、前記導電箔の厚みよりも浅い分離溝を形成して導電路を形成する工程と、
所望の前記導電路上に回路素子の表面電極を固着する工程と、
前記回路素子の裏面電極と所望の前記導電路を金属接続板で接続する工程と、
前記回路素子を被覆し、前記分離溝に充填されるように絶縁性樹脂でモールドする工程と、
前記分離溝を設けていない厚み部分の前記導電箔を除去する工程と、
前記絶縁性樹脂を切断して個別の回路装置に分離する工程とを具備することを
特徴とする回路装置の製造方法。
Preparing a conductive foil, forming a conductive path by forming a separation groove shallower than the thickness of the conductive foil on the conductive foil excluding at least a region to be a conductive path; and
Fixing a surface electrode of a circuit element on a desired conductive path;
Connecting the back electrode of the circuit element and the desired conductive path with a metal connection plate;
Covering the circuit element and molding with an insulating resin so as to fill the separation groove;
Removing the conductive foil in a thickness portion not provided with the separation groove;
And a step of cutting the insulating resin and separating it into individual circuit devices.
導電箔を用意し、少なくとも導電路と成る領域を除いた前記導電箔に、前記導電箔の厚みよりも浅い分離溝を形成して導電路を形成する工程と、
所望の前記導電路上に複数の回路素子の表面電極を固着する工程と、
前記回路素子の裏面電極と所望の前記導電路を金属接続板で接続する工程と、
前記複数の回路素子を被覆し、前記分離溝に充填されるように絶縁性樹脂でモールドする工程と、
前記分離溝を設けていない厚み部分の前記導電箔を除去する工程と、
前記絶縁性樹脂を切断して個別の回路装置に分離する工程とを具備することを特徴とする回路装置の製造方法。
Preparing a conductive foil, forming a conductive path by forming a separation groove shallower than the thickness of the conductive foil on the conductive foil excluding at least a region to be a conductive path; and
Fixing the surface electrodes of a plurality of circuit elements on a desired conductive path;
Connecting the back electrode of the circuit element and the desired conductive path with a metal connection plate;
Coating the plurality of circuit elements and molding with an insulating resin so as to fill the separation grooves;
Removing the conductive foil in a thickness portion not provided with the separation groove;
And a step of cutting the insulating resin and separating it into individual circuit devices.
導電箔を用意し、少なくとも導電路と成る領域を除いた前記導電箔に、前記導電箔の厚みよりも浅い分離溝を形成して導電路を形成する工程と、
所望の前記導電路上に回路素子の表面電極を固着する工程と、
前記回路素子の裏面電極と所望の前記導電路を金属接続板で接続する工程と、
前記回路素子を被覆し、前記分離溝に充填されるように絶縁性樹脂でモールドする工程と、
前記分離溝を設けていない厚み部分の前記導電箔を裏面より一様に除去し前記導電路の裏面と前記分離溝間の前記絶縁性樹脂とを実質的に平坦面にする工程とを具備することを特徴とする回路装置の製造方法。
Preparing a conductive foil, forming a conductive path by forming a separation groove shallower than the thickness of the conductive foil on the conductive foil excluding at least a region to be a conductive path; and
Fixing a surface electrode of a circuit element on a desired conductive path;
Connecting the back electrode of the circuit element and the desired conductive path with a metal connection plate;
Covering the circuit element and molding with an insulating resin so as to fill the separation groove;
Removing the conductive foil of a thickness portion not provided with the separation groove uniformly from the back surface to make the back surface of the conductive path and the insulating resin between the separation grooves substantially flat. A method for manufacturing a circuit device.
導電箔を用意し、少なくとも導電路となる領城を除いた前記導電箔に、前記導電箔の厚みよりも浅い分離溝を形成して導電路を形成する工程と、
所望の前記導電路上に回路素子の表面電極を固着する工程と、
前記回路素子の裏面電極と所望の前記導電路を金属接続板で接続する工程と、
前記回路素子を被覆し、前記分離溝に充填されるように絶縁性樹脂でモールドする工程と、
前記分離溝を設けていない厚み部分の前記導電箔を裏面より一様に除去し前記導電路の裏面と前記分離溝間の前記絶縁性樹脂とを実質的に平坦面にする工程と、
前記絶縁性樹脂を切断して個別の回路装置に分離する工程とを具備することを特徴とする回路装置の製造方法。
Preparing a conductive foil, forming a conductive path by forming a separation groove shallower than the thickness of the conductive foil on the conductive foil excluding the castle that becomes a conductive path; and
Fixing a surface electrode of a circuit element on a desired conductive path;
Connecting the back electrode of the circuit element and the desired conductive path with a metal connection plate;
Covering the circuit element and molding with an insulating resin so as to fill the separation groove;
Removing the conductive foil of the thickness portion not provided with the separation groove uniformly from the back surface to make the insulating resin between the back surface of the conductive path and the separation groove substantially flat; and
And a step of cutting the insulating resin and separating it into individual circuit devices.
前記導電箔は銅、アルミニウム、鉄−ニッケルのいずれかで構成されることを特徴とする請求項から請求項のいずれかに記載された回路装置の製造方法。The conductive foil is copper, aluminum, iron - method of manufacturing has been the circuit device according to any one of claims 1 to 6, characterized in that it is composed of either nickel. 前記導電被膜はニッケル、金あるいは銀メッキ形成されることを特徴とする請求項に記載された回路装置の製造方法。 3. The method of manufacturing a circuit device according to claim 2 , wherein the conductive film is formed by nickel, gold or silver plating. 前記導電箔に選択的に形成される前記分離溝は化学的あるいは物理的エッチングにより形成されることを特徴とする請求項から請求項のいずれかに記載された回路装置の製造方法。The isolation trench chemical or physical method of manufacturing has been the circuit device according to any one of claims 1 to 6, characterized in that it is formed by etching is selectively formed on the conductive foil. 前記導電被膜を前記分離溝形成時のマスクの一部として使用することを特徴とする請求項に記載された回路装置の製造方法。9. The method of manufacturing a circuit device according to claim 8 , wherein the conductive film is used as a part of a mask when the separation groove is formed. 前記回路素子は半導体ベアチップを固着されることを特徴とする請求項から請求項のいずれかに記載された回路装置の製造方法。The circuit element manufacturing method of the a circuit device according to claims 1, characterized in that it is affixed to a semiconductor bare chip to claim 6. 前記金属接続板は半田あるいは導電ぺーストで固着されることを特徴とする請求項から請求項のいずれかに記載された回路装置の製造方法。Method for producing a metal connecting plate is a circuit device according to any one of claims 1 to 6, characterized in that it is secured by solder or conductive paste. 前記絶縁性樹脂はトランスファーモールドで付着されることを特徴とする請求項から請求項のいずれかに記載された回路装置の製造方法。The insulating resin production method of the a circuit device according to any one of claims 1 to 6, characterized in that it is deposited in the transfer molding. 前記絶縁性樹脂はダイシングにより個別の回路装置に分離することを特徴とする請求項、請求項あるいは請求項のいずれかに記載された回路装置の製造方法。The insulating resin according to claim 3, characterized in that the separation into individual circuit devices by dicing, a manufacturing method of the a circuit device according to claim 4 or claim 6. 少なくとも導電路と成る領域を除いた導電箔に、該導電箔の厚みよりも浅い分離溝を形成して導電路が形成された導電箔を用意する工程と、  A step of preparing a conductive foil in which a conductive path is formed by forming a separation groove shallower than the thickness of the conductive foil on the conductive foil excluding at least a region to be a conductive path;
所望の前記導電路上に回路素子の表面電極を固着する工程と、  Fixing a surface electrode of a circuit element on a desired conductive path;
該回路素子の裏面電極と所望の前記導電路を金属接続板で接続する工程と、  Connecting the back electrode of the circuit element and the desired conductive path with a metal connection plate;
前記回路素子を被覆し、前記分離溝に充填されるように絶縁性樹脂でモールドする工程と、  Covering the circuit element and molding with an insulating resin so as to fill the separation groove;
前記分離溝を設けていない厚み部分の前記導電箔を除去する工程とを具備することを特徴とする回路装置の製造方法。  And a step of removing the conductive foil in a thickness portion where the separation groove is not provided.
少なくとも導電路と成る領域を除いた導電箔に、該導電箔の厚みよりも浅い分離溝を形成して導電路が形成された導電箔を用意する工程と、  A step of preparing a conductive foil in which a conductive path is formed by forming a separation groove shallower than the thickness of the conductive foil on the conductive foil excluding at least a region to be a conductive path;
所望の前記導電路上に複数の回路素子の表面電極を固着する工程と、  Fixing the surface electrodes of a plurality of circuit elements on a desired conductive path;
前記回路素子の裏面電極と所望の前記導電路を金属接続板で接続する工程と、  Connecting the back electrode of the circuit element and the desired conductive path with a metal connection plate;
前記複数の回路素子を被覆し、前記分離溝に充填されるように絶縁性樹脂でモールドする工程と、  Coating the plurality of circuit elements and molding with an insulating resin so as to fill the separation grooves;
前記分離溝を設けていない厚み部分の前記導電箔を除去する工程と、  Removing the conductive foil in a thickness portion not provided with the separation groove;
前記絶縁性樹脂を切断して個別の回路装置に分離する工程とを具備することを特徴とする回路装置の製造方法。  And a step of cutting the insulating resin and separating it into individual circuit devices.
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