JP5003418B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which comprises a PoP structure of a vertical semiconductor element and does not use a bonding wire for connecting the semiconductor elements, and its manufacturing method. <P>SOLUTION: The semiconductor device 100 includes the PoP structure in which a packaged High-side MOS 32 and a packaged Low-side MOS 28 are sequentially stacked on a circuit board 2. A first source electrode 39 of a High-side MOS 34 is connected to a second drain electrode 24 of a Low-side MOS 22 through two conductive plates 10d, 16c pinching solder 14. Each of conducting path groups 6a, 6b, 6c, 6d and 6e which is energized to electrode groups 39, 38 and 40 of the High-side MOS 34 and electrode groups 20, 26 and 24 of the Low-side MOS 22 penetrates a sealing resin 30 of a package at a low step to be connected to the circuit board 2. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device in which packaged vertical semiconductor elements are stacked and a manufacturing method thereof.

  Semiconductor devices in which packaged semiconductor elements are connected in series have become widespread. For example, a semiconductor device in which a vertical semiconductor element that controls high power, such as a power MOS or IGBT, is packaged for surface mounting on a circuit board and connected in series is widely used.

  FIG. 23 shows an example of a cross-sectional view of a conventional semiconductor device 200 in which packaged power MOSs are connected in series. The semiconductor device 200 includes a first packaged power MOS 82, a second packaged power MOS 78, and a circuit board 92. The first packaged power MOS 82 and the second packaged power MOS 78 are surface-mounted on a circuit board 92, respectively.

  The first packaged power MOS 82 includes a vertical power MOS 84 and a sealing resin 70 that covers the power MOS 84. The power MOS 84 includes a first gate electrode 88 exposed at a part of the upper surface, a first source electrode 89 exposed at the remaining portion of the upper surface, and a first drain electrode 90 exposed at the lower surface. . The first source electrode 89 is connected to the first source circuit 76 c on the circuit board 92 via the bonding wire 58 c, the first source terminal 96 c, and the solder 94. The first gate electrode 88 is connected to the first gate circuit 76 a on the circuit board 92 through the bonding wire 58 d, the first gate terminal 96 a, and the solder 94. The first drain electrode 90 is connected to the first drain terminal 96 b and the first drain circuit 76 b on the circuit board 92 via the solder 94.

  The second packaged power MOS 78 includes a vertical power MOS 64 and a sealing resin 70 that covers the power MOS 64. The structure of the second packaged power MOS 78 is similar to the structure of the first packaged power MOS 82. The power MOS 64 includes a second gate electrode 68 exposed at a part of the upper surface, a second source electrode 69 exposed at the remaining portion of the upper surface, and a second drain electrode 80 exposed at the lower surface. . The second source electrode 69 is connected to the second source circuit 76 f on the circuit board 92 through the bonding wire 58 a, the second source terminal 96 f, and the solder 94. The second gate electrode 68 is connected to the second gate circuit 76 d on the circuit board 92 through the bonding wire 58 b, the second gate terminal 96 d, and the solder 94. The second drain electrode 80 is connected to the second drain terminal 96e and the second drain circuit 76e on the circuit board 92 via the solder 94. On the circuit board 92, the first source circuit 76c and the second drain circuit 76e are connected.

  FIG. 24 is a perspective view of a part of the semiconductor device 200. The packaged power MOSs 82 and 78 are surface-mounted on the circuit board 92 via solder 94, respectively. The second drain circuit 76e is electrically connected to the first source circuit 76c on the circuit board 92. A circuit connecting the second drain circuit 76e and the first source circuit 76c is branched, and the branched circuit is connected to the intermediate circuit 76g. A part of the drain current of the power MOS 64 can be taken out from the intermediate circuit 76g.

  Next, the operation of the semiconductor device 200 will be described. The semiconductor device 200 includes five circuits 76 a, 76 b, 76 d, 76 f, and 76 g that can flow current from the outside and can extract current from the outside. The power MOS 64 is turned on by turning on the second source circuit 76f and the second gate circuit 76d. When the power MOS 64 is turned on, a drain current flows through the second drain circuit 76e. The power MOS 84 is turned on by turning on the first source circuit 76c using a part of the drain current and further turning on the first gate circuit 76a. When the power MOS 84 is turned on, a drain current flows through the first drain circuit 76b, and the drain current can be extracted to the outside.

  Since the semiconductor device 200 has two packaged power MOSs 82 and 78 arranged on the circuit board 92 and surface-mounted, the board area required for mounting is large. Further, since the circuit wiring is provided on the circuit board 92 and the two packaged power MOSs 82 and 78 are connected, there is a concern about the influence of noise due to the inductance of the circuit wiring.

  On the other hand, by laminating the two packaged power MOSs 82 and 78, the substrate area required for surface mounting can be reduced, and the influence of noise caused by circuit wiring can be eliminated. Thus, a structure in which two packages are stacked is known as a Package on Package structure (hereinafter referred to as a PoP structure). However, a semiconductor device having a PoP structure of a vertical semiconductor element such as the power MOSs 82 and 78 has not been proposed so far.

  In order to form a PoP structure in which two packaged vertical power MOSs are stacked, it is necessary to connect the drain electrode of the power MOS stacked in the upper stage and the source electrode of the lower power MOS. It becomes. When two electrodes are connected by a bonding wire, there is a concern about the influence of noise caused by the wire.

  The present invention has been proposed to solve the above problems. That is, the present invention proposes a semiconductor device having a vertical semiconductor element PoP structure and using no wires for connection between the semiconductor elements. Another object of the present invention is to provide a method for manufacturing such a semiconductor device.

The present invention relates to a semiconductor device in which a first packaged semiconductor element and a second packaged semiconductor element are sequentially stacked on a circuit board.
In the semiconductor device of the present invention, the first packaged semiconductor element has a first control electrode exposed at a part of the upper surface, a first upper main electrode exposed at the remaining portion of the upper surface, and a lower surface. An exposed first lower main electrode is provided. That is, in the semiconductor device of the present invention, the first packaged semiconductor element is a vertical semiconductor element. The kind of semiconductor element is not limited. As long as it is a vertical semiconductor element, it may be, for example, a power MOS or an IGBT. The first control electrode may be divided into a plurality of electrodes. Some of the control electrodes may be electrodes for detecting a state of the semiconductor device and extracting a state quantity for contributing to control.

  In the semiconductor device of the present invention, the first packaged semiconductor element is connected to the sealing resin that covers a portion other than the electrode of the semiconductor element, and the first control electrode via the conductive material, and the sealing resin A first control conductive plate exposed from the upper surface of the first upper conductive plate, a first upper main conductive plate connected to the first upper main electrode via a conductive material and exposed from the upper surface of the sealing resin, A first lower main conductive plate is connected to the lower main electrode via a conductive material and exposed from the lower surface of the sealing resin. The material of the conductive plate is not limited. Further, the conductive material is not limited. For example, it may be solder or an anisotropic conductive material. When the control conductive plate is divided into a plurality of parts, the control conductive plate is also divided into a plurality of parts.

  In the semiconductor device of the present invention, the first packaged semiconductor element includes a plurality of conductive path groups penetrating the sealing resin in the thickness direction and exposed from the lower surface of the sealing resin. The conductive path group includes a main conductive path, an intermediate conductive path, a first control conductive path, and a second control conductive path. The material constituting the conductive path group is not limited to one type. It includes a structure in which a plurality of conductive plates are connected via a conductive material to form one conductive path. Each of the conductive path groups is not in contact with each other, and is insulated from other conductive paths via a sealing resin.

  In the semiconductor device of the present invention, the main conductive path includes a main conductive path conductive plate that is connected to the upper surface of the main conductive path via a conductive material and exposed from the upper surface of the sealing resin. The intermediate conductive path includes an intermediate conductive plate that is connected to the upper surface via a conductive material and exposed from the upper surface of the sealing resin. The first control conductive path includes a relay conductive plate that is connected to the upper surface via a conductive material and exposed from the upper surface of the sealing resin. The second control conductive path includes a second control conductive path conductive plate that is connected to the upper surface of the second control conductive path via a conductive material and exposed from the upper surface of the sealing resin. The material of the conductive plate is not limited.

  In the semiconductor device of the present invention, the second packaged semiconductor element has a second control electrode exposed at a part of the upper surface, a second upper main electrode exposed at the remaining upper surface, and a lower surface. An exposed second lower main electrode is provided. That is, in the semiconductor device of the present invention, the second packaged semiconductor element is a vertical semiconductor element. The kind of semiconductor element is not limited. As long as it is a vertical semiconductor element, it may be, for example, a power MOS or an IGBT.

  In the semiconductor device of the present invention, the second packaged semiconductor element is electrically connected to the sealing resin that covers a portion other than the second lower main electrode of the semiconductor element, and the lower surface of the sealing resin. And a control terminal which is electrically connected to the second control electrode and exposed from the lower surface of the sealing resin. Each of the main terminal and the control terminal may be electrically connected to the semiconductor element, and the connection means is not limited. For example, they may be connected by bonding wires.

  In the semiconductor device of the present invention, the second packaged semiconductor element is connected to the second lower main electrode through the conductive material and exposed from the lower surface of the sealing resin. And a relay terminal exposed from the lower surface of the sealing resin. The relay terminal is not connected to the second packaged semiconductor element.

  In the semiconductor device of the present invention, the main terminal is connected to the main conductive path conductive plate via the conductive material, and the second lower main conductive plate is connected to the intermediate conductive plate and the first upper main conductive plate via the conductive material. The relay terminal is connected to the first control conductive plate and the relay conductive plate via the conductive material, and the control terminal is connected to the second control conductive path conductive plate via the conductive material. That is, the main conductive path is electrically connected to the second upper main electrode through the main terminal. The second lower main electrode is electrically connected to the intermediate conductive plate and the first upper main electrode through the second lower main conductive plate. The first control conductive path is electrically connected to the first control electrode via the relay terminal. The second control conductive path is electrically connected to the second control electrode via the control terminal.

  In the semiconductor device of the present invention, each lower surface of the conductive path group and the first lower main conductive plate are connected to the circuit board via a conductive material. When a current flows from the upper main electrode to the lower main electrode, the second packaged semiconductor element is turned on by flowing a current from the substrate circuit to the main conductive path and a current to the second control conductive path. When the second packaged semiconductor element is turned on, a current flows through the second lower main conductive plate. A part of the current flows in the intermediate conductive path. The remaining current flows through the first upper main electrode. At this time, by passing a current through the first control conductive path, a current flows through the first control electrode, and the first packaged semiconductor element is turned on. When the first packaged semiconductor element is turned on, a current flows through the first lower main conductive plate, and the current can be extracted to the outside.

According to the semiconductor device of the present invention, it is possible to realize a PoP structure in which two packaged vertical semiconductor elements are stacked. By stacking the two packages up and down, the board area required for surface mounting can be reduced as compared with the case where surface mounting is performed side by side. Miniaturization of the semiconductor device can be realized.
Furthermore, according to the semiconductor device of the present invention, the first packaged semiconductor element and the second packaged semiconductor element are connected via the conductive material. Therefore, no bonding wire is used to connect the semiconductor elements. Since noise is reduced by eliminating wires connecting semiconductor elements, high-speed switching can be realized.

Another semiconductor device of the present invention relates to a semiconductor device in which n packaged semiconductor elements are sequentially stacked on a circuit board.
According to another semiconductor device of the present invention, a packaged semiconductor element stacked in the k-th stage (1 ≦ k ≦ n−1) is exposed to a part of the upper surface of the semiconductor element. A k-th upper main electrode exposed at the remaining portion of the upper surface of the semiconductor element, and a k-th lower main electrode exposed at the lower surface of the semiconductor element. That is, in another semiconductor device of the present invention, the packaged semiconductor elements stacked in the k-th stage are vertical semiconductor elements.

  In another semiconductor device of the present invention, a packaged semiconductor element stacked in the k-th stage is connected to a sealing resin that covers a portion other than the electrode of the semiconductor element and a k-th control electrode through a conductive material. And the kth control conductive plate exposed from the upper surface of the sealing resin and the kth upper surface exposed from the upper surface of the sealing resin while being connected to the kth main electrode through the conductive material The main conductive plate is connected to the k-th lower main electrode through a conductive material and is exposed from the lower surface of the sealing resin, and penetrates the sealing resin in the thickness direction. In addition, a plurality of conductive path groups exposed from the lower surface of the sealing resin are provided. The conductive path group includes one main conductive path, nk intermediate conductive path groups, and nk + 1 control conductive path groups. For example, when n is 5, the packaged semiconductor element stacked in the third stage includes one main conductive path, two intermediate conductive path groups, and three control conductive path groups. Yes.

  In another semiconductor device of the present invention, the xth (1 ≦ x ≦ n−k) intermediate conductive path of the group of intermediate conductive paths of the packaged semiconductor elements stacked in the k-th stage is k + x intermediate. It is assumed that the conductive path is the yth (1 ≦ y ≦ n−k + 1) control conductive path in the control conductive path group, which is the k + y−1 control conductive path. For example, when n = 5, the third intermediate conductive path among the intermediate conductive path groups of the packaged semiconductor elements stacked in the second stage is the fifth intermediate conductive path, and the control conductive path group is The third control conductive path is defined as a fourth control conductive path.

  In a packaged semiconductor element stacked in the k-th stage of another semiconductor device of the present invention, the (k + 1) -th intermediate conductive path is connected to the upper surface via a conductive material and exposed from the upper surface of the sealing resin. An intermediate conductive plate is provided. The k + x (here, x ≧ 2) intermediate conductive path includes an x + k intermediate connection conductive plate that is connected to the upper surface via a conductive material and exposed from the upper surface of the sealing resin. For example, when n = 5, in the packaged semiconductor element stacked in the second stage, the third intermediate conductive path includes an intermediate conductive plate, and the fourth intermediate conductive path is the fourth intermediate connection conductive plate. The fifth intermediate conductive path includes a fifth intermediate connection conductive plate.

  In a packaged semiconductor element stacked in the k-th stage of another semiconductor device of the present invention, the k-th control conductive path is connected to the upper surface via a conductive material and exposed from the upper surface of the sealing resin. The relay conductive plate is provided. The k + y-1 (where y ≧ 2) control conductive path is connected to the upper surface of the conductive plate for the (k + y-1) control conductive path and is exposed from the upper surface of the sealing resin. I have. For example, when n = 5, the second control conductive path of the packaged semiconductor element stacked in the second stage includes a relay conductive plate, and the third control conductive path is a third control conductive path conductor. A fourth control conductive path is provided with a fourth control conductive path conductive plate, and a fifth control conductive path is provided with a fifth control conductive path conductive plate.

  In a packaged semiconductor element stacked in the k-th stage of another semiconductor device of the present invention, the main conductive path is connected to the upper surface via a conductive material and exposed from the upper surface of the sealing resin. A main conductive path conductive plate. One main conductive path is formed in each of the packaged semiconductor elements other than the n-th stage. Further, the packaged semiconductor element stacked in the k-th stage excluding the first stage includes a relay terminal exposed from the lower surface of the sealing resin.

  A packaged semiconductor element stacked in the nth stage of another semiconductor device of the present invention has an nth control electrode exposed on a part of the upper surface of the semiconductor element and an exposed part of the upper surface of the semiconductor element. And an nth lower main electrode exposed on the lower surface of the semiconductor element. That is, in another semiconductor device of the present invention, a packaged semiconductor element stacked in the nth stage is a vertical semiconductor element.

  A packaged semiconductor element stacked in the nth stage of another semiconductor device of the present invention is electrically connected to a sealing resin covering a portion other than the nth lower main electrode of the semiconductor element and the nth control electrode. Conductive material is applied to the nth control terminal exposed from the lower surface of the sealing resin, the nth main terminal exposed to the lower surface of the sealing resin while being electrically connected to the nth upper main electrode. And an nth lower main conductive plate exposed from the lower surface of the sealing resin and a relay terminal exposed from the lower surface of the sealing resin.

  Between the packaged semiconductor element stacked in the k-th stage (where k is other than n−1) and the packaged semiconductor element stacked in the (k + 1) -th stage of another semiconductor device of the present invention. , The main conductive path of the packaged semiconductor element stacked in the (k + 1) th stage is connected to the conductive plate for the main conductive path of the packaged semiconductor element stacked in the kth stage via a conductive material. For example, when n = 5, the main conductive path of the packaged semiconductor element stacked in the third stage and the main conductive path of the packaged semiconductor element stacked in the fourth stage are connected via the main conductive plate. It is connected.

  Between the packaged semiconductor element stacked in the k-th stage (where k is other than n−1) and the packaged semiconductor element stacked in the (k + 1) -th stage of another semiconductor device of the present invention. The k + x intermediate conductive path of the packaged semiconductor element stacked in the (k + 1) th stage is connected to the k + x intermediate connection conductive plate of the packaged semiconductor element stacked in the kth stage through the conductive material. Has been. For example, when n = 5, the fourth intermediate conductive path of the packaged semiconductor element stacked in the third stage and the fourth intermediate conductive path of the packaged semiconductor element stacked in the second stage are They are connected via an intermediate connection conductive plate.

  Between the packaged semiconductor element stacked in the k-th stage (where k is other than n−1) and the packaged semiconductor element stacked in the (k + 1) -th stage of another semiconductor device of the present invention. , K + y−1 control conduction path of the packaged semiconductor element stacked in the kth stage through the conductive material, and the k + y−1 control conduction path of the packaged semiconductor element stacked in the kth stage through the conductive material. It is connected to the road conductive plate. For example, when n = 5, the fourth control conductive path of the packaged semiconductor element stacked in the third stage and the fourth control conductive path of the packaged semiconductor element stacked in the second stage are The fourth control conductive path conductive plates are connected.

  Between the packaged semiconductor element stacked in the k-th stage (where k is other than n−1) and the packaged semiconductor element stacked in the (k + 1) -th stage of another semiconductor device of the present invention. , The (k + 1) th lower main conductive plate of the (k + 1) th packaged semiconductor element is connected to the intermediate conductive plate and the kth upper main conductive plate of the kth packaged semiconductor element via a conductive material. . For example, when n = 5, the third lower main conductive plate of the packaged semiconductor element stacked in the third stage is connected to the intermediate conductive path of the packaged semiconductor element stacked in the second stage. The second upper main electrode is connected to the second upper main electrode via an intermediate conductive plate and a second upper main conductive plate, respectively.

  Between the packaged semiconductor element stacked in the k-th stage (where k is other than n−1) and the packaged semiconductor element stacked in the (k + 1) -th stage of another semiconductor device of the present invention. , The relay terminal of the k + 1-stage packaged semiconductor element is connected to the k-th control conductive plate and the relay conductive board of the k-th packaged semiconductor element via a conductive material. For example, when n = 5, the relay terminal of the packaged semiconductor element stacked in the third stage is connected to the second control conductive path and the second of the packaged semiconductor element stacked in the second stage. The control electrode is connected to the control electrode via a relay conductive plate and a second control conductive plate, respectively.

  In another semiconductor device of the present invention, a main terminal is connected to a main conductive path through a conductive material between an n-1th packaged semiconductor element and an nth packaged semiconductor element. Yes. The nth lower main conductive plate of the nth packaged semiconductor element is connected to the intermediate conductive plate of the n−1th packaged semiconductor element and the n−1th upper main electrode through a conductive material. ing. The nth relay terminal of the nth stage packaged semiconductor element is connected to the n−1th control conductive plate and the relay conductive board of the n−1th stage packaged semiconductor element via a conductive material. . The control terminal is connected to the conductive plate for the nth control conductive path via a conductive material.

  In another semiconductor device of the present invention, the lower surface of each conductive path group of the first-stage packaged semiconductor element and the first lower main conductive plate are connected to the circuit board via a conductive material. When a current flows from the upper main electrode to the lower main electrode, a current flows from the main conductive path to the nth upper main electrode by flowing a current from the substrate circuit to the main conductive path. By causing a current to flow from the substrate circuit to the nth control conductive path, a current flows from the nth control conductive path to the nth control electrode. By supplying both currents, the nth (uppermost) packaged semiconductor element is turned on. When the nth packaged semiconductor element is turned on, a current flows through the nth lower main conductive plate. A part of the current flows through an intermediate conductive path connected to the nth lower main conductive plate. The remaining current flows to the (n-1) -th upper main electrode of the packaged semiconductor element in the (n-1) th stage. At this time, by supplying a current to the (n−1) th control conductive path connected to the (n−1) th control electrode, the n−1th stage packaged semiconductor element is turned on.

  In another semiconductor device of the present invention, when an n−1th packaged semiconductor element is turned on, a current flows through the n−1th lower main conductive plate. A part of the current flows through an intermediate conductive path connected to the (n-1) th lower main conductive plate. The remaining current flows to the (n-2) -th upper main electrode. At this time, by supplying a current to the n-2th control conductive path connected to the n-2th control electrode, the n-2th packaged semiconductor element is turned on. Thereafter, the packaged semiconductor elements from the n-3rd stage to the first stage are turned on by the same procedure. When the first-stage packaged semiconductor element is turned on, a current flows through the first lower main conductive plate of the first-stage packaged semiconductor element, and the current can be extracted to the outside.

According to the above semiconductor device, a structure in which three or more packaged vertical semiconductor elements are sequentially stacked can be realized. By laminating three or more packaged semiconductor elements in order, the board area required for surface mounting is increased compared to the case where three or more packaged semiconductor elements are arranged side by side and surface mounted. Can be reduced. Miniaturization of the semiconductor device can be realized.
Further, according to the semiconductor device, the packaged semiconductor elements are connected via the conductive material. Therefore, no bonding wire is used to connect the semiconductor elements. Since noise is reduced by eliminating wires connecting semiconductor elements, high-speed switching can be realized.

The method for manufacturing a semiconductor device of the present invention relates to a method for manufacturing a first packaged semiconductor element (hereinafter referred to as a first package manufacturing method). The second packaged semiconductor element can be manufactured by a conventional manufacturing method as described later.
The manufacturing method of the 1st package of this invention is equipped with the process (1st mask formation process) of forming the metal plating or resist film which has the patterned opening on the upper surface of a 1st electroconductive board.
In the first package manufacturing method of the present invention, after the first mask formation step, a plurality of convex portions are formed by etching from the upper surface side to a depth not penetrating the first conductive plate using a metal plating or resist film as a mask. (First etching step). The etching method is not limited. Isotropic etching may be performed or anisotropic etching may be performed. When the resist film is used as a mask, the resist film is removed by ashing after the first etching step.

The manufacturing method of the 1st package of this invention is equipped with the process (connection fixing process) of connecting and fixing a semiconductor element in the range etched at the 1st etching process. As a semiconductor device connection fixing method, for example, die bonding is performed. By connecting and fixing the semiconductor element to the first conductive plate, the first lower main electrode of the semiconductor element and the first conductive plate become conductive.
In the first package manufacturing method of the present invention, the second conductive plate connected to the upper surface of the plurality of convex portions, the first upper main electrode of the semiconductor element, and the first control electrode via the conductive material is formed. A process (electrode formation process) is provided. As the second conductive plate, individual conductive plates may be used, or a single continuous conductive plate may be used. Further, solder may be used as the conductive material, or another conductive material such as an anisotropic conductive material may be used.
The manufacturing method of the 1st package of this invention is equipped with the process (sealing process) of resin sealing so that a part other than the electrode of a semiconductor element and a 1st conductive plate may be covered, and a 2nd conductive plate may be exposed. .

  In the first package manufacturing method of the present invention, the first conductive plate is etched from the lower surface side, and a part of the first conductive plate is removed so that the first lower main electrode and each of the plurality of convex portions are insulated. The process to do is provided. The etching method is not limited. Isotropic etching may be performed or anisotropic etching may be performed. Since the upper surface side of the first conductive plate is covered with the sealing resin, the sealing resin serves as an etching stop, and the progress of etching from the lower surface side stops. Here, the lower surface side refers to the rear surface side when the upper surface is the front surface. By this etching, a plurality of conductive path groups are formed which penetrate the sealing resin in the thickness direction and whose both ends are exposed from the sealing resin.

With the above manufacturing method, the first packaged semiconductor device of the present invention can be manufactured.
The second packaged semiconductor device can be manufactured by a process similar to the conventional method for manufacturing a packaged semiconductor device. Each of the conductive path group of the first packaged semiconductor element manufactured by the method and the second main conductive plate is connected to the circuit board via a conductive material. Further, the second packaged semiconductor element manufactured by the conventional manufacturing method is stacked on the first packaged semiconductor element, and the packaged semiconductor elements are connected via the conductive material. Thus, a semiconductor device can be manufactured. A semiconductor device having a packaged vertical semiconductor element PoP structure can be manufactured.

According to the semiconductor device manufactured by the above manufacturing method, by stacking the two packages up and down, the substrate area required for surface mounting can be reduced as compared with the case where surface mounting is performed side by side. Miniaturization of the semiconductor device can be realized.
Furthermore, according to the semiconductor device manufactured by the above manufacturing method, the first packaged semiconductor element and the second packaged semiconductor element are connected via the conductive material. Therefore, noise is reduced by eliminating the wires between the semiconductor elements, so that high-speed switching can be realized. By manufacturing the first packaged semiconductor element by the manufacturing method of the present invention, a semiconductor device having a vertical semiconductor element PoP structure and using no bonding wire for connection between the semiconductor elements is provided. Can be manufactured.

  In the first package manufacturing method of the present invention, the second conductive plate used in the electrode forming step is one continuous conductive plate, and in the sealing step, the space between the first conductive plate and the second conductive plate is filled with a sealing resin. And a second mask forming step for forming a metal plating or resist film having openings patterned on the surface of the second conductive plate after the sealing step, and a mask for the metal plating or resist film after the second mask forming step. The second conductive plate is further etched to remove a part of the second conductive plate so that the first upper main electrode, the first control electrode, and the plurality of convex portions are insulated from each other. It is preferable.

  According to the above manufacturing method, one continuous conductive plate is connected as the second conductive plate to the top surfaces of the plurality of convex portions, the first upper main electrode of the semiconductor element, and the first control electrode, Two conductive plates are etched away. Therefore, it is not necessary to individually connect the second conductive plate to the top surfaces of the plurality of convex portions, the first upper main electrode of the semiconductor element, and the first control electrode. In addition, the separated second conductive plates connected to the upper surfaces of the plurality of convex portions and the first main electrode and the control electrode of the semiconductor element are formed on the same plane. Furthermore, since a sealing resin is filled between the first conductive plate and the second conductive plate in the sealing step, no mold is required for resin sealing. The sealing process can be easily performed.

  In the first package manufacturing method of the present invention, the second conductive plate used in the electrode forming step is one continuous conductive plate, and after the connection fixing step, a resist film is formed on the surface of the first conductive plate, and then The second mask formation step, the second etching step, and the sealing step are sequentially performed. In the sealing step, resin sealing is performed so as to cover the second conductive plate, and then the second conductive plate is exposed until the second conductive plate is exposed. It is preferable to further include a step of polishing the resin from the upper surface side.

  According to the above manufacturing method, one conductive plate is used as the second conductive plate, connected to the upper surfaces of the plurality of convex portions, the first main electrode and the control electrode of the semiconductor element, and then the second conductive plate is etched. To separate. Therefore, it is not necessary to individually connect the second conductive plate to the top surfaces of the plurality of convex portions, the first upper main electrode of the semiconductor element, and the first control electrode. In addition, since the second conductive plate is exposed by polishing the upper surface side of the sealing resin after the sealing step, the upper surface of the sealing resin and the second conductive plate can be formed in the same plane. The upper surface side of the first packaged semiconductor element can be formed flat.

  According to the present invention, it is possible to provide a semiconductor device having a PoP structure of vertical semiconductor elements and using no bonding wires for connection between the semiconductor elements. A method for manufacturing such a semiconductor device can also be provided. Further, it is possible to provide a semiconductor device having a structure in which three or more packaged vertical semiconductor elements are stacked and using no bonding wire for connection between the semiconductor elements.

Preferred features of the embodiments described below are listed.
(First Feature) A high melting point solder is used as a conductive material used in the package, and a cut groove that opens to the outside of the package is formed at one or more locations in the first source conductive plate and the first gate conductive plate.

(First embodiment)
FIG. 1 is a sectional view of a semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device 100 includes two vertical power MOSs 32 and 28 that are packaged. The semiconductor device 100 has a PoP structure. The power MOS 34 in the lower package is a high-side MOS 34. The power MOS 22 in the package stacked in the upper stage is a low-side MOS 22. In the semiconductor device 100, a high-side MOS 32 packaged on the circuit board 2 (hereinafter referred to as a lower package 32) and a packaged low-side MOS 28 (hereinafter referred to as an upper package 28) are sequentially stacked. Has been.

The high-side MOS 34 includes a first gate electrode (first control electrode) 38 exposed at a part of the upper surface, a first source electrode (first upper main electrode) 39 exposed at the remaining portion of the upper surface, A first drain electrode (first lower main electrode) 40 exposed on the lower surface is provided.
The low-side MOS 22 includes a second gate electrode (second control electrode) 26 exposed at a part of the upper surface, a second source electrode (second upper main electrode) 20 exposed at the remaining portion of the upper surface, A second drain electrode (second lower main electrode) 24 exposed on the lower surface is provided.

  The lower package 32 is covered with a sealing resin 30 except for the electrodes of the high-side MOS 34. A first gate conductive plate (first control conductive plate) 10 c is connected to the first gate electrode 38 through a high melting point solder 8. A first source conductive plate (first upper main conductive plate) 10 d is connected to the first source electrode 39 through a high melting point solder 8. A first drain conductive plate (first lower main conductive plate) 6c is connected and fixed to the first drain electrode 40 by die bonding. Note that the solder connecting the first drain electrode 40 and the first drain conductive plate 6c is not shown. The first source conductive plate 10 d and the first gate conductive plate 10 c are exposed from the upper surface of the sealing resin 30. The first drain conductive plate 6 c is exposed from the lower surface of the sealing resin 30.

  The lower package 32 further includes a plurality of conductive path groups 6 a, 6 b, 6 d, and 6 e that penetrate through the sealing resin 30 in the thickness direction and are exposed from the lower surface of the sealing resin 30. These conductive path groups include a source conductive path (main conductive path) 6e, an intermediate conductive path 6d, a first gate conductive path (first control conductive path) 6b, and a second gate conductive path (second control conductive path). 6a.

  In the upper package 28, the portion other than the second drain electrode 24 of the low-side MOS 22 is covered with the sealing resin 30. The second gate electrode 26 is connected to the gate terminal (control terminal) 16a by a bonding wire 18b. The second source electrode 20 is connected to a source terminal (main terminal) 16d by a bonding wire 18a. The second drain electrode 24 is connected and fixed to the second drain conductive plate (second lower main conductive plate) 16c by die bonding. Note that the solder connecting the second drain electrode 24 and the second drain conductive plate 16c is not shown. The upper package 28 further includes a relay terminal 16b. The relay terminal 16b is not connected to the low-side MOS 22. The source terminal 16d, the second drain conductive plate 16c, the relay terminal 16b, and the gate terminal 16a are exposed from the lower surface of the sealing resin 30, respectively.

  In the semiconductor device 100, a structure of a connection portion between the lower package 32 and the upper package 28 will be described. The source terminal 16d is connected to the source conductive path conductive plate (main conductive path conductive plate) 10f that is electrically connected to the source conductive path 6e via the solder 14. The second drain conductive plate 16c is connected via the solder 14 to the intermediate conductive plate 10e and the first source conductive plate 10d that are conducted to the intermediate conductive path 6d. The relay terminal 16b is connected to the first gate conductive plate 10c conducting to the first gate electrode 38 and the relay conductive plate 10b conducting to the first gate conductive path 6b via the solder 14. The gate terminal 16a is connected to a second gate conductive path conductive plate (second control conductive path conductive plate) 10a which is electrically connected to the second gate conductive path 6a through the solder 14. That is, the source conductive path 6e is electrically connected to the second source electrode 20 of the low-side MOS 22 via the source terminal 16d. The second drain electrode 24 of the low-side MOS 22 is electrically connected to the intermediate conductive path 6d and the first source electrode 39 of the high-side MOS 34 via the second drain conductive plate 16c. The first gate conductive path 6b is electrically connected to the first gate electrode 38 of the high-side MOS 34 via the relay terminal 16b. The second gate conductive path 6a is electrically connected to the second gate electrode 26 of the low-side MOS 22 through the gate terminal 16a.

  In the semiconductor device 100, the conductive path group and the first drain conductive plate 6c are connected to the circuit board 2 via solder. The low-side MOS 22 is turned on by passing a current from the source circuit 36e to the source conductive path 6e and a current from the second gate circuit 36a to the second gate conductive path 6a. When the low-side MOS 22 is turned on, a current flows through the second drain conductive plate 16c. A part of the current can be taken out from the intermediate circuit 36d through the intermediate conductive path 6d. The remaining current flows through the first source electrode 39 of the high-side MOS 34. At the same time, a current flows from the first gate circuit 36b to the first gate conductive path 6b, whereby a current flows to the first gate electrode 38 of the high-side MOS 34, and the high-side MOS 34 is turned on. When the high-side MOS 34 is turned on, a current flows through the first drain conductive plate 6c, and the current can be taken out from the drain circuit 36c.

The semiconductor device 100 has a PoP structure in which two packaged vertical power MOSs 32 and 28 are stacked. By stacking the two packages up and down, the board area required for surface mounting can be reduced as compared with the case where surface mounting is performed side by side. Miniaturization of the semiconductor device can be realized.
Further, in the semiconductor device 100, the lower package 32 and the upper package 28 are connected via the solder 14. Therefore, no bonding wire is used to connect the packages. Since noise is reduced by eliminating the wires connecting the power MOSs 32 and 28, high-speed switching can be realized.

Next, a method for manufacturing the semiconductor device 100 will be described.
2 to 7 show an example of a method for manufacturing the lower package 32 of the semiconductor device 100. FIG. The upper package 28 can be manufactured by a conventional manufacturing method as will be described later.
First, as shown in FIG. 2, a first conductive plate 6 made of a metal such as Cu is prepared.
Next, as shown in FIG. 3, a resist film having patterned openings is formed (first mask forming step). Thereafter, the resist film is used as a mask to etch to a depth not penetrating the first conductive plate 6 to form a plurality of convex portion groups 9 (first etching step). The etching method is not limited. Isotropic etching may be performed or anisotropic etching may be performed. Thereafter, the resist film is removed by ashing.

Next, as shown in FIG. 4, the high-side MOS 34 is connected and fixed to the area 7 etched in the first etching process by die bonding (connection fixing process). Note that the solder connecting the high-side MOS 34 and the first conductive plate 6 is not shown.
Next, as shown in FIG. 5, the second conductive plate 10 a is connected to the upper surface of the plurality of convex portion groups 9, the first source electrode 39 of the high-side MOS 34, and the first gate electrode 38 via high melting point solder 8. 10b, 10c, 10d, 10e, and 10f are individually connected (electrode forming step). At this time, the height is adjusted so that the second conductive plates 10a, 10b, 10c, 10d, 10e, and 10f are connected on the same plane.
Next, as shown in FIG. 6, the portions other than the electrodes of the high-side MOS 34 and the first conductive plate 6 are covered, and the upper surfaces of the second conductive plates 10a, 10b, 10c, 10d, 10e, and 10f are exposed. The resin is sealed with the sealing resin 30 (sealing process).

  Next, as shown in FIG. 7, after forming a mask having a hole formed in the lower surface side of the first conductive plate 6 with a resist film or the like, the first conductive plate 6 is etched from the lower surface side. A part of the first conductive plate 6 is removed so that the one drain electrode 40 and each of the plurality of convex portion groups 9 are insulated. The etching method is not limited. Isotropic etching may be performed or anisotropic etching may be performed. Thereafter, the resist film is removed by ashing. Since the upper surface side of the first conductive plate 6 is covered with the sealing resin 30, the sealing resin 30 serves as an etching stop, and the progress of etching from the lower surface side stops. By this etching, a plurality of conductive path groups that are formed in parallel with the high-side MOS 34 and penetrate the sealing resin 30 in the thickness direction and both ends are exposed from the sealing resin 30 are formed. . Each of the plurality of conductive path groups is formed by laminating the first conductive plate 6, the high melting point solder 8, and the second conductive plates 10a, 10b, 10c, 10d, 10e, and 10f in order from the lower surface side.

The lower package 32 can be manufactured by the above manufacturing method.
One conductive plate is used in the conventional manufacturing method. If an attempt is made to form a conductive path that penetrates the sealing resin 30 using a single conductive plate, a conductive plate equal to the thickness of the package is required. When such a thick conductive plate is used, the amount of side etching increases when etching is performed, and the distance between the conductive paths increases. The substrate area required for surface mounting cannot be reduced. According to the manufacturing method of the lower package 32 of the present invention, since another conductive plate is connected to the upper portion of the first conductive plate 6, it is not necessary to use the thick first conductive plate 6. The distance between the conductive paths does not increase.
In addition, since the electrode portion of the high-side MOS 34 is thin, it is difficult for the conventional manufacturing method to expose the electrode surface and seal the resin so as to cover the high-side MOS 34. However, according to the method of manufacturing the lower package 32 of the present invention, the electrode portion is raised by the high melting point solder 8 and the second conductive plates 10c and 10d. Therefore, the second conductive plates 10c and 10d connected to the electrodes are easily exposed and resin-sealed so as to cover the high-side MOS 34.

The upper package 28 can be manufactured by a process similar to the conventional manufacturing method. An example of a conventional manufacturing method for manufacturing the upper package 28 is shown in FIGS.
First, as shown in FIG. 8, a third conductive plate 16 made of a metal such as Cu is prepared.
Next, as shown in FIG. 9, a resist film having patterned openings is formed. Thereafter, the resist film is used as a mask to etch to a depth not penetrating the third conductive plate 16 to form the convex portion group 59. Thereafter, the resist film is removed by ashing.
Next, as shown in FIG. 10, the low-side MOS 22 is connected and fixed to the area 57 where the third conductive plate 16 is etched by die bonding. At this time, when the lower package 32 and the upper package 28 are stacked, the first source electrode 39 of the high-side MOS 34 and the second drain electrode 24 of the low-side MOS 22 are connected in the thickness direction. Connect to the area that overlaps with. Note that the solder connecting the low-side MOS 22 and the third conductive plate 16 is not shown. Thereafter, the second source electrode 20 and the second gate electrode 26 of the low-side MOS 22 are connected to the convex portion group 59 using bonding wires 18a and 18b, respectively.

Next, as shown in FIG. 11, resin sealing is performed with a sealing resin 30 so as to cover the low-side MOS 22, the bonding wires 18 a and 18 b, and the third conductive plate 16.
Next, as shown in FIG. 12, after forming a mask having a hole to be etched on the lower surface side of the third conductive plate 16 with Au plating 12, the third conductive plate 16 is etched from the lower surface side, A part of the third conductive plate 16 is removed so that the second drain electrode 24 and the convex portion group 59 are insulated from each other. The sealing resin 30 becomes an etching stop, and the progress of etching from the lower surface side stops. The third conductive plate 16 is separated by etching the third conductive plate 16 (reference numerals 16a, 16b, 16c, 16d). At this time, as shown in FIG. 12, the third conductive plate 16 c (second drain conductive plate 16 c) conducting to the second drain electrode 24 may be etched so that a larger area than the second drain electrode 24 remains. preferable. This is because the second drain electrode 24 is conducted not only to the first source electrode 39 but also to the intermediate conductive path 6d in a later step.

The upper package 28 can be manufactured by the above manufacturing method.
The lower package 32 is connected to the circuit board 2 via the solder 4, the upper package 28 manufactured by the conventional manufacturing method is stacked on the lower package 32, and the packages are connected to each other via the solder 14. 100 can be manufactured. The semiconductor device 100 having the PoP structure of the packaged power MOSs 32 and 28 can be manufactured. Note that after the lower package 32 and the upper package are connected, the Au plating 12 does not remain because it diffuses into the solder 14.

When the first source electrode 39 of the high-side MOS 34 is directly connected to the second drain electrode 24 of the low-side MOS 22 via the solder 8 by using a conventional manufacturing method, a thermal stress causes a gap between the semiconductor element and the electrode. There is a high possibility of cracking. When the method for manufacturing the semiconductor device 100 according to the present invention is used, the two electrodes are connected via the two conductive plates sandwiching the solder 14, so that the occurrence of such cracks is suppressed.
Further, the conductive path groups 6a, 6b, 6d, and 6e that are electrically connected to the electrode group are all connected to the substrate circuit 2 through the lower package 32 and are surface-mounted. There is no need to form a conductive path.

(Second embodiment)
Another method for manufacturing the lower package 32 of the semiconductor device 100 according to the second embodiment is shown in FIGS.
Since the procedure up to the connection fixing step is the same as that of the first embodiment, description thereof is omitted.
In the electrode forming step performed after the connection fixing step, as shown in FIG. 13, the upper surface of the plurality of projections 9, the first source electrode 39 of the high-side MOS 34, and the first gate electrode 38 are interposed via the high melting point solder 8. One continuous second conductive plate 10 is connected.
In the sealing step performed after the electrode forming step, the space between the first conductive plate 6 and the second conductive plate 10 is filled with a sealing resin 30 as shown in FIG. Since the sealing resin 30 is filled between two conductive plates, a mold is not used to perform resin sealing. Resin sealing can be performed easily.
After the sealing step, as shown in FIG. 14, Au plating 12 is formed on the surface of the second conductive plate 10 (second mask forming step). The Au plating 12 is formed with a pattern having an opening in an area where the first source electrode 39, the first gate electrode 38, and the plurality of convex portion groups 9 are etched so as to be insulated.

After the second mask formation step, as shown in FIG. 15, the second conductive plate 10 is etched using the Au plating 12 as a mask to each of the plurality of convex portions 9, the first source electrode 39, and the first gate electrode 38. A part of the second conductive plate is removed so as to be insulated (second etching step). By etching the second conductive plate 10, the second conductive plate 10 is separated (reference numerals 10a, 10b, 10c, 10d, 10e, 10f).
After the second mask formation step, as shown in FIG. 16, after forming a mask having a hole to be etched on the lower surface side of the first conductive plate 6 with a resist film or the like, the first conductive plate 6 is moved to the lower surface side. Then, a part of the first conductive plate 6 is removed so that the first drain electrode 40 and each of the plurality of convex portion groups 9 are insulated. Thereafter, the resist film is removed.

The lower package 32 can also be manufactured by the above manufacturing method.
According to the manufacturing method of the lower package 32 described above, one continuous conductive plate is connected as the second conductive plate 10 to each of the plurality of convex portions 9, the first source electrode 39, and the first gate electrode 38. Then, the second conductive plate 10 is separated by etching. Therefore, it is not necessary to individually connect the second conductive plate 10 to the upper surfaces of the plurality of convex portion groups 9, the first source electrode 39, and the first gate electrode 38. Further, the separated second conductive plates 10a, 10b, 10c, 10d, 10e, 10f connected to the upper surfaces of the plurality of projections 9 and the first source electrode 39 and the first gate electrode 38 of the semiconductor element, respectively. Can be formed on the same plane. Furthermore, since the Au plating 12 remains on the upper surface side after the manufacture of the lower package 32, solderability is good when the upper package 28 is connected to the lower package 32 via the solder 14.

(Third embodiment)
Another method for manufacturing the lower package 32 of the semiconductor device 100 according to the third embodiment is shown in FIGS.
Since the procedure up to the connection fixing step is the same as that of the first embodiment, description thereof is omitted.
After the connection fixing step, a resist film 42 is formed on the surface of the first conductive plate 6 as shown in FIG.
In the electrode formation step performed after the formation of the resist film 42, as shown in FIG. 18, the high melting point solder 8 is applied to the upper surface of the plurality of convex portion groups 9, the first source electrode 39 of the high-side MOS 34, and the first gate electrode 38. One continuous second conductive plate 10 is connected through the vias. After the electrode forming step, as shown in FIG. 19, the second mask forming step and the second etching step are sequentially performed by the same procedure as in the second embodiment. In the second etching step, since the resist film 42 is formed on the surface of the first conductive plate 6, the first conductive plate 6 is not etched.
In the sealing step performed after the second etching step, resin sealing is performed so as to cover the second conductive plate 10 and the Au plating 12 as shown in FIG.
After the sealing step, as shown in FIG. 21, the sealing resin 30 is polished from the upper surface side until the second conductive plate 10 is exposed. In the method of manufacturing the lower package 32 of the third embodiment, the Au plating 12 is polished, and therefore does not remain after the lower package 32 is manufactured.
After the polishing, as shown in FIG. 22, after forming a mask having a hole to be etched on the lower surface side of the first conductive plate 6 with a resist film or the like, the first conductive plate 6 is etched from the lower surface side. Then, a part of the first conductive plate 6 is removed so that the first drain electrode 40 and each of the plurality of convex portion groups 9 are insulated. Thereafter, the resist film is removed.

The lower package 32 can also be manufactured by the above manufacturing method.
According to the manufacturing method of the lower package 32 described above, one continuous conductive plate is connected as the second conductive plate 10 to each of the plurality of convex portions 9, the first source electrode 39, and the first gate electrode 38. Then, the second conductive plate 10 is separated by etching. Therefore, it is not necessary to individually connect the second conductive plate 10 to the upper surfaces of the plurality of convex portion groups 9, the first source electrode 39, and the first gate electrode 38. Further, since the second conductive plate 10 is exposed by polishing the upper surface side of the sealing resin 30 after the sealing step, the upper surfaces of the sealing resin 30 and the second conductive plate 10 can be formed in the same plane. . The upper surface side of the lower package 32 can be formed flat.

In the method for manufacturing a semiconductor device of the present invention, high melting point solder is used as a conductive material used in the package, and holes are opened to one or more locations in the first source conductive plate 10d and the first gate conductive plate 10c to the outside of the package. It is preferable to form a cut groove. By using the high melting point solder or the alloyed high melting point solder, it is possible to prevent the solder in the package from melting when mounted on the circuit board. As the high melting point solder, for example, solder of Pb 85% or more, or a solder made of CuSn alloy (Cu ₃ melting point: 640 ° C., Cu ₆ Sn ₅ melting point: 415 ° C.) using Sn-based solder may be used. it can. Further, when a high melting point solder is used as a conductive material used in the package, a void may be generated inside the high melting point solder formed on the surface of the first source electrode or the first gate electrode. When voids occur, the characteristics of the semiconductor device deteriorate. By forming a notch groove that opens to the outside of the package in one or more places in the first source conductive plate or the first gate conductive plate connected to the high melting point solder, the generated voids are moved to the outside of the package. I can escape. Degradation of the semiconductor device can be suppressed.

As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, in the embodiment, a semiconductor device in which packaged power MOSs are stacked is described, but other semiconductor elements may be used. For example, an IGBT may be used. In the embodiment, the semiconductor device in which two packaged semiconductor elements are stacked is described. However, a semiconductor device in which three or more packaged semiconductor elements are stacked may be used.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1 is a sectional view of a semiconductor device 100 according to a first embodiment of the present invention. Process (1) of the method of manufacturing the lower package of the semiconductor device 100 of the first embodiment is shown. Process (2) of the method of manufacturing the lower package of the semiconductor device 100 of the first embodiment is shown. Process (3) of the method for manufacturing the lower package of the semiconductor device 100 of the first embodiment will be described. Process (4) of the manufacturing method of the lower package of the semiconductor device 100 of 1st Example is shown. Process (5) of the method for manufacturing the lower package of the semiconductor device 100 of the first embodiment will be described. Process (6) of the method for manufacturing the lower package of the semiconductor device 100 of the first embodiment will be described. 2 shows a step (1) of a conventional method for manufacturing an upper package of the semiconductor device 100. FIG. Step (2) of the conventional method for manufacturing the upper package of the semiconductor device 100 is shown. 2 shows a step (3) of a conventional method for manufacturing an upper package of the semiconductor device 100. FIG. Step (4) of a conventional method for manufacturing an upper package of the semiconductor device 100 is shown. Step (5) of the conventional method for manufacturing the upper package of the semiconductor device 100 is shown. Process (1) of the method for manufacturing the lower package of the semiconductor device 100 of the second embodiment will be described. Process (2) of the method for manufacturing the lower package of the semiconductor device 100 of the second embodiment will be described. Process (3) of the method for manufacturing the lower package of the semiconductor device 100 of the second embodiment will be described. Process (4) of the method for manufacturing the lower package of the semiconductor device 100 of the second embodiment will be described. Process (1) of the method for manufacturing the lower package of the semiconductor device 100 of the third embodiment will be described. Process (2) of the method for manufacturing the lower package of the semiconductor device 100 of the third embodiment will be described. Process (3) of the method for manufacturing the lower package of the semiconductor device 100 of the third embodiment will be described. Process (4) of the method for manufacturing the lower package of the semiconductor device 100 of the third embodiment will be described. Process (5) of the method for manufacturing the lower package of the semiconductor device 100 of the third embodiment will be described. Process (6) of the method of manufacturing the lower package of the semiconductor device 100 of 3rd Example is shown. A cross-sectional view of a conventional semiconductor device 200 is shown. A perspective view of a part of a conventional semiconductor device 200 is shown.

Explanation of symbols

2, 92: Circuit boards 4, 14, 94: Solder 6: First conductive plate 6a: Second gate conductive path (first conductive plate)
6b: first gate conductive path (first conductive plate)
6c: first drain conductive plate (first conductive plate)
6d: Intermediate conductive path (first conductive plate)
6e: Source conductive path (first conductive plate)
7: Range in which first conductive plate is etched 8: High melting point solder 9, 59: Convex group 10: Second conductive plate 10a: Second source conductive path conductive plate (second conductive plate)
10b: Relay conductive plate (second conductive plate)
10c: first gate conductive plate (second conductive plate)
10d: first source conductive plate (second conductive plate)
10e: Intermediate conductive plate (second conductive plate)
10f: Source conductive path conductive plate (second conductive plate)
12: Au plating 16: Third conductive plate 16a: Gate terminal (third conductive plate)
16b: Relay terminal (third conductive plate)
16c: second drain conductive plate (third conductive plate)
16d: Source terminal (third conductive plate)
18a, 18b, 58a, 58b: Bonding wire 20: Second source electrode 22: Low-side MOS
24: second drain electrode 26: second gate electrode 28: upper package (packaged low-side MOS 22)
30, 70: sealing resin 32: lower package (packaged high-side MOS 34)
34: High-side MOS
36a, 76d: second gate circuit 36b, 76a: first gate circuit 36c: drain circuit 36d, 76g: intermediate circuit 36e: source circuit 76g: intermediate circuit 38: first gate electrode 39: first source electrode 40: first Drain electrode 57: Range in which third conductive plate is etched 64, 84: Power MOS
68: second gate electrode 69: second source electrode 76b: first drain circuit 76c: first source circuit 76e: second drain circuit 76f: second source circuit 78: first packaged semiconductor element 80: first 2 drain electrode 82: second packaged semiconductor element 88: first gate electrode 89: first source electrode 90: first drain electrode 96 a: first gate terminal 96 b: first source terminal 96 d: second gate terminal 96f: second source terminal 100, 200: semiconductor device

Claims (5)

A semiconductor device in which a first packaged semiconductor element and a second packaged semiconductor element are sequentially stacked on a circuit board,
The first packaged semiconductor element is:
A first control electrode exposed on a part of the upper surface of the semiconductor element;
A first upper main electrode exposed at a remaining portion of the upper surface of the semiconductor element;
A first lower main electrode exposed on the lower surface of the semiconductor element;
Sealing resin covering a portion other than the electrode of the semiconductor element;
A first control conductive plate connected to the first control electrode via a conductive material and exposed from the upper surface of the sealing resin;
A first upper main conductive plate connected to the first upper main electrode via a conductive material and exposed from the upper surface of the sealing resin;
A first lower main conductive plate connected to the first lower main electrode via a conductive material and exposed from the lower surface of the sealing resin;
It comprises a plurality of conductive path groups that penetrate the sealing resin in the thickness direction and are exposed from the lower surface of the sealing resin,
The conductive path group includes a main conductive path, an intermediate conductive path, a first control conductive path, and a second control conductive path.
The main conductive path includes a conductive plate for a main conductive path that is connected to an upper surface of the main conductive path via a conductive material and exposed from the upper surface of the sealing resin.
The intermediate conductive path includes an intermediate conductive plate that is connected to the upper surface via a conductive material and exposed from the upper surface of the sealing resin,
The first control conductive path includes a relay conductive plate that is connected to the upper surface of the first control conductive path via a conductive material and exposed from the upper surface of the sealing resin.
The second control conductive path includes a second control conductive path conductive plate that is connected to the upper surface of the second control conductive path via a conductive material and exposed from the upper surface of the sealing resin.
The second packaged semiconductor element is:
A second control electrode exposed on a part of the upper surface of the semiconductor element;
A second upper main electrode exposed in the remaining portion of the upper surface of the semiconductor element;
A second lower main electrode exposed on the lower surface of the semiconductor element;
A sealing resin covering a portion other than the second lower main electrode of the semiconductor element;
A main terminal electrically connected to the second upper main electrode and exposed from the lower surface of the sealing resin;
A control terminal electrically connected to the second control electrode and exposed from the lower surface of the sealing resin;
A second lower main conductive plate connected to the second lower main electrode via a conductive material and exposed from the lower surface of the sealing resin;
It has a relay terminal exposed from the lower surface of the sealing resin,
The main terminal is connected to the conductive plate for the main conductive path via a conductive material;
The second lower main conductive plate is connected to the intermediate conductive plate and the first upper main conductive plate via a conductive material;
The relay terminal is connected to the first control conductive plate and the relay conductive plate via a conductive material;
The control terminal is connected to the second control conductive path conductive plate via a conductive material;
A semiconductor device, wherein a lower surface of each of the conductive path groups and the first lower main conductive plate are connected to the circuit board via a conductive material. A semiconductor device in which n packaged semiconductor elements are sequentially stacked on a circuit board;
Packaged semiconductor elements stacked in the k-th stage (1 ≦ k ≦ n−1)
A kth control electrode exposed on a part of the upper surface of the semiconductor element;
The k-th upper main electrode exposed in the remaining portion of the upper surface of the semiconductor element;
A k-th lower main electrode exposed on the lower surface of the semiconductor element;
Sealing resin covering a portion other than the electrode of the semiconductor element;
A kth control conductive plate connected to the kth control electrode via a conductive material and exposed from the upper surface of the sealing resin;
A k-th upper main conductive plate connected to the k-th upper main electrode through a conductive material and exposed from the upper surface of the sealing resin;
A k-th lower main conductive plate connected to the k-th lower main electrode through a conductive material and exposed from the lower surface of the sealing resin;
It comprises a plurality of conductive path groups that penetrate the sealing resin in the thickness direction and are exposed from the lower surface of the sealing resin,
The conductive path group includes one main conductive path, n−k intermediate conductive path groups, and n−k + 1 control conductive path groups.
The xth (1 ≦ x ≦ n−k) intermediate conductive path in the intermediate conductive path group is defined as the k + x intermediate conductive path,
When the y-th (1 ≦ y ≦ n−k + 1) control conductive path in the control conductive path group is the k + y−1 control conductive path,
The (k + 1) -th intermediate conductive path includes an intermediate conductive plate that is connected to the upper surface via a conductive material and exposed from the upper surface of the sealing resin,
The k + x intermediate conductive path (x ≧ 2) includes an x + k intermediate connection conductive plate that is connected to the upper surface via a conductive material and exposed from the upper surface of the sealing resin,
The k-th control conductive path includes a relay conductive plate that is connected to the upper surface via a conductive material and exposed from the upper surface of the sealing resin,
The k + y-1 (y ≧ 2) control conductive path includes a conductive plate for the (k + y-1) control conductive path that is connected to the upper surface of the control conductive path via a conductive material and exposed from the upper surface of the sealing resin. And
The main conductive path includes a conductive plate for a main conductive path that is connected to an upper surface of the main conductive path via a conductive material and exposed from the upper surface of the sealing resin.
The packaged semiconductor element stacked in the k-th stage excluding the first stage further includes a relay terminal exposed from the lower surface of the sealing resin,
The packaged semiconductor element stacked in the nth stage is
An nth control electrode exposed on a part of the upper surface of the semiconductor element;
An n-th upper main electrode exposed in the remaining portion of the upper surface of the semiconductor element;
An nth lower main electrode exposed on the lower surface of the semiconductor element;
Sealing resin covering a portion other than the nth lower main electrode of the semiconductor element;
A control terminal electrically connected to the nth control electrode and exposed from the lower surface of the sealing resin;
A main terminal electrically connected to the n-th upper main electrode and exposed from the lower surface of the sealing resin;
An nth lower main conductive plate connected to the nth lower main electrode through a conductive material and exposed from the lower surface of the sealing resin;
It has a relay terminal exposed from the lower surface of the sealing resin,
Between the packaged semiconductor elements stacked in the kth stage excluding k = n−1 and the packaged semiconductor elements stacked in the k + 1th stage,
The main conductive path of the packaged semiconductor element stacked in the (k + 1) th stage is connected to the conductive plate for the main conductive path of the packaged semiconductor element stacked in the kth stage via a conductive material. The k + x intermediate conductive path of the packaged semiconductor element stacked in the eye is connected to the k + x intermediate connection conductive plate of the packaged semiconductor element stacked in the k-th stage through the conductive material. And
The k + y−1 control conduction path of the packaged semiconductor element stacked in the kth stage through the conductive material is the k + y−1 control conduction path of the packaged semiconductor element stacked in the (k + 1) th stage. Connected to the conductive plate for the road,
The (k + 1) th lower main conductive plate of the (k + 1) th packaged semiconductor element is connected to the intermediate conductive plate and the kth upper main conductive plate of the kth packaged semiconductor element via a conductive material. And
a relay terminal of the k + 1 stage packaged semiconductor element is connected to the kth control conductive plate and the relay conductive board of the kth stage packaged semiconductor element via a conductive material;
Between the n-1th stage packaged semiconductor element and the nth stage packaged semiconductor element,
The main terminal is connected to the main conductive path via a conductive material;
The nth lower main conductive plate of the nth packaged semiconductor element is connected to the intermediate conductive plate of the n−1th packaged semiconductor element and the n−1th upper main electrode through a conductive material. And
The nth relay terminal of the nth packaged semiconductor element is connected to the n-1th control conductive plate and the relay conductive plate of the n−1th packaged semiconductor element through a conductive material. ,
The control terminal is connected to the conductive plate for the nth control conductive path via a conductive material;
A semiconductor device, wherein a lower surface of each of the conductive path groups of the first-stage packaged semiconductor element and the first lower main conductive plate are connected to the circuit board via a conductive material. A method of manufacturing the semiconductor device according to claim 1,
A method of manufacturing the first packaged semiconductor device comprises:
A first mask forming step of forming a metal plating or resist film having openings patterned on the upper surface of the first conductive plate;
A first etching step of forming a plurality of convex portions by etching from the upper surface side to a depth not penetrating the first conductive plate using the metal plating or resist film as a mask after the first mask forming step;
A connection fixing step of connecting and fixing the semiconductor element in a range etched in the first etching step;
An electrode forming step of forming a second conductive plate connected to each of the upper surface of the plurality of convex portion groups, the first upper main electrode of the semiconductor element, and the control electrode via a conductive material;
A sealing step of covering the portion other than the electrodes of the semiconductor element and the first conductive plate and sealing the resin so that the second conductive plate is exposed;
Etching the first conductive plate from the lower surface side, and removing a part of the first conductive plate so that the first lower main electrode and each of the plurality of convex portions are insulated from each other. A method of manufacturing a semiconductor device. The second conductive plate used in the electrode forming step is one continuous conductive plate;
And in the sealing step, the space between the first conductive plate and the second conductive plate is filled with a sealing resin,
A second mask forming step of forming a metal plating or resist film having openings patterned on the surface of the second conductive plate after the sealing step;
After the second mask formation step, the second conductive plate is etched using the metal plating or resist film as a mask to insulate each of the first upper main electrode, the first control electrode, and the plurality of convex portions. The method of manufacturing a semiconductor device according to claim 3, further comprising a second etching step of removing a part of the second conductive plate. The second conductive plate used in the electrode forming step is one continuous conductive plate;
Forming a resist film on the surface of the first conductive plate after the connection fixing step;
Thereafter, the second mask forming step, the second etching step, and the sealing step are sequentially performed.
In the sealing step, resin sealing is performed so as to cover the second conductive plate,
4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of polishing the sealing resin from the upper surface side until the second conductive plate is exposed thereafter.

Images