JP3632024B2 - Chip package and manufacturing method thereof - Google Patents

Chip package and manufacturing method thereof Download PDF

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JP3632024B2
JP3632024B2 JP2003003804A JP2003003804A JP3632024B2 JP 3632024 B2 JP3632024 B2 JP 3632024B2 JP 2003003804 A JP2003003804 A JP 2003003804A JP 2003003804 A JP2003003804 A JP 2003003804A JP 3632024 B2 JP3632024 B2 JP 3632024B2
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chip package
layer
chip
conductive layer
conductive
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JP2003273281A (en
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▲峻▼ ▲皓▼ 尹
龍 七 崔
錫 洙 ▲斐▼
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三星電機株式会社
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Description

【０００１】
【発明の属する技術分野】
本発明はチップパッケージに関するもので、とりわけトランジスタ素子のように一面に二つの端子と、該一面に対向する他面に一つの端子が設けられたチップ型電子素子を含んだチップパッケージ及びその製造方法に関するものである。
【０００２】
【従来の技術】
一般に、トランジスタなどの半導体素子はパッケージを成して印刷回路基板上に実装される。こうしたパッケージは、半導体素子の端子を印刷回路基板の信号パターンに容易に連結させ得る構造から成っており、外部の影響から素子を保護して信頼性を確保する役目を果たす。
【０００３】
こうした半導体素子パッケージは製品の小型化の流れに伴い漸次小型化されつつある。かかる小型化の代表的なパッケージ方式として、チップスケールパッケージ（ｃｈｉｐ ｓｃａｌｅ ｐａｃｋａｇｅ）が挙げられる。図５は従来のチップスケールパッケージの構造を示す概略断面図である。図５に示すパッケージ構造はセラミック基板を用いた方式として、三つの端子を設けたトランジスタパッケージの一形態である。図５によると、セラミック基板２０１には三つのバイアホール２０２ａ、２０２ｂ、２０２ｃが形成される。前記バイアホール２０２ａ、２０２ｂ、２０２ｃの内部は基板２０１の上下面が相互に電気的に連結されるよう所定の導電性物質が充填され、前記三つのバイアホール２０２ａ、２０２ｂ、２０２ｃの上部には第１ないし第３上部導電性ランド２０３ａ、２０３ｂ、２０３ｃが形成され、その下部には各々第１ないし第３下部導電性ランド２０４ａ、２０４ｂ、２０４ｃが形成されている。さらに、前記第３上部導電性ランド２０４ｃはトランジスタ２０５の実装面に形成された一側端子と連結され、前記第１及び第２上部導電性ランド２０４ａ、２０４ｂはチップの上部端子と一端が連結されたワイヤ２０７に連結される。このようにトランジスタ２０５が実装されたセラミック基板２０１は、その上面に外部の影響からトランジスタを保護すべく通常の樹脂でモールディング部２０９を形成したパッケージ２１０に完成される。
【０００４】
こうして完成されたトランジスタパッケージ２１０は図６のように、リフローはんだ付け方式により印刷回路基板２２０に実装される。前記トランジスタパッケージ２１０は、その下面に形成された第１ないし第３下部導電性ランド２０４ａ、２０４ｂ、２０４ｃを信号パターンの所望の位置に配置してから各々はんだ付け２１５を形成する方法で前記印刷回路基板２２０に実装される。
【０００５】
図５及び図６において説明したとおり、一般にトランジスタは対向する面に端子が各々形成されるので、ワイヤによる連結を要する。しかし、かかるワイヤはチップの上部空間をかなり占める。したがって、全体のパッケージ高が高くなってしまう問題がある。さらに、セラミック基板にチップ端子連結のため少なくとも三つのバイアホールを形成しなくてはならないので、該バイアホールの直径に応じた基板面積を要するばかりでなく、該バイアホールの上下面に形成される導電性ランドが互いに短絡しないよう最小限の間隔を保たねばならない。こうした条件を満たす程の充分な面積を有するよう基板を製造しなくてはならない。結局、全体としてのパッケージ寸法を小型化するのに大きな制約となる。
【０００６】
さらに、パッケージに用いる基板は比較的高価のセラミック基板なので製造コストが高く、従来のパッケージ製造工程はダイオードを基板に付着するダイボンディング（ｄｉｅ ｂｏｎｄｉｎｇ）工程ばかりでなく、ワイヤボンディング及びモールディング工程を伴うので製造工程が複雑であるという問題を抱えていた。したがって、当技術分野においては、かかる制約を解消させてより小型化が可能でありながらも製造工程が容易である新たなパッケージ構造が要求されてきた。
【０００７】
【発明が解決しようとする課題】
本発明は、前記諸問題を解決するために案出されたもので、その目的は、二つの端子が形成された上面と一つの端子が形成された下面とを有するチップ素子（ｃｈｉｐ ｔｙｐｅ ｄｅｖｉｃｅ）を印刷回路基板に実装するためにパッケージングする際に、二つの端子領域を除くチップ素子の上面に絶縁層と、該絶縁層上に前記各端子に連結された導電層とを形成し、チップ素子の下面には導電層を形成してから前記各導電層側面中同じ方向の側面に印刷回路基板の連結パッドに連結するための電極面を形成することによりパッケージを画期的に小型化できるばかりでなく、その製造工程が簡素でありながらもチップの信頼性を保障できる新たな構造のパッケージを提供することにある。
【０００８】
本発明の他の目的は、新たなチップパッケージの構造に応じた新たな実装方式を有するチップパッケージアセンブリーを提供することにある。本発明の更に異なる目的は、新たな構造から成るチップパッケージの製造方法を提供することにもある。
【０００９】
【課題を解決するための手段】
前記課題を成し遂げるべく本発明は、二つの端子が形成された第１面及び前記第１面に対向しながら一つの端子が形成された第２面を有するチップ素子と、前記二つの端子領域を除く前記第１面に形成された絶縁層と、前記絶縁層上に形成されて前記第１面に形成された前記端子に各々連結され、所定の間隔で電気的に分離された第１及び第２導電層と、前記チップ素子の第２面に形成されて該第２面の端子と連結された第３導電層と、前記第１、第２、及び第３導電層の側面中前記チップ素子の同じ側面に接する一側面に各々形成された電極面とを含むチップパッケージを提供する。
【００１０】
また、本発明の他の実施の形態においては、二つの端子が形成された第１面及び前記第１面に対向しながら一つの端子が形成された第２面を有するチップ素子と、前記二つの端子領域を除く前記第１面に形成された絶縁層と、前記絶縁層上に形成されて前記第１面上に形成された各端子に連結され、所定の間隔で分離された第１及び第２導電層と、前記チップ素子の第２面に端子と連結されて形成された第３導電層と、前記第１、第２及び第３導電層の側面中前記チップ素子の同じ側面に接する一側面に各々形成された電極面とを含むチップパッケージ；及び、少なくとも三つの連結パッドと前記連結パッドに各々連結された所定の回路パターンが形成された印刷回路基板とを含み、前記電極面が各々前記連結パッドに付着されて前記チップパッケージが前記印刷回路基板に実装されたチップパッケージアセンブリーを提供する。
【００１１】
さらに、本発明は、本発明によるチップパッケージを製造するための方法を提供する。前記チップパッケージ製造方法は、上面に二つの端子と下面に一つの端子を有する複数個のチップ素子が形成されたウェーハを用意する段階と、前記二つの端子が形成された領域を除く前記ウェーハ上面に絶縁層を形成する段階と、前記絶縁層上に前記ウェーハ上面に形成された二つの端子と連結されるよう上部導電層を形成する段階と、前記ウェーハ下面に該下面の端子と連結されるよう下部導電層を形成する段階と、前記絶縁層上に形成された導電層を前記二つの端子に各々連結された二つの導電層に分離する段階と、チップパッケージの一側面が形成されるよう前記ウェーハを１次ダイシングする段階と、前記１次ダイシングにより形成された前記導電層の一側面に各々電極面を形成する段階、及びチップパッケージ単位で完全に分離されるよう前記結果物を２次ダイシングする段階とを含む。
【００１２】
【発明の実施の形態】
以下、図面に基づき本発明を好ましき実施の形態からより詳しく説明する。図１（Ａ）及び１（Ｂ）は本発明の好ましき実施の形態によるチップパッケージを示す斜視図及び断面図である。図１（Ａ）によると、前記チップパッケージ３０はチップ素子３５と、その上面に形成された絶縁層３３と、前記絶縁層３３の上面及びチップ素子３５の下面に各々形成された導電層３１ａ、３１ｂ、３１ｃ及び前記導電層３１ａ、３１ｂ、３１ｃの同じ側面上に各々形成された電極面３７ａ、３７ｂ、３７ｃを含む。図１（Ａ）には図示していないが、前記チップ素子３５は上面に二つの端子を形成しており、その下面に一つの端子を設けた素子であり、その代表例としてトランジスタであり得る。
【００１３】
図１（Ｂ）は前記図１（Ａ）のＡ−Ａ線による断面図であり、後述する図３（Ｂ）に示す二つの端子Ａ，Ｂに導電層が形成された箇所の断面図である。前記図１（Ｂ）によると、上面の端子Ａ、Ｂ領域を除く前記チップ素子３５の上面には絶縁層３３が形成され、前記絶縁層３３上には第１及び第２導電層３１ａ、３１ｂが形成される。前記第１及び第２導電層３１ａ、３１ｂはチップ素子３５の上面に設けられた端子Ａ、Ｂに各々連結され、所定の間隔で分離形成される。さらに、前記チップ素子３５の下面には第３導電層３１ｃが形成され、該下面に設けられた端子に電気的に連結される。
【００１４】
前記導電層３１ａ、３１ｂ、３１ｃは、好ましくは銅から成る金属層を用いることができるが、本発明がこれに必ずしも限定されるものではない。さらに、前記導電層３１ａ、３１ｂ、３１ｃの厚さは印刷回路基板の種類に応じて異なるが、その印刷回路基板の連結パッド同士の間隔を考慮して設定する。即ち、前記チップパッケージを印刷回路基板上に実装する際、導電層の一面に形成される電極面が各々連結パッド上に位置しなければならないので、前記導電層を充分な厚さに形成する必要がある。
【００１５】
前記導電層３１ａ、３１ｂ、３１ｃを所定の厚さに形成する工程としては、前記導電層はメッキ工程によりメッキ層に必要な厚さに製造できるが、これはかなりの工程時間及び費用がかかるので、好ましくは電解メッキ法を利用して金属層を形成した後に該金属層上に、少なくとも一つの銅箔を積層する方式を用いることができる。
【００１６】
さらに、前記各導電層３１ａ、３１ｂ、３１ｃは、同じ方向に位置する一側面に電極面３７ａ、３７ｂ、３７ｃが形成される。前記電極面３７ａ、３７ｂ、３７ｃは印刷回路基板上の連結パッドに電気的且つ機械的に連結すべく設けられたもので、はんだ付け工程に適しながら電気的伝導性に優れた金（Ａｕ）から形成することが好ましい。
【００１７】
前記図１（Ｂ）のようなチップパッケージ３０の構造においては、前記チップ素子３５の上面に設けられた二つの端子を含む領域Ａ、Ｂを除いて絶縁層３３が形成され、前記絶縁層３３上には前記二つの端子Ａ、Ｂに各々連結された導電層３１ａ、３１ｂが形成される。さらに、前記チップ素子３５の上面に形成された二つの導電層３１ａ、３１ｂの一側面と該側面と同じ方向の側面である導電層３１ｃの側面には、各々電極面３７ａ、３７ｂ、３７ｃが形成される。こうして電極面３７ａ、３７ｂ、３７ｃが形成された側面は印刷回路基板に接する実装面を成し、前記チップパッケージ３０は実装面が下向きになるよう９０°回転させた状態で印刷回路基板上に搭載させる新たな実装方式による。
【００１８】
一方、導電層３１ａ、３１ｂ、３１ｃは露出された外部面において生じる自然酸化により酸化膜を形成し得る。こうした酸化膜は導電層の信頼性を保障する保護膜として作用することができる。しかし、パッケージの使用環境によって素子の信頼性に至大なる影響を及ぼす深刻な酸化現象を引き起こすかも知れないので、これを防止すべく図示のように、前記導電層３１ａ、３１ｂ、３１ｃには電極面３７ａ、３７ｂ、３７ｃが形成された面を除いて保護層３９を形成してもよい。こうした保護層３９は絶縁性樹脂を塗布して形成した絶縁性被膜を用いることが好ましく、必要に応じて外部に露出したチップ素子３５の側面にも形成することができる。
【００１９】
図２は本発明によるチップパッケージ４０と印刷回路基板５１とを含んだチップパッケージアセンブリー５０の一形態を示す。図２のように、前記チップパッケージアセンブリー５０はチップパッケージ４０と該チップパッケージが実装された印刷回路基板５１とで成る。前記チップパッケージ４０は、図１（Ａ）及び１（Ｂ）に示す構造のように、チップ素子４５はその上面に絶縁層４３と二つの端子（図示せず）に各々連結された導電層４１ａ、４１ｂを形成しており、その下面に形成された端子（図示せず）は他の導電層４１ｃに連結される。さらに、前記導電層４１ａ、４１ｂ、４１ｃの一面に電極面４７ａ、４７ｂ、４７ｃが各々形成され、チップパッケージ４０の実装面を成す。前記各電極面４７ａ、４７ｂ、４７ｃは導電層４１ａ、４１ｂ、４１ｃを介してチップ素子４５の各端子に連結される。前記チップパッケージの電極面４７ａ、４７ｂ、４７ｃを印刷回路基板５１の連結パッド５７ａ、５７ｂ、５７ｃ上に各々配置し、はんだ付けを施すことにより、図２に示すチップパッケージアセンブリー５０が完成する。本発明によるチップパッケージアセンブリーにおいては、印刷回路基板に形成された所定の回路は連結パッド５７ａ、５７ｂ、５７ｃに連結されたパッケージ４０の電極４７ａ、４７ｂ、４７ｃを介してチップ素子４５の各端子に連結されることができる。その為に、先に説明したように、前記導電層４１ａ、４１ｂは少なくとも連結パッド５７ａ、５７ｂ同士の間隔を考慮してその厚さを設定する必要がある。
【００２０】
さらに、本発明は前記チップパッケージの製造方法を提供する。図３（Ａ）ないし４（Ｃ）は本発明の好ましき実施の形態によるチップパッケージの製造方法を説明するための工程図である。
【００２１】
先ず、図３（Ａ）のように、上下面に各々端子を設けた複数個のチップ素子が形成されたウェーハ１０５を用意する。ここで、前記ウェーハ１０５の上面に線で区分した領域は各チップ素子の単位を示す。前記ウェーハ１０５は行と列に沿って複数個のチップ素子が配列された直方形の構造に示されるが、当業者であれば図３（Ａ）に示すウェーハが所定の口径から成る通常のウェーハであることを了解できるであろう。前記チップ素子はその上面に二つの端子１０１ａ、１０１ｂを設け、下面には一つの端子を設ける。さらに、本実施の形態において、前記ウェーハに設けられたチップ素子は、通常のトランジスタのように、上面には酸化膜から成る窓層１０６を設け、その開口部を通して端子１０１ａ、１０１ｂを形成する構造となる。
【００２２】
次いで、図３（Ｂ）のように、前記ウェーハ上面に絶縁層１１３を形成する。前記絶縁層１１３は二つの端子領域を除く上面領域に形成する。続いて、図３（Ｃ）のように、前記絶縁層１１３の上面とウェーハ１０５の下面に各々上部及び下部導電層１２１ａ、１２１ｂを形成する。この際、上部導電層１２１ａは前記両端子に連結されるよう形成しなければならない。したがって、前記絶縁層の形成されない部分が充填されるよう金属層を形成するために、メッキ法により上部導電層を形成することが好ましいが、先に説明したとおり、前記導電層は連結パッドの間隔を考慮して電極面の形成に充分な側面を有するよう所定の厚さで形成しなければならないので、先ず端子領域に該当する絶縁層が形成されていない部分がしっかり充填されるようメッキ層を形成してから少なくとも一つの銅箔を積層して設けることが最も好ましい。続いて、図３（Ｃ）のＹ−Ｙ’線に沿ってチップ素子の列を二つのライン単位でダイシングする。
【００２３】
前記ダイシング段階後、図４（Ａ）のように二つのライン単位で分離された結果物が得られ、かかる構造において各チップ素子は一側面のみ形成される。前記ダイシングにより得た一側面を成す上部及び下部導電層１２１ａ、１２１ｂの側面上に各々電極面１３７’、１３７”を形成する。かかる電極面１３７’、１３７”は電解メッキ方法によって、シリコン材質のチップ素子側面には電極を形成せずに、金属材質のメッキ層１２１ａ、１２１ｂの側面にのみ選択的に形成され得る。
【００２４】
次に、図４（Ａ）のＸ−Ｘ’線に該当する上部導電層１２１ａを取り除き、図４（Ｂ）のように各チップ素子の二つの端子に各々連結された上部導電層１２１ａと上部導電層に形成された電極面１３７’とを二つの領域に分離する。この際、絶縁層１１３は二つの端子を電気的に分離すると共に、上部導電層１２１ａを分離する工程においてチップ素子の損傷を防ぐ役目を果たす。
【００２５】
続いて、図４（Ｂ）に示す結果物がチップ素子単位で完全に分離されるよう最終ダイシング工程を行う。こうして、最終チップパッケージ１４０が完成する。さらに、図４（Ｃ）に示すように、前記チップパッケージ１４０の露出された導電層外部面に保護層１３９をさらに形成してもよい。かかる保護層１３９は、前記上下部導電層１２１ａ、１２１ｂに絶縁性樹脂を塗布して形成した絶縁性被膜から成り、前記導電層１２１ａ、１２１ｂの酸化を防いでパッケージの信頼性をより安定的に保障することができる。かかる保護層１３９はチップパッケージの使用環境などによっては省くこともできる。
【００２６】
さらに、図３（Ａ）ないし図４（Ｃ）に示す本発明によるチップパッケージの製造工程は様々な変形から具現されることができる。とりわけ、保護層及び電極面形成工程はチップパッケージにダイシングする工程に応じてその構成を異ならせられる。例えば、図３（Ａ）ないし図４（Ｃ）に示す実施の形態の場合、保護層を形成する工程を、前記２次ダイシング後に前記電極面の形成されていない前記導電層の外部面に保護層を形成する方式により１回塗布工程するものとしているが、これと異なり、前記上部及び下部導電層を形成後に前記上部及び下部導電層上に保護層を形成し、前記２次ダイシングしてから、前記電極面の形成されていない導電層側面に保護層を形成することもできる。前者によると、ウェーハをダイシングする際、導電層が形成されたウェーハ背面がテープまたは真空装置により固定されて後続工程においてその導電層に保護層を形成するのが困難であるが、後者の方法ではダイシング工程前にウェーハ下面の導電層に保護層を予め形成するのでかかる問題を解決できるという利点がある。
【００２７】
一方、図４（Ｂ）のように前記絶縁層上に形成された導電層を二つの導電層に分離する段階は、図４（Ｃ）の２次ダイシングを行う段階において同時に具現することができる。 即ち、２次ダイシング段階を行う際、導電層の分離において切削深さを導電層の厚さに相当する深さに調節することで導電層を分離する工程とチップパッケージ単位に分離する工程とを同時に行えるのである。
【００２８】
このように、本発明によるチップパッケージの製造方法における特徴は、前記得られたウェーハを一つのチップ素子を含むパッケージにダイシングしながら、前記各チップパッケージの一側面を成す前記導電層の側面には電極面を形成し、前記二つの導電層の他の側面には保護層を形成する方法であれば多様な形態に改造及び変形できる。したがって、チップパッケージの側面を形成するための各ダイシング工程は保護層または電極面を形成する工程の順序と方式を多様に変更してもよいが、そうした改良または変更された形態も本発明の範囲に含まれるものである。
【００２９】
【発明の効果】
上述のとおり、本発明によるチップパッケージによると、全体としてのパッケージ寸法を画期的に小型化できるばかりでなく、バイアホール形成工程やワイヤ工程等を省け、その製造工程が簡素でありながらもチップの信頼性を保障できる新たな構造から成るチップパッケージ及びこれを含んだチップパッケージアセンブリーを製造することができる。
【図面の簡単な説明】
【図１】（Ａ）及び（Ｂ）は本発明の一実施の形態によるチップパッケージの斜視図及び断面図である。
【図２】本発明の一実施の形態によるチップパッケージアセンブリーを示す斜視図である。
【図３】（Ａ）ないし（Ｃ）は本発明の好ましき実施の形態によるチップパッケージの製造方法を示す工程別断面図である。
【図４】（Ａ）ないし（Ｃ）は本発明の好ましき実施の形態によるチップパッケージの製造方法を示す工程別断面図である。
【図５】従来のチップパッケージを示す断面図である。
【図６】従来のチップパッケージアセンブリーを示す断面図である。
【符号の説明】
３０ チップパッケージ
３１ａ、３１ｂ、３１ｃ 導電層
３３ 絶縁層
３７ａ、３７ｂ、３７ｃ 電極面
３５ チップ素子
５１ 印刷回路基板
５７ａ、５７ｂ、５７ｃ 連結パッド[0001]
BACKGROUND OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip package, and in particular, a chip package including a chip-type electronic device in which two terminals are provided on one surface and one terminal is provided on the other surface opposite to the one surface, such as a transistor device, and a manufacturing method thereof It is about.
[0002]
[Prior art]
Generally, semiconductor elements such as transistors are mounted on a printed circuit board in a package. Such a package has a structure in which the terminals of the semiconductor element can be easily connected to the signal pattern of the printed circuit board, and serves to protect the element from external influences and ensure reliability.
[0003]
Such semiconductor element packages are gradually being reduced in size with the trend toward miniaturization of products. As a typical package system for such miniaturization, there is a chip scale package. FIG. 5 is a schematic cross-sectional view showing the structure of a conventional chip scale package. The package structure shown in FIG. 5 is one form of a transistor package provided with three terminals as a system using a ceramic substrate. According to FIG. 5, three via holes 202 a, 202 b, 202 c are formed in the ceramic substrate 201. The via holes 202a, 202b, and 202c are filled with a predetermined conductive material so that the upper and lower surfaces of the substrate 201 are electrically connected to each other. The upper portions of the three via holes 202a, 202b, and 202c First to third upper conductive lands 203a, 203b, and 203c are formed, and first to third lower conductive lands 204a, 204b, and 204c are formed below the first to third upper conductive lands 203a, 203b, and 203c, respectively. Further, the third upper conductive land 204c is connected to one terminal formed on the mounting surface of the transistor 205, and the first and second upper conductive lands 204a and 204b are connected to the upper terminal of the chip and one end. The wire 207 is connected. Thus, the ceramic substrate 201 on which the transistor 205 is mounted is completed into a package 210 in which a molding part 209 is formed on the upper surface of the ceramic substrate 201 with an ordinary resin so as to protect the transistor from external influences.
[0004]
The completed transistor package 210 is mounted on the printed circuit board 220 by reflow soldering as shown in FIG. In the transistor package 210, the first to third lower conductive lands 204a, 204b, and 204c formed on the lower surface of the transistor package 210 are disposed at desired positions in the signal pattern, and then the soldering 215 is formed. Mounted on the substrate 220.
[0005]
As described with reference to FIGS. 5 and 6, since a transistor is generally formed with terminals on opposite surfaces, connection with a wire is required. However, such wires occupy a significant amount of the chip headspace. Therefore, there is a problem that the overall package height becomes high. Furthermore, since at least three via holes must be formed on the ceramic substrate for chip terminal connection, not only the substrate area corresponding to the diameter of the via hole is required, but also the upper and lower surfaces of the via hole are formed. Minimal spacing must be maintained so that the conductive lands do not short-circuit each other. The substrate must be manufactured to have a sufficient area to satisfy these conditions. Eventually, this is a major limitation in reducing the overall package size.
[0006]
Further, since the substrate used for the package is a relatively expensive ceramic substrate, the manufacturing cost is high, and the conventional package manufacturing process involves not only a die bonding process for attaching the diode to the substrate but also a wire bonding and molding process. The manufacturing process was complicated. Accordingly, there has been a demand in the art for a new package structure that can eliminate the restriction and can be further miniaturized, but can be easily manufactured.
[0007]
[Problems to be solved by the invention]
The present invention has been devised to solve the above-described problems, and its purpose is to provide a chip device having an upper surface on which two terminals are formed and a lower surface on which one terminal is formed. When packaging for mounting on a printed circuit board, an insulating layer is formed on the upper surface of the chip element excluding two terminal regions, and a conductive layer connected to each of the terminals is formed on the insulating layer. By forming a conductive layer on the lower surface of the element and then forming an electrode surface for connecting to the connection pad of the printed circuit board on the side surface in the same direction among the side surfaces of each conductive layer, the package can be reduced in size. In addition to providing a package with a new structure that can guarantee the reliability of the chip while the manufacturing process is simple.
[0008]
Another object of the present invention is to provide a chip package assembly having a new mounting method according to the structure of a new chip package. Another object of the present invention is to provide a method for manufacturing a chip package having a new structure.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a chip element having a first surface on which two terminals are formed and a second surface on which one terminal is formed while facing the first surface, and the two terminal regions. The first and second insulating layers formed on the first surface excluding the first and second terminals are connected to the terminals formed on the insulating layer and formed on the first surface, and are electrically separated at a predetermined interval. Two conductive layers, a third conductive layer formed on the second surface of the chip element and connected to a terminal of the second surface, and the chip element in the side surface of the first, second, and third conductive layers And an electrode surface formed on one side surface in contact with the same side surface.
[0010]
In another embodiment of the present invention, a chip element having a first surface on which two terminals are formed and a second surface on which one terminal is formed while facing the first surface; An insulating layer formed on the first surface excluding one terminal region; and first and second terminals formed on the insulating layer and connected to the terminals formed on the first surface and separated at a predetermined interval. A second conductive layer, a third conductive layer formed on the second surface of the chip element and connected to a terminal, and a side surface of the first, second, and third conductive layers are in contact with the same side surface of the chip element. A chip package including electrode surfaces formed on one side surface; and at least three connection pads and a printed circuit board on which a predetermined circuit pattern connected to the connection pads is formed. Each of the chips attached to the connection pad Kkeji provides a chip package assembly that is mounted on the printed circuit board.
[0011]
Furthermore, the present invention provides a method for manufacturing a chip package according to the present invention. The chip package manufacturing method includes a step of preparing a wafer on which a plurality of chip elements having two terminals on the upper surface and one terminal on the lower surface are formed, and the upper surface of the wafer excluding the region where the two terminals are formed. Forming an insulating layer on the insulating layer; forming an upper conductive layer on the insulating layer to be connected to two terminals formed on the upper surface of the wafer; and connecting the lower surface with a terminal on the lower surface of the wafer. Forming a lower conductive layer, separating the conductive layer formed on the insulating layer into two conductive layers connected to the two terminals, and forming a side surface of the chip package. The wafer is subjected to primary dicing, the electrode surface is formed on one side surface of the conductive layer formed by the primary dicing, and the wafer is completely separated in units of chip packages. It is to include a step of secondary dicing the resulting structure.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in more detail from preferred embodiments with reference to the drawings. 1A and 1B are a perspective view and a sectional view showing a chip package according to a preferred embodiment of the present invention. Referring to FIG. 1A, the chip package 30 includes a chip element 35, an insulating layer 33 formed on the upper surface thereof, a conductive layer 31a formed on the upper surface of the insulating layer 33 and the lower surface of the chip element 35, 31b, 31c and electrode surfaces 37a, 37b, 37c formed on the same side surfaces of the conductive layers 31a, 31b, 31c, respectively. Although not shown in FIG. 1A, the chip element 35 is an element in which two terminals are formed on the upper surface and one terminal is provided on the lower surface, and a representative example thereof may be a transistor. .
[0013]
1B is a cross-sectional view taken along line AA in FIG. 1A, and is a cross-sectional view of a portion where a conductive layer is formed on two terminals A and B shown in FIG. 3B described later. is there. Referring to FIG. 1B, an insulating layer 33 is formed on the upper surface of the chip element 35 excluding the terminal A and B regions on the upper surface, and the first and second conductive layers 31a and 31b are formed on the insulating layer 33. Is formed. The first and second conductive layers 31a and 31b are respectively connected to terminals A and B provided on the upper surface of the chip element 35, and are separated and formed at a predetermined interval. Further, a third conductive layer 31c is formed on the lower surface of the chip element 35 and is electrically connected to a terminal provided on the lower surface.
[0014]
As the conductive layers 31a, 31b, and 31c, metal layers preferably made of copper can be used, but the present invention is not necessarily limited thereto. Furthermore, although the thickness of the conductive layers 31a, 31b, and 31c varies depending on the type of the printed circuit board, it is set in consideration of the interval between the connection pads of the printed circuit board. That is, when the chip package is mounted on the printed circuit board, the electrode surface formed on one surface of the conductive layer must be positioned on the connection pad, so that the conductive layer needs to be formed with a sufficient thickness. There is.
[0015]
As a process of forming the conductive layers 31a, 31b, and 31c to a predetermined thickness, the conductive layer can be manufactured to a thickness required for the plating layer by a plating process, but this requires considerable process time and cost. Preferably, a method in which at least one copper foil is laminated on the metal layer after the metal layer is formed by using an electrolytic plating method can be used.
[0016]
Furthermore, each of the conductive layers 31a, 31b, and 31c has electrode surfaces 37a, 37b, and 37c formed on one side surface that is located in the same direction. The electrode surfaces 37a, 37b, and 37c are provided to be electrically and mechanically connected to connection pads on a printed circuit board. The electrode surfaces 37a, 37b, and 37c are made of gold (Au) that is suitable for a soldering process but has excellent electrical conductivity. It is preferable to form.
[0017]
In the structure of the chip package 30 as shown in FIG. 1B, an insulating layer 33 is formed except for the regions A and B including two terminals provided on the upper surface of the chip element 35. Conductive layers 31a and 31b connected to the two terminals A and B are formed on the top. Further, electrode surfaces 37a, 37b, and 37c are formed on one side surface of the two conductive layers 31a and 31b formed on the upper surface of the chip element 35 and on the side surface of the conductive layer 31c that is the side surface in the same direction as the side surface. Is done. The side surfaces on which the electrode surfaces 37a, 37b, and 37c are formed in this way form a mounting surface that contacts the printed circuit board, and the chip package 30 is mounted on the printed circuit board in a state rotated 90 ° so that the mounting surface faces downward. Depending on the new implementation method.
[0018]
On the other hand, the conductive layers 31a, 31b, and 31c can form oxide films by natural oxidation that occurs on the exposed external surfaces. Such an oxide film can act as a protective film that ensures the reliability of the conductive layer. However, since a serious oxidation phenomenon having a great influence on the reliability of the device may be caused depending on the use environment of the package, the conductive layers 31a, 31b, and 31c include electrodes on the conductive layers 31a, 31b, and 31c as shown in FIG. The protective layer 39 may be formed except for the surface on which the surfaces 37a, 37b, and 37c are formed. Such a protective layer 39 is preferably an insulating film formed by applying an insulating resin, and can also be formed on the side surface of the chip element 35 exposed to the outside as required.
[0019]
FIG. 2 shows an embodiment of a chip package assembly 50 including a chip package 40 and a printed circuit board 51 according to the present invention. As shown in FIG. 2, the chip package assembly 50 includes a chip package 40 and a printed circuit board 51 on which the chip package is mounted. The chip package 40 has a structure shown in FIGS. 1A and 1B, and the chip element 45 has a conductive layer 41a connected to an insulating layer 43 and two terminals (not shown) on its upper surface. 41b, and a terminal (not shown) formed on the lower surface thereof is connected to another conductive layer 41c. Further, electrode surfaces 47a, 47b, and 47c are formed on one surface of the conductive layers 41a, 41b, and 41c, respectively, and form a mounting surface of the chip package 40. The electrode surfaces 47a, 47b, 47c are connected to the terminals of the chip element 45 through conductive layers 41a, 41b, 41c. The chip package assembly 50 shown in FIG. 2 is completed by arranging the electrode surfaces 47a, 47b, 47c of the chip package on the connection pads 57a, 57b, 57c of the printed circuit board 51 and soldering. In the chip package assembly according to the present invention, the predetermined circuit formed on the printed circuit board is connected to each terminal of the chip element 45 via the electrodes 47a, 47b, 47c of the package 40 connected to the connection pads 57a, 57b, 57c. Can be linked to. Therefore, as described above, it is necessary to set the thickness of the conductive layers 41a and 41b in consideration of at least the distance between the connection pads 57a and 57b.
[0020]
Furthermore, the present invention provides a method for manufacturing the chip package. 3A to 4C are process diagrams for explaining a method of manufacturing a chip package according to a preferred embodiment of the present invention.
[0021]
First, as shown in FIG. 3A, a wafer 105 having a plurality of chip elements each provided with terminals on the upper and lower surfaces is prepared. Here, a region divided by lines on the upper surface of the wafer 105 represents a unit of each chip element. The wafer 105 is shown as a rectangular structure in which a plurality of chip elements are arranged along rows and columns. However, those skilled in the art will understand that the wafer shown in FIG. 3A is a normal wafer having a predetermined diameter. You can understand that. The chip element is provided with two terminals 101a and 101b on the upper surface and one terminal on the lower surface. Further, in the present embodiment, the chip element provided on the wafer has a structure in which a window layer 106 made of an oxide film is provided on the upper surface and terminals 101a and 101b are formed through the openings as in a normal transistor. It becomes.
[0022]
Next, as shown in FIG. 3B, an insulating layer 113 is formed on the upper surface of the wafer. The insulating layer 113 is formed on the upper surface region excluding the two terminal regions. Subsequently, as shown in FIG. 3C, upper and lower conductive layers 121a and 121b are formed on the upper surface of the insulating layer 113 and the lower surface of the wafer 105, respectively. At this time, the upper conductive layer 121a must be formed to be connected to both terminals. Therefore, in order to form the metal layer so that the portion where the insulating layer is not formed is filled, it is preferable to form the upper conductive layer by a plating method. However, as described above, the conductive layer has a gap between the connection pads. Therefore, the plating layer must be formed so that the portion where the insulation layer corresponding to the terminal area is not formed is filled firmly. Most preferably, at least one copper foil is laminated after being formed. Subsequently, the row of chip elements is diced in units of two lines along the line YY ′ in FIG.
[0023]
After the dicing step, a resultant product separated in units of two lines is obtained as shown in FIG. 4A. In this structure, each chip element is formed on only one side. Electrode surfaces 137 ′ and 137 ″ are respectively formed on the side surfaces of the upper and lower conductive layers 121a and 121b forming one side surface obtained by the dicing. The electrode surfaces 137 ′ and 137 ″ are formed of a silicon material by an electrolytic plating method. An electrode may not be formed on the side surface of the chip element, but can be selectively formed only on the side surface of the metal plating layers 121a and 121b.
[0024]
Next, the upper conductive layer 121a corresponding to the line XX ′ in FIG. 4A is removed, and the upper conductive layer 121a and the upper portion connected to the two terminals of each chip element as shown in FIG. 4B. The electrode surface 137 ′ formed in the conductive layer is separated into two regions. At this time, the insulating layer 113 serves to prevent the chip element from being damaged in the process of electrically separating the two terminals and separating the upper conductive layer 121a.
[0025]
Subsequently, a final dicing process is performed so that the resultant product shown in FIG. Thus, the final chip package 140 is completed. Further, as shown in FIG. 4C, a protective layer 139 may be further formed on the exposed outer surface of the conductive layer of the chip package 140. The protective layer 139 is made of an insulating film formed by applying an insulating resin to the upper and lower conductive layers 121a and 121b, and prevents the conductive layers 121a and 121b from being oxidized, thereby improving the reliability of the package. Can be ensured. The protective layer 139 can be omitted depending on the usage environment of the chip package.
[0026]
Further, the manufacturing process of the chip package according to the present invention shown in FIGS. 3A to 4C can be implemented from various modifications. In particular, the structure of the protective layer and electrode surface forming process can be varied depending on the process of dicing into the chip package. For example, in the case of the embodiment shown in FIGS. 3A to 4C, the step of forming a protective layer protects the outer surface of the conductive layer where the electrode surface is not formed after the secondary dicing. The coating process is performed once according to the method of forming a layer, but unlike this, after forming the upper and lower conductive layers, a protective layer is formed on the upper and lower conductive layers, and then the secondary dicing is performed. A protective layer may be formed on the side surface of the conductive layer where the electrode surface is not formed. According to the former, when the wafer is diced, it is difficult to form a protective layer on the conductive layer in the subsequent process because the back surface of the wafer on which the conductive layer is formed is fixed by a tape or a vacuum device. Since a protective layer is formed in advance on the conductive layer on the lower surface of the wafer before the dicing process, there is an advantage that such a problem can be solved.
[0027]
On the other hand, the step of separating the conductive layer formed on the insulating layer into two conductive layers as shown in FIG. 4B can be implemented at the same time as the secondary dicing step shown in FIG. 4C. . That is, when performing the secondary dicing step, the process of separating the conductive layer by separating the conductive layer by adjusting the cutting depth to a depth corresponding to the thickness of the conductive layer and the process of separating the chip package unit. It can be done at the same time.
[0028]
As described above, the chip package manufacturing method according to the present invention is characterized in that the obtained wafer is diced into a package including one chip element, and the side surface of the conductive layer forming one side surface of each chip package is dicing. Any method for forming an electrode surface and forming a protective layer on the other side surface of the two conductive layers can be modified and modified into various forms. Therefore, each dicing step for forming the side surface of the chip package may be variously changed in order and method of forming the protective layer or the electrode surface, and such an improved or changed form is also within the scope of the present invention. Is included.
[0029]
【The invention's effect】
As described above, according to the chip package of the present invention, not only can the overall package dimensions be dramatically reduced, but also the via hole forming process, the wire process, etc. can be omitted, and the manufacturing process can be simplified. It is possible to manufacture a chip package having a new structure and a chip package assembly including the chip package.
[Brief description of the drawings]
FIGS. 1A and 1B are a perspective view and a sectional view of a chip package according to an embodiment of the present invention.
FIG. 2 is a perspective view showing a chip package assembly according to an embodiment of the present invention.
FIGS. 3A to 3C are cross-sectional views showing a method for manufacturing a chip package according to a preferred embodiment of the present invention.
FIGS. 4A to 4C are cross-sectional views showing process steps in a chip package manufacturing method according to a preferred embodiment of the present invention. FIGS.
FIG. 5 is a cross-sectional view showing a conventional chip package.
FIG. 6 is a cross-sectional view showing a conventional chip package assembly.
[Explanation of symbols]
30 Chip package 31a, 31b, 31c Conductive layer 33 Insulating layer 37a, 37b, 37c Electrode surface 35 Chip element 51 Printed circuit board 57a, 57b, 57c Connection pad

Claims (27)

二つの端子が形成された第１面と前記第１面に対向して一つの端子が形成された第２面とを有するチップ素子と、
前記二つの端子領域を除く前記第１面に形成された絶縁層と、
前記絶縁層上に形成されて前記第１面上の各端子に連結され、所定の間隔で電気的に分離された第１及び第２導電層と、
前記チップ素子の第２面に形成されて前記第２面の端子と連結された第３導電層と、
前記第１、第２、及び第３導電層の側面中前記チップ素子の同じ側面に接する一側面に各々形成された電極面と、
を備えたことを特徴とするチップパッケージ。A chip element having a first surface on which two terminals are formed and a second surface on which one terminal is formed opposite to the first surface;
An insulating layer formed on the first surface excluding the two terminal regions;
First and second conductive layers formed on the insulating layer and connected to the terminals on the first surface and electrically separated at a predetermined interval;
A third conductive layer formed on the second surface of the chip element and connected to the terminal of the second surface;
Electrode surfaces respectively formed on one side surface in contact with the same side surface of the chip element among the side surfaces of the first, second, and third conductive layers;
A chip package characterized by comprising: 前記チップパッケージは、前記電極面が形成された一側面を除く前記導電層の外郭面に形成された保護層をさらに備えたことを特徴とする請求項１に記載のチップパッケージ。The chip package according to claim 1, further comprising a protective layer formed on an outer surface of the conductive layer except for one side surface on which the electrode surface is formed. 前記保護層は、絶縁性樹脂を塗布して形成した被膜から成ることを特徴とする請求項２に記載のチップパッケージ。The chip package according to claim 2, wherein the protective layer is made of a coating formed by applying an insulating resin. 前記チップ素子の側面と前記導電層の電極面が形成された側面とは、一つの平坦面を成すことを特徴とする請求項１に記載のチップパッケージ。The chip package according to claim 1, wherein the side surface of the chip element and the side surface on which the electrode surface of the conductive layer is formed form one flat surface. 前記導電層は銅を含んだ金属層であることを特徴とする請求項１に記載のチップパッケージ。2. The chip package according to claim 1, wherein the conductive layer is a metal layer containing copper. 前記電極面は金を含んだ金属層であることを特徴とする請求項１に記載のチップパッケージ。2. The chip package according to claim 1, wherein the electrode surface is a metal layer containing gold. 前記導電層は、メッキ層から成る第１層と、前記第１層上に積層された少なくとも一つの銅箔から成る第２層とを備えたことを特徴とする請求項１に記載のチップパッケージ。2. The chip package according to claim 1, wherein the conductive layer includes a first layer made of a plated layer and a second layer made of at least one copper foil laminated on the first layer. . 前記チップ素子はトランジスタであることを特徴とする請求項１に記載のチップパッケージ。The chip package according to claim 1, wherein the chip element is a transistor. 二つの端子が形成された第１面と前記第１面に対向して一つの端子が形成された第２面とを有するチップ素子と、前記二つの端子領域を除く前記第１面に形成された絶縁層と、前記絶縁層上に形成されて前記第１面上の各端子に連結され、所定の間隔で分離された第１及び第２導電層と、前記チップ素子の第２面に端子と連結されて形成された第３導電層と、前記第１、第２及び第３導電層の側面中前記チップ素子の同じ側面に接する一側面に各々形成された電極面とを含んだチップパッケージと、
少なくとも三つの連結パッドと、前記連結パッドに各々連結された所定の回路パターンが形成された印刷回路基板とを含み、
前記電極面が各々前記連結パッドに付着されて前記チップパッケージが前記印刷回路基板に実装された構造物と、
を備えたことを特徴とするチップパッケージアセンブリー。A chip element having a first surface on which two terminals are formed and a second surface on which one terminal is formed opposite to the first surface; and formed on the first surface excluding the two terminal regions. An insulating layer, first and second conductive layers formed on the insulating layer and connected to the terminals on the first surface and separated at a predetermined interval, and terminals on the second surface of the chip element. A chip package comprising: a third conductive layer connected to the first conductive layer; and electrode surfaces formed on one side of the side surfaces of the first, second and third conductive layers contacting the same side surface of the chip element. When,
Including at least three connection pads and a printed circuit board on which predetermined circuit patterns connected to the connection pads are formed;
A structure in which each of the electrode surfaces is attached to the connection pad and the chip package is mounted on the printed circuit board;
A chip package assembly comprising: 前記チップパッケージは、前記印刷回路基板に実装される面を除く前記導電層の外郭面に形成された保護層をさらに備えたことを特徴とする請求項９に記載のチップパッケージアセンブリー。The chip package assembly according to claim 9, further comprising a protective layer formed on an outer surface of the conductive layer excluding a surface mounted on the printed circuit board. 前記保護層は、絶縁性樹脂を塗布して形成された被膜から成ることを特徴とする請求項１０に記載のチップパッケージアセンブリー。The chip package assembly according to claim 10, wherein the protective layer is made of a coating formed by applying an insulating resin. 前記導電層は銅を含んだ金属層であることを特徴とする請求項９に記載のチップパッケージアセンブリー。The chip package assembly according to claim 9, wherein the conductive layer is a metal layer containing copper. 前記電極面は金を含んだ金属層であることを特徴とする請求項９に記載のチップパッケージアセンブリー。The chip package assembly according to claim 9, wherein the electrode surface is a metal layer including gold. 前記導電層は、メッキ層から成る第１層と、前記第１層に積層された少なくとも一つの銅箔から成る第２層とを備えたことを特徴とする請求項９に記載のチップパッケージアセンブリー。10. The chip package assembly according to claim 9, wherein the conductive layer includes a first layer made of a plating layer and a second layer made of at least one copper foil laminated on the first layer. Lee. 前記チップ素子はトランジスタであることを特徴とする請求項９に記載のチップパッケージアセンブリー。The chip package assembly according to claim 9, wherein the chip element is a transistor. 上面に二つの端子と下面に一つの端子を設けた複数個のチップ素子が形成されたウェーハを用意する段階と、
前記二つの端子が形成された領域を除く前記ウェーハ上面に絶縁層を形成する段階と、
前記絶縁層上に前記ウェーハ上面に形成された二つの端子と連結されるよう上部導電層を形成する段階と、
前記ウェーハ下面に該下面の端子と連結されるよう下部導電層を形成する段階と、
チップパッケージの一側面が形成されるよう前記ウェーハを１次ダイシングする段階と、
前記１次ダイシングにより形成された前記導電層の一側面に各々電極面を形成する段階と、
前記絶縁層上に形成された導電層を前記二つの端子に各々連結された二つの導電層に分離する段階と、
チップパッケージ単位で完全に分離されるよう前記段階により形成された結果物を２次ダイシングする段階と、
を有することを特徴とするチップパッケージの製造方法。Preparing a wafer on which a plurality of chip elements having two terminals on the upper surface and one terminal on the lower surface are formed;
Forming an insulating layer on the upper surface of the wafer excluding a region where the two terminals are formed;
Forming an upper conductive layer on the insulating layer to be connected to two terminals formed on the wafer upper surface;
Forming a lower conductive layer on the lower surface of the wafer to be connected to a terminal on the lower surface;
Primary dicing the wafer to form one side of a chip package;
Forming each electrode surface on one side surface of the conductive layer formed by the primary dicing;
Separating the conductive layer formed on the insulating layer into two conductive layers respectively connected to the two terminals;
Secondary dicing the resultant formed by the above-mentioned step so as to be completely separated in chip package units;
A method of manufacturing a chip package, comprising: 前記上部及び下部導電層を形成してから、前記上部及び下部導電層上に保護層を形成する段階と、
前記２次ダイシング後に、前記電極面の形成されていない導電層の側面に保護層を形成する段階と、
をさらに有することを特徴とする請求項１６に記載のチップパッケージの製造方法。Forming the upper and lower conductive layers and then forming a protective layer on the upper and lower conductive layers;
After the secondary dicing, forming a protective layer on a side surface of the conductive layer on which the electrode surface is not formed;
The method of manufacturing a chip package according to claim 16, further comprising: 前記２次ダイシング後に、前記電極面の形成されていない前記導電層の外部面に保護層を形成する段階をさらに有することを特徴とする請求項１６に記載のチップパッケージの製造方法。The method of manufacturing a chip package according to claim 16, further comprising a step of forming a protective layer on the outer surface of the conductive layer on which the electrode surface is not formed after the secondary dicing. 前記保護層は絶縁性樹脂を塗布して形成されることを特徴とする請求項１７または１８に記載のチップパッケージの製造方法。19. The method of manufacturing a chip package according to claim 17, wherein the protective layer is formed by applying an insulating resin. 前記１次ダイシングする段階は、前記ウェーハ上にチップ素子が配列されたラインを基準として二つのライン単位で分離されるよう前記ウェーハをダイシングする段階であることを特徴とする請求項１６に記載のチップパッケージの製造方法。The method of claim 16, wherein the primary dicing step is a step of dicing the wafer so that the wafer is separated in units of two lines based on a line in which chip elements are arranged on the wafer. Chip package manufacturing method. 前記絶縁層上に形成された導電層を二つの導電層に分離する段階は、切削深さを調節して前記２次ダイシングする段階と同時に行うことを特徴とする請求項１６に記載のチップパッケージの製造方法。The chip package of claim 16, wherein the step of separating the conductive layer formed on the insulating layer into two conductive layers is performed simultaneously with the step of secondary dicing by adjusting a cutting depth. Manufacturing method. 前記導電層はメッキ法により形成することを特徴とする請求項１６に記載のチップパッケージの製造方法。The method according to claim 16, wherein the conductive layer is formed by a plating method. 前記導電層は銅を含んだ金属層であることを特徴とする請求項１６に記載のチップパッケージ。The chip package according to claim 16, wherein the conductive layer is a metal layer containing copper. 前記電極面は金を含んだ金属層であることを特徴とする請求項１６に記載のチップパッケージ。The chip package according to claim 16, wherein the electrode surface is a metal layer containing gold. 前記導電層を形成する段階は、前記各端子に連結されるメッキ層を形成してから、前記メッキ層の上面に少なくとも一つの銅箔を積層する段階であることを特徴とする請求項１６に記載のチップパッケージの製造方法。The step of forming the conductive layer is a step of forming a plating layer connected to each terminal and then laminating at least one copper foil on the upper surface of the plating layer. The manufacturing method of the chip package of description. 前記電極面はメッキ法により形成されることを特徴とする請求項１６に記載のチップパッケージの製造方法。The method of manufacturing a chip package according to claim 16, wherein the electrode surface is formed by a plating method. 前記チップ素子はトランジスタであることを特徴とする請求項１６に記載のチップパッケージの製造方法。The method of claim 16, wherein the chip element is a transistor.
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