CN104576416A - Double-layer convex-point diode chip preparation method - Google Patents
Double-layer convex-point diode chip preparation method Download PDFInfo
- Publication number
- CN104576416A CN104576416A CN201310504121.5A CN201310504121A CN104576416A CN 104576416 A CN104576416 A CN 104576416A CN 201310504121 A CN201310504121 A CN 201310504121A CN 104576416 A CN104576416 A CN 104576416A
- Authority
- CN
- China
- Prior art keywords
- diode chip
- double
- ball
- backlight unit
- layer convex
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 14
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 229910001128 Sn alloy Inorganic materials 0.000 abstract 2
- 238000012858 packaging process Methods 0.000 abstract 1
- 230000008054 signal transmission Effects 0.000 abstract 1
- 229910000831 Steel Inorganic materials 0.000 description 8
- 239000010959 steel Substances 0.000 description 8
- 238000005245 sintering Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
Abstract
The invention discloses a double-layer convex-point diode chip preparation method which comprises the following steps: after the negative electrode and the positive electrode of a diode are metalized, implanting a tin alloy ball at the bonding point of the negative electrode and the positive electrode in a ball implanting mode, and heating to melt the tin alloy ball, thereby enabling the metal electrodes to be in ohmic contact and forming a double-layer convex-point diode chip structure. By adopting the method, the later packaging process is simplified, the electric signal transmission is improved, and the packaging cost is lowered.
Description
Technical field
The present invention is a kind of double-deck salient point diode chip for backlight unit preparation method, belongs to semi-conductor discrete device diode chip for backlight unit technical field.
Background technology
The lead portion of the rear road encapsulation of diode chip for backlight unit has metal lead wire bonding and weld tabs to sinter two kinds of modes, what wherein adopt the technique of weld tabs sintering usually to take is semi-automatic or manual mode, what generally take is that the diode chip for backlight unit of sliver is carried out chip prewelding (chip two sides burn-on solder) by the method for silk screen, then carry out chip to shelve (being filled on the lead frames by the chip welded in advance), the technique eventually passing heat-agglomerating completes the bonding of lead-in wire.This mode is owing to taking twice silk screen printing, and a step pendulum, efficiency is low, and yield is low, and easily produces weld defect.
The BGA(ball bar array of integrated circuit (IC) chip) encapsulation technology, what take is BGA tin ball, by planting the mode of ball, BGA tin ball is planted on IC chip, good wire contacts can be obtained, and reduce lead resistance power loss and improve heat dispersion, having obtained general application.Wherein BGA tin ball is as BGA package welding material, produces standardization, and cheap.
Summary of the invention
The present invention is a kind of double-deck salient point diode chip for backlight unit preparation method.
After emphasis of the present invention considers semiconductor diode chip, road encapsulates the defect of weld tabs sintering process, one is provided to be convenient to the double-deck salient point diode chip for backlight unit of rear road packaging sintering process, give the preparation method realizing salient point diode chip for backlight unit, and double-deck bump chip structure.
Advantage of the present invention and good effect are: ashbury metal ball direct sintering in diode chip for backlight unit metal electrode bonding point position; as the extension of technique after diode chip for backlight unit negative electrode, anode metallization; the batched operation that full wafer circle is brilliant can be realized; high and the good reliability of efficiency; the chip pre-welding technique in rear road encapsulation process can be saved; shorten packaging technology flow process; reduce packaging cost, this has very positive meaning to road packaging technology after generally taking the diode of semi-automatic and manual mode pendulum operation.
accompanying drawing explanation
Fig. 1 is diode chip for backlight unit schematic diagram after metallization
Fig. 2 is that diode chip for backlight unit anode plants ball process schematic
Fig. 3 anode salient point diode chip for backlight unit schematic diagram
Fig. 4 is that diode chip for backlight unit negative electrode secondary plants ball process schematic
Fig. 5 is double-deck salient point diode chip structure schematic diagram
Embodiment
Patent specific implementation method of the present invention is:
After semiconductor diode chip has metallized, structural representation as shown in Figure 1, see Fig. 2, whole disk anode surface is rushed to, disk is shelved the steel mesh 5 made according to chip layout size and aims at, steel mesh is punched the anode 2 bonding point place one_to_one corresponding of position and each diode chip, ashbury metal ball 6 is implanted at bonding pad opening place by steel mesh 5, the diameter of ashbury metal ball is less than steel mesh and punches size, remove steel mesh, ashbury metal ball is made to melt backflow by heating the diode chip for backlight unit of planting good shot, after cooling, ashbury metal ball 6 and diode chip for backlight unit metal anode 2 form ohmic contact, and form anode salient point diode chip structure, see Fig. 3.Anode salient point diode chip for backlight unit is overturn, its cathode plane is rushed to, and steel mesh 5 is shelved above diode chip for backlight unit negative electrode 3, the position of opening of steel mesh 5 and each tube core negative electrode bonding point one_to_one corresponding is made by aiming at, usual diode cathode is planless metal level, the aligned position of negative electrode steel mesh will with the position one_to_one corresponding of chip anode bonding point.Repeat anode and plant ball process, the secondary carrying out diode chip for backlight unit plants ball, as shown in Figure 4, finally obtains double-deck salient point diode chip structure, as shown in Figure 5.Finally cut in brilliant scribe line 4 position of circle, form the single bilayered later road of salient point diode chip for backlight unit and encapsulate.
Claims (1)
1. a double-deck salient point diode chip for backlight unit preparation method, after it is characterized in that diode cathode and anode metallization complete, ashbury metal ball is implanted by the mode of planting ball at negative electrode and anode linkage point position, by the mode of heating, ashbury metal ball is melted, form ohmic contact with metal electrode, and form double-deck salient point diode chip structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310504121.5A CN104576416A (en) | 2013-10-24 | 2013-10-24 | Double-layer convex-point diode chip preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310504121.5A CN104576416A (en) | 2013-10-24 | 2013-10-24 | Double-layer convex-point diode chip preparation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104576416A true CN104576416A (en) | 2015-04-29 |
Family
ID=53092172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310504121.5A Pending CN104576416A (en) | 2013-10-24 | 2013-10-24 | Double-layer convex-point diode chip preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104576416A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030127720A1 (en) * | 2002-01-07 | 2003-07-10 | Jen-Kuang Fang | Multi-chip stack package and fabricating method thereof |
| CN1445846A (en) * | 2002-03-18 | 2003-10-01 | 三星电机株式会社 | Chip ratio package and manufacturing method thereof |
| US20100320531A1 (en) * | 2008-06-30 | 2010-12-23 | Tao Feng | Standing chip scale package |
-
2013
- 2013-10-24 CN CN201310504121.5A patent/CN104576416A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030127720A1 (en) * | 2002-01-07 | 2003-07-10 | Jen-Kuang Fang | Multi-chip stack package and fabricating method thereof |
| CN1445846A (en) * | 2002-03-18 | 2003-10-01 | 三星电机株式会社 | Chip ratio package and manufacturing method thereof |
| US20100320531A1 (en) * | 2008-06-30 | 2010-12-23 | Tao Feng | Standing chip scale package |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150429 |
|
| WD01 | Invention patent application deemed withdrawn after publication |