CN103050465A - Wafer-thinning single-chip encapsulation piece with copper pillars and manufacturing technology thereof - Google Patents
Wafer-thinning single-chip encapsulation piece with copper pillars and manufacturing technology thereof Download PDFInfo
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- CN103050465A CN103050465A CN201210534210XA CN201210534210A CN103050465A CN 103050465 A CN103050465 A CN 103050465A CN 201210534210X A CN201210534210X A CN 201210534210XA CN 201210534210 A CN201210534210 A CN 201210534210A CN 103050465 A CN103050465 A CN 103050465A
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- chip
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- nickel gold
- tin silver
- salient point
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The invention relates to a wafer-thinning single-chip encapsulation piece with copper pillars and a manufacturing technology thereof. The encapsulation piece mainly consists of a substrate, nickel gold pads, a chip, the copper pillars, tin silver bumpings, a base filler and tin balls, wherein the nickel gold pads are fixedly connected onto the substrate; the copper pillars are fixedly connected onto the chip; the tin silver bumpings are fixedly connected onto the respective copper pillar; the tin silver bumpings overlap with and are in welding connection with the center line of the respective nickel gold pad; the base filler fills gaps between the substrate and the chip and further surrounds the nickel gold pads, the copper pillars and the tin silver bumpings; and the tin silver bumpings and the nickel gold pads are soldered through the adoption of soldering fluxes. The manufacturing technology is implemented according to the following steps of installing the chip and reflow soldering; washing with deionized water; filling; solidifying; thinning a wafer; and implanting the tin balls, inspecting, packing and warehousing. With the adoption of the wafer-thinning single-chip encapsulation piece with copper pillars and the manufacturing technology thereof, the high-density high-reliability encapsulation can be realized.
Description
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Technical field
The invention belongs to the integrated antenna package technical field, specifically a kind of single-chip package part and manufacture craft thereof of the wafer attenuate with the copper post.
Background technology
Flip Chip flip-chip is a kind of chip interconnects technology, is again a kind of desirable die bonding technology. and IBM Corporation has researched and developed this technology of having used before 30 years.Flip-Chip just became the packing forms that often adopts in high-end device and the high-density packages field but until in recent years.Today, the range of application of Flip-Chip encapsulation technology is increasingly extensive, and packing forms is variation more, to the also thereupon raising of requirement of Flip-Chip encapsulation technology.Simultaneously, Flip-Chip has also proposed a series of new severe challenges to the producer, for the technology of this complexity provides encapsulation, and the reliable support of assembling and test.One-level sealing technique in the past all is that the active area with chip faces up, bonding behind substrate and the paster, as strong the closing and carrier band automatically sound (TAB) that go between.FC then faces substrate with the chip active area, realize the interconnection of chip and substrate by the solder bump that is arrayed on the chip. silicon chip directly with the back-off mode be installed to substrate from silicon chip to around draw I/O, interconnected length shortens greatly, reduced the RC delay, effectively improved electrical property. obviously, this chip interconnects mode can provide higher I/O density. and the upside-down mounting occupied area is almost consistent with die size. and in all surface mounting technique, flip-chip can reach minimum, the thinnest encapsulation.But because the limitation of conventional package in the past, wafer can only be thinned to 200 μ m, and particularly being thinned to the following thickness of 100 μ m is easy warpage, and package reliability can not be guaranteed.
Along with circuit structure becomes increasingly complex, the I/O of chip output is more and more, and the pitch (pitch) between the chip bump (bumping) requires more and more less.Tradition paste solder printing salient point (bumping) spacing can not satisfy the package reliability requirement.
Summary of the invention
The problem that exists in order to overcome above-mentioned prior art, the manufacture craft that the purpose of this invention is to provide a kind of single-chip package part of the wafer attenuate with the copper post, make package size thinner, when significantly improving the reliability of packaging part, the realization high density high reliability encapsulates, and solves the deficiency of traditional paste solder printing salient point.Can accomplish now that with the pitch between the tin silver salient point of copper post the salient point after the upside-down mounting is difficult for bridge joint below the 100 μ m in reflux course, can effectively increase I/O density and the reliability of chip.
Technical scheme of the present invention is: a kind of single-chip package part of the wafer attenuate with the copper post mainly is comprised of substrate, nickel gold solder dish, chip, copper post, tin silver salient point, end filler, tin ball; Described nickel gold solder dish is fixedly connected on substrate, and the copper post is fixedly connected on the chip, and tin silver salient point is fixedly connected on the copper post; The central lines of described tin silver salient point and nickel gold solder dish also is welded to connect; Filler of the described end is filled the space between substrate and the chip, and surrounds nickel gold solder dish, copper post and Xi Yin salient point; The scaling powder welding is adopted in the welding of described tin silver salient point and nickel gold solder dish.
A kind of manufacture craft of single-chip package part of the wafer attenuate with the copper post, it carries out according to following steps:
The first step, upper core, Reflow Soldering: at first, brush the scaling powder of one deck 35 μ m--60 μ m at the nickel gold solder dish of substrate; Secondly, tin silver salient point is cohered contacts with the central lines of nickel gold solder dish and by scaling powder; Again, under 255 ± 5 ℃ reflux temperature, nickel gold solder dish and tin silver salient point effectively form the welding knot, namely form intermetallic compound; At last, chip is welded on the substrate securely;
Second step, washed with de-ionized water: remain in scaling powder and other impurity on the tin silver salient point with the washed with de-ionized water about 10M Ω CM;
The 3rd goes on foot, fills out down: at first, substrate is carried out the baking of 125 ℃/150min, remove the steam on substrate and the chip; Secondly, product is cleaned with plasma gas; Again, use end filler to fill the space of chip and substrate;
Traditional handicraft is adopted in the 4th step, curing: adopt the baking oven of cleaning, 150 ℃ of temperature, 2 hours duration were cured the product of filling out down;
The 5th step, wafer attenuate: roughly grind first with type diamond grinding wheel, then finish grind, final wafer thickness is thinned to below the 100 μ m;
The 6th the step, plant ball, check, packing, warehouse-in all with traditional technique.
Figure of description
Fig. 1 is the substrate profile;
Fig. 2 is substrate brush scaling powder profile;
Fig. 3 is product profile after upper core, the Reflow Soldering;
Fig. 4 fills out rear product profile under being;
Fig. 5 is product profile after the chip corase grind;
Fig. 6 is the rear product profile of correct grinding;
Fig. 7 is for planting finished product profile behind the ball.
Among the figure, 1 is that substrate, 2 is the tin ball for correct grinding part, 10 for corase grind part, 9 for end filler, 8 for tin silver salient point, 7 for copper post, 6 for chip, 5 for scaling powder, 4 for nickel gold solder dish, 3.
Embodiment
The present invention is described further below in conjunction with accompanying drawing.
As shown in the figure, a kind of single-chip package part of the wafer attenuate with the copper post mainly is comprised of substrate 1, nickel gold solder dish 2, chip 4, copper post 5, tin silver salient point 6, end filler 7, tin ball 10; Described nickel gold solder dish 2 is fixedly connected on the substrate 1, and copper post 5 is fixedly connected on the chip 4, and tin silver salient point 6 is fixedly connected on the copper post 5; The central lines of described tin silver salient point 6 and nickel gold solder dish 2 also is welded to connect; The space that filler of the described end 7 is filled between substrate 1 and the chip 4, and surround nickel gold solder dish 2, copper post 5 and Xi Yin salient point 6; Described tin silver salient point 6 adopts scaling powder 3 welding with the welding of nickel gold solder dish 2.
As shown in the figure, a kind of manufacture craft of single-chip package part of the wafer attenuate with the copper post, it carries out according to following steps:
The first step, upper core, Reflow Soldering: at first, at the scaling powder 3 of nickel gold solder dish 2 brush one decks 35 μ m--60 μ m of substrate 1, as shown in Figure 2; Secondly, the tin silver salient point 6 of chip 4 is also contacted with the central lines of the nickel gold solder dish 2 of substrate 1, because the stickiness of scaling powder 3, nickel gold solder dish 2 firmly contacts and difficult skew with Xi Yin salient point 6; Again, under 255 ± 5 ℃ reflux temperature, nickel gold solder dish 2 effectively forms the welding knot with tin silver salient point 6, namely forms intermetallic compound, and scaling powder 3 can be removed oxide when welding, and has catalysis welding effect; At last, chip 4 is welded on the substrate 1 securely.As shown in Figure 3.
Second step, plasma cleaning: remain in scaling powder 3 and other impurity on the tin silver salient point 6 with the washed with de-ionized water about 10M Ω CM.Because the residual meeting of scaling powder 3 after backflow reduces the flowability of end filler 7, make the fillibility variation of end filler 7.
The 3rd step, fill out down: at first, substrate 1 is carried out the baking of 125 ℃/150min, removes the steam on substrate 1 and the chip 4, avoid under fill out with rear solidification process in end filler 7 produce the cavity; Secondly, product is cleaned with plasma gas, principle is that inert gas is ionized into ion and high speed impact substrate surface in high voltage electric field, removes some dusts or particle, so that the flowability of end filler 7 between substrate 1 and chip 4 is better; Again, use end filler 7 to fill the space of chips 4 and substrate 1, one side end filler 7 flows to chip 4 another sides by capillarity from chip 4.Here, can according to the space of the shape of chip 4, chip 4 thickness, chip 4 and substrate 1, copper post 5 arrange and density is selected suitable end filler 7 and suitable process conditions (glue temperature, basal plate preheating temperature, some rubber moulding formula etc.), to prevent the generation in cavity.Profile after filling out down is shown in 4.
Traditional handicraft is adopted in the 4th step, rear curing: adopt the baking oven of cleaning, 150 ℃ of temperature, 2 hours duration were cured the product of filling out down.Cross-linking reaction occurs in end filler 7 when high temperature, intensity, thermal endurance and the resistance to wear of colloid are improved greatly, effectively tamper seal piece installing.
The 5th step, wafer attenuate: roughly grind first with type diamond grinding wheel, then finish grind, final wafer thickness is thinned to below the 100 μ m.Such as Fig. 5 with roughly grind as shown in Figure 6 part 8 and correct grinding part 9.
The 6th the step, plant ball, check, packing, warehouse-in all with traditional technique.Finished product as shown in Figure 7 after planting ball.
The advantage of this single-chip package part wafer thinning technique is: 1) be easy to security wafer transmission and transportation; 2) do not need thinning back side before the Wafer Dicing; 3) be easy to wafer cutting, collapse limit and sliver when having reduced cutting; 4) the chip sliver possibility in FLIP CHIP encapsulation process reduces greatly; 5) thinning back side of silicon wafer has the heat radiation when utilizing chip operation, thereby has improved the life-span of product; 6) wafer has certain thickness in cutting and encapsulation process, the Crack risk when greatly reducing chip package, and then promoted product encapsulation acceptance rate.
Claims (2)
1. the single-chip package part with the wafer attenuate of copper post is characterized in that: mainly be comprised of substrate (1), nickel gold solder dish (2), chip (4), copper post (5), tin silver salient point (6), end filler (7), tin ball (10); Described nickel gold solder dish (2) is fixedly connected on the substrate (1), and copper post (5) is fixedly connected on the chip (4), and tin silver salient point (6) is fixedly connected on the copper post (5); The central lines of described tin silver salient point (6) and nickel gold solder dish (2) also is welded to connect; Filler of the described end (7) is filled the space between substrate (1) and the chip (4), and surrounds nickel gold solder dish (2), copper post (5) and tin silver salient point (6); Described tin silver salient point (6) adopts scaling powder (3) welding with the welding of nickel gold solder dish (2).
2. manufacture craft with the single-chip package part of the wafer attenuate of copper post, it is characterized in that: it carries out according to following steps:
The first step, upper core, Reflow Soldering: at first, brush the scaling powder (3) of one deck 35 μ m--60 μ m at the nickel gold solder dish (2) of substrate (1); Secondly, tin silver salient point (6) is cohered contacts with the central lines of nickel gold solder dish (2) and by scaling powder (3); Again, under 255 ± 5 ℃ reflux temperature, nickel gold solder dish (2) effectively forms the welding knot with tin silver salient point (6), namely forms intermetallic compound; At last, chip (4) is welded on the substrate (1) securely;
Second step, washed with de-ionized water: remain in scaling powder (3) and other impurity on the tin silver salient point (6) with the washed with de-ionized water about 10M Ω CM;
The 3rd goes on foot, fills out down: at first, substrate (1) is carried out the baking of 125 ℃/150min, remove the steam on substrate (1) and the chip (4); Secondly, product is cleaned with plasma gas; Again, use end filler (7) to fill the space of chip (4) and substrate (1);
Traditional handicraft is adopted in the 4th step, curing: adopt the baking oven of cleaning, 150 ℃ of temperature, 2 hours duration were cured the product of filling out down;
The 5th step, wafer attenuate: roughly grind first with type diamond grinding wheel, then finish grind, final wafer thickness is thinned to below the 100 μ m;
The 6th the step, plant ball, check, packing, warehouse-in all with traditional technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201210534210XA CN103050465A (en) | 2012-12-12 | 2012-12-12 | Wafer-thinning single-chip encapsulation piece with copper pillars and manufacturing technology thereof |
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| CN201210534210XA CN103050465A (en) | 2012-12-12 | 2012-12-12 | Wafer-thinning single-chip encapsulation piece with copper pillars and manufacturing technology thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456649A (en) * | 2013-08-28 | 2013-12-18 | 南通富士通微电子股份有限公司 | Method for encapsulating semiconductors |
| CN104465586A (en) * | 2014-12-26 | 2015-03-25 | 江苏长电科技股份有限公司 | Novel wafer level packaging structure and technological method thereof |
| CN110233110A (en) * | 2019-05-30 | 2019-09-13 | 同辉电子科技股份有限公司 | A kind of welding method of GaN flip-chip |
| CN113113395A (en) * | 2021-03-25 | 2021-07-13 | Tcl华星光电技术有限公司 | Substrate and method for manufacturing light-emitting substrate |
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| JP2004063515A (en) * | 2002-07-25 | 2004-02-26 | Matsushita Electric Ind Co Ltd | Method of manufacturing semiconductor device |
| US20060003550A1 (en) * | 2004-07-01 | 2006-01-05 | Agency For Science, Technology And Research | Method for ultra thinning bumped wafers for flip chip |
| CN102208358A (en) * | 2011-04-25 | 2011-10-05 | 北京大学深圳研究生院 | Method for soldering flip chip on base plate and packaging apparatus |
| US20110260303A1 (en) * | 2010-04-23 | 2011-10-27 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Openings in Thermally-Conductive Frame of FO-WLCSP to Dissipate Heat and Reduce Package Height |
| CN203055899U (en) * | 2012-12-12 | 2013-07-10 | 华天科技（西安）有限公司 | Wafer-thinning single-chip encapsulation piece with copper pillars |
-
2012
- 2012-12-12 CN CN201210534210XA patent/CN103050465A/en active Pending
Patent Citations (5)
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|---|---|---|---|---|
| JP2004063515A (en) * | 2002-07-25 | 2004-02-26 | Matsushita Electric Ind Co Ltd | Method of manufacturing semiconductor device |
| US20060003550A1 (en) * | 2004-07-01 | 2006-01-05 | Agency For Science, Technology And Research | Method for ultra thinning bumped wafers for flip chip |
| US20110260303A1 (en) * | 2010-04-23 | 2011-10-27 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Openings in Thermally-Conductive Frame of FO-WLCSP to Dissipate Heat and Reduce Package Height |
| CN102208358A (en) * | 2011-04-25 | 2011-10-05 | 北京大学深圳研究生院 | Method for soldering flip chip on base plate and packaging apparatus |
| CN203055899U (en) * | 2012-12-12 | 2013-07-10 | 华天科技（西安）有限公司 | Wafer-thinning single-chip encapsulation piece with copper pillars |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456649A (en) * | 2013-08-28 | 2013-12-18 | 南通富士通微电子股份有限公司 | Method for encapsulating semiconductors |
| CN104465586A (en) * | 2014-12-26 | 2015-03-25 | 江苏长电科技股份有限公司 | Novel wafer level packaging structure and technological method thereof |
| CN104465586B (en) * | 2014-12-26 | 2018-07-10 | 江苏长电科技股份有限公司 | A kind of wafer-level package structure and its process |
| CN110233110A (en) * | 2019-05-30 | 2019-09-13 | 同辉电子科技股份有限公司 | A kind of welding method of GaN flip-chip |
| CN113113395A (en) * | 2021-03-25 | 2021-07-13 | Tcl华星光电技术有限公司 | Substrate and method for manufacturing light-emitting substrate |
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