CN102208358A - Method for soldering flip chip on base plate and packaging apparatus - Google Patents
Method for soldering flip chip on base plate and packaging apparatus Download PDFInfo
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- CN102208358A CN102208358A CN 201110103595 CN201110103595A CN102208358A CN 102208358 A CN102208358 A CN 102208358A CN 201110103595 CN201110103595 CN 201110103595 CN 201110103595 A CN201110103595 A CN 201110103595A CN 102208358 A CN102208358 A CN 102208358A
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- chip
- flip
- solder bump
- protective layer
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
The invention discloses a method for soldering a flip chip on a base plate and a packaging apparatus. The method comprises the following steps: manufacturing one of a solder ball bump or a copper pillar on the flip chip; overlapping one or more solder balls on the solder ball bump or the copper pillar, or manufacturing one or more solder balls overlapped on the solder ball bump or the copper pillar on the base plate; and soldering the flip chip on the base plate. By using the technical scheme provided by the invention, the problem that a soldering spot between the chip and the base plate is easy to deform to cause the low reliability of the packaging apparatus in the prior art is solved.
Description
Technical field
The present invention relates to electronic technology field, relate in particular to a kind of method of flip-chip and packaging of flip-chip of on substrate, welding.
Background technology
At present, method at welding flip-chip on the substrate is normally made solder bump or copper post on flip-chip, by solder bump on the flip-chip or copper post, directly flip-chip is mounted on the substrate, Fig. 1 is the schematic diagram of Flip-Chip Using device in the prior art, comprise chip 1, substrate 2, chip bonding pad 3, substrate pads 4, solder bump 5, technological process generally comprises: at first, on semiconductor wafer, make solder bump, by electroplating, methods such as printing or soldered ball are placed on scolder on a plurality of small pad of disk, through making the scolder on the pad form salient point after the Reflow Soldering of 240-260 celsius temperature, scolder can be eutectic tin-lead alloy 63%Sn 37%Pb again, or SAC series leadless alloy etc.; Secondly, disk is cut into a plurality of chips, and chip is mounted on the substrate the other way around, when mounting solder bump is stained with some scaling powders, and solder bump contacts with the pad of substrate, and welds together after Reflow Soldering.
Because the coefficient of expansion of chip and substrate is different, when variations in temperature, solder joint between chip and the substrate is easy to take place deformation, the size of deformation is relevant with factors such as solder joint height, die size, substrate thickness, usually solder joint height is high more, relative deformation is more little, and the deformation of solder joint will cause the fatigue fracture of solder joint and the open circuit on the electricity.Mounting in the bismaleimide-triazine resin copper-clad plate with semiconductor chip is example, the coefficient of expansion of bismaleimide-triazine resin copper-clad plate is between 9-14ppm/ ℃, the coefficient of expansion of semiconductor chip is about 3ppm/ ℃, and the solder joint when semiconductor chip and the substrate coefficient of expansion different cause variations in temperature between them is easy to take place serious deformation.The ceramic substrate coefficient of expansion and chip are close, and the stress of solder bump is little when variations in temperature, and the reliability of packaging is higher, but ceramic substrate costs an arm and a leg, and are unfavorable for the large-scale promotion of chip encapsulation technology.
Summary of the invention
The invention provides a kind of method of flip-chip and packaging of flip-chip of welding on substrate, deformation takes place in solder joint easily between solution prior art chips and the substrate, causes the lower problem of packaging reliability.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
A kind of method of welding flip-chip on substrate comprises:
On described flip-chip, make a kind of in solder bump or the copper post;
The one or more soldered balls of stack are perhaps made on described substrate and are used for and described solder bump or the superimposed one or more soldered balls of copper post on described solder bump or copper post;
Described flip-chip is welded on the described substrate.
Before described flip-chip is welded on described substrate; also be included in described flip-chip top and form the solder bump that covers on described flip-chip and the described flip-chip or the protective layer of copper post, described protective layer exposes the top of described solder bump or copper post.
Described protective layer is that macromolecular material is made.
Described macromolecular material comprises epoxide resin material.
Described epoxide resin material comprises under the room temperature and to be a kind of in the solid-state epoxide resin material under liquid epoxide resin material or the room temperature; form described protective layer for the method for liquid epoxide resin material by rotary coating (Spin Coating) or sputter under the described room temperature; make laminar film earlier for solid-state epoxide resin material under the described room temperature, the method by vacuum hotpressing forms described protective layer again.
Also be included in and fill end filler between described flip-chip or described protective layer and the described substrate.
A kind of packaging of flip-chip, comprise substrate and flip-chip, be manufactured with a kind of in solder bump or the copper post on the described flip-chip, between described substrate and described flip-chip, also comprise solder bump or the superimposed soldered ball of copper post on the one or more and described flip-chip.
Also comprise protective layer, described protective layer covers described flip-chip and the solder bump on it or the surface of copper post, and described protective layer exposes the top of described solder bump or copper post.
Described protective layer is the protective layer that macromolecular material is made.
Also comprise packed layer, described packed layer is formed between described flip-chip or described protective layer and the described substrate.
The invention provides a kind of method of flip-chip and packaging of flip-chip of on substrate, welding, because the soldered ball of stack can be shared the deformation that Welding Structure causes because of chip is different with the substrate heat coefficient of expansion, can reduce the possibility of solder bump or the fatigue fracture of copper post, so the present invention is by the one or more soldered balls of stack on solder bump on the flip-chip or copper post, perhaps make on the substrate be used for flip-chip on solder bump or the mode of the superimposed one or more soldered balls of copper post, after being welded on flip-chip on the substrate, can improve the reliability of whole Welding Structure thermal stress, this method is applicable to many cheap substrates simultaneously, can promote the large-scale promotion of chip encapsulation technology, and simple to operate.
Description of drawings
Fig. 1 is the schematic diagram of Flip-Chip Using device in the prior art;
Fig. 2 is the embodiment of the invention is welded flip-chip on substrate a flow chart;
Fig. 3 a is the schematic diagram that the embodiment of the invention has the flip-chip of stack soldered ball;
Fig. 3 b is the schematic diagram of the invention process spr substrate;
Fig. 4 is the schematic diagram of embodiment of the invention Flip-Chip Using device;
Fig. 5 is another embodiment of the present invention is welded flip-chip on substrate a flow chart;
Fig. 6 a is the schematic diagram of another embodiment of the present invention flip-chip;
Fig. 6 b is the schematic diagram that another embodiment of the present invention has the substrate of stack soldered ball.
Embodiment
In conjunction with the accompanying drawings the present invention is described in further detail below by embodiment.
Embodiment one:
Present embodiment is soldered ball of stack on the solder bump of chip or copper post, and according to actual needs, two or more soldered balls that can also superpose, Fig. 2 are the embodiment of the invention is welded flip-chip on substrate flow chart, please refer to Fig. 2:
S21, forming solder bump or copper post on the silicon wafer: the technology that forms solder bump or copper post on silicon wafer can be imitated prior art, the method that forms solder bump on silicon wafer comprises: by electroplating, methods such as printing or soldered ball are placed on scolder on a plurality of small pad of disk, make the scolder on the pad form salient point through the high temperature reflux postwelding again, the temperature of high temperature reflux weldering can be 240-260 degree centigrade, scolder can be an eutectic tin-lead alloy, 63%Sn 37%Pb wherein, or SAC series leadless alloy etc., the copper post can be plated on the pad by electric plating method.
S22; protective mulch on silicon wafer: protective layer is that macromolecular material is made; epoxy resin material preferably; cover on silicon wafer and the solder bump or copper post on it by methods such as rotary coating or sputters for liquid epoxide resin material under the room temperature; can make laminar film earlier for solid-state epoxide resin material under the room temperature; method by vacuum hotpressing covers on silicon wafer and the solder bump or copper post on it; can the protective layer that form further be heated; make the macromolecular material full solidification; if appearance is different because of the coefficient of expansion of macromolecular material and disk; cause the crooked excessive phenomenon of protective layer; can protective layer not heated yet, but make it to be in the softer partly solidified or state that do not solidify.In addition; can also utilize the manufacturing materials of end filler as protective layer; in the present embodiment; protective layer all covers solder bump on chip and the chip or copper post; in practical operation; also can be that part covers, promptly expose the top of solder bump or copper post, be connected so that carry out electricity with the external world.
The top of S23, exposure solder bump or copper post: the top protected seam of solder bump or copper post covers; its top need be exposed; could carry out electricity with the external world is connected; the method that is come out in the top of solder bump or copper post is multiple; such as mechanical grinding; be about to polish on the emery wheel that one side that disk has protective layer is placed on rotation, such as laser ablation, utilize photoetching to cover chemical corrosion that film carries out etc., the present invention is not limited to above cited method.
S24, soldered ball superposes on solder bump or copper post: for spacing bigger solder bumps or copper post, can use traditional soldered ball mounting process, be to be stained with some scaling powders or scaling powder on the soldered ball, then soldered ball is placed on the disk, again through being welded to the top of solder bump or copper post after the Reflow Soldering, less for spacing, as solder bump below 100 microns or copper post, can adopt electric plating method to make soldered ball.Fig. 3 a is the schematic diagram that the embodiment of the invention has the flip-chip of stack soldered ball; please refer to Fig. 3 a, the flip-chip that present embodiment has the soldered ball of stack comprises that flip-chip 1, chip bonding pad 3, solder bump 5, covering flip-chip 1 and the protective layer 6 of solder bump 5, the top of solder bump 5 are connected with the soldered ball 7 of stack.Fig. 3 b is the schematic diagram of the invention process spr substrate, please refer to Fig. 3 b, comprises substrate 2, substrate pads 4.
S25, cutting silicon wafer become a plurality of chips, because disk surfaces has the macromolecular material protective layer, the diamond cutter are had certain viscous effect, so in cutting, appropriateness reduces cutter and selects speed and translational speed.
S26, will have a stack the chip attachment of soldered ball on substrate: the soldered ball of stack is stained with scaling powder, perhaps prints soldering paste on substrate, chip is turned around be placed on the substrate, through after the Reflow Soldering, chip attachment is on substrate.
Fig. 4 is the schematic diagram of embodiment of the invention Flip-Chip Using device; please refer to Fig. 4: a kind of packaging of flip-chip; comprise flip-chip 1 and substrate 2; chip bonding pad 3 is arranged on the flip-chip 1; substrate pads 4 is arranged on the substrate 2; be manufactured with solder bump 5 on the chip bonding pad 3; also comprise the protective layer 6 that covers flip-chip 1 and solder bump 5; the top of solder bump 5 is connected with the soldered ball 7 of stack; the soldered ball 7 of stack contacts with substrate pads 4; through after the Reflow Soldering, flip-chip 1 mounts on the substrate.
Because the soldered ball of stack can be shared the deformation that Welding Structure causes because of chip is different with the substrate heat coefficient of expansion, can reduce the possibility of solder bump or the fatigue fracture of copper post, so, the present invention can improve the reliability of whole welded thermal stress, this method is applicable to many cheap substrates simultaneously, can promote the large-scale promotion of chip encapsulation technology, and simple to operate.
Further; present embodiment has the protective layer that exposes solder bump or copper column top in the surface coverage of the flip-chip that is manufactured with solder bump or copper post; this diaphragm can play a protective role to chip; the electrical testing of chip before helping mounting; unprotected technical scheme is that the electrical measurement of chip brings difficulty in the prior art; difficult definite chip is known good chip (Known Good Die); simultaneously; because in high temperature reflux weldering cooling procedure; solder bump solidifies; because of its coefficient of expansion is bigger,, different with the chip coefficient of expansion as being about 26ppm/ ℃ under the room temperature; can on the chip under the solder bump corner, produce a bigger local stress; the local fracture that may cause chip, solder bump are down and the also fracture easily of the dielectric layer of the high dielectric constant of near dielectric layer, particularly fragility.Solder joint was to the fracture damage of chip and chip medium layer when therefore, the protective layer in the present embodiment also had the minimizing of utilizing to mount.
Further; also be included in and fill end filler between the protective layer on flip-chip or flip-chip surface and the substrate; end filler is filled in the gap between chip and the substrate; the height of filling end filler can be the ball height that is superposeed; the reliability that the combination of the soldered ball of stack and the end filler of filling can further improve thermal stress satisfies the requirement of high reliability device.
Embodiment two:
Present embodiment be make on the relevant position of substrate be used for flip-chip on a solder bump or a superimposed soldered ball of copper post, can be one be used for chip on solder bump or the superimposed soldered ball of copper post, or a plurality of be used for chip on solder bump or the superimposed soldered ball of copper post, manufacture craft and embodiment one difference are: present embodiment is that the soldered ball that will superpose is placed on the pad of substrate, rather than the top of solder bumps on the disk or copper post, correspondingly, present embodiment be with chip attachment on the substrate of soldered ball with stack, scaling powder can attach on the soldered ball of the stack on the substrate, perhaps the top of solder bump that exposes on the chip or copper post forms and the identical encapsulating structure of embodiment one outward appearance after the Reflow Soldering.
Fig. 5 is another embodiment of the present invention is welded flip-chip on substrate a flow chart, please refer to Fig. 5:
S51, forming solder bump or copper post on the silicon wafer: the technology that forms solder bump or copper post on silicon wafer can be imitated prior art, the method that forms solder bump on silicon wafer comprises: by electroplating, methods such as printing or soldered ball are placed on scolder on a plurality of small pad of disk, make the scolder on the pad form salient point through the high temperature reflux postwelding again, the temperature of high temperature reflux weldering can be 240-260 degree centigrade, scolder can be an eutectic tin-lead alloy, 63%Sn 37%Pb wherein, or SAC series leadless alloy etc., the copper post can be plated on the pad by electric plating method.
S52; protective mulch on silicon wafer: protective layer is that macromolecular material is made; epoxy resin material preferably; cover on silicon wafer and the solder bump or copper post on it by methods such as rotary coating Spin Coating or sputters for liquid epoxide resin material under the room temperature; can make laminar film earlier for solid-state epoxide resin material under the room temperature; method by vacuum hotpressing covers on silicon wafer and the solder bump or copper post on it; can the protective layer that form further be heated; make the macromolecular material full solidification; if appearance is different because of the coefficient of expansion of macromolecular material and disk; cause the crooked excessive phenomenon of protective layer; can protective layer not heated yet, but make it to be in the softer partly solidified or state that do not solidify.In addition; can also utilize the manufacturing materials of end filler as protective layer; in the present embodiment; protective layer all covers solder bump on chip and the chip or copper post; in practical operation; also can be that part covers, promptly expose the top of solder bump or copper post, be connected so that carry out electricity with the external world.
The top of S53, exposure solder bump or copper post: the top protected seam of solder bump or copper post covers; its top need be exposed; could carry out electricity with the external world is connected; the method that is come out in the top of solder bump or copper post is multiple; such as mechanical grinding; be about to polish on the emery wheel that one side that disk has protective layer is placed on rotation, such as laser ablation, utilize photoetching to cover chemical corrosion that film carries out etc., the present invention is not limited to above cited method.
The soldered ball of S54, formation stack on the pad of substrate: for spacing bigger solder bumps or copper post, can use traditional soldered ball mounting process, be to be stained with some scaling powders or scaling powder on the soldered ball, then soldered ball is placed on the substrate, less for spacing, as solder bump below 100 microns or copper post, can adopt electric plating method to make soldered ball.Fig. 6 a is the schematic diagram of another embodiment of the present invention flip-chip, please refer to Fig. 6 a, comprises the protective layer 6 of flip-chip 1, chip bonding pad 3, solder bump 5, covering flip-chip 1 and solder bump 5, and protective layer 6 exposes the top of solder bump 5.Fig. 6 b is the schematic diagram that another embodiment of the present invention has the substrate of stack soldered ball, please refer to Fig. 6 b, comprises substrate 2, substrate pads 4, also comprises the soldered ball 7 of the stack on the substrate pads 4.
S55, cutting silicon wafer become a plurality of chips, because disk surfaces has the macromolecular material protective layer, the diamond cutter are had certain viscous effect, so in cutting, appropriateness reduces cutter and selects speed and translational speed.
S56, with chip attachment on the substrate of soldered ball with stack: the soldered ball of the stack on the substrate is stained with scaling powder, scaling powder is stained with at the top of solder bump that perhaps exposes on chip or copper post, chip is turned around, be placed on the substrate, make the top of the solder bump that exposes on the chip or copper post align with soldered ball on the substrate, through after the Reflow Soldering, chip attachment is on substrate.The top of solder bump 5 alignd with the soldered ball 7 of stack to be contacted, and through after the Reflow Soldering, obtains as packaging shown in Figure 4.
Further; also be included in and fill end filler between the protective layer on flip-chip or flip-chip surface and the substrate; end filler is filled in the gap between chip and the substrate; the height of filling end filler can be the ball height that is superposeed; the reliability that the combination of the soldered ball of stack and the end filler of filling can further improve thermal stress satisfies the requirement of high reliability device.
Above content be in conjunction with concrete execution mode to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (10)
1. the method for a welding flip-chip on substrate is characterized in that, comprising:
On described flip-chip, make a kind of in solder bump or the copper post;
The one or more soldered balls of stack are perhaps made on described substrate and are used for and described solder bump or the superimposed one or more soldered balls of copper post on described solder bump or copper post;
Described flip-chip is welded on the described substrate.
2. the method for claim 1; it is characterized in that; before described flip-chip is welded on described substrate; also be included in described flip-chip top and form the solder bump that covers on described flip-chip and the described flip-chip or the protective layer of copper post, described protective layer exposes the top of described solder bump or copper post.
3. method as claimed in claim 2 is characterized in that, described protective layer is that macromolecular material is made.
4. method as claimed in claim 3 is characterized in that described macromolecular material comprises epoxide resin material.
5. method as claimed in claim 4; it is characterized in that; described epoxide resin material comprises under the room temperature and to be a kind of in the solid-state epoxide resin material under liquid epoxide resin material or the room temperature; form described protective layer for the method for liquid epoxide resin material by rotary coating or sputter under the described room temperature; make laminar film earlier for solid-state epoxide resin material under the described room temperature, the method by vacuum hotpressing forms described protective layer again.
6. as each described method of claim 1 to 5, it is characterized in that, also be included in and fill end filler between described flip-chip or described protective layer and the described substrate.
7. packaging, comprise substrate and flip-chip, be manufactured with a kind of in solder bump or the copper post on the described flip-chip, it is characterized in that, between described substrate and described flip-chip, also comprise solder bump or the superimposed soldered ball of copper post on the one or more and described flip-chip.
8. device as claimed in claim 7 is characterized in that, also comprises protective layer, and described protective layer covers described flip-chip and the solder bump on it or the surface of copper post, and described protective layer exposes the top of described solder bump or copper post.
9. device as claimed in claim 8 is characterized in that, described protective layer is the protective layer that macromolecular material is made.
10. as each described device of claim 7 to 9, it is characterized in that, also comprise packed layer, described packed layer is formed between described flip-chip or described protective layer and the described substrate.
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| CN 201110103595 CN102208358A (en) | 2011-04-25 | 2011-04-25 | Method for soldering flip chip on base plate and packaging apparatus |
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| CN 201110103595 CN102208358A (en) | 2011-04-25 | 2011-04-25 | Method for soldering flip chip on base plate and packaging apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102623414A (en) * | 2012-04-11 | 2012-08-01 | 日月光半导体制造股份有限公司 | Semiconductor package |
| CN103050465A (en) * | 2012-12-12 | 2013-04-17 | 华天科技（西安）有限公司 | Wafer-thinning single-chip encapsulation piece with copper pillars and manufacturing technology thereof |
| CN103094236A (en) * | 2012-12-28 | 2013-05-08 | 华天科技（西安）有限公司 | Single-chip package part with wafer thinned after bottom fillers cures and manufacture process thereof |
| CN104136364A (en) * | 2011-12-09 | 2014-11-05 | 罗伯特·博世有限公司 | Mems chip scale package |
| CN106145026A (en) * | 2016-06-30 | 2016-11-23 | 清华大学 | Air-tight packaging structure and method for packing for MEMS |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104136364A (en) * | 2011-12-09 | 2014-11-05 | 罗伯特·博世有限公司 | Mems chip scale package |
| CN102623414A (en) * | 2012-04-11 | 2012-08-01 | 日月光半导体制造股份有限公司 | Semiconductor package |
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| CN106145026B (en) * | 2016-06-30 | 2018-03-27 | 清华大学 | Air-tight packaging structure and method for packing for MEMS |
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Application publication date: 20111005 |