CN102244021B - Low-k chip encapsulating method - Google Patents
Low-k chip encapsulating method Download PDFInfo
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- CN102244021B CN102244021B CN2011102002578A CN201110200257A CN102244021B CN 102244021 B CN102244021 B CN 102244021B CN 2011102002578 A CN2011102002578 A CN 2011102002578A CN 201110200257 A CN201110200257 A CN 201110200257A CN 102244021 B CN102244021 B CN 102244021B
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
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Abstract
The invention relates to a Low-k chip encapsulating method, belonging to the technical field of chip encapsulation. The Low-k chip encapsulating method comprises the following technical processes of: preparing for a carrier wafer, attaching a layer of temporary stripping film on the carrier wafer, inversely installing a chip on the carrier wafer, attaching a thin film layer I (2-4) on the carrier wafer for carrying out encapsulation, bonding a supporting wafer (2-5) on the thin film layer I (2-4), finishing a wiring metal routing (2-6) on the thin film layer I (2-4), then forming a metal post (2-7) on the terminal of the wiring metal routing (2-6), attaching a thin film layer II (2-8) on the surface of the metal post (2-7) for encapsulation and curing, plating a metal layer (2-9) on the top end of the metal post (2-7); forming BGA (ball grid array) welded balls (2-10) on the metal layer (2-9) in a printing or ball attachment manner; and finally cutting reconstructed wafers forming the BGA welded balls into single BGA encapsulating bodies. The low-k chip encapsulating method is low in cost and can solve the problem that in the encapsulation process of the chip, the stress concentration results in the failure of the Low-k chip.
Description
Technical field
The present invention relates to a kind of Low-k chip packaging method, belong to the chip encapsulation technology field.
Background technology
In the semiconductor manufacturing, Moore's Law is the power that the spur industry advances always, and wherein Intel performs meritorious deeds never to be obliterated in this regard.The chips wire wide node mainly is divided into several stages: in 0.18 μ m stage, for metal-oxide-semiconductor begins to be the primary stage of manufacture of semiconductor fashionable the time, the size of the chip of manufacturing is relatively large; 0.13 the μ m stage, people are very confident to manufacture of semiconductor, post and wish to dwindle chip area and cost by reducing characteristic size; The micron system stage that this two stages are often said for us.Development along with nanometer technology, people's sight is far above in micron technology, begin manufacture of semiconductor advanced to nanoscale, the initial nanometer that occurs is the support of 90nm, but along with the exponential increase of number of die on the unit are according to Moore's Law, 65 nanometers have appearred in succession, 45 nanometers, 32 nanometers and 22 present nanometer technologies, the rapid reduction of this characteristic size, cause dielectric material to pursue low-dielectric loss constant (being commonly referred to Low-k), to reduce the dead resistance of circuit structure, electric capacity and inductance guarantee that simultaneously circuit has good insulation property.Usually, low-k materials be chosen as porous material, this causes material relatively crisp, in the situation that applied stress is easily cracked, causes line out of service.
Because low-K material is cracked characteristic easily, the packaging technology of chip need to be done the demand that corresponding lifting is used to adapt to product, adopt or common inverted structure or Bonding mode for the encapsulation of low k product at present, cause the encapsulation yield loss more, the dielectric layer that the structure of failure analysis is all pointed under the bonding electrode (Bonding and back bonding) is cracked.Present common settling mode is that wire bond package is encapsulated with back bonding, simultaneously before back bonding on substrate is put the end filler glue of illiquidity, this encapsulating structure and flow process such as Fig. 1, shown in Figure 2, the character of this filler glue of existing common end of end filler glue, the character that the backflow solder flux is also arranged, thereby can form wetting between soldered ball and the substrate weld pad, the benefit of the method is the problem that soldered ball stress causes the damage of chip internal dielectric layer when having improved common reverse installation process backflow, by filler glue at the bottom of the illiquidity stress that refluxes is redistributed, can not caused the chip inner layer dielectric layer to sustain damage because stress concentrates.But the disadvantage of this mode is the existence because of end filler glue causes the wetting action of solder flux not strong, and can't guarantee that each soldered ball is combined with pad well, and because existence and the reflux technique of solder flux easily causes the end filler glue cavity to occur in solidification process, and potting process is complicated, and cost is higher.
In sum, in the encapsulation process of Low-k chip, the problem that mainly contains two aspects that exists at present:
1, adopts Bonding and conventional reverse installation process, because technical process stress causes chip electrode place stress to be concentrated, and then break and understand easily cracked Low-K dielectric layer, cause chip failure;
2, filler mode reverse installation process exists failure welding and cured glue body hole defective at the bottom of the employing illiquidity, causes product reliability low.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of Low-k chip packaging method and encapsulating structure are provided, can solve the chip package process stress and concentrate and to cause Low-k chip failure problem, encapsulate cheaply solution for the encapsulation of Low-K chip provides.
The object of the present invention is achieved like this: a kind of Low-k chip packaging method, and described method comprises following technical process:
Step 1, get a Low-k disk, this Low-k disk is cut into single chips;
Step 2, preparation a slice carrier disk form the contraposition sign by photolithographicallpatterned on the carrier disk, finish the pattern layout on the carrier disk;
Step 3, stick the interim stripping film of one deck at the carrier disk, single chips that step 1 is cut into one by one upside-down mounting is finished flip-chip posting on the carrier disk of interim stripping film;
Step 4, stick thin layer I at the carrier disk of finishing flip-chip and seal, will support wafer bonding in encapsulation process to thin layer I, cured film layer I then forms by chip, thin layer I and supports the reconstruct wafer that disk forms;
Step 5, above-mentioned reconstruct wafer and carrier disk are peeled off, and the chip surface of reconstruct wafer is cleaned up the exposed chip electrode;
Step 6, finish again wiring metal cabling of single or multiple lift by modes such as photoetching, sputter or plating at thin layer I and chip surface, by wiring metal cabling again chip electrode is guided to the chip neighboring area;
Step 7, form metal column in the terminal of the again wiring metal cabling of the finishing mode by photoetching or plating;
Step 8, stick thin layer II at the reconstruct crystal column surface that forms metal column and seal and solidify, then the mode of utilizing laser ablation etches away the thin-film material on metal column top, form the complete or part opening of metal column, make the metal column top expose thin layer II;
Step 9, plate metal level on the metal column top of exposing thin layer II;
Step 10, form the BGA soldered ball by printing or the mode of planting ball at described metal level, the reconstruct wafer that will form at last the BGA soldered ball cuts into single BGA packaging body.
Described metal column adopts the conducting metals such as copper, nickel, and its height is between 50 μ m ~ 100 μ m.
Described metal level is multiple layer metal, and its structure is Ni/Au or Ni/Pd/Au, and the thickness of metal level is no more than 5 μ m.
Described thin layer I and thin layer II adopt the non-photosensitivity material.
Described support disk is silicon chip or sheet metal.
Described carrier disk adopts silicon substrate or glass baseplate.
Compared with prior art, the invention has the beneficial effects as follows:
1, with the direct upside-down mounting of chip on the carrier disk, do not experience reflux course, unstressed concentrated experience has solved in the present Low-k chip BGA encapsulation reverse installation process process stress and has concentrated the problem that causes chip failure;
2, utilized the technique of wafer level that chip electrode is extended down to non-chip region outside connecting up again, the BGA structure is mounted the stress transfer that process produces, chip area is in the state of not stressing;
3, utilize metal column technology and structure, realize high-power current-carrying and electric current uniform distribution, utilize simultaneously the height of copper post, buffering makes it not arrive again wiring layer from the stress of BGA soldered ball.
4, in conjunction with wafer level packaging technique and metal column technique, when realizing Low-k chip high reliability packaging, can also realize the cost degradation that encapsulates;
5, utilize the film Filming Technology to replace existing wrapper technology, reduced the requirement of packaging technology to equipment;
6, integrate bump process, reverse installation process and substrate process, realized the wafer manufacturing process of BGA encapsulation.
Description of drawings
Fig. 1 is the schematic diagram of present Low-k chip-packaging structure.
Fig. 2 is the packaging technology flow chart of present Low-k chip-packaging structure.
Fig. 3 is the schematic diagram of Low-k chip-packaging structure of the present invention.
Fig. 4 is the packaging technology flow chart of Low-k chip-packaging structure of the present invention.
Wherein:
Chip body 1-1
Chip electrode 1-2
Surface passivation layer 1-3
Ubm layer 1-4
Solder bumps 1-5
Substrate 1-6
Substrate pads I1-7
Low sizing glue 1-8
Substrate pads II1-9
BGA soldered ball 1-10
Chip body 2-1
Chip electrode 2-2
Chip surface passivation layer 2-3
Thin layer I2-4
Support disk 2-5
Wiring metal cabling 2-6 again
Metal column 2-7
Thin layer II2-8
Metal level 2-9
Soldered ball 2-10.
Embodiment
Referring to Fig. 3 ~ 4, a kind of Low-k chip-packaging structure of the present invention, it comprises chip body 2-1, chip electrode 2-2 and chip surface passivation layer 2-3, described chip body 2-1 is coated with thin layer I2-4, described thin layer I2-4 back side bonding is provided with and supports disk 2-5, described chip electrode 2-2 is transferred on the outer thin layer I2-4 of chip periphery via wiring metal cabling 2-6 again, be provided with metal column 2-7 in the terminal of wiring metal cabling 2-6 again, described metal column 2-7 is coated with thin layer II2-8, metal column 2-7 exposes thin layer II2-8 in the top, be provided with metal level 2-9 on the metal column 2-7 top of exposing, be provided with soldered ball 2-10 on the described metal level 2-9.
The implementation procedure of Low-k chip-packaging structure of the present invention is as follows:
Step 1, get a Low-k disk, this Low-k disk is cut into single chips.
Step 2, preparation a slice carrier disk form the contraposition sign by photolithographicallpatterned on the carrier disk, finish the pattern layout on the carrier disk.
Described carrier disk can be selected silicon substrate or glass baseplate, and convenient follow-up flip-chip when forming the purpose of contraposition sign can guarantee in desirable position chip.
Step 3, stick the interim stripping film of one deck at the carrier disk, single chips that step 1 is cut into one by one upside-down mounting is posting on the carrier disk of interim stripping film.
Described interim stripping film is two-sided all to have viscosity, can with the carrier disk be connected the chip of upside-down mounting and form and to be connected preferably, this stripping film is that hot soarfing is from attribute or UV photospallation attribute, if be UV photospallation attribute, need to use the carrier disk of glass baseplate or quartz substrate, shine because the UV photospallation need to use UV, therefore need select transparent base to realize seeing through of UV light.
Chip selects upside-down mounting that two purposes are arranged, and is in order to guarantee the different-thickness chip in follow-up technique chips front at grade on the one hand, is chip front side glue-free covering on the reconstruct wafer on the other hand, conveniently to carry out follow-up technique.
Step 4, stick thin layer I2-4 at the carrier disk of finishing flip-chip and seal, to support disk 2-5 in encapsulation process is bonded on the thin layer I2-4, then cured film layer I2-4 forms the reconstruct wafer that is comprised of chip, thin layer I2-4 and support disk 2-5.
Described support disk 2-5 is silicon chip or sheet metal, utilizes thin layer I2-4 good flowability under heating state when sealing, and has guaranteed the planarization of disk surfaces.
Step 5, utilize UV irradiation or hot soarfing from mode above-mentioned reconstruct wafer and carrier disk are peeled off, and the chip surface of reconstruct wafer is cleaned up exposed chip electrode 2-2.
The modes such as step 6, the photoetching by wafer level technique, sputter or plating are finished again wiring metal cabling 2-6 of single or multiple lift at thin layer I2-4 and chip surface, by wiring metal cabling 2-6 again chip electrode 2-2 are guided to chip neighboring area (not containing chip area).
Step 7, form metal column 2-7 in the terminal of the again wiring metal cabling 2-6 that the finishes mode by photoetching or plating.
Described metal column 2-7 is the conducting metals such as copper, nickel, and the height of metal column 2-7 can be regulated according to topology requirement, and height should be not less than 50 μ m, usually between 50 μ m ~ 100 μ m.Metal column 2-7 has effect aspect two at this, and the one, reduce current-crowding effect, can be with balanced current distribution, thus reduce the generation of ELECTROMIGRATION PHENOMENON; On the other hand, utilize the height buffering of metal column 2-7 from the stress of soldered ball 2-10, thus protection Low-k chip.
Step 8: stick thin layer II2-8 at the reconstruct crystal column surface that forms metal column 2-7 and seal and solidify, then the mode of utilizing laser ablation etches away the thin-film material on metal column top, form the complete or part opening of metal column 2-7, make the metal column top expose thin layer II2-8.
Described thin layer I2-4 and thin layer II2-8 are non-photosensitivity insulation resin class material.
Step 9, plate metal level 2-9 on the metal column 2-7 top of exposing thin layer II2-8.
Described metal level 2-9 is the single or multiple lift metal, and common structure is Ni/Au or Ni/Pd/Au, and the thickness of metal level 2-9 should not surpass 5 μ m, stops tin in the scolder and the phase counterdiffusion between the copper during its purpose, the reliability of improving product.
Step 10, form BGA soldered ball 2-10 by printing or the mode of planting ball at described metal level 2-9, the reconstruct wafer that will form at last the BGA soldered ball cuts into single BGA packaging body.
Claims (8)
1. Low-k chip packaging method, it is characterized in that: described method comprises following technical process:
Step 1, get a Low-k disk, this Low-k disk is cut into single chips;
Step 2, preparation a slice carrier disk form the contraposition sign by photolithographicallpatterned on the carrier disk, finish the pattern layout on the carrier disk;
Step 3, stick the interim stripping film of one deck at the carrier disk, single chips that step 1 is cut into one by one upside-down mounting is finished flip-chip posting on the carrier disk of interim stripping film;
Step 4, stick thin layer I(2-4 at the carrier disk of finishing flip-chip) seal, in encapsulation process, will support disk (2-5) and be bonded to thin layer I(2-4) on, then cured film layer I(2-4), form by chip, thin layer I(2-4) and the reconstruct wafer that forms of support disk (2-5);
Step 5, above-mentioned reconstruct wafer and carrier disk are peeled off, and the chip surface of reconstruct wafer is cleaned up exposed chip electrode (2-2);
Step 6, by photoetching, sputter and plating mode at thin layer I(2-4) and chip surface finish again wiring metal cabling (2-6) of single or multiple lift, by wiring metal cabling (2-6) again chip electrode (2-2) is guided to the chip neighboring area;
Step 7, form metal column (2-7) in the terminal of the again wiring metal cabling (2-6) of the finishing mode by photoetching and plating;
Step 8, stick thin layer II(2-8 at the reconstruct crystal column surface that forms metal column (2-7)) seal and solidify, then the mode of utilizing laser ablation etches away the thin-film material on metal column top, form the complete or part opening of metal column (2-7), make metal column (2-7) top expose thin layer II(2-8);
Step 9, exposing thin layer II(2-8) metal column (2-7) plated surface on metal level (2-9);
Step 10, by printing or the mode of planting ball at described metal level (2-9) formation BGA soldered ball (2-10), the reconstruct wafer that will form at last the BGA soldered ball cuts into single BGA packaging body.
2. a kind of Low-k chip packaging method according to claim 1 is characterized in that: chip body (2-1) is when upside-down mounting is to the carrier disk and without salient point.
3. a kind of Low-k chip packaging method according to claim 1 is characterized in that: chip electrode (2-2) by wafer scale again the mode of Wiring technique be directed to the periphery of packaging body.
4. a kind of Low-k chip packaging method according to claim 1 is characterized in that: described thin layer I(2-4) and thin layer II(2-8) adopt the mode of pad pasting to adhere on the disk.
5. a kind of Low-k chip packaging method according to claim 1 is characterized in that: described thin layer I(2-4) and thin layer II(2-8) adopt the mode opening of laser ablation.
6. a kind of Low-k chip packaging method according to claim 1 is characterized in that: described metal column (2-7) is that the mode by photoetching, sputter, plating forms.
7. a kind of Low-k chip packaging method according to claim 1 is characterized in that: described metal level (2-9) is that the mode by chemical plating forms.
8. a kind of Low-k chip packaging method according to claim 1 is characterized in that: peeling off of carrier disk and reconstruct wafer can be adopted hot stripping method or UV irradiation stripping method.
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| CN2011102002578A CN102244021B (en) | 2011-07-18 | 2011-07-18 | Low-k chip encapsulating method |
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| CN2011102002578A CN102244021B (en) | 2011-07-18 | 2011-07-18 | Low-k chip encapsulating method |
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| CN117238781B (en) * | 2023-11-16 | 2024-02-23 | 江苏芯德半导体科技有限公司 | Wafer-level ultrathin four-side pin-free chip packaging method and chip packaging structure |
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| US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
| JP3929966B2 (en) * | 2003-11-25 | 2007-06-13 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP5039384B2 (en) * | 2004-12-03 | 2012-10-03 | ローム株式会社 | Semiconductor device |
| US20080085572A1 (en) * | 2006-10-05 | 2008-04-10 | Advanced Chip Engineering Technology Inc. | Semiconductor packaging method by using large panel size |
| CN101425469A (en) * | 2007-10-30 | 2009-05-06 | 育霈科技股份有限公司 | Semi-conductor packaging method using large size panel |
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