CN208608186U - Chip-packaging structure - Google Patents
Chip-packaging structure Download PDFInfo
- Publication number
- CN208608186U CN208608186U CN201821165747.2U CN201821165747U CN208608186U CN 208608186 U CN208608186 U CN 208608186U CN 201821165747 U CN201821165747 U CN 201821165747U CN 208608186 U CN208608186 U CN 208608186U
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- chip
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- dao
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Abstract
The utility model provides a kind of chip-packaging structure, comprising: a lead frame, the lead frame have an at least Ji Dao and an at least pin；An at least chip is arranged on the Ji Dao, and the back side of each chip is connect with the loading end of the Ji Dao, and multiple conductive bumps connecting with the weld pad of chip are provided on the active face of each chip；An at least conductive column is arranged in the pin upper surface；At least one reroutes layer, connect respectively with the conductive bump and the conductive column, the weld pad of the chip is connected to the pin.The utility model has the advantage of, the utility model chip-packaging structure is radiated by Ji Dao, the chip passes through conductive bump, rewiring layer and conductive column connection and pin, with high thermal conductivity and good electric conductivity, adapt to the chip package and modularized encapsulation of the highly conductive demand of high-power and high thermal conductivity, the electrical and thermal conductivity performance of chip package can greatly be optimized, effectively promote the service performance of chip.
Description
Technical field
The utility model relates to field of semiconductor package more particularly to a kind of chip-packaging structures.
Background technique
In IC package industry, Wire Bonding Technology (Wire Bonding, abbreviation WB) using metal wire realize chip with
Exposed pin connection conducting, its shortcoming is that, packaging body is limited to the diameter and length of metal wire itself, core in terms of electrical property
The electric conductivity of piece is poor.
Flip-chip welding technology (Flip Chip Bonding Technology, abbreviation FC) is a kind of to be connected to chip
Multiple chip mats are configured on the active surface of chip by the encapsulation technology of carrier mainly in the way of the array of face,
And convex block is formed on chip mat, then by chip turn-over and then via these convex blocks, these chip mats of chip are distinguished
Contact on electricity and structural connectivity to carrier.Since flip-chip welding technology is applicable to the chip package knot of high pin count
Structure, and there is many advantages, such as reducing chip package area and shortening signal transmission path simultaneously, so that flip-chip welding technology
The chip package field of high-order is had been widely used at present.Its shortcoming is that since chip is by convex block or weight cloth
The modes such as line layer are connect with exposed pin, and there are the filling and isolation of plastic packaging layer in centre, so that the heating conduction of chip is poor.
Therefore, develop a kind of encapsulating structure with excellent conductive performance and heating conduction to be of great significance.
Utility model content
Technical problem to be solved by the utility model is to provide a kind of chip-packaging structures, can have high thermal conductivity
Performance and good electric conductivity adapt to the chip package and modularized encapsulation of the highly conductive demand of high-power and high thermal conductivity, can
The greatly electrical and thermal conductivity performance of optimization chip package, effectively promotes the service performance of chip.
To solve the above-mentioned problems, the utility model provides a kind of chip-packaging structure, comprising: a lead frame, institute
Lead frame is stated with an at least Ji Dao and an at least pin；An at least chip is arranged on the Ji Dao, the back of each chip
Face is connect with the loading end of the Ji Dao, and multiple conductive studs connecting with the weld pad of chip are provided on the active face of each chip
Block；An at least conductive column is arranged in the pin upper surface；At least one reroutes layer, respectively with the conductive bump and described
Conductive column connection, is connected to the pin for the weld pad of the chip.
In one embodiment, the chip is connect with the loading end of the Ji Dao by conductive and heat-conductive adhesive layer.
In one embodiment, the Ji Dao is conductive base island.
In one embodiment, the back side Ji Dao opposite with loading end is provided with external pin.
In one embodiment, it is connected between adjacent rewiring layer by conducting block.
The utility model has the advantage of the utility model chip-packaging structure is radiated by Ji Dao, and the chip passes through
Conductive bump reroutes layer and conductive column connection and pin, has high thermal conductivity and good electric conductivity, adapts to high-power
With the chip package and modularized encapsulation of the highly conductive demand of high thermal conductivity, it can greatly optimize the electrical and thermal conductivity performance of chip package,
Effectively promote the service performance of chip.
Detailed description of the invention
Fig. 1 is the schematic diagram of the first embodiment of the utility model chip-packaging structure；
Fig. 2 is the schematic diagram of the second embodiment of the utility model chip-packaging structure；
Fig. 3 A~Fig. 3 H is the process flow chart of an embodiment of the utility model preparation method；
Fig. 4 is a flow chart of another embodiment of the utility model preparation method；
Fig. 5 A~Fig. 5 C is a flow chart of another embodiment of the utility model preparation method；
Fig. 6 A~Fig. 6 C is a flow chart of another embodiment of the utility model preparation method.
Specific embodiment
It elaborates with reference to the accompanying drawing to the specific embodiment of chip-packaging structure provided by the utility model.
The utility model provides a kind of chip-packaging structure.Fig. 1 is the first implementation of the utility model chip-packaging structure
The schematic diagram of example.Referring to Fig. 1, the chip-packaging structure includes: a lead frame 1, at least a chip 2, at least one conduction
Column 3 and at least one rewiring layer 4.
The lead frame 1 has an at least base island 10 and an at least pin 11.In the present embodiment, it is schematically painted
The island Chu Yigeji 10 and two pins 11, described two pins 11 are located at the two sides on base island 10.
Wherein, in the present embodiment, at the back side on the base island 10, i.e., opposite with the loading end on the base island 10 one
Face is provided with an external pin 12, is also equipped with external pin 12 in the lower surface of the pin 11, the external pin 12 be used for it is outer
The electrical connection of portion's structure.Certainly, in other embodiments, can also the island Jin Ji 10 the back side be arranged external pin 12.
Further, the base island 10 is conductive base island, such as copper-based island, and the pin 11 is conductive pin, such as copper draws
Foot.
The chip 2 is arranged on the base island 10.The utility model to the quantity of the chip 2 without limiting, can
It is selected according to actual use.In the present embodiment, the quantity of the chip 2 is one.
The back side of each chip 2 is connect with the loading end on the base island 10, and the back side of the chip 2 can pass through conductive and heat-conductive
Adhesive layer 20 is connect with the loading end on the base island 10.The material of the conductive and heat-conductive adhesive layer includes but is not limited to glue
Water, metal or metal mixture, such as silver paste etc..The back side of the chip 2 is connect with the loading end on the base island 10, is increased
The heat dissipation area of the chip 2 improves the heat dissipation performance of the chip 2.
Multiple conductive studs connecting with the weld pad (not being painted in attached drawing) of chip 2 are provided on the active face of each chip 2
Block 21.The conductive bump 21 can be used metal material and be made, for example, copper product.It is described to lead compared with traditional metal lead wire
Electric convex block 21 increases the area that the weld pad is connect with the external world, improves the electric conductivity of chip.
The conductive column 3 is arranged in 11 upper surface of pin.The conductive column 3 includes but is not limited to metallic conduction post.
The conductive column 3 is conducted with the pin 11.
The rewiring layer 4 is connect with the conductive bump 21 and the conductive column 3 respectively, by the weldering of the chip 2
Pad is connected to the pin 11.In the present embodiment, the chip-packaging structure includes one layer of rewiring layer, which reroutes layer
For patterned conductive layer, each conductive bump 21 is connect with a conductive column 3, so that each conductive bump 21 draws with one
Foot 11 connects.The chip 2 is electrically connected by conductive bump 21, rewiring layer 4, conductive column 3 with the pin 11 realization, energy
Existing metal lead wire is enough avoided to connect the bad disadvantage of brought electric conductivity.
Further, the chip-packaging structure further includes a plastic-sealed body 5, lead frame 1 described in 5 plastic packaging of plastic-sealed body,
Chip 2, conductive column 3 and rewiring layer 4.The plastic-sealed body 5 is made of the material of this field routine.
The utility model also provides a kind of second embodiment of chip-packaging structure.Fig. 2 is the utility model chip package
The schematic diagram of structure second embodiment.Referring to Fig. 2, the difference of the present embodiment and first embodiment is, the chip package
Structure includes two layers of rewiring layer 4, i.e., first reroutes layer 40 and the second rewiring layer 41.Described first reroutes layer 40 and leads
Electric convex block 21 and partially electronically conductive column 3 connect, and described second reroutes layer 41 connects with the first rewiring layer 40 and partially electronically conductive column 3
It connects, and then realizes that each conductive bump 21 is connect with the electrical connection of pin 11.Described first reroutes layer 40 and described the
Double wiring layer 41 is graphical, to realize connection.Wherein, it is connected between adjacent rewiring layer by conducting block 42, for example,
It is connected between the first rewiring layer 40 and the second rewiring layer 41 by conducting block 42.The conducting block 42 include but
It is not limited to metal block.In the utility model other embodiments, the rewiring layer 4 can be set as needed it is multiple, using phase
Same method can form multilayer and reroute layer.
Wherein, in this second embodiment, the back side on the base island 10 and the back side of the pin 11 and not set outer tube
The back side of foot, the back side of the Ji Dao and the pin is used directly as external pin.
The preparation method of said chip encapsulating structure includes the following steps:
Fig. 3 A is please referred to, a lead frame 1 is provided, the lead frame 1 has at least a base island 10 and at least a pin
11.In the present embodiment, an island Ge Ji 10 and two pins 11 are schematically shown, described two pins 11 are located at base
The two sides on island 10.Wherein, in the present embodiment, the lead frame 1 further includes a supporting layer 13, and the setting of supporting layer 13 exists
The back side of the lead frame 1 is used to support the lead frame 1.In another embodiment, as shown in figure 4, the base island 10
The back side opposite with loading end is provided with external pin 12, and the back side of the pin 11 is also equipped with external pin 12, the supporting layer
13 are arranged except the external pin 12.Wherein, the forming method of the lead frame 1 can be to be formed on supporting layer 13
Metal layer, the graphical metal layer form lead frame, wherein multi-layer graphical figure layer can be formed, so as to formed by
The lead frame that more metal layers are formed, wherein one layer can be used as Ji Dao and pin, wherein another layer can be used as outer limb.
Fig. 3 B is please referred to, an at least chip 2 is provided.Conductive bump 21 is formed on the active face of each chip 2, it is described to lead
The weld pad (not being painted in attached drawing) of each chip 2 of electric convex block 21 connects.In the present embodiment, the quantity of the chip 2 is one.
The conductive bump 21 can be used metal material and be made, for example, copper product.
Fig. 3 C is please referred to, a conductive column 3 is formed, the conductive column 3 is arranged in 11 upper surface of pin.In the present embodiment
In, conductive column 3 is formed on the surface of the pin 11, wherein the side of patterned metal layer can be used in the formation of the conductive column 3
Method is formed, and is the prior art, is repeated no more.The conductive column 2 includes but is not limited to metallic conduction post.The conductive column 3 with
The pin 11 conducts.
Fig. 3 D is please referred to, the chip 2 is welded on the loading end on the base island 10.The chip 2 it is active towards
On, the back side opposite with the active face is connect with the loading end on the base island 10, i.e., the described chip 2 is provided with conductive bump 21
One face upward.The chip 2 is connect by conductive and heat-conductive adhesive layer 20 with the loading end on the base island 10.The conduction is led
The material of hot adhesion oxidant layer includes but is not limited to glue, metal or metal mixture, such as silver paste etc..The back side of the chip 2
It is connect with the loading end on the base island 10, increases the heat dissipation area of the chip 2, improve the heat dissipation performance of the chip 2.
Fig. 3 E is please referred to, forms plastic-sealed body 50, and expose the upper surface of conductive bump 21 and the upper surface of conductive column 3.
Wherein, in plastic packaging, plastic packaging material can cover the upper surface of the conductive bump 21 and the upper surface of conductive column 3, complete in plastic packaging
Afterwards, the method that grinding or etching can be used removes the plastic packaging material of the upper surface of the conductive bump 21 and the upper surface of conductive column 3,
So that the upper surface of conductive bump 21 and the upper surface of conductive column 3 are exposed to the plastic-sealed body 50.Alternatively, in plastic packaging,
The plastic packaging material does not cover the upper surface of the conductive bump 21 and the upper surface of conductive column 3 directly, thus be omitted grinding or
The step of etching.
In another embodiment of the utility model preparation method, after the step of providing a chip shown in Fig. 3 B,
Fig. 5 A is please referred to, the chip 2 is welded on the loading end on the base island 10；Fig. 5 B is please referred to, plastic packaging is carried out, forms plastic packaging
Body 50, and expose the upper surface of 11 upper surface of pin and conductive bump 21；Fig. 5 C is please referred to, is formed in the upper surface of pin 11
Conductive column 3, the upper surface of the conductive column 3 are exposed to the plastic-sealed body 50.Wherein, structure shown in Fig. 5 C is formed, can be used
Following method: through-hole is formed on the surface of the plastic-sealed body, the through-hole exposes the upper surface of pin, fills and lead in through-hole
Electric material, to form conductive column, the upper surface of the conductive column is exposed to plastic-sealed body.
Please continue to refer to Fig. 3 F, forms at least one and reroute layer.In the present embodiment, one layer of rewiring layer 4 is formed.It is described
It is graphical to reroute layer 4, is connect respectively with conductive bump 21 and conductive column 3, so that the weld pad of chip and pin 11 are electrically connected
It connects.The forming method for rerouting layer 4 includes but is not limited to the method for using patterned metal layer.
Please refer to Fig. 3 G, plastic packaging.In this step, 4 plastic packaging of rewiring layer is formed by the core using plastic packaging material 51
Chip package.The plastic package method is the conventional method of this field.
In other embodiments, multilayer can be formed and reroute layer.The step of then forming multiple wiring layer includes: to please refer to
Fig. 6 A forms one first and reroutes layer 40, described first reroutes layer 40 and the conductive bump after forming plastic-sealed body 50
21 and partially electronically conductive column 3 connect, formed it is described first reroute layer 40 the step of with above-mentioned formation rewiring layer the step of it is identical,
It has been described above, details are not described herein again；Fig. 6 B, plastic packaging are please referred to, and forms one second on plastic-sealed body 60 and reroutes layer
41, the second rewiring layer 41 is connect by an at least conducting block 42 with the first rewiring layer 40 and partially electronically conductive column 3,
And then it connect each conductive bump 42 with pin 11；Fig. 6 C is please referred to, is rerouted using described in 70 plastic packaging of plastic packaging material second
Layer 41 forms the utility model chip-packaging structure.In other embodiments, and so on, multiple rewiring layers are formed, so that
Each conductive bump 21 is connect with a pin 11.
Fig. 3 H is please referred to, after plastic packaging step, further includes the steps that the removal supporting layer 13, so far, forms this
Utility model chip-packaging structure.
The above is only the preferred embodiment of the utility model, it is noted that for the common skill of the art
Art personnel can also make several improvements and modifications without departing from the principle of this utility model, these improvements and modifications
Also it should be regarded as the protection scope of the utility model.
Claims (5)
1. a kind of chip-packaging structure characterized by comprising
One lead frame, the lead frame have an at least Ji Dao and an at least pin；
An at least chip is arranged on the Ji Dao, and the back side of each chip is connect with the loading end of the Ji Dao, each chip
Active face on be provided with multiple conductive bumps connecting with the weld pad of chip；
An at least conductive column is arranged in the pin upper surface；
At least one reroutes layer, connect respectively with the conductive bump and the conductive column, and the weld pad of the chip is connected
To the pin.
2. chip-packaging structure according to claim 1, which is characterized in that the loading end of the chip and the Ji Dao are logical
Cross the connection of conductive and heat-conductive adhesive layer.
3. chip-packaging structure according to claim 1, which is characterized in that the Ji Dao is conductive base island.
4. chip-packaging structure according to claim 1, which is characterized in that the back side Ji Dao opposite with loading end is set
It is equipped with external pin.
5. chip-packaging structure according to claim 1, which is characterized in that pass through conducting block between adjacent rewiring layer
Connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821165747.2U CN208608186U (en) | 2018-07-20 | 2018-07-20 | Chip-packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821165747.2U CN208608186U (en) | 2018-07-20 | 2018-07-20 | Chip-packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208608186U true CN208608186U (en) | 2019-03-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201821165747.2U Active CN208608186U (en) | 2018-07-20 | 2018-07-20 | Chip-packaging structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878297A (en) * | 2018-07-20 | 2018-11-23 | 合肥矽迈微电子科技有限公司 | Chip-packaging structure and preparation method thereof |
| US11239141B2 (en) | 2020-07-03 | 2022-02-01 | Industrial Technology Research Institute | Lead frame package |
-
2018
- 2018-07-20 CN CN201821165747.2U patent/CN208608186U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878297A (en) * | 2018-07-20 | 2018-11-23 | 合肥矽迈微电子科技有限公司 | Chip-packaging structure and preparation method thereof |
| US11239141B2 (en) | 2020-07-03 | 2022-02-01 | Industrial Technology Research Institute | Lead frame package |
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