JP4777692B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4777692B2
JP4777692B2 JP2005165800A JP2005165800A JP4777692B2 JP 4777692 B2 JP4777692 B2 JP 4777692B2 JP 2005165800 A JP2005165800 A JP 2005165800A JP 2005165800 A JP2005165800 A JP 2005165800A JP 4777692 B2 JP4777692 B2 JP 4777692B2
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semiconductor device
semiconductor chip
island
resin substrate
semiconductor
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JP2006339595A (en
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泰正 糟谷
基治 芳我
弘招 松原
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2005165800A priority Critical patent/JP4777692B2/en
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to CN200680013260.6A priority patent/CN101164162B/en
Priority to CN201010162179A priority patent/CN101834167A/en
Priority to US11/887,103 priority patent/US20090051049A1/en
Priority to KR20077023933A priority patent/KR20080013865A/en
Priority to PCT/JP2006/311014 priority patent/WO2006132130A1/en
Priority to TW095120053A priority patent/TW200735293A/en
Publication of JP2006339595A publication Critical patent/JP2006339595A/en
Priority to US13/036,869 priority patent/US8810016B2/en
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Publication of JP4777692B2 publication Critical patent/JP4777692B2/en
Priority to US14/322,461 priority patent/US9520374B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29499—Shape or distribution of the fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

In a semiconductor device, a semiconductor chip is prevented from being damaged, even when a solder bonding material is used for bonding the rear plane of the semiconductor chip with a bonding plane of a chip bonding section such as an island and a die pad. The semiconductor device includes the semiconductor chip, and the chip bonding section having a bonding plane whereupon the rear plane of thesemiconductor chip is bonded through the solder bonding material. The area of the bonding plane is smaller than that of the rear plane of the semiconductor chip. Furthermore, the semiconductor devicepreferably includes a plurality of extending sections which extend in a direction parallel to the bonding plane from the periphery of the bonding plane.

Description

この発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

表面実装型パッケージの代表的なものとして、たとえば、ＢＧＡ（Ball Grid Array）が知られている。
図４は、ＢＧＡが採用された半導体装置の構成を示す図解的な断面図である。この半導体装置は、半導体チップ１０１と、半導体チップ１０１が搭載されるインタポーザ１０２と、半導体チップ１０１およびインタポーザ１０２の半導体チップ１０１に対向する面を封止する封止樹脂１０３とを備えている。 For example, BGA (Ball Grid Array) is known as a representative surface mount package.
FIG. 4 is a schematic cross-sectional view showing a configuration of a semiconductor device employing a BGA. The semiconductor device includes a semiconductor chip 101, an interposer 102 on which the semiconductor chip 101 is mounted, and a sealing resin 103 that seals the semiconductor chip 101 and a surface of the interposer 102 that faces the semiconductor chip 101.

インタポーザ１０２は、絶縁性樹脂からなる樹脂基板１０４を基体とし、その樹脂基板１０４の一方面に、アイランド１０５および複数の内部端子１０６を備えている。アイランド１０５は、平面視において、半導体チップ１０１よりも大きなサイズを有する略矩形状に形成されている。このアイランド１０５には、半導体チップ１０１の裏面が接合剤１０７を介して接合される。複数の内部端子１０６は、アイランド１０５の周囲に配置されており、アイランド１０５に接合された半導体チップ１０１の表面上の電極パッド（図示せず）とボンディングワイヤ１０８によって電気的に接続される。また、樹脂基板１０４の他方面には、実装基板（プリント配線板）上のランドとの電気接続のための複数のボール状の外部端子１０９が整列して配置されている。そして、樹脂基板１０４の一方面上の内部端子１０６と他方面上の外部端子１０９とは、樹脂基板１０４の一方面と他方面との間を貫通するスルーホール（図示せず）内に設けられた金属を介して電気的に接続されている。
特開２００１−１８１５６３号公報 The interposer 102 includes a resin substrate 104 made of an insulating resin as a base, and includes an island 105 and a plurality of internal terminals 106 on one surface of the resin substrate 104. The island 105 is formed in a substantially rectangular shape having a size larger than that of the semiconductor chip 101 in plan view. The back surface of the semiconductor chip 101 is bonded to the island 105 via a bonding agent 107. The plurality of internal terminals 106 are arranged around the island 105, and are electrically connected to electrode pads (not shown) on the surface of the semiconductor chip 101 bonded to the island 105 by bonding wires 108. A plurality of ball-shaped external terminals 109 for electrical connection with lands on the mounting substrate (printed wiring board) are arranged on the other surface of the resin substrate 104 in an aligned manner. The internal terminal 106 on one surface of the resin substrate 104 and the external terminal 109 on the other surface are provided in a through hole (not shown) penetrating between the one surface and the other surface of the resin substrate 104. Are electrically connected via metal.
JP 2001-181563 A

このような半導体装置では、半導体チップ１０１をアイランド１０５に接合させるための接合剤１０７として、エポキシ樹脂系接着剤や銀ペースト、絶縁ペーストを用いるのが一般的であり、現在のところ、はんだ接合剤を用いたものは提供されていない。
たとえば、パワーＩＣが作り込まれた半導体チップは、その裏面（半導体基板の裏面）をグランドとして動作する。そのため、図４に示す半導体チップ１０１としてパワーＩＣが作り込まれた半導体チップが備えられる場合、アイランド１０５と外部端子１０９とを電気的に接続するとともに、導電性を有する接合剤１０７を用いて、半導体チップ１０１の裏面をアイランド１０５に接合させなければならない。ところが、接合剤１０７としてはんだ接合剤を用いた場合、半導体装置の温度が急激に変化したときや、高温下での接合後の温度低下時に、接合剤１０７から半導体チップ１０１の裏面側の周縁部に応力が加わり、その周縁部にクラックなどの損傷を生じるおそれがある。たとえば、はんだ接合剤を接合剤１０７に用いた場合、リフローが必須となり、そのリフロー後の冷却時に、インタポーザ１０２（樹脂基板１０４）と半導体チップ１０１とに熱収縮量の差が生じ、この熱収縮量の差による応力が接合剤１０７から半導体チップ１０１の裏面側の周縁部に伝達される。 In such a semiconductor device, an epoxy resin adhesive, silver paste, or insulating paste is generally used as the bonding agent 107 for bonding the semiconductor chip 101 to the island 105. At present, a solder bonding agent is used. Those using are not provided.
For example, a semiconductor chip in which a power IC is built operates with its back surface (back surface of the semiconductor substrate) as the ground. Therefore, when a semiconductor chip in which a power IC is built as the semiconductor chip 101 shown in FIG. 4 is provided, the island 105 and the external terminal 109 are electrically connected, and a conductive bonding agent 107 is used. The back surface of the semiconductor chip 101 must be bonded to the island 105. However, when a solder bonding agent is used as the bonding agent 107, when the temperature of the semiconductor device changes abruptly or when the temperature decreases after bonding at a high temperature, the peripheral portion on the back side of the semiconductor chip 101 from the bonding agent 107 There is a risk that stress will be applied to the surface and damage such as cracks may occur at the peripheral edge. For example, when a solder bonding agent is used as the bonding agent 107, reflow is indispensable, and during the cooling after the reflow, a difference in heat shrinkage occurs between the interposer 102 (resin substrate 104) and the semiconductor chip 101. Stress due to the difference in amount is transmitted from the bonding agent 107 to the peripheral portion on the back surface side of the semiconductor chip 101.

このような問題は、はんだ接合剤を用いて、半導体チップを比較的肉厚の小さなリードフレームのダイパッドに接合する場合にも生じる。
この発明の目的は、半導体チップの裏面をアイランドやダイパッドなどのチップ接合部の接合面に接合させるためにはんだ接合剤を用いても、半導体チップの損傷の発生を防止することができる半導体装置を提供することである。 Such a problem also occurs when a semiconductor chip is bonded to a die pad of a lead frame having a relatively small thickness using a solder bonding agent.
An object of the present invention is to provide a semiconductor device capable of preventing the occurrence of damage to a semiconductor chip even when a solder bonding agent is used to bond the back surface of the semiconductor chip to a bonding surface of a chip bonding portion such as an island or a die pad. Is to provide.

上記の目的を達成するための請求項１記載の発明は、半導体装置において、平面視矩形の半導体チップと、樹脂基板と、前記樹脂基板の一方面に形成された平面視矩形状のアイランドと、前記樹脂基板の一方面において前記アイランドの四隅から延出するように前記アイランドと一体的に形成された延出部と、前記アイランドと前記半導体チップの裏面とを接合する接合剤とを含み、平面視において前記延出部が前記樹脂基板の周縁に達しない位置まで延出しており、前記半導体チップの角が、前記延出部上に載っていることを特徴としている。
この構成によれば、たとえば、アイランドにはんだ接合剤（クリーム状のはんだ）を塗布し、そのはんだ接合剤上に半導体チップを配置しても、はんだ接合剤は、半導体チップの側面に回り込まない。そのため、半導体装置の温度が急激に変化したときや、高温下での接合後の温度低下時に、半導体チップと樹脂基板との間に熱収縮差が生じても、半導体チップの裏面側の周縁部に応力が加わることを防止することができ、半導体チップの損傷の発生を防止することができる。 The invention according to claim 1 for achieving the above object is a semiconductor device, wherein a semiconductor chip having a rectangular shape in plan view , a resin substrate, and an island having a rectangular shape in plan view formed on one surface of the resin substrate, the includes a extending portion which is the island integrally formed so as to extend from the four corners of the island at one surface of the resin substrate, and a bonding agent for bonding the back surface of the island and the semiconductor chip, the plane The extension part extends to a position where it does not reach the periphery of the resin substrate in view, and the corner of the semiconductor chip is placed on the extension part .
According to this configuration, For example other, solder joint agent (cream solder) is applied to the island, be arranged semiconductor chip on the solder bonding agent, solder bonding agent, wrap the sides of the semiconductor chip Absent. Therefore, even when the temperature of the semiconductor device changes suddenly or when the temperature drops after bonding at high temperature, even if a thermal shrinkage difference occurs between the semiconductor chip and the resin substrate , the peripheral edge on the back side of the semiconductor chip It is possible to prevent stress from being applied to the semiconductor chip and to prevent the semiconductor chip from being damaged.

また、この発明の構成によれば、たとえば、アイランドにはんだ接合剤を塗布し、そのはんだ接合剤上に半導体チップを配置して、リフローを行うと、はんだ接合剤が溶融し、その融液が流動することによって、半導体チップが樹脂基板上で動く。複数の延出部が設けられているので、たとえば、半導体チップが或る延出部側に少し偏った位置に配置されても、その場合には、はんだ接合剤の融液が他の延出部に多く流れ込み、その融液の流れによって、半導体チップをアイランドの中心上に導くことができる。そのため、半導体チップをアイランド上に配置するときの公差を大きくとることができ、半導体装置の生産性の向上を図ることができる。 Further, according to the configuration of this invention, for example, solder bonding agent is applied to the island, by placing the semiconductor chip on the solder bonding agent, when the reflow solder bonding agent is melted, the melt The semiconductor chip moves on the resin substrate by flowing. Since a plurality of extending portions are provided, for example, even when the semiconductor chip is disposed at a position slightly deviated toward a certain extending portion side, in that case, the melt of the solder bonding agent is not extended to other extending portions. The semiconductor chip can be guided to the center of the island by the flow of the melt. Therefore, it is possible to increase a tolerance when the semiconductor chip is arranged on the island , and it is possible to improve the productivity of the semiconductor device.

なお、請求項２に記載のように、前記延出部は、前記半導体チップが前記アイランドに接合された状態において、前記半導体チップの表面を垂直に見下ろす平面視で、その先端部が前記半導体チップの周縁の外側に達していてもよい。 According to a second aspect of the present invention, in the planar view in which the extension portion has a vertical view of the surface of the semiconductor chip in a state where the semiconductor chip is bonded to the island , the tip portion thereof is the semiconductor chip. It may have reached the outside of the peripheral edge .

請求項３記載の発明は、前記樹脂基板の前記一方面に形成された内部端子と、前記半導体チップの表面と前記内部端子とを接続するボンディングワイヤとをさらに含むことを特徴とする、請求項１または２に記載の半導体装置である。
請求項４記載の発明は、前記内部端子が複数設けられており、前記複数の内部端子が互いに間隔を開けて前記アイランドおよび前記延出部の周囲に形成されていることを特徴とする、請求項３に記載の半導体装置である。
請求項５記載の発明は、前記内部端子が銅を用いて形成されていることを特徴とする、請求項３または４に記載の半導体装置である。
前記内部端子の数は、８であってもよい。
請求項６記載の発明は、前記半導体チップは、最表面を覆う表面保護膜を有していることを特徴とする、請求項１〜５のいずれか一項に記載の半導体装置である。
前記半導体チップの周縁部には、電極パッドが前記表面保護膜から露出した状態に設けられていてもよい。
請求項７記載の発明は、前記樹脂基板が、ガラスエポキシ樹脂からなることを特徴とする、請求項１〜６のいずれか一項に記載の半導体装置である。
前記延出部は、前記アイランドの各角部から前記樹脂基板の周縁に向けて放射状に延びていてもよい。
請求項８記載の発明は、前記樹脂基板の他方面に設けられた外部端子をさらに含むことを特徴とする、請求項１〜７のいずれか一項に記載の半導体装置である。
請求項９記載の発明は、前記外部端子が、金属材料を用いてボール状に形成されていることを特徴とする、請求項８に記載の半導体装置である。
請求項１０記載の発明は、前記外部端子が複数設けられており、複数の前記外部端子が格子状に整列して配置されていることを特徴とする、請求項８または９に記載の半導体装置である。
前記半導体装置は、ＢＧＡ（Ball Grid Array）型であってもよい。
請求項１１記載の発明は、前記半導体装置がＬＧＡ（Land Grid Array）型であることを特徴とする、請求項８に記載の半導体装置である。
請求項１２記載の発明は、前記外部端子は、前記樹脂基板の一方面と他方面との間を貫通するスルーホール内に設けられた金属を介して、前記樹脂基板の一方面に形成されたアイランドまたは内部端子と電気的に接続されていることを特徴とする、請求項８〜１１のいずれか一項に記載の半導体装置である。
請求項１３記載の発明は、前記接合剤がはんだ接合剤であることを特徴とする、請求項１〜１２のいずれか一項に記載の半導体装置である。
前記はんだ接合剤は、粒径かつ融点（組成）の異なる複数種類のはんだ粉末がフラックス中に混合されたはんだペーストから形成されたものであってもよい。このようなはんだ接合剤は、フラックス中におけるはんだ粉末の密度が高いので、リフローで溶融したときに、はんだ接合剤中にボイドが発生することを防止できる。また、たとえボイドが発生しても、各粒径のはんだ粉末の融点が異なることにより、そのボイドをはんだ接合剤外へ押し出すことができる。そのため、半導体チップの裏面とチップ接合部の接合面との良好な接合を達成することができる。
請求項１４記載の発明は、前記はんだ接合剤が、組成がＰｂ−５Ｓｎ−２．５Ａｇであるはんだ粉末と、組成が３７Ｐｂ−Ｓｎであるはんだ粉末とを含むはんだペーストから形成されたものであることを特徴とする、請求項１３に記載の半導体装置である。
請求項１５記載の発明は、前記はんだ接合剤が、粒径が３０〜８０μｍのはんだ粉末を含むはんだペーストから形成されたものであることを特徴とする、請求項１３または１４に記載の半導体装置である。
請求項１６記載の発明は、前記半導体チップの各辺が、前記アイランドの対応する辺と平行であることを特徴とする、請求項１〜１５のいずれか一項に記載の半導体装置である。
請求項１７記載の発明は、前記半導体チップの全ての角が前記延出部の上に載っていることを特徴とする、請求項１〜１６のいずれか一項に記載の半導体装置である。
請求項１８記載の発明は、前記アイランドは、平面視において、前記半導体チップよりもサイズが小さく、前記半導体チップの周縁の内側に全体が位置していることを特徴とする、請求項１〜１７のいずれか一項に記載の半導体装置である。
請求項１９記載の発明は、前記半導体チップは、パワーＩＣが作り込まれた半導体基板を含むことを特徴とする、請求項１〜１８のいずれか一項に記載の半導体装置である。
請求項２０記載の発明は、前記樹脂基板の一方面を封止する封止樹脂をさらに含むことを特徴とする、請求項１〜１９のいずれか一項に記載の半導体装置である。
The invention described in claim 3 further includes an internal terminal formed on the one surface of the resin substrate, and a bonding wire connecting the surface of the semiconductor chip and the internal terminal. The semiconductor device according to 1 or 2.
The invention according to claim 4 is characterized in that a plurality of the internal terminals are provided, and the plurality of internal terminals are formed around the island and the extension part at intervals. Item 4. The semiconductor device according to Item 3.
A fifth aspect of the present invention is the semiconductor device according to the third or fourth aspect, wherein the internal terminal is formed using copper.
The number of pre-Symbol internal terminal, may be I 8 der.
A sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the semiconductor chip has a surface protective film covering the outermost surface.
The periphery of the front Symbol semiconductor chip, may be provided in a state where the electrode pads are exposed from the surface protective film.
Invention according to claim 7, wherein the resin substrate, characterized by comprising a glass epoxy resin, a semiconductor device according to any one of claims 1-6.
Before Kinobede portion may extend radially toward the periphery of the resin substrate from each corner of the island.
The invention according to claim 8 is the semiconductor device according to any one of claims 1 to 7 , further comprising an external terminal provided on the other surface of the resin substrate.
The invention according to claim 9 is the semiconductor device according to claim 8 , wherein the external terminal is formed in a ball shape using a metal material.
Invention of claim 10 wherein, prior Kigai portion provided with a plurality terminals, and a plurality of said external terminals are aligned in a lattice shape, according to claim 8 or 9 It is a semiconductor device.
Before Symbol semiconductor device, may it BGA (Ball Grid Array) type Der.
The invention according to claim 11 is the semiconductor device according to claim 8 , characterized in that the semiconductor device is an LGA (Land Grid Array) type.
According to a twelfth aspect of the present invention, the external terminal is formed on one surface of the resin substrate via a metal provided in a through hole penetrating between one surface and the other surface of the resin substrate. The semiconductor device according to any one of claims 8 to 11 , wherein the semiconductor device is electrically connected to an island or an internal terminal.
A thirteenth aspect of the invention is the semiconductor device according to any one of the first to twelfth aspects, wherein the bonding agent is a solder bonding agent.
Before SL solder bonding agent may it der a plurality kinds of solder powders having different particle sizes and melting point (composition) is formed from a mixed solder paste in the flux. Since such a solder bonding agent has a high density of solder powder in the flux, voids can be prevented from occurring in the solder bonding agent when melted by reflow. Moreover, even if voids are generated, the voids can be pushed out of the solder bonding agent because the melting points of the solder powders of the respective particle sizes are different. Therefore, it is possible to achieve good bonding between the back surface of the semiconductor chip and the bonding surface of the chip bonding portion.
In the invention described in claim 14 , the solder bonding agent is formed from a solder paste containing a solder powder having a composition of Pb-5Sn-2.5Ag and a solder powder having a composition of 37Pb-Sn. The semiconductor device according to claim 13 , wherein:
The invention according to claim 15 is the semiconductor device according to claim 13 or 14 , wherein the solder bonding agent is formed from a solder paste containing solder powder having a particle size of 30 to 80 µm. It is.
The invention of claim 16 wherein the sides of said semiconductor chip, characterized in that it is parallel to the corresponding sides of the island, which is a semiconductor device according to any one of claims 1 to 15.
The invention according to claim 17 is the semiconductor device according to any one of claims 1 to 16 , wherein all corners of the semiconductor chip are placed on the extension portion.
Invention of claim 18, wherein the islands in plan view, reduced in size than the semiconductor chip, characterized in that the entire inside of the peripheral edge of said semiconductor chip are positioned, according to claim 1 to 17 A semiconductor device according to any one of the above.
The invention according to claim 19 is the semiconductor device according to any one of claims 1 to 18 , wherein the semiconductor chip includes a semiconductor substrate in which a power IC is formed.
The invention according to claim 20 is the semiconductor device according to any one of claims 1 to 19 , further comprising a sealing resin for sealing one surface of the resin substrate.

以下では、この発明の実施の形態を、添付図面を参照して詳細に説明する。
図１は、この発明の一実施形態に係る半導体装置の構成を示す図解的な断面図である。この半導体装置は、ＢＧＡ（Ball Grid Array）が採用された半導体装置であり、平面視矩形の半導体チップ１と、半導体チップ１が搭載されるインタポーザ２と、半導体チップ１およびインタポーザ２の半導体チップ１に対向する面を封止する封止樹脂３とを備えている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. This semiconductor device is a semiconductor device adopting a BGA (Ball Grid Array), a semiconductor chip 1 having a rectangular shape in plan view , an interposer 2 on which the semiconductor chip 1 is mounted, and a semiconductor chip 1 of the semiconductor chip 1 and the interposer 2. And a sealing resin 3 for sealing the surface facing the surface.

半導体チップ１の基体をなす半導体基板（たとえば、シリコン基板）には、たとえば、パワーＩＣが作り込まれている。半導体チップ１の最表面は、表面保護膜で覆われており、その周縁部には、複数の電極パッド（図示せず）が表面保護膜から露出した状態に設けられている。
インタポーザ２は、絶縁性樹脂（たとえば、ガラスエポキシ樹脂）からなる樹脂基板４を備えている。 For example, a power IC is formed in a semiconductor substrate (for example, a silicon substrate) that forms the base of the semiconductor chip 1. The outermost surface of the semiconductor chip 1 is covered with a surface protective film, and a plurality of electrode pads (not shown) are provided on the periphery thereof so as to be exposed from the surface protective film.
The interposer 2 includes a resin substrate 4 made of an insulating resin (for example, a glass epoxy resin).

樹脂基板４の一方面（上面）５には、図２に示すように、平面視矩形状のアイランド６と、このアイランド６の４つの各角部（四隅）からアイランド６の表面７と平行な方向（樹脂基板４の一方面５に沿う方向）に延出する延出部８とが一体的に形成されている。さらに、アイランド６および延出部８の周囲には、複数（この実施形態では８個）の内部端子９が互いに適当な間隔を空けて形成されている。これらのアイランド６、延出部８および内部端子９は、たとえば、銅などの金属材料を用いためっきによって形成することができる。 On one surface (upper surface) 5 of the resin substrate 4, as shown in FIG. 2, an island 6 having a rectangular shape in plan view and parallel to the surface 7 of the island 6 from four corners (four corners) of the island 6 are provided. An extending portion 8 extending in a direction (a direction along the one surface 5 of the resin substrate 4) is integrally formed. Further, a plurality (eight in this embodiment) of internal terminals 9 are formed around the island 6 and the extension portion 8 with appropriate intervals. These islands 6, extending portions 8, and internal terminals 9 can be formed by plating using a metal material such as copper, for example.

アイランド６は、半導体チップ１と比べて、平面視におけるサイズ（外形）が小さく形成されており、平面視において、半導体チップ１の周縁の内側に全体が位置している。アイランド６の表面７に、半導体チップ１の裏面１０が接合剤１１を介して接合される。言い換えれば、アイランド６の表面７は、半導体チップ１の裏面１０が接合剤１１を介して接合される接合面であり、半導体チップ１の裏面１０の面積よりも小さな面積を有している。半導体チップ１の裏面１０が接合剤１１を介してアイランド６の接合面７に接合されることにより、半導体チップ１のインタポーザ２への搭載（ダイボンディング）が達成される。半導体チップ１の各辺は、アイランド６の対応する辺と平行である。半導体チップ１の４つの角は、４つの延出部８の上にそれぞれ載っている。 The island 6 is smaller in size (outer shape) in plan view than the semiconductor chip 1, and is entirely located inside the periphery of the semiconductor chip 1 in plan view. The back surface 10 of the semiconductor chip 1 is bonded to the front surface 7 of the island 6 via the bonding agent 11. In other words, the front surface 7 of the island 6 is a bonding surface to which the back surface 10 of the semiconductor chip 1 is bonded via the bonding agent 11, and has an area smaller than the area of the back surface 10 of the semiconductor chip 1. By mounting the back surface 10 of the semiconductor chip 1 to the bonding surface 7 of the island 6 via the bonding agent 11, mounting of the semiconductor chip 1 on the interposer 2 (die bonding) is achieved. Each side of the semiconductor chip 1 is parallel to the corresponding side of the island 6. The four corners of the semiconductor chip 1 are respectively placed on the four extending portions 8.

４つの延出部８は、アイランド６の各角部から樹脂基板４の周縁に向けて延びる放射状をなしている。各延出部８は、半導体チップ１がアイランド６に接合された状態において、平面視で、その先端部が半導体チップ１の周縁の外側に達している。
各内部端子９は、図１に示すように、たとえば、金細線からなるボンディングワイヤ１２を介して、半導体チップ１の表面の各電極パッドに接続（ワイヤボンディング）される。これにより、半導体チップ１が、ボンディングワイヤ１２を介して内部端子９と電気的に接続される。 The four extending portions 8 have a radial shape extending from each corner of the island 6 toward the periphery of the resin substrate 4. Each extending portion 8 has a tip portion reaching the outer periphery of the semiconductor chip 1 in a plan view in a state where the semiconductor chip 1 is bonded to the island 6.
As shown in FIG. 1, each internal terminal 9 is connected (wire bonded) to each electrode pad on the surface of the semiconductor chip 1 via, for example, a bonding wire 12 made of a fine gold wire. Thereby, the semiconductor chip 1 is electrically connected to the internal terminal 9 via the bonding wire 12.

一方、樹脂基板４の他方面（下面）１３には、実装基板（プリント配線板）上のランド（電極）との電気接続のための複数の外部端子１４が設けられている。外部端子１４は、たとえば、はんだなどの金属材料を用いてボール状に形成されており、格子状に整列して配置されている。各外部端子１４は、樹脂基板４の一方面５と他方面１３との間を貫通するスルーホール（図示せず）内に設けられた金属を介して、アイランド６または内部端子９と電気的に接続されている。   On the other hand, the other surface (lower surface) 13 of the resin substrate 4 is provided with a plurality of external terminals 14 for electrical connection with lands (electrodes) on a mounting substrate (printed wiring board). The external terminals 14 are formed in a ball shape using, for example, a metal material such as solder, and are arranged in a lattice shape. Each external terminal 14 is electrically connected to the island 6 or the internal terminal 9 through a metal provided in a through hole (not shown) penetrating between the one surface 5 and the other surface 13 of the resin substrate 4. It is connected.

そして、この半導体装置は、樹脂基板４の他方面１３側を実装基板に対向させて、各外部端子１４を実装基板上のランドに接続することにより、実装基板に対する表面実装が達成される。すなわち、樹脂基板４の一方面５上の内部端子９と、他方面１３上の外部端子１４とが電気的に接続されているので、外部端子１４を実装基板上のランドに接続することにより、そのランドと内部端子９との電気的な接続を達成することができ、ひいてはランドと半導体チップ１との電気的な接続を達成することができる。   In this semiconductor device, surface mounting on the mounting substrate is achieved by connecting the external terminals 14 to lands on the mounting substrate with the other surface 13 side of the resin substrate 4 facing the mounting substrate. That is, since the internal terminal 9 on the one surface 5 of the resin substrate 4 and the external terminal 14 on the other surface 13 are electrically connected, by connecting the external terminal 14 to the land on the mounting substrate, Electrical connection between the land and the internal terminal 9 can be achieved, and as a result, electrical connection between the land and the semiconductor chip 1 can be achieved.

また、この半導体装置では、半導体チップ１の裏面１０をアイランド６の接合面７に接合するための接合剤として、はんだ接合剤１１が採用されている。そのため、半導体装置が実装基板に実装された状態で、所定の外部端子１４が実装基板上のグランド電極に接続されることにより、半導体チップ１の裏面１０がグランド電極と電気的に接続される。これにより、半導体チップ１の裏面をグランド電位とすることができ、半導体チップ１の良好な動作（パワーＩＣの動作）を確保することができる。   In this semiconductor device, a solder bonding agent 11 is employed as a bonding agent for bonding the back surface 10 of the semiconductor chip 1 to the bonding surface 7 of the island 6. Therefore, the predetermined external terminal 14 is connected to the ground electrode on the mounting substrate while the semiconductor device is mounted on the mounting substrate, whereby the back surface 10 of the semiconductor chip 1 is electrically connected to the ground electrode. Thereby, the back surface of the semiconductor chip 1 can be set to the ground potential, and a good operation (power IC operation) of the semiconductor chip 1 can be ensured.

半導体チップ１のインタポーザ２への搭載（ダイボンディング）は、複数のインタポーザ２に対して一括して行うことができる。すなわち、複数のインタポーザ２の樹脂基板４がその一方面５と平行な方向に連結された元基板を用意し、各樹脂基板４上のアイランド６の接合面７の中央部（図２にハッチングを付して示す領域）に、はんだ接合剤１１の材料であるクリーム状のはんだ（はんだペースト）を塗布する。次いで、半導体チップ１の裏面１０を接合面７に対向させて、その接合面７に塗布されたはんだ上に半導体チップ１を載置する。その後、はんだを溶融させるために、元基板をはんだの溶融温度以上に加熱するリフローを行うことにより、複数のインタポーザ２に対する半導体チップ１の一括搭載が達成される。そして、そのリフロー後に、元基板を各樹脂基板４に切り分けることにより、インタポーザ２上に半導体チップ１が搭載された組立体が得られる。   Mounting (die bonding) of the semiconductor chip 1 on the interposer 2 can be performed on a plurality of interposers 2 in a lump. That is, an original substrate in which the resin substrates 4 of the plurality of interposers 2 are connected in a direction parallel to the one surface 5 is prepared, and the center portion of the bonding surface 7 of the island 6 on each resin substrate 4 (hatching in FIG. 2 is performed). In the region shown), cream-like solder (solder paste), which is the material of the solder bonding agent 11, is applied. Next, the back surface 10 of the semiconductor chip 1 is opposed to the bonding surface 7, and the semiconductor chip 1 is placed on the solder applied to the bonding surface 7. Thereafter, in order to melt the solder, reflow is performed by heating the original substrate to a temperature equal to or higher than the melting temperature of the solder, so that the semiconductor chips 1 are collectively mounted on the plurality of interposers 2. After the reflow, the original substrate is cut into the resin substrates 4 to obtain an assembly in which the semiconductor chip 1 is mounted on the interposer 2.

アイランド６の接合面７の面積が半導体チップ１の裏面１０の面積よりも小さいので、接合面７にはんだ接合剤１１（の材料であるクリーム状のはんだ）を塗布し、そのはんだ接合剤１１上に半導体チップ１を配置しても、はんだ接合剤１１は、半導体チップ１の側面に回り込まない。そのため、半導体装置の温度が急激に変化し、半導体チップ１とインタポーザ２（樹脂基板４）との間に熱収縮差が生じても、はんだ接合剤１１から半導体チップ１の裏面１０側の周縁部に応力が加わることを防止することができ、半導体チップ１の損傷の発生を防止することができる。   Since the area of the bonding surface 7 of the island 6 is smaller than the area of the back surface 10 of the semiconductor chip 1, a solder bonding agent 11 (cream solder which is a material of the solder bonding agent 11) is applied to the bonding surface 7. Even if the semiconductor chip 1 is arranged, the solder bonding agent 11 does not go around the side surface of the semiconductor chip 1. Therefore, even if the temperature of the semiconductor device changes suddenly and a thermal contraction difference occurs between the semiconductor chip 1 and the interposer 2 (resin substrate 4), the peripheral portion on the back surface 10 side of the semiconductor chip 1 from the solder bonding agent 11 It is possible to prevent stress from being applied to the semiconductor chip 1 and to prevent the semiconductor chip 1 from being damaged.

また、アイランド６の各角部から延出部８が延出しているので、たとえば、半導体チップ１をはんだ接合剤１１上に配置するときに、半導体チップ１が或る延出部８側に少し偏った位置に配置されても、その場合には、はんだ接合剤１１の融液が他の延出部８に多く流れ込み、その融液の流れによって、半導体チップ１が接合面７の中心上に導かれる。そのため、半導体チップ１を接合面７上に配置するときの公差を大きくとることができるので、上述のように、複数のインタポーザ２に対して半導体チップ１を一括して搭載することができる。その結果、半導体装置の生産性の向上を図ることができる。   Further, since the extended portions 8 extend from the respective corner portions of the island 6, for example, when the semiconductor chip 1 is disposed on the solder bonding agent 11, the semiconductor chip 1 slightly moves toward the certain extended portion 8. In this case, a large amount of the melt of the solder bonding agent 11 flows into the other extension 8 and the semiconductor chip 1 is placed on the center of the bonding surface 7 by the flow of the melt. Led. Therefore, a large tolerance can be taken when the semiconductor chip 1 is arranged on the bonding surface 7, so that the semiconductor chips 1 can be collectively mounted on the plurality of interposers 2 as described above. As a result, the productivity of the semiconductor device can be improved.

なお、はんだ接合剤１１としては、たとえば、フラックス１５中に、組成がＰｂ−５Ｓｎ−２．５Ａｇであるはんだ粉末と、組成が３７Ｐｂ−Ｓｎであるはんだ粉末とを混合したものが採用されている。また、それらのはんだ粉末は、たとえば、粒径が３０〜８０μｍに形成されており、図３に図解的に示すように、フラックス１５中には、その粒径の範囲内で相対的に大きな粒径を有するはんだ粉末１６と、相対的に小さな粒径を有するはんだ粉末１７とが混合されている。このように、粒径の異なるはんだ粉末１６，１７が混合されていることにより、フラックス１５中におけるはんだ粉末１６，１７の密度が高いので、リフローで溶融したときに、はんだ接合剤１１中にボイドが発生することを防止できる。また、はんだ粉末１６の融点が約３００℃であるのに対し、はんだ粉末１７の融点は１８３℃であるので、リフローの途中でボイドが発生しても、そのボイドをはんだ接合剤１１外へ押し出すことができる。そのため、半導体チップ１の裏面１０とアイランド６の接合面７との良好な接合を達成することができる。 As the solder bonding agent 11, for example, a mixture of a solder powder having a composition of Pb-5Sn-2.5Ag and a solder powder having a composition of 37Pb-Sn in the flux 15 is employed. . Moreover, those solder powders are formed to have a particle size of 30 to 80 μm, for example, and as shown schematically in FIG. 3, relatively large particles within the range of the particle size are contained in the flux 15. A solder powder 16 having a diameter and a solder powder 17 having a relatively small particle diameter are mixed. Since the solder powders 16 and 17 having different particle diameters are mixed as described above, the density of the solder powders 16 and 17 in the flux 15 is high. Therefore, when the solder powders 16 and 17 are melted by reflow, voids are formed in the solder bonding agent 11. Can be prevented. Further, since the melting point of the solder powder 16 is about 300 ° C., the melting point of the solder powder 17 is 183 ° C. Therefore, even if a void is generated during reflow, the void is pushed out of the solder bonding agent 11. be able to. Therefore, it is possible to achieve good bonding between the back surface 10 of the semiconductor chip 1 and the bonding surface 7 of the island 6.

以上、この発明の一実施形態を説明したが、この発明は、他の形態で実施することもできる。たとえば、上述の実施形態では、ＢＧＡが採用された半導体装置を取り上げたが、この発明は、ボール状の外部端子１４に代えて、薄板状の外部端子が整列した、いわゆるＬＧＡ（Land Grid Array）が採用された半導体装置に適用されてもよい。 Although one embodiment of the present invention has been described above, the present invention can be implemented in other forms. For example, in the above-described embodiment, the semiconductor device adopting the BGA is taken up. However, in the present invention, a so-called LGA (Land Grid Array) in which thin plate-like external terminals are arranged instead of the ball-like external terminals 14 is arranged. The present invention may be applied to a semiconductor device employing the above .

その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。   In addition, various design changes can be made within the scope of matters described in the claims.

この発明の一実施形態に係る半導体装置の構成を示す図解的な断面図である。1 is an illustrative sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. 図１に示す半導体装置に備えられるインタポーザの平面図である。FIG. 2 is a plan view of an interposer provided in the semiconductor device shown in FIG. 1. 図１に示す半導体装置に用いられるはんだペーストの構成を図解的に示す図である。It is a figure which shows the structure of the solder paste used for the semiconductor device shown in FIG. 1 schematically. ＢＧＡが採用された半導体装置の構成を示す図解的な断面図である。It is an illustration sectional view showing the composition of the semiconductor device which adopted BGA.

符号の説明Explanation of symbols

１ 半導体チップ
２ インタポーザ（チップ接合部）
７ 接合面
８ 延出部
１０ 裏面
１１ はんだ接合剤 1 Semiconductor chip 2 Interposer (chip joint)
7 Bonding surface 8 Extending portion 10 Back surface 11 Solder bonding agent

Claims (20)

平面視矩形の半導体チップと、
樹脂基板と、
前記樹脂基板の一方面に形成された平面視矩形状のアイランドと、
前記樹脂基板の一方面において前記アイランドの四隅から延出するように前記アイランドと一体的に形成された延出部と、
前記アイランドと前記半導体チップの裏面とを接合する接合剤とを含み、
平面視において前記延出部が前記樹脂基板の周縁に達しない位置まで延出しており、
前記半導体チップの角が、前記延出部上に載っていることを特徴とする、半導体装置。 A rectangular semiconductor chip in plan view;
A resin substrate;
A rectangular island in plan view formed on one surface of the resin substrate;
An extension part formed integrally with the island so as to extend from the four corners of the island on one surface of the resin substrate;
A bonding agent for bonding the island and the back surface of the semiconductor chip;
Extending in a plan view to the position where the extension does not reach the periphery of the resin substrate,
The semiconductor device according to claim 1, wherein corners of the semiconductor chip are placed on the extension portion. 前記延出部は、前記半導体チップが前記アイランドに接合された状態において、前記半導体チップの表面を垂直に見下ろす平面視で、その先端部が前記半導体チップの周縁の外側に達していることを特徴とする、請求項１記載の半導体装置。   The extending portion has a tip portion reaching the outside of the peripheral edge of the semiconductor chip in a plan view in which the surface of the semiconductor chip is vertically looked down in a state where the semiconductor chip is bonded to the island. The semiconductor device according to claim 1. 前記樹脂基板の前記一方面に形成された内部端子と、
前記半導体チップの表面と前記内部端子とを接続するボンディングワイヤとをさらに含むことを特徴とする、請求項１または２に記載の半導体装置。 An internal terminal formed on the one surface of the resin substrate;
The semiconductor device according to claim 1, further comprising a bonding wire that connects a surface of the semiconductor chip and the internal terminal. 前記内部端子が複数設けられており、前記複数の内部端子が互いに間隔を開けて前記アイランドおよび前記延出部の周囲に形成されていることを特徴とする、請求項３に記載の半導体装置。   4. The semiconductor device according to claim 3, wherein a plurality of the internal terminals are provided, and the plurality of internal terminals are formed around the island and the extension portion at intervals. 前記内部端子が銅を用いて形成されていることを特徴とする、請求項３または４に記載の半導体装置。   The semiconductor device according to claim 3, wherein the internal terminal is formed using copper. 前記半導体チップは、最表面を覆う表面保護膜を有していることを特徴とする、請求項１〜５のいずれか一項に記載の半導体装置。 The semiconductor chip is characterized in that it has a surface protective film covering the outermost surface, the semiconductor device according to any one of claims 1-5. 前記樹脂基板が、ガラスエポキシ樹脂からなることを特徴とする、請求項１〜６のいずれか一項に記載の半導体装置。 Said resin substrate, characterized by comprising a glass epoxy resin, the semiconductor device according to any one of claims 1-6. 前記樹脂基板の他方面に設けられた外部端子をさらに含むことを特徴とする、請求項１〜７のいずれか一項に記載の半導体装置。 Characterized in that it further comprises an external terminal provided on the other surface of the resin substrate, the semiconductor device according to any one of claims 1-7. 前記外部端子が、金属材料を用いてボール状に形成されていることを特徴とする、請求項８に記載の半導体装置。 The semiconductor device according to claim 8 , wherein the external terminal is formed in a ball shape using a metal material. 前記外部端子が複数設けられており、複数の前記外部端子が格子状に整列して配置されていることを特徴とする、請求項８または９に記載の半導体装置。 Before Kigai unit has terminals provided in plural, and a plurality of said external terminals are aligned in a lattice shape, the semiconductor device according to claim 8 or 9. 前記半導体装置がＬＧＡ（Land Grid Array）型であることを特徴とする、請求項８に記載の半導体装置。 9. The semiconductor device according to claim 8 , wherein the semiconductor device is an LGA (Land Grid Array) type. 前記外部端子は、前記樹脂基板の一方面と他方面との間を貫通するスルーホール内に設けられた金属を介して、前記樹脂基板の一方面に形成されたアイランドまたは内部端子と電気的に接続されていることを特徴とする、請求項８〜１１のいずれか一項に記載の半導体装置。 The external terminal is electrically connected to an island or an internal terminal formed on one surface of the resin substrate through a metal provided in a through hole penetrating between one surface and the other surface of the resin substrate. characterized in that it is connected, the semiconductor device according to any one of claims 8-11. 前記接合剤がはんだ接合剤であることを特徴とする、請求項１〜１２のいずれか一項に記載の半導体装置。 Wherein the bonding agent is a solder bonding agent, a semiconductor device according to any one of claims 1 to 12. 前記はんだ接合剤が、組成がＰｂ−５Ｓｎ−２．５Ａｇであるはんだ粉末と、組成が３７Ｐｂ−Ｓｎであるはんだ粉末とを含むはんだペーストから形成されたものであることを特徴とする、請求項１３に記載の半導体装置。 The solder bonding agent is formed from a solder paste including a solder powder having a composition of Pb-5Sn-2.5Ag and a solder powder having a composition of 37Pb-Sn. 14. The semiconductor device according to 13 . 前記はんだ接合剤が、粒径が３０〜８０μｍのはんだ粉末を含むはんだペーストから形成されたものであることを特徴とする、請求項１３または１４に記載の半導体装置。 The semiconductor device according to claim 13 or 14 , wherein the solder bonding agent is formed from a solder paste containing a solder powder having a particle size of 30 to 80 µm. 前記半導体チップの各辺が、前記アイランドの対応する辺と平行であることを特徴とする、請求項１〜１５のいずれか一項に記載の半導体装置。 Wherein each side of the semiconductor chip, characterized in that it is parallel to the corresponding sides of said island semiconductor device according to any one of claims 1 to 15. 前記半導体チップの全ての角が前記延出部の上に載っていることを特徴とする、請求項１〜１６のいずれか一項に記載の半導体装置。 Characterized in that all corners of the semiconductor chip is on the top of the extending portion, the semiconductor device according to any one of claims 1-16. 前記アイランドは、平面視において、前記半導体チップよりもサイズが小さく、前記半導体チップの周縁の内側に全体が位置していることを特徴とする、請求項１〜１７のいずれか一項に記載の半導体装置。   18. The island according to claim 1, wherein the island is smaller in size than the semiconductor chip in a plan view and is located entirely inside a periphery of the semiconductor chip. Semiconductor device. 前記半導体チップは、パワーＩＣが作り込まれた半導体基板を含むことを特徴とする、請求項１〜１８のいずれか一項に記載の半導体装置。 The semiconductor chip is characterized in that it comprises a semiconductor substrate which is built a power IC, a semiconductor device according to any one of claims 1 to 18. 前記樹脂基板の一方面を封止する封止樹脂をさらに含むことを特徴とする、請求項１〜１９のいずれか一項に記載の半導体装置。 And further comprising a sealing resin for sealing one surface of the resin substrate, the semiconductor device according to any one of claims 1 to 19.
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