WO2015129185A1 - Resin-sealed semiconductor device, production method therefor, and mounting body therefor - Google Patents

Resin-sealed semiconductor device, production method therefor, and mounting body therefor Download PDF

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Publication number
WO2015129185A1
WO2015129185A1 PCT/JP2015/000653 JP2015000653W WO2015129185A1 WO 2015129185 A1 WO2015129185 A1 WO 2015129185A1 JP 2015000653 W JP2015000653 W JP 2015000653W WO 2015129185 A1 WO2015129185 A1 WO 2015129185A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
top surface
sealing resin
lead terminals
lead terminal
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PCT/JP2015/000653
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French (fr)
Japanese (ja)
Inventor
老田　成志
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パナソニックＩｐマネジメント株式会社
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Publication of WO2015129185A1 publication Critical patent/WO2015129185A1/en

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Definitions

  • the present disclosure relates to a resin-encapsulated semiconductor device in which a semiconductor chip and a lead frame are encapsulated with an encapsulating resin, and a mounting body thereof. In particular, a part of a lead terminal is exposed from the encapsulating resin. Is related to the structure.
  • Patent Document 1 In response to such a requirement, for example, a semiconductor device described in Patent Document 1 is known.
  • FIG. 11 is a side sectional view showing a configuration of a conventional semiconductor device.
  • a conventional semiconductor device 100 is mounted on a chip mounting portion 102 on which a semiconductor chip 101 is mounted, a lead frame having a terminal portion to be a lead terminal 103, and the chip mounting portion 102, and is electrically connected to the terminal portion. And a semiconductor chip 101.
  • a through groove that penetrates the terminal portion from one surface that is the surface on the semiconductor chip 101 side to the other surface in the thickness direction, a lid portion 104 that closes an end portion of the through groove on one surface side of the terminal portion, A resin portion 105 for sealing the semiconductor chip 101 so as to expose the other surface of the terminal portion and the inner surface of the through groove, and the plating film 106 is the other surface of the terminal portion and the inner surface of the through groove. It is covered.
  • solder is easily attached to the side surface of the lead terminal 103 of the semiconductor device 100.
  • the side surface of the lead terminal 103 of the semiconductor device 100 contributes to the improvement of solder wettability, and further, the improvement of the solder connection strength can be maintained in the mounting body of the semiconductor device 100.
  • an object of the present disclosure is to greatly improve the solder connection strength of a printed circuit board mounting body without substantially changing the sizes of conventional semiconductor devices and lead terminals.
  • the semiconductor device includes a semiconductor chip, a plurality of lead terminals electrically connected to the semiconductor chip, and a sealing resin portion that seals the semiconductor chip and the plurality of lead terminals.
  • the plurality of lead terminals are formed inside the rectangular sealing resin region formed by the outermost peripheral side of the sealing resin portion when viewed from the top surface.
  • At least one of the plurality of lead terminals is a top surface exposed lead terminal having a top surface exposed from the sealing resin portion in the sealing resin region.
  • solder bonding strength can be obtained when solder bonding is performed with a printed circuit board.
  • the size of the lead terminal hardly needs to be changed from the conventional one.
  • the semiconductor device may include a die pad on which the semiconductor chip is placed.
  • the sealing resin portion may seal the semiconductor chip, the plurality of lead terminals, and the die pad.
  • bottom surfaces of the plurality of lead terminals may not be covered with the sealing resin portion.
  • the top surface exposed lead terminal may be located at a corner portion of the semiconductor device.
  • solder joint state of the solder joint portion at the corner portion of the semiconductor device where stress is most concentrated can be strengthened, sufficient solder joint strength can be obtained.
  • top surface exposed lead terminals may be arranged at the four corners of the semiconductor device.
  • a plating film may be coated on at least one of the top surface, the bottom surface, and the side surface of the top surface exposed lead terminal.
  • solder wettability is remarkably improved, a sufficient solder joint strength can be obtained when a semiconductor device is mounted on a printed board.
  • the top surface of the top surface exposed lead terminal is inclined toward the bottom surface side of the semiconductor device from the central portion toward the outer peripheral portion of the semiconductor device.
  • solder material can easily reach the top surface side of the top surface exposed lead terminal, the wet spread area can be increased and the wet spread speed can be improved, and a solder fillet is easily formed.
  • a groove or a recess may be formed on the top surface of the top surface exposed lead terminal.
  • solder material comes into contact with the top surface side of the top surface exposed lead terminal, the solder material spreads along the groove and the concave portion by a so-called capillary phenomenon. Accordingly, it is possible to increase the wet spread area and improve the wet spread speed, and as a result, solder fillets are easily formed.
  • groove or the recess may be formed from the center of the semiconductor device toward the outer periphery.
  • top-surface exposed lead terminal may have a shape that is curved outward from the bottom surface of the semiconductor device at the outer peripheral portion of the semiconductor device.
  • top surface of the top exposed lead terminal may be the same height as the top surface of the sealing resin portion.
  • a mounting body of a semiconductor device includes any one of the semiconductor devices described above, a printed circuit board having a wiring pattern, and a solder material that connects a plurality of lead terminals and the wiring pattern of the semiconductor device. Are also arranged on the top surface of the top exposed lead terminal of the semiconductor device.
  • the shape of the solder material for connecting the semiconductor device and the printed circuit board that is, the so-called solder fillet can be made strong, and a highly reliable mounting body of the semiconductor device can be obtained.
  • the first method for manufacturing a semiconductor device includes the following first to sixth steps. That is, the method includes a first step of preparing a plurality of lead terminals and a semiconductor chip, and a second step of joining the semiconductor chip and the plurality of lead terminals with a thin metal wire. Then, a third step of placing the resin adhesion preventing material on a part of at least one top surface of the plurality of lead terminals, and a fourth step of sealing the plurality of lead terminals, the semiconductor chip, and the fine metal wires with a sealing resin And a process. Furthermore, the resin adhesion preventing material is removed to provide a fifth step for obtaining a sealing resin body, and a sixth step for obtaining a semiconductor device by dividing the sealing resin body individually.
  • the second method for manufacturing a semiconductor device includes the following first to sixth steps. That is, the method includes a first step of preparing a plurality of lead terminals and a semiconductor chip, and a second step of joining the semiconductor chip and the plurality of lead terminals with a thin metal wire. Then, a third step of placing a resin adhesion preventing material on a part of at least one top surface of the plurality of lead terminals, and molding by sealing the plurality of lead terminals, the semiconductor chip, and the fine metal wires with a sealing resin And a fourth step of obtaining a sealing resin body to be performed. Furthermore, a fifth step of dividing the sealing resin body individually and a sixth step of obtaining a semiconductor device by removing the resin adhesion preventing material are provided.
  • a lead frame having a plurality of lead terminals, a die pad for mounting the semiconductor chip, and a suspension lead for supporting the die pad may be prepared. Further, a seventh step of placing the semiconductor chip on the die pad may be provided between the first step and the second step.
  • the semiconductor device and the mounting body thereof according to the present disclosure have a lead terminal that cuts out the sealing resin on the surface side of the semiconductor device and exposes the top surface, so that there is almost no need to change the size of the lead terminal.
  • the effect that the solder joint strength with the substrate is improved can be achieved.
  • FIG. 1 is a perspective view showing the configuration of the semiconductor device according to the first embodiment.
  • 2A is a view of the semiconductor device of FIG. 1 when viewed from the top surface direction.
  • 2B is a cross-sectional view of the semiconductor device of FIG. 2A taken along the line IIb-IIb.
  • 2C is a view of the semiconductor device of FIG. 1 when viewed from the bottom.
  • FIG. 3A is a view of another example of the semiconductor device according to the first embodiment when viewed from the top surface direction.
  • FIG. 3B is a diagram of another example of the semiconductor device according to the first embodiment viewed from the top surface direction.
  • 4 is a cross-sectional view of the mounting body of the semiconductor device shown in FIG. FIG.
  • FIG. 5 is a cross-sectional view comparing manufacturing flows of the semiconductor device shown in FIG. 1 and a conventional semiconductor device.
  • FIG. 6 is a cross-sectional view for comparing manufacturing flows of the semiconductor device according to the second embodiment and a conventional semiconductor device.
  • FIG. 7 is a side cross-sectional view of a mounting body including a semiconductor device according to the third embodiment.
  • FIG. 8A is a diagram illustrating a main part when an example of the semiconductor device according to the fourth embodiment is viewed from the top surface direction.
  • FIG. 8B is a diagram illustrating a main part when an example of the semiconductor device according to the fourth embodiment is viewed from the top surface direction.
  • 8C is a cross-sectional view of the semiconductor device of FIG. 8A taken along the line VIIIc-VIIIc.
  • FIG. 8D is a cross-sectional view of the semiconductor device of FIG. 8B taken along line VIIId-VIIId.
  • FIG. 9 is a side cross-sectional view of a mounting body including a semiconductor device according to the fifth embodiment.
  • FIG. 10 is a side cross-sectional view of a mounting body including a semiconductor device according to the sixth embodiment.
  • FIG. 11 is a side sectional view showing a configuration of a conventional semiconductor device.
  • FIG. 12 is a diagram for explaining a problem of a conventional semiconductor device.
  • FIG. 1 is a perspective view of the semiconductor device according to the first embodiment.
  • the semiconductor device 11 of the present embodiment includes a semiconductor chip 12, a die pad 13 on which the semiconductor chip 12 is placed, and a plurality of leads electrically connected to the semiconductor chip 12 by metal thin wires 14. And a terminal 15. And it has the sealing resin part 16 which seals at least one part of the semiconductor chip 12, the die pad 13, the metal fine wire 14, and the lead terminal 15.
  • the semiconductor device 11 is called a so-called QFN (Quad-Flat-Non-Lead) package in which a plurality of lead terminals 15 are formed inside the resin region of the sealing resin portion 16 when viewed from the top surface direction.
  • QFN Quad-Flat-Non-Lead
  • a feature is that a part of the top surface of at least one lead terminal 15 is exposed from the sealing resin portion 16.
  • the QFN package has a rectangular shape.
  • the lead terminals arranged on the back surface side of the semiconductor device are covered with sealing resin, and the top surface of the lead terminal is sealed. Not exposed from the resin.
  • the sealing resin region is formed by a rectangular region equal to the bottom surface of the semiconductor device 11 formed by the sealing resin portion 16 and the lead terminal 15 or by a side constituting the outermost periphery of the sealing resin portion 16. This is a square area.
  • the lead terminal 15 whose top surface is exposed from the sealing resin portion 16 is particularly referred to as a top surface exposed lead terminal 17.
  • reference numeral 15 represents a lead terminal whose top surface is covered with the sealing resin portion 16, and reference numeral 17 represents a top exposed lead terminal of the present disclosure.
  • the lead terminal 15 has a terminal width of about 0.1 to 0.4 mm and a terminal pitch of about 0.4 to 1.27 mm, and the terminal width is 0.15 to 0 with the recent miniaturization of the QFN package. .2mm and terminal pitch is 0.4 to 0.65mm.
  • FIG. 2A to 2C are diagrams of the semiconductor device of FIG. 1 when viewed from a plurality of directions.
  • 2A is a plan view as viewed from the top surface side of the semiconductor device
  • FIG. 2B is a cross-sectional view of the semiconductor device of FIG. 2A taken along the line IIb-IIb
  • FIG. 2C is as viewed from the bottom surface side of the semiconductor device. It is a top view.
  • the bottom surfaces of all the lead terminals 15 and 17 including the top surface exposed lead terminals 17 are exposed on the bottom surface of the semiconductor device 11, and the appearance is not different from the conventional QFN package.
  • a notch 30 is formed in a part of the sealing resin portion 16 on the outer peripheral side of the semiconductor device 11.
  • the top surface of the lead terminal is exposed from the portion 30 (top surface exposed lead terminal 17).
  • the top surface of the normal lead terminal 15 is completely covered with the sealing resin portion 16, whereas the top surface exposed lead In the terminal 17, a part of the top surface on the outer peripheral side of the semiconductor device 11 is exposed at the corner portion and the side surface portion of the semiconductor device 11.
  • the exposed portion of the top surface exposed lead terminal 17 is to be soldered to the wiring pattern 19 of the printed circuit board 18 in a reflow mounting process described later (see FIG. 4).
  • FIG. 3A and 3B are plan views seen from the top side showing another example of the first embodiment.
  • FIG. 1 and FIG. 2 an example is described in which the top exposed lead terminals 17 are installed in a corner portion and a side portion adjacent to the corner portion in the outer peripheral portion of the semiconductor device 11.
  • the present invention is not limited to these examples.
  • the top surface exposed lead terminal 17 may be provided only in the corner portion, or may be provided only in the side surface portion as shown in FIG. 3B.
  • the top exposed lead terminal 17 is connected to the four corners of the semiconductor device 11 in view of difficulty in joining with a wiring pattern of a printed circuit board to be described later, difficulty in manufacturing a semiconductor device, manufacturing cost of the semiconductor device, and the like. You may provide in a part and may provide in two corner parts on a diagonal.
  • the top exposed lead terminal 17 may be formed by exposing a part of the upper surface of all the lead terminals 15 in the side surface portion. Further, the top exposed lead terminals 17 may be provided only on one side surface, or the top exposed lead terminals 17 and the lead terminals 15 may be provided alternately. Moreover, the top surface exposed lead terminal 17 may be provided on either one of the corner portion or the side surface portion, or may be provided on both. That is, at least one of the plurality of lead terminals 15 may be the top surface exposed lead terminal 17.
  • FIG. 4 is a cross-sectional view of a mounting body using the semiconductor device of FIG.
  • a solder paste (not shown) is applied to the wiring pattern 19 of the printed circuit board 18. Then, the solder paste and the lead terminal 15 and the top exposed lead terminal 17 of the semiconductor device 11 are placed in face-to-face alignment and heated at a high temperature with a reflow device or the like, thereby mounting the package 20 of the semiconductor device 11 of the present disclosure. Is completed.
  • the bottom surface side of the top exposed lead terminal 17 is widely connected to the wiring pattern 19 of the printed circuit board 18 by the solder material 21, it can stably supply and demand electrical signals. Further, since the top surface side of the top surface exposed lead terminal 17 is connected to the solder alloy so as to be pressed against the wiring pattern 19 of the printed circuit board 18 by the solder material 21, the mounting strength can be maintained high.
  • printed circuit boards often have a thickness of about 0.5mm to 2.0mm, and the layer structure consists of a single-sided board where the conductor layer exists only on one side and two layers where the conductive layer exists on both the front and back sides.
  • the layer structure consists of a single-sided board where the conductor layer exists only on one side and two layers where the conductive layer exists on both the front and back sides.
  • These printed circuit boards are selectively used as necessary, such as the wiring density rule of semiconductor devices, heat dissipation, and the generation of set equipment to be used.
  • solder paste material melts at a maximum temperature of about 260 ° C. in consideration of the burden on the reflow heating device and the heat resistance of the semiconductor device.
  • solder pastes such as Sn, Ag, and Cu are generally used in many cases.
  • the mounting body 20 shown in FIG. 4. The thickness of the semiconductor device 11 and the size in the planar direction, the lead terminal 15, the top exposed lead terminal 17, the sealing resin portion 16, the solder material 21, and the printed board 18
  • the mounting body 20 is subjected to expansion and contraction stress loads depending on the physical property specification values such as the thermal expansion coefficient, the respective processing methods, the manufacturing flow and the connection conditions for connecting each other. Therefore, a particularly large load is applied to the solder material 21 that joins the semiconductor device 11 and the printed circuit board 18.
  • the structure is not capable of stress relaxation as in the QFP (Quad-Flat-Package) with the gull wing leads, so a large load is applied to the solder material 21. It is clear that it takes.
  • the mounting body 20 inside the housing is not comparable to the conventional one. It is often stressed and it can be easily imagined that electrical open defects are caused.
  • the portion most susceptible to the influence is a portion related to the solder material 21 connecting the semiconductor device 11 and the printed board 18 shown in FIG. Therefore, it goes without saying that the reliability of the mounting body 20 described above can be improved by making the shape of the solder material 21, that is, a so-called solder fillet, into a firm shape.
  • a so-called face-up type semiconductor chip in which the electrode of the semiconductor chip 12 faces the top surface side. 12 and a thin metal wire 14 are used.
  • a so-called face-down method in which the electrodes of the semiconductor chip 12 face the bottom surface may be used.
  • bumps may be interposed using flip chip bonding, or the electrodes of the semiconductor chip 12 and the lead terminals 15 may be electrically connected by direct bonding by forming a eutectic alloy or the like.
  • fine metal wire 14 an aluminum fine wire, a gold wire, or the like can be used.
  • the sealing resin portion 16 does not exist on the bottom surface of the die pad 13 on which the semiconductor chip 12 is placed, and the bottom surface of the die pad 13 is exposed.
  • the die pad 13 also plays a role of efficiently releasing heat generated from the semiconductor chip 12. Therefore, by soldering the printed circuit board 18 with the solder material 21, the heat dissipation of the semiconductor chip 12 can be enhanced, and the function of the semiconductor chip 12 can be kept stable.
  • the present embodiment may be applied to a so-called die pad upset QFN package in which the bottom surface of the die pad 13 is covered with the sealing resin portion 16. Further, without using the die pad 13, a part of the lead terminal 15 may be insulated and the semiconductor chip 12 may be supported on the insulator. Further, an insulating resin tape may be provided and the semiconductor chip 12 may be mounted on the insulating resin tape. That is, this embodiment may be applied to a die padless lead frame instead of using the die pad 13.
  • all the lead terminals 15 and the die pad 13 including the top surface exposed lead terminals 17 may be formed by the same lead frame due to manufacturing advantages, but may not necessarily be the same.
  • a lead terminal and a die pad manufactured by different materials or by different manufacturing methods may be prepared by a method of combining and forming in a later step.
  • the lead frame has a copper (Cu) material frame, a nickel (Ni) layer as a base plating, a palladium (Pd) layer thereon, and a thin gold (Au) layer as an uppermost layer.
  • Cu copper
  • Ni nickel
  • Pd palladium
  • Au gold
  • the lead frame has a copper (Cu) material frame, a nickel (Ni) layer as a base plating, a palladium (Pd) layer thereon, and a thin gold (Au) layer as an uppermost layer.
  • Cu copper
  • Ni nickel
  • Pd palladium
  • Au gold
  • the step of coating the plating film may be a so-called pre-plating (pre-plating) method performed before placing the semiconductor chip 12 on the die pad 13. Further, a so-called post-plating method in which the plating film is coated after the semiconductor device 11 is sealed with resin may be used.
  • FIG. 5 is a diagram for comparing the manufacturing flow between the semiconductor device shown in FIG. 1 and a conventional semiconductor device.
  • the left side of the alternate long and short dash line is a cross-sectional view showing the manufacturing flow of the semiconductor device of the present embodiment
  • the right side is a cross-sectional view showing the manufacturing flow of the conventional semiconductor device.
  • the semiconductor chip 12 is electrically connected to the semiconductor chip 12 by a metal pad 14, and a die pad 13 on which the semiconductor chip 12 is bonded and mounted by an adhesive, so-called die bonding material.
  • a lead frame 22 provided with the lead terminals 15 is prepared.
  • the die pad 13 is supported by the suspension leads, it is not shown in the cross section in FIG. Further, the suspension lead is bent in the thickness direction to form a so-called depressed portion, and a part of the suspension lead is covered with a sealing resin described later.
  • the material of the lead frame 22, the plating film coated on the surface of the lead frame 22, the direction of the semiconductor chip 12, and the type of the fine metal wires 14 are as described above.
  • the resin adhesion preventing pin 23 is brought into contact with the top surface of the lead terminal 15 that becomes the top surface exposed lead terminal 17 in the subsequent process. Note that this process does not exist in the conventional manufacturing flow. Further, the resin adhesion preventing pin 23 is not provided on the top surface of the normal lead terminal 15 covered with the sealing resin portion 16.
  • the resin adhesion prevention pin 23 serves as a mask that prevents the sealing resin from entering the top surface of the top surface exposed lead terminal 17 during resin sealing. That is, the presence of the resin adhesion preventing pin 23 can prevent the sealing resin burr from being formed on the top surface of the top surface exposed lead terminal 17. Then, the process B in FIG. 5 is an important process that finally determines the structure of the top exposed lead terminal 17 of the semiconductor device 11 of the present disclosure.
  • the resin adhesion prevention pin 23 is provided in the mold for resin sealing and has a structure that can be removed after the sealing resin is cured by contacting the top exposed lead terminal 17 before injecting the sealing resin. It has become.
  • the resin sealing mold it is not necessarily attached to the resin sealing mold to reduce the cost of the resin sealing mold, and is resistant to the high temperature environment at the time of resin sealing as will be described later.
  • the material may be removed or disappear after completion or after individual dicing. That is, the resin adhesion preventing pin 23 may be removed by any method.
  • the fine metal wires 14 are connected to the top surface exposed lead terminals 17 that are in contact with the resin adhesion preventing pins 23 and are shown as electrically effective signal pins. 11, only lead terminals located at the four corners, so-called reinforcing lands, may be used as the top exposed lead terminals 17, and the resin adhesion preventing pins 23 may be brought into contact with each other. That is, the resin adhesion preventing pin 23 may be brought into contact with at least one top surface of the plurality of lead terminals 15.
  • step C of FIG. 5 all lead terminals except for the semiconductor chip 12, the fine metal wires 14, part of the die pad 13, and part of the top face of the top exposed lead terminal 17 are injected with sealing resin. A sealing resin portion 16 for sealing the top surface of 15 is formed.
  • step D of FIG. 5 the resin adhesion preventing pins 23 that have been in contact with the top exposed lead terminals 17 are removed and divided individually by a dicing saw 25 or the like to complete the semiconductor device 11.
  • the notch portion 30 is formed in the sealing resin portion 16 by removing the resin adhesion preventing pin 23.
  • the semiconductor device 11 is a resin-encapsulated semiconductor device called a so-called QFN package in which the lead terminals 15 are formed inside the resin region of the encapsulating resin portion 16 when viewed from the top surface direction. That is, the resin-encapsulated semiconductor device 11 having a structure (a top exposed lead terminal 17) in which at least a part of at least one lead terminal 15 in the top surface direction is exposed from the sealing resin portion 16 is completed.
  • the exposed surface on the top surface side of the top surface exposed lead terminal 17 of the present disclosure if a so-called post-plating method for covering the plating film after the semiconductor device 11 is sealed with resin is used, the exposed surface on the top surface side of the top surface exposed lead terminal 17 of the present disclosure, Of course, a plating film is formed on the exposed surface on the bottom side. Further, since the plating film can be formed on the side surfaces of all the lead terminals 15 including the top surface exposed lead terminals 17 where the metal material is exposed by cutting with the dicing saw 25, the solder wettability is improved. Improve dramatically.
  • the manufacturing method of the present disclosure is not limited to the case where the lead frame 22 is used.
  • the shape of the top exposed lead terminal 17 that is a basic concept of the present disclosure is applicable to all semiconductor devices having a semiconductor chip mounted and having a lead terminal.
  • the substrate type, TAB type, ceramic type, etc. are widely used. It is possible to apply.
  • FIG. 6 is a diagram for comparing manufacturing flows of the semiconductor device according to the second embodiment and a conventional semiconductor device.
  • components having substantially the same function are denoted by the same reference numerals as those in the first embodiment, and detailed description may be omitted.
  • the left side of the alternate long and short dash line is a cross-sectional view showing the manufacturing flow of the semiconductor device of the present embodiment
  • the right side is a cross-sectional view showing the manufacturing flow of the conventional semiconductor device.
  • Step A in FIG. 6 is the same as Step A in FIG. 6
  • step B of FIG. 6 the resin adhesion preventing lid member 24 is brought into contact with the top surface of the lead terminal 15.
  • This resin adhesion preventing lid member 24 serves to serve as a mask that prevents the sealing resin from entering the top surface of the top exposed lead terminal 17 during resin sealing. That is, it is possible to prevent the sealing resin burr from being formed on the top surface of the top surface exposed lead terminal 17 due to the presence of the resin adhesion preventing lid member 24.
  • the process B in FIG. 6 is an important process that finally determines the structure of the top exposed lead terminal 17 of the semiconductor device 11 of the present disclosure.
  • the resin adhesion prevention lid member 24 is placed so as to come into contact with the lead terminal 15 serving as the top exposed lead terminal 17 before injecting the sealing resin.
  • the fine metal wire 14 is connected to the top surface exposed lead terminal 17 that is in contact with the resin adhesion preventing lid member 24 and is shown as an electrically effective signal pin. Only the lead terminals located at the four corners of the device 11, that is, so-called reinforcing lands, may be used as the top exposed lead terminals 17, and the resin adhesion preventing lid member 24 may be brought into contact therewith. That is, the resin adhesion prevention lid member 24 may be brought into contact with at least one top surface of the plurality of lead terminals 15.
  • step C of FIG. 6 all lead terminals except for the semiconductor chip 12, the fine metal wires 14, part of the die pad 13, and part of the top surface of the top surface exposed lead terminal 17 are injected with sealing resin. A sealing resin portion 16 for sealing the top surface of 15 is formed.
  • step D of FIG. 6 the resin adhesion prevention lid member 24 that is in contact with the top surface exposed lead terminal 17 appears on the side surface of the semiconductor device 11 by being divided individually by a dicing saw 25 or the like.
  • step E of FIG. 6 by removing the resin adhesion prevention lid member 24, a structure in which the top surface of the lead terminal 15 is exposed (top surface exposed lead terminal 17) can be formed.
  • the notch portion 30 is formed in the sealing resin portion 16 by removing the resin adhesion preventing lid member 24.
  • the resin adhesion preventing lid member 24 is preferably a material that is resistant to a high temperature environment at the time of resin sealing, and further disappears (including when removed) after being divided individually.
  • the same metal material as the top surface exposed lead terminal 17 or the same epoxy resin material as the sealing resin portion 16 may be used.
  • a metal piece formed with the same composition as the solder material 21 is resistant to heating in a resin sealing process at around 170 ° C., and can be melted together with the solder paste material during reflow mounting. Therefore, formation of a good solder fillet can be expected.
  • FIG. 7 is a side cross-sectional view of a mounting body including a semiconductor device according to the third embodiment.
  • components having substantially the same function are denoted by the same reference numerals as those in the first embodiment, and detailed description may be omitted.
  • the top surface exposed lead terminal 17 whose top surface is exposed from the sealing resin portion 16 does not form a parallel state between the top surface and the bottom surface, and the top surface and the bottom surface are formed in the outer peripheral portion of the semiconductor device 11. It is characterized by a structure in which the distance in the thickness direction becomes thinner in a tapered shape as it goes toward the outer periphery.
  • the bottom surface of the top surface exposed lead terminal 17 is parallel to the bottom surface of the semiconductor device 11, whereas the top surface of the top surface exposed lead terminal 17 is inclined with respect to the bottom surface of the semiconductor device 11.
  • the mounting strength can be improved.
  • the top exposed lead 17 in the present embodiment may be installed at either the corner portion or the side surface portion, and in order to maintain higher solder connection reliability, You may apply to all the lead terminals of a corner part and a side part.
  • FIG. 8A and FIG. 8B are views showing main parts of an example of the semiconductor device according to the fourth embodiment, respectively, and FIG. 8A and FIG. 8B are plan views when the semiconductor device is viewed from the top surface side, respectively.
  • 8C is a cross-sectional view of the semiconductor device of FIG. 8A taken along the line VIIIc-VIIIc.
  • 8D is a cross-sectional view of the semiconductor device of FIG. 8B taken along line VIIId-VIIId.
  • the top surface exposed lead terminal 17 whose top surface is exposed from the sealing resin portion 16 in the fourth embodiment is characterized in that a groove portion 17a or a concave portion 17a is formed on the top surface.
  • the groove portion 17 a or the recess portion 17 a extends from the center direction of the semiconductor device 11 toward the outer peripheral portion of the semiconductor device 11. As long as the groove part 17a or the recessed part 17a is extended in the direction which goes to an outer peripheral part, it may be linear as shown to FIG. 8A, or may be curvilinear as shown to FIG. 8B. Further, both may be mixed in the same top exposed lead terminal 17.
  • solder material 21 comes into contact with the top surface side of the top surface exposed lead terminal 17, the solder material 21 can spread along the groove portion 17a and the recess portion 17a by a so-called capillary phenomenon.
  • capillary phenomenon it is possible to increase the wet spreading area and improve the wet spreading speed, and as a result, an effect that a solder fillet is easily formed can be expected.
  • the mounting strength can be improved.
  • the top-surface exposed lead terminal 17 in the present embodiment may be installed in either the corner portion or the side portion. Further, in order to maintain higher solder connection reliability, the present invention may be applied to all lead terminals in the corner portion and the side portion. Moreover, it is good also as a structure combined with 3rd Embodiment.
  • FIG. 9 is a side cross-sectional view of a mounting body including a semiconductor device according to the fifth embodiment.
  • components having substantially the same function are denoted by the same reference numerals as those in the first embodiment, and detailed description may be omitted.
  • the top exposed lead terminal 17 whose upper surface is exposed from the sealing resin portion 16 in the fifth embodiment has a structure that is curved in the thickness direction toward the printed circuit board 18 as it approaches the outer peripheral portion of the semiconductor device 11. It is characterized by that.
  • the end portion of the top surface exposed lead terminal 17 is disposed closer to the printed circuit board 18 than the bottom surface of the semiconductor device 11 (the bottom surface of the sealing resin portion 16). With such a structure, a gap between the bottom surface of the top surface exposed lead terminal 17 and the printed board 18, a so-called standoff can be secured.
  • the bottom surface of the top surface exposed lead terminal 17 protrudes from the bottom surface of the sealing resin portion 16. Therefore, the stand-off height of the top surface exposed lead terminal 17 is ensured to be high when the top surface exposed lead terminal 17 and the wiring pattern 19 on the printed circuit board 18 are joined when the semiconductor device 11 is mounted on the printed circuit board 18. Can do. Therefore, the thickness of the solder material inevitably increases and a structure capable of absorbing more strain can be obtained, so that the bonding strength can be improved.
  • the top exposed lead terminal 17 in the present embodiment may be installed at either the corner or the side surface, and in order to maintain higher solder connection reliability. It may be applied to all the lead terminals in the corner portion and the side portion. Moreover, it is good also as a structure combined with 4th Embodiment.
  • FIG. 10 is a side cross-sectional view of a mounting body including a semiconductor device according to the sixth embodiment.
  • components having substantially the same function are denoted by the same reference numerals as those in the first embodiment, and detailed description may be omitted.
  • the top-surface exposed lead terminal 17 whose upper surface is exposed from the sealing resin portion 16 in the sixth embodiment is characterized by a structure in which the side surface is extended in the thickness direction.
  • top exposed lead terminal 17 exposed from the sealing resin portion 16 from the bottom surface to the top surface of the semiconductor device 11 at the corner portion of the semiconductor device 11. That is, the top surface of the sealing resin portion 16 and the top surface of the top surface exposed lead terminal 17 have the same height and are flush with each other.
  • the top exposed lead terminal 17 is L-shaped in the cross-sectional view of the semiconductor device 11 in the thickness direction. With such a structure, the solder material 21 existing on the top surface of the top surface exposed lead terminal 17 can further wet in the thickness direction, and a thicker solder fillet can be formed.
  • the mounting strength can be improved.
  • the shape of the top exposed lead terminal 17 may be a structure combined with the third to fifth embodiments.
  • the semiconductor device 11 since the lead terminal is formed inside the sealing resin region as in the conventional QFN package, the semiconductor device 11 itself can be reduced in size and soldered to the printed circuit board 18. It is possible to provide a QFN package with excellent performance that connection strength can be improved.
  • the present disclosure has an effect that a solder fillet can be formed from the top surface direction of a lead terminal in a mounting body of a semiconductor device, and a strong solder connection strength can be maintained. Therefore, a semiconductor having a minute lead terminal This is useful for keeping the solder connection strength between the apparatus and the printed circuit board strong, and is useful as a mounting body that can sufficiently withstand a load of a large mechanical stress or thermal stress.

Abstract

The present invention greatly improves the solder connection strength of a mounting body for a printed circuit board while causing almost no change to the sizes of conventional semiconductor devices and lead terminals. A semiconductor device (11) is provided with a semiconductor chip (12), a plurality of lead terminals (15) that are electrically connected with the semiconductor chip, and a sealing resin section (16) that seals the semiconductor chip and the plurality of lead terminals. When viewed from the top surface, the plurality of lead terminals are formed more to the inside than a sealing resin area of a square that is configured from the outermost periphery of the sealing resin section. At least one of the plurality of lead terminals is an exposed top surface lead terminal (17) having a top surface that is exposed from the sealing resin within the sealing resin area.

Description

樹脂封止型半導体装置、およびその製造方法、ならびにその実装体Resin-sealed semiconductor device, manufacturing method thereof, and mounting body thereof
　本開示は、半導体チップおよびリードフレームを封止樹脂で封止した樹脂封止型半導体装置、およびその実装体に関するものであり、特にリード端子の一部の面を封止樹脂から露出させるようにした構造に関するものである。 The present disclosure relates to a resin-encapsulated semiconductor device in which a semiconductor chip and a lead frame are encapsulated with an encapsulating resin, and a mounting body thereof. In particular, a part of a lead terminal is exposed from the encapsulating resin. Is related to the structure.
　近年、ＯＡ（Office Automation）機器や家電製品等の軽薄短小化、および一般ユーザーからの幅広い要望に応える多種多機能化にともない、電子機器に搭載される半導体装置は小型化・薄型化・多ピン化が進んでいる。一方で、最近では自動車や航空機器の電子化にともないプリント基板実装体に対しては、車載レベルに充分耐え得る信頼性が求められてきている。狭小面積のリード端子を用いて、高耐性の実装信頼性を実現するために、実装体のハンダ接合部の強度向上は必須課題となってきている。 In recent years, semiconductor devices mounted on electronic devices have become smaller, thinner, and multi-pinned as OA (Office Automation) devices and home appliances have become lighter, thinner, and smaller, and have a variety of functions to meet a wide range of requests from general users. Is progressing. On the other hand, recently, with the digitization of automobiles and aeronautical equipment, there has been a demand for reliability that can sufficiently withstand the in-vehicle level for printed circuit board mounting bodies. In order to achieve highly reliable mounting reliability using a lead terminal with a small area, it is essential to improve the strength of the solder joint of the mounting body.
　このような要求に対して、例えば、特許文献１に記載されている半導体装置が知られている。 In response to such a requirement, for example, a semiconductor device described in Patent Document 1 is known.
　以下、従来の半導体装置について図１１を参照しながら説明する。図１１は、従来の半導体装置の構成を示す側面断面図である。従来の半導体装置１００は、半導体チップ１０１が搭載されるチップ搭載部１０２、及びリード端子１０３となる端子部を備えたリードフレームと、チップ搭載部１０２に搭載され、端子部と電気的に接続された半導体チップ１０１とを有する。さらに端子部を半導体チップ１０１側の面である一方の面から他方の面に厚さ方向に貫通する貫通溝と、端子部の一方の面側の貫通溝の端部を塞ぐ蓋部１０４と、端子部の他方の面及び貫通溝の内側面を露出するように半導体チップ１０１を封止する樹脂部１０５と、を有し、端子部の他方の面及び貫通溝の内側面がメッキ膜１０６で被覆されている。この構成により、半導体装置１００のリード端子１０３の側面にハンダが付き易いとされている。このような構成を採用することにより、半導体装置１００のリード端子１０３の側面はハンダ濡れ性向上に寄与し、さらに半導体装置１００の実装体においてはハンダ接続強度向上を維持できるとしている。 Hereinafter, a conventional semiconductor device will be described with reference to FIG. FIG. 11 is a side sectional view showing a configuration of a conventional semiconductor device. A conventional semiconductor device 100 is mounted on a chip mounting portion 102 on which a semiconductor chip 101 is mounted, a lead frame having a terminal portion to be a lead terminal 103, and the chip mounting portion 102, and is electrically connected to the terminal portion. And a semiconductor chip 101. Furthermore, a through groove that penetrates the terminal portion from one surface that is the surface on the semiconductor chip 101 side to the other surface in the thickness direction, a lid portion 104 that closes an end portion of the through groove on one surface side of the terminal portion, A resin portion 105 for sealing the semiconductor chip 101 so as to expose the other surface of the terminal portion and the inner surface of the through groove, and the plating film 106 is the other surface of the terminal portion and the inner surface of the through groove. It is covered. With this configuration, it is assumed that solder is easily attached to the side surface of the lead terminal 103 of the semiconductor device 100. By adopting such a configuration, the side surface of the lead terminal 103 of the semiconductor device 100 contributes to the improvement of solder wettability, and further, the improvement of the solder connection strength can be maintained in the mounting body of the semiconductor device 100.
特開２０１３－２２５５９５号公報JP 2013-225595 A
　しかしながら上記の構成では、図１２に示すように、ハンダ接合部に厚み方向の応力ダメージが掛かった場合、半導体装置１００がプリント基板１０７から離反しようとする応力を完全に留めることができないため、半導体装置１００のオープン不良を招く恐れがある。 However, in the above configuration, as shown in FIG. 12, when the solder joint is subjected to stress damage in the thickness direction, the stress that the semiconductor device 100 tries to separate from the printed circuit board 107 cannot be completely retained. There is a risk of causing an open failure of the device 100.
　かかる点に鑑みて、本開示は、従来の半導体装置およびリード端子のサイズをほとんど変更することなく、プリント基板実装体のハンダ接続強度を大きく向上させることを課題とする。 In view of the above, an object of the present disclosure is to greatly improve the solder connection strength of a printed circuit board mounting body without substantially changing the sizes of conventional semiconductor devices and lead terminals.
　上記課題を解決するため本開示によって次のような解決手段を講じた。すなわち、半導体装置は、半導体チップと、半導体チップと電気的に接続される複数のリード端子と、半導体チップおよび前記複数のリード端子を封止する封止樹脂部とを備える。そして複数のリード端子は、頂面から見て封止樹脂部の最外周の辺で構成される方形の封止樹脂領域よりも内側に形成されている。そして複数のリード端子のうち少なくとも一つは、封止樹脂領域内において頂面が前記封止樹脂部から露出している頂面露出リード端子である。 In order to solve the above-mentioned problems, the present disclosure has taken the following solutions. That is, the semiconductor device includes a semiconductor chip, a plurality of lead terminals electrically connected to the semiconductor chip, and a sealing resin portion that seals the semiconductor chip and the plurality of lead terminals. The plurality of lead terminals are formed inside the rectangular sealing resin region formed by the outermost peripheral side of the sealing resin portion when viewed from the top surface. At least one of the plurality of lead terminals is a top surface exposed lead terminal having a top surface exposed from the sealing resin portion in the sealing resin region.
　このような半導体装置によると、プリント基板とハンダ接合する場合において、十分なハンダ接合強度を得ることができる。また、少なくとも１つのリード端子の頂面を露出させた頂面露出リード端子を配置すればよいため、リード端子のサイズを従来のものからほとんど変更する必要がない。 According to such a semiconductor device, sufficient solder bonding strength can be obtained when solder bonding is performed with a printed circuit board. In addition, since it is only necessary to arrange a top exposed lead terminal in which the top surface of at least one lead terminal is exposed, the size of the lead terminal hardly needs to be changed from the conventional one.
　また、上記半導体装置は、半導体チップが載置されるダイパッドを備えていてもよく、この場合、封止樹脂部は、半導体チップおよび複数のリード端子、ならびにダイパッドを封止すればよい。 In addition, the semiconductor device may include a die pad on which the semiconductor chip is placed. In this case, the sealing resin portion may seal the semiconductor chip, the plurality of lead terminals, and the die pad.
　なお、複数のリード端子の底面は封止樹脂部に覆われていなくてもよい。 Note that the bottom surfaces of the plurality of lead terminals may not be covered with the sealing resin portion.
　また、頂面露出リード端子は、当該半導体装置のコーナー部に位置していてもよい。 Moreover, the top surface exposed lead terminal may be located at a corner portion of the semiconductor device.
　このようにすると、最もストレスが集中する半導体装置のコーナー部のハンダ接合部のハンダ接合状態を強固にすることができるため、十分なハンダ接合強度を得ることができる。 In this case, since the solder joint state of the solder joint portion at the corner portion of the semiconductor device where stress is most concentrated can be strengthened, sufficient solder joint strength can be obtained.
　なお、頂面露出リード端子は、上記半導体装置の４つのコーナー部に配置されていてもよい。 Note that the top surface exposed lead terminals may be arranged at the four corners of the semiconductor device.
　また、頂面露出リード端子の、頂面、底面、および側面の少なくとも１つには、メッキ膜が被覆されていてもよい。 Further, a plating film may be coated on at least one of the top surface, the bottom surface, and the side surface of the top surface exposed lead terminal.
　このようにすると、ハンダ濡れ性が飛躍的に向上するため、プリント基板に半導体装置を実装する場合において、十分なハンダ接合強度を得ることができる。 In this case, since the solder wettability is remarkably improved, a sufficient solder joint strength can be obtained when a semiconductor device is mounted on a printed board.
　頂面露出リード端子の頂面は、当該半導体装置の中央部から外周部に向かって当該半導体装置の底面側に傾斜している。 The top surface of the top surface exposed lead terminal is inclined toward the bottom surface side of the semiconductor device from the central portion toward the outer peripheral portion of the semiconductor device.
　このようにすると、頂面露出リード端子の頂面側にハンダ材料が届き易くなり、濡れ拡がり面積の拡大および濡れ拡がり速度の向上が実現でき、ひいてはハンダフィレットが形成されやすくなる。 In this way, the solder material can easily reach the top surface side of the top surface exposed lead terminal, the wet spread area can be increased and the wet spread speed can be improved, and a solder fillet is easily formed.
　また、頂面露出リード端子の頂面には溝部または凹部が形成されていてもよい。 Moreover, a groove or a recess may be formed on the top surface of the top surface exposed lead terminal.
　このようにすると、頂面露出リード端子の頂面側にハンダ材料が接触した際に、いわゆる毛細管現象によりハンダ材料が溝部や凹部に沿って濡れ拡がるようになる。したがって、濡れ拡がり面積の拡大および濡れ拡がり速度の向上が実現でき、ひいてはハンダフィレットが形成されやすくなる。 In this way, when the solder material comes into contact with the top surface side of the top surface exposed lead terminal, the solder material spreads along the groove and the concave portion by a so-called capillary phenomenon. Accordingly, it is possible to increase the wet spread area and improve the wet spread speed, and as a result, solder fillets are easily formed.
　なお、溝部または凹部は、当該半導体装置の中央部から外周部に向かって形成されていてもよい。 Note that the groove or the recess may be formed from the center of the semiconductor device toward the outer periphery.
　また、頂面露出リード端子は、当該半導体装置の外周部において、当該半導体装置の底面よりも外側に湾曲した形状であってもよい。 Further, the top-surface exposed lead terminal may have a shape that is curved outward from the bottom surface of the semiconductor device at the outer peripheral portion of the semiconductor device.
　このようにすると、頂面露出リード端子のスタンドオフ高さが高く確保されることになり、そのためハンダ材料の厚みが必然的に増加し、より多くの歪を吸収できる構造となるため、接合強度の向上を図ることができる。また、スタンドオフ高さを高くすることにより、リフロー実装時におけるプリント基板の反りの影響を受けること無くハンダ接合実装が可能となる。これにより、プリント基板の反りによる半導体装置自身の製品持ち上がり現象や製品浮き現象を防止できるため、頂面露出リード端子を含むすべてのリード端子のオープン不良を防ぐことができる。 This ensures a high standoff height for the exposed lead terminal on the top surface, which inevitably increases the thickness of the solder material and allows the structure to absorb more strain. Can be improved. Further, by increasing the standoff height, it is possible to perform solder joint mounting without being affected by the warping of the printed circuit board during reflow mounting. As a result, the product lifting phenomenon and the product floating phenomenon of the semiconductor device due to the warping of the printed circuit board can be prevented, so that open defects of all lead terminals including the top exposed lead terminal can be prevented.
　また、頂面露出リード端子の最上面は、封止樹脂部の上面と同じ高さであってもよい。 Further, the top surface of the top exposed lead terminal may be the same height as the top surface of the sealing resin portion.
　本開示に係る半導体装置の実装体は、上記いずれか１つの半導体装置と、配線パターンを有するプリント基板と、半導体装置の複数のリード端子と配線パターンとを接続するハンダ材料とを備え、ハンダ材料は、半導体装置の前記頂面露出リード端子の頂面にも配置されている。 A mounting body of a semiconductor device according to the present disclosure includes any one of the semiconductor devices described above, a printed circuit board having a wiring pattern, and a solder material that connects a plurality of lead terminals and the wiring pattern of the semiconductor device. Are also arranged on the top surface of the top exposed lead terminal of the semiconductor device.
　これによると、半導体装置とプリント基板とを接続するハンダ材料の形状、いわゆるハンダフィレットを強固な形状とすることができ、信頼性の高い半導体装置の実装体を得ることができる。 According to this, the shape of the solder material for connecting the semiconductor device and the printed circuit board, that is, the so-called solder fillet can be made strong, and a highly reliable mounting body of the semiconductor device can be obtained.
　本開示に係る半導体装置の第１の製造方法は、以下に示す第１の工程～第６の工程を備えている。すなわち、複数のリード端子と半導体チップとを準備する第１の工程と、半導体チップと複数のリード端子とを金属細線により接合する第２の工程と、を備えている。そして複数のリード端子の少なくとも１つの頂面の一部に樹脂付着防止材料を載置する第３の工程と、複数のリード端子および半導体チップおよび金属細線を封止樹脂により封止する第４の工程と、を備えている。さらに樹脂付着防止材料を除去して、封止樹脂体を得る第５の工程と、封止樹脂体を個別に分割することによって、半導体装置を得る第６の工程とを備えている。 The first method for manufacturing a semiconductor device according to the present disclosure includes the following first to sixth steps. That is, the method includes a first step of preparing a plurality of lead terminals and a semiconductor chip, and a second step of joining the semiconductor chip and the plurality of lead terminals with a thin metal wire. Then, a third step of placing the resin adhesion preventing material on a part of at least one top surface of the plurality of lead terminals, and a fourth step of sealing the plurality of lead terminals, the semiconductor chip, and the fine metal wires with a sealing resin And a process. Furthermore, the resin adhesion preventing material is removed to provide a fifth step for obtaining a sealing resin body, and a sixth step for obtaining a semiconductor device by dividing the sealing resin body individually.
　また、本開示に係る半導体装置の第２の製造方法は、以下に示す第１の工程～第６の工程を備えている。すなわち、複数のリード端子と半導体チップとを準備する第１の工程と、半導体チップと複数のリード端子とを金属細線により接合する第２の工程と、を備えている。そして複数のリード端子の少なくとも１つの頂面の一部に樹脂付着防止材料を載置する第３の工程と、複数のリード端子および半導体チップおよび金属細線を封止樹脂で封止することによって成型される封止樹脂体を得る第４の工程と、を備えている。さらに封止樹脂体を個別に分割する第５の工程と、樹脂付着防止材料を除去することによって、半導体装置を得る第６の工程とを備えている。 Further, the second method for manufacturing a semiconductor device according to the present disclosure includes the following first to sixth steps. That is, the method includes a first step of preparing a plurality of lead terminals and a semiconductor chip, and a second step of joining the semiconductor chip and the plurality of lead terminals with a thin metal wire. Then, a third step of placing a resin adhesion preventing material on a part of at least one top surface of the plurality of lead terminals, and molding by sealing the plurality of lead terminals, the semiconductor chip, and the fine metal wires with a sealing resin And a fourth step of obtaining a sealing resin body to be performed. Furthermore, a fifth step of dividing the sealing resin body individually and a sixth step of obtaining a semiconductor device by removing the resin adhesion preventing material are provided.
　なお、上記各製造方法において、第１の工程では、複数のリード端子と、前記半導体チップを載置するダイパッドと、前記ダイパッドを支持する吊りリードとを有するリードフレームを準備してもよい。また、第１の工程と第２の工程との間において、前記半導体チップをダイパッド上に載置する第７の工程を備えていてもよい。 In each of the above manufacturing methods, in the first step, a lead frame having a plurality of lead terminals, a die pad for mounting the semiconductor chip, and a suspension lead for supporting the die pad may be prepared. Further, a seventh step of placing the semiconductor chip on the die pad may be provided between the first step and the second step.
　本開示に係る半導体装置およびその実装体は、半導体装置の表面側の封止樹脂を切り欠き、頂面を露出するリード端子を有することにより、リード端子のサイズをほとんど変更する必要がなく、プリント基板とのハンダ接合強度が向上するという効果を奏することができる。 The semiconductor device and the mounting body thereof according to the present disclosure have a lead terminal that cuts out the sealing resin on the surface side of the semiconductor device and exposes the top surface, so that there is almost no need to change the size of the lead terminal. The effect that the solder joint strength with the substrate is improved can be achieved.
図１は、第１の実施形態に係る半導体装置の構成を示す斜視図である。FIG. 1 is a perspective view showing the configuration of the semiconductor device according to the first embodiment. 図２Ａは、図１の半導体装置を頂面の方向から見た場合の図である。2A is a view of the semiconductor device of FIG. 1 when viewed from the top surface direction. 図２Ｂは、図２Ａの半導体装置をIIb-IIb線で切った場合の断面図である。2B is a cross-sectional view of the semiconductor device of FIG. 2A taken along the line IIb-IIb. 図２Ｃは、図１の半導体装置を底面から見た場合の図である。2C is a view of the semiconductor device of FIG. 1 when viewed from the bottom. 図３Ａは、第１の実施形態に係る半導体装置の他の例を頂面の方向から見た場合の図である。FIG. 3A is a view of another example of the semiconductor device according to the first embodiment when viewed from the top surface direction. 図３Ｂは、第１の実施形態に係る半導体装置の他の例を頂面の方向から見た場合の図である。FIG. 3B is a diagram of another example of the semiconductor device according to the first embodiment viewed from the top surface direction. 図４は、図１に示す半導体装置の実装体の断面図である。4 is a cross-sectional view of the mounting body of the semiconductor device shown in FIG. 図５は、図１に示す半導体装置と従来の半導体装置との製造フローを比較した断面図である。FIG. 5 is a cross-sectional view comparing manufacturing flows of the semiconductor device shown in FIG. 1 and a conventional semiconductor device. 図６は、第２の実施形態に係る半導体装置と従来の半導体装置との製造フローを比較するためのした断面図である。FIG. 6 is a cross-sectional view for comparing manufacturing flows of the semiconductor device according to the second embodiment and a conventional semiconductor device. 図７は、第３の実施形態に係る半導体装置を備えた実装体の側面断面図である。FIG. 7 is a side cross-sectional view of a mounting body including a semiconductor device according to the third embodiment. 図８Ａは、第４の実施形態に係る半導体装置の一例を頂面の方向から見た場合の主要部を示す図である。FIG. 8A is a diagram illustrating a main part when an example of the semiconductor device according to the fourth embodiment is viewed from the top surface direction. 図８Ｂは、第４の実施形態に係る半導体装置の一例を頂面の方向から見た場合の主要部を示す図である。FIG. 8B is a diagram illustrating a main part when an example of the semiconductor device according to the fourth embodiment is viewed from the top surface direction. 図８Ｃは、図８Ａの半導体装置をVIIIc-VIIIc線で切った場合の断面図である。8C is a cross-sectional view of the semiconductor device of FIG. 8A taken along the line VIIIc-VIIIc. 図８Ｄは、図８Ｂの半導体装置をVIIId-VIIId線で切った場合の断面図である。8D is a cross-sectional view of the semiconductor device of FIG. 8B taken along line VIIId-VIIId. 図９は、第５の実施形態に係る半導体装置を備えた実装体の側面断面図である。FIG. 9 is a side cross-sectional view of a mounting body including a semiconductor device according to the fifth embodiment. 図１０は、第６の実施形態に係る半導体装置を備えた実装体の側面断面図である。FIG. 10 is a side cross-sectional view of a mounting body including a semiconductor device according to the sixth embodiment. 図１１は、従来の半導体装置の構成を示す側面断面図である。FIG. 11 is a side sectional view showing a configuration of a conventional semiconductor device. 図１２は、従来の半導体装置の課題を説明するための図である。FIG. 12 is a diagram for explaining a problem of a conventional semiconductor device.
　以下、本発明の実施形態について図面を参照しながら説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　＜第１の実施形態＞
　図１は、第１の実施形態に係る半導体装置の斜視図である。 <First Embodiment>
FIG. 1 is a perspective view of the semiconductor device according to the first embodiment.
　図１に示すように、本実施形態の半導体装置１１は、半導体チップ１２と、半導体チップ１２が載置されたダイパッド１３と、金属細線１４により半導体チップ１２と電気的に接続された複数のリード端子１５と、を有している。そして、半導体チップ１２およびダイパッド１３および金属細線１４およびリード端子１５の少なくとも一部分を封止する封止樹脂部１６を有している。 As shown in FIG. 1, the semiconductor device 11 of the present embodiment includes a semiconductor chip 12, a die pad 13 on which the semiconductor chip 12 is placed, and a plurality of leads electrically connected to the semiconductor chip 12 by metal thin wires 14. And a terminal 15. And it has the sealing resin part 16 which seals at least one part of the semiconductor chip 12, the die pad 13, the metal fine wire 14, and the lead terminal 15.
　半導体装置１１は、その頂面方向から見ると、封止樹脂部１６の樹脂領域よりも内側に複数のリード端子１５が形成されている、いわゆるＱＦＮ（Quad-Flat-Non-Lead）パッケージと呼ばれる樹脂封止型半導体装置である。そして、少なくとも１本以上のリード端子１５の頂面の一部分が封止樹脂部１６から露出している構造を特徴としている。 The semiconductor device 11 is called a so-called QFN (Quad-Flat-Non-Lead) package in which a plurality of lead terminals 15 are formed inside the resin region of the sealing resin portion 16 when viewed from the top surface direction. This is a resin-encapsulated semiconductor device. A feature is that a part of the top surface of at least one lead terminal 15 is exposed from the sealing resin portion 16.
　一般にＱＦＮパッケージは方形であり、通常のＱＦＮパッケージでは、頂面側から見た場合、半導体装置の裏面側に配置されたリード端子は封止樹脂に覆われており、リード端子の上面は封止樹脂から露出していない。 In general, the QFN package has a rectangular shape. In the normal QFN package, when viewed from the top surface side, the lead terminals arranged on the back surface side of the semiconductor device are covered with sealing resin, and the top surface of the lead terminal is sealed. Not exposed from the resin.
　これに対して、本実施形態では、方形のＱＦＮパッケージにおいて、頂面側から見た場合、封止樹脂領域内にリード端子の頂面方向の一部分が封止樹脂から露出している構造となっている。すなわち、半導体装置１１の裏面側に配置されたリード端子１５において、半導体装置１１の外周部（封止樹脂領域の外周部）に沿った上面に封止樹脂部１６の切り欠き部３０が存在する構造である。 On the other hand, in this embodiment, when viewed from the top surface side in the square QFN package, a part of the lead terminal in the top surface direction is exposed from the sealing resin in the sealing resin region. ing. That is, in the lead terminal 15 disposed on the back surface side of the semiconductor device 11, the cutout portion 30 of the sealing resin portion 16 exists on the upper surface along the outer peripheral portion (the outer peripheral portion of the sealing resin region) of the semiconductor device 11. Structure.
　なお、封止樹脂領域とは、封止樹脂部１６とリード端子１５とで形成される半導体装置１１の底面に等しい方形領域、或いは、封止樹脂部１６の最外周を構成する辺で形成される方形領域である。ここで、複数のリード端子１５のうち、頂面が封止樹脂部１６から露出しているリード端子１５を、特に頂面露出リード端子１７とする。 The sealing resin region is formed by a rectangular region equal to the bottom surface of the semiconductor device 11 formed by the sealing resin portion 16 and the lead terminal 15 or by a side constituting the outermost periphery of the sealing resin portion 16. This is a square area. Here, among the plurality of lead terminals 15, the lead terminal 15 whose top surface is exposed from the sealing resin portion 16 is particularly referred to as a top surface exposed lead terminal 17.
　つまり、符号１５は、頂面が封止樹脂部１６に覆われているリード端子を表し、符号１７は、本開示の頂面露出リード端子を表す。 That is, reference numeral 15 represents a lead terminal whose top surface is covered with the sealing resin portion 16, and reference numeral 17 represents a top exposed lead terminal of the present disclosure.
　リード端子１５の端子巾が約０．１～０．４ｍｍ、端子ピッチが約０．４～１．２７ｍｍ間隔が多いが、近年のＱＦＮパッケージの小型化にともない、端子巾は０．１５～０．２ｍｍ、端子ピッチは０．４～０．６５ｍｍ間隔のものが主流である。 The lead terminal 15 has a terminal width of about 0.1 to 0.4 mm and a terminal pitch of about 0.4 to 1.27 mm, and the terminal width is 0.15 to 0 with the recent miniaturization of the QFN package. .2mm and terminal pitch is 0.4 to 0.65mm.
　図２Ａ～図２Ｃは、図１の半導体装置を複数の方向から見た場合の図である。図２Ａは、半導体装置の頂面側から見た平面図、図２Ｂは、図２Ａの半導体装置をIIｂ－IIｂ線で切った場合の断面図、図２Ｃは、半導体装置の底面側から見た平面図である。 2A to 2C are diagrams of the semiconductor device of FIG. 1 when viewed from a plurality of directions. 2A is a plan view as viewed from the top surface side of the semiconductor device, FIG. 2B is a cross-sectional view of the semiconductor device of FIG. 2A taken along the line IIb-IIb, and FIG. 2C is as viewed from the bottom surface side of the semiconductor device. It is a top view.
　図２Ｃに示すように、半導体装置１１の底面では頂面露出リード端子１７を含むすべてのリード端子１５，１７の底面が露出しており、外見上は従来のＱＦＮパッケージと何ら変わることは無い。 As shown in FIG. 2C, the bottom surfaces of all the lead terminals 15 and 17 including the top surface exposed lead terminals 17 are exposed on the bottom surface of the semiconductor device 11, and the appearance is not different from the conventional QFN package.
　一方、図２Ａに示すように、半導体装置１１を頂面側から見た場合、半導体装置１１の外周部側の封止樹脂部１６の一部に切り欠き部３０が形成されており、切り欠き部３０からリード端子の頂面が露出している（頂面露出リード端子１７）。 On the other hand, as shown in FIG. 2A, when the semiconductor device 11 is viewed from the top surface side, a notch 30 is formed in a part of the sealing resin portion 16 on the outer peripheral side of the semiconductor device 11. The top surface of the lead terminal is exposed from the portion 30 (top surface exposed lead terminal 17).
　また、図２Ｂに示すように、半導体装置１１を側面側から見た場合、通常のリード端子１５の頂面は封止樹脂部１６によって完全に覆われているのに対して、頂面露出リード端子１７は、半導体装置１１のコーナー部、及び側面部において、半導体装置１１の外周部側の頂面の一部が露出している。 Further, as shown in FIG. 2B, when the semiconductor device 11 is viewed from the side, the top surface of the normal lead terminal 15 is completely covered with the sealing resin portion 16, whereas the top surface exposed lead In the terminal 17, a part of the top surface on the outer peripheral side of the semiconductor device 11 is exposed at the corner portion and the side surface portion of the semiconductor device 11.
　頂面露出リード端子１７の露出部分が、後述するリフロー実装工程においてプリント基板１８の配線パターン１９とハンダ接続するものである（図４参照）。 The exposed portion of the top surface exposed lead terminal 17 is to be soldered to the wiring pattern 19 of the printed circuit board 18 in a reflow mounting process described later (see FIG. 4).
　図３Ａおよび図３Ｂは、第１実施形態の他の例を示す頂面側から見た平面図である。図１および図２において、頂面露出リード端子１７を、半導体装置１１の外周部のうち、コーナー部とそのコーナー部に隣接する側面部に設置した一例を記載している。しかしながらこれら一例に限らず、例えば、図３Ａに示すように、頂面露出リード端子１７をコーナー部のみに設けても良く、図３Ｂに示すように、側面部のみに設けてもよい。 3A and 3B are plan views seen from the top side showing another example of the first embodiment. In FIG. 1 and FIG. 2, an example is described in which the top exposed lead terminals 17 are installed in a corner portion and a side portion adjacent to the corner portion in the outer peripheral portion of the semiconductor device 11. However, the present invention is not limited to these examples. For example, as shown in FIG. 3A, the top surface exposed lead terminal 17 may be provided only in the corner portion, or may be provided only in the side surface portion as shown in FIG. 3B.
　通常、半導体装置のコーナー部のハンダ接合部に最もストレスが集中することが知られているため、後述する半導体装置１１の実装体２０において、このコーナー部に頂面露出リード端子１７を設置して、ハンダ接合状態を強固にすることは、信頼性向上に最も効果的であるといえる。 Usually, it is known that stress is concentrated most at the solder joint portion of the corner portion of the semiconductor device. Therefore, in the mounting body 20 of the semiconductor device 11 to be described later, a top exposed lead terminal 17 is installed at this corner portion. It can be said that strengthening the solder joint state is most effective for improving the reliability.
　一方、近年の半導体装置の多機能化にともないリード端子は多ピン化傾向にあり、リード端子の数量を極力多く設置する工夫が必要である。この場合、頂面の面積が大きなリード端子をコーナー部に設けるよりも、側面部と同じ面積のリード端子を多数設置することが望ましいといえる。 On the other hand, with the recent increase in the number of functions of semiconductor devices, the number of lead terminals tends to be increased, and it is necessary to devise a way to install as many lead terminals as possible. In this case, it can be said that it is desirable to install a large number of lead terminals having the same area as that of the side surface portion rather than providing a lead terminal having a large top surface area at the corner portion.
　以上の理由のほか、後述するプリント基板の配線パターンとの接合難易度、半導体装置の製造難易度、半導体装置の製造費用などを鑑み、頂面露出リード端子１７を、半導体装置１１の４つのコーナー部に設けてもよいし、対角線上の２つのコーナー部に設けてもよい。また、側面部における全リード端子１５の上面の一部を露出させて頂面露出リード端子１７としてもよい。また、一側面側のみに頂面露出リード端子１７を設けてもよく、頂面露出リード端子１７とリード端子１５とを交互に設けてもよい。また、頂面露出リード端子１７を、コーナー部および側面部のいずれか一方に設けてもよいし、両方に設けてもよい。つまり、複数のリード端子１５のうち少なくとも１つが頂面露出リード端子１７であればよい。 In addition to the above reasons, the top exposed lead terminal 17 is connected to the four corners of the semiconductor device 11 in view of difficulty in joining with a wiring pattern of a printed circuit board to be described later, difficulty in manufacturing a semiconductor device, manufacturing cost of the semiconductor device, and the like. You may provide in a part and may provide in two corner parts on a diagonal. Alternatively, the top exposed lead terminal 17 may be formed by exposing a part of the upper surface of all the lead terminals 15 in the side surface portion. Further, the top exposed lead terminals 17 may be provided only on one side surface, or the top exposed lead terminals 17 and the lead terminals 15 may be provided alternately. Moreover, the top surface exposed lead terminal 17 may be provided on either one of the corner portion or the side surface portion, or may be provided on both. That is, at least one of the plurality of lead terminals 15 may be the top surface exposed lead terminal 17.
　図４は、図１の半導体装置を用いた実装体の断面図である。図４に示すように、プリント基板１８の配線パターン１９にハンダペースト（図示せず）を塗布する。そして、そのハンダペーストと半導体装置１１のリード端子１５及び頂面露出リード端子１７とを対面位置合わせして載置し、リフロー装置などで高温加熱することにより本開示の半導体装置１１の実装体２０が完成する。 FIG. 4 is a cross-sectional view of a mounting body using the semiconductor device of FIG. As shown in FIG. 4, a solder paste (not shown) is applied to the wiring pattern 19 of the printed circuit board 18. Then, the solder paste and the lead terminal 15 and the top exposed lead terminal 17 of the semiconductor device 11 are placed in face-to-face alignment and heated at a high temperature with a reflow device or the like, thereby mounting the package 20 of the semiconductor device 11 of the present disclosure. Is completed.
　頂面露出リード端子１７の底面側は、ハンダ材料２１によりプリント基板１８の配線パターン１９と広くハンダ合金接続されるため電気信号を安定的に需給することができる。さらに、頂面露出リード端子１７の頂面側は、ハンダ材料２１によりプリント基板１８の配線パターン１９に押し付けられるようにハンダ合金接続されるため実装強度を高く維持することができる。 Since the bottom surface side of the top exposed lead terminal 17 is widely connected to the wiring pattern 19 of the printed circuit board 18 by the solder material 21, it can stably supply and demand electrical signals. Further, since the top surface side of the top surface exposed lead terminal 17 is connected to the solder alloy so as to be pressed against the wiring pattern 19 of the printed circuit board 18 by the solder material 21, the mounting strength can be maintained high.
　通常、プリント基板は厚みが０．５ｍｍ～２．０ｍｍ程度のものが多く、その層構成は、導体層が片方の面にのみ存在する片面基板、導体層が表裏両方の面に存在する２層両面基板、導体層が内蔵されている多層基板、あるいはビルドアップ工法を用いた高密度配線基板などがある。これらのプリント基板は、半導体装置の配線密度ルールや放熱性、使用するセット機器の世代など、必要に応じて使い分けられる。 Usually, printed circuit boards often have a thickness of about 0.5mm to 2.0mm, and the layer structure consists of a single-sided board where the conductor layer exists only on one side and two layers where the conductive layer exists on both the front and back sides. There are a double-sided board, a multilayer board with a built-in conductor layer, and a high-density wiring board using a build-up method. These printed circuit boards are selectively used as necessary, such as the wiring density rule of semiconductor devices, heat dissipation, and the generation of set equipment to be used.
　また、ハンダペースト材料は、リフロー加熱装置への負担や半導体装置の耐熱性を考慮し、最高温度がおよそ２６０℃近傍までで溶融するのが望ましい。近年の環境問題を鑑みると、例えばＳｎ，Ａｇ，Ｃｕを代表とする鉛フリーハンダペーストが一般的に使用されていることが多い。 Also, it is desirable that the solder paste material melts at a maximum temperature of about 260 ° C. in consideration of the burden on the reflow heating device and the heat resistance of the semiconductor device. In view of recent environmental problems, for example, lead-free solder pastes such as Sn, Ag, and Cu are generally used in many cases.
　半導体装置１１をプリント基板１８へハンダ付けを行う、いわゆるリフロー実装においては、リフローの際の高温加熱とリフロー完了後の常温さらしにより、実装体２０の様々な箇所で膨張や収縮が起こりうる。 In so-called reflow mounting in which the semiconductor device 11 is soldered to the printed circuit board 18, expansion and contraction can occur at various locations of the mounting body 20 due to high-temperature heating during reflow and exposure to normal temperature after completion of reflow.
　このことを図４に示す実装体２０で説明すると、半導体装置１１の厚みや平面方向のサイズ、リード端子１５および頂面露出リード端子１７や封止樹脂部１６やハンダ材料２１やプリント基板１８が持つ熱膨張係数などの物性スペック値、それぞれの加工方法、お互いを接続する製造フローや接続条件などにより、実装体２０は膨張と収縮の応力負荷を受ける。そのため、半導体装置１１とプリント基板１８とを接合しているハンダ材料２１には、特に大きな負荷がかかっている。 This will be described with reference to the mounting body 20 shown in FIG. 4. The thickness of the semiconductor device 11 and the size in the planar direction, the lead terminal 15, the top exposed lead terminal 17, the sealing resin portion 16, the solder material 21, and the printed board 18 The mounting body 20 is subjected to expansion and contraction stress loads depending on the physical property specification values such as the thermal expansion coefficient, the respective processing methods, the manufacturing flow and the connection conditions for connecting each other. Therefore, a particularly large load is applied to the solder material 21 that joins the semiconductor device 11 and the printed circuit board 18.
　さらに、ＱＦＮパッケージのようにリード端子とプリント基板との距離が短い場合は、ガルウイングリードを持つＱＦＰ（Quad-Flat-Package）のように応力緩和が出来る構造ではないため、ハンダ材料２１に大きな負荷がかかることは明らかである。 Further, when the distance between the lead terminal and the printed circuit board is short as in the QFN package, the structure is not capable of stress relaxation as in the QFP (Quad-Flat-Package) with the gull wing leads, so a large load is applied to the solder material 21. It is clear that it takes.
　また、近年、自動車や航空機器の電子化により実装信頼性の向上が強く求められてきている。また、一般ユーザーの不注意な取り扱いによる携帯電子機器の落下衝撃や折り曲げストレス、そして電子機器を包む筺体自身の簡素化などにより、筺体内部の実装体２０には、従来とは比較にならないほどのストレスが加わることが多く、電気的なオープン不良を引き起こすことは容易に想像できる。 In recent years, there has been a strong demand for improved mounting reliability through the digitization of automobiles and aircraft equipment. In addition, due to the drop impact and bending stress of portable electronic devices due to careless handling by general users, and the simplification of the housing itself that wraps the electronic devices, the mounting body 20 inside the housing is not comparable to the conventional one. It is often stressed and it can be easily imagined that electrical open defects are caused.
　その影響をもっとも受けやすいのが、図４に示す、半導体装置１１とプリント基板１８とを接続するハンダ材料２１に係る部分である。したがって、このハンダ材料２１の形状、いわゆるハンダフィレットを強固な形状とすることで、上述の実装体２０の信頼性を向上させることができるのは言うまでも無い。 The portion most susceptible to the influence is a portion related to the solder material 21 connecting the semiconductor device 11 and the printed board 18 shown in FIG. Therefore, it goes without saying that the reliability of the mounting body 20 described above can be improved by making the shape of the solder material 21, that is, a so-called solder fillet, into a firm shape.
　本実施形態では、半導体チップ１２の電極（図示せず）とリード端子１５とを電気的に接続する手段として、半導体チップ１２の電極が頂面側に向いている、いわゆるフェースアップ方式の半導体チップ１２と金属細線１４を用いた例を挙げている。これに対して、半導体チップ１２の電極が底面側に向いている、いわゆるフェースダウン方式であってもよい。例えば、フリップチップ接合を利用してバンプを介在させたり、共晶合金の形成による直接接合などにより半導体チップ１２の電極とリード端子１５とを電気的に接続したりしてもよい。 In this embodiment, as a means for electrically connecting an electrode (not shown) of the semiconductor chip 12 and the lead terminal 15, a so-called face-up type semiconductor chip in which the electrode of the semiconductor chip 12 faces the top surface side. 12 and a thin metal wire 14 are used. On the other hand, a so-called face-down method in which the electrodes of the semiconductor chip 12 face the bottom surface may be used. For example, bumps may be interposed using flip chip bonding, or the electrodes of the semiconductor chip 12 and the lead terminals 15 may be electrically connected by direct bonding by forming a eutectic alloy or the like.
　金属細線１４としては、アルミニウム細線、金線などを用いることができる。 As the fine metal wire 14, an aluminum fine wire, a gold wire, or the like can be used.
　本実施形態では、半導体チップ１２を載置するダイパッド１３の底面には封止樹脂部１６は存在せず、ダイパッド１３の底面が露出している。ダイパッド１３は半導体チップ１２を支持する役割のほか、半導体チップ１２から発する熱を効率良く放出する役割も担っている。そのため、ハンダ材料２１によりプリント基板１８とハンダ接続することにより、半導体チップ１２の放熱性を高めることができ、半導体チップ１２の機能の安定化を維持することができる。 In this embodiment, the sealing resin portion 16 does not exist on the bottom surface of the die pad 13 on which the semiconductor chip 12 is placed, and the bottom surface of the die pad 13 is exposed. In addition to supporting the semiconductor chip 12, the die pad 13 also plays a role of efficiently releasing heat generated from the semiconductor chip 12. Therefore, by soldering the printed circuit board 18 with the solder material 21, the heat dissipation of the semiconductor chip 12 can be enhanced, and the function of the semiconductor chip 12 can be kept stable.
　また、ダイパッド１３の底面を封止樹脂部１６で覆い隠す、いわゆるダイパッドアップセット方式のＱＦＮパッケージに対して、本実施形態を適用してもよい。また、ダイパッド１３を用いずに、リード端子１５の一部を絶縁化しその絶縁体の上で半導体チップ１２を支持してもよい。また、絶縁樹脂テープを設けてその絶縁樹脂テープの上に半導体チップ１２を搭載してもよい。すなわち、ダイパッド１３を用いる場合に替えて、ダイパッドレスリードフレームに対して本実施形態を適用してもよい。 Further, the present embodiment may be applied to a so-called die pad upset QFN package in which the bottom surface of the die pad 13 is covered with the sealing resin portion 16. Further, without using the die pad 13, a part of the lead terminal 15 may be insulated and the semiconductor chip 12 may be supported on the insulator. Further, an insulating resin tape may be provided and the semiconductor chip 12 may be mounted on the insulating resin tape. That is, this embodiment may be applied to a die padless lead frame instead of using the die pad 13.
　本実施形態における頂面露出リード端子１７を含むすべてのリード端子１５およびダイパッド１３は、製造上の利点により、同一のリードフレームによって形成されていてもよいが、必ずしも同一でなくてもよい。例えば、放熱性の向上を追及するなどの理由により、異なる材質や異なる製造工法で製造したリード端子とダイパッドを、のちの工程で合体形成する工法で準備してもよい。 In the present embodiment, all the lead terminals 15 and the die pad 13 including the top surface exposed lead terminals 17 may be formed by the same lead frame due to manufacturing advantages, but may not necessarily be the same. For example, for the purpose of pursuing improvement in heat dissipation, a lead terminal and a die pad manufactured by different materials or by different manufacturing methods may be prepared by a method of combining and forming in a later step.
　本実施形態におけるリードフレームは、銅（Ｃｕ）素材のフレームに、下地メッキとしてニッケル（Ｎｉ）層が、その上にパラジウム（Ｐｄ）層が、最上層に薄膜の金（Ａｕ）層が、それぞれメッキされた３層の金属メッキの場合を例に挙げている。ただし、銅（Ｃｕ）素材以外にも、例えば、鉄（Ｆｅ）系素材、４２アロイ素材を使用してもよい。また、ニッケル（Ｎｉ）、パラジウム（Ｐｄ）、金（Ａｕ）以外の貴金属メッキが施されても良く、かならずしも３層メッキでなくてもよい。 In this embodiment, the lead frame has a copper (Cu) material frame, a nickel (Ni) layer as a base plating, a palladium (Pd) layer thereon, and a thin gold (Au) layer as an uppermost layer. The case of the plated three-layer metal plating is taken as an example. However, in addition to the copper (Cu) material, for example, an iron (Fe) material or a 42 alloy material may be used. Moreover, noble metal plating other than nickel (Ni), palladium (Pd), and gold (Au) may be applied, and it is not always necessary to use three-layer plating.
　さらに、メッキ膜を被覆する工程は、半導体チップ１２をダイパッド１３に載置する以前に行う、いわゆるプリメッキ（前メッキ）工法でもよい。また、半導体装置１１が樹脂封止された以降にメッキ膜の被覆を行う、いわゆる後メッキ工法でもよい。 Furthermore, the step of coating the plating film may be a so-called pre-plating (pre-plating) method performed before placing the semiconductor chip 12 on the die pad 13. Further, a so-called post-plating method in which the plating film is coated after the semiconductor device 11 is sealed with resin may be used.
　次に、本実施形態の半導体装置１１の製造方法について、図５を参照しながら説明する。図５は、図１に示す半導体装置と従来の半導体装置との製造フローを比較するための図である。図５の工程Ａ～工程Ｄにおいて、一点鎖線の左側が本実施形態の半導体装置の製造フローを示す断面図であり、右側が従来の半導体装置の製造フローを示す断面図である。 Next, a method for manufacturing the semiconductor device 11 of this embodiment will be described with reference to FIG. FIG. 5 is a diagram for comparing the manufacturing flow between the semiconductor device shown in FIG. 1 and a conventional semiconductor device. In Step A to Step D of FIG. 5, the left side of the alternate long and short dash line is a cross-sectional view showing the manufacturing flow of the semiconductor device of the present embodiment, and the right side is a cross-sectional view showing the manufacturing flow of the conventional semiconductor device.
　まず、図５の工程Ａに示すように、半導体チップ１２と、半導体チップ１２が接着剤、いわゆるダイボンド材によって接着載置されたダイパッド１３と、金属細線１４により半導体チップ１２と電気的に接続されたリード端子１５と、が設けられているリードフレーム２２を準備する。なお、ダイパッド１３は吊りリードによって支持されているが、図５中の断面には図示していない。また、吊りリードには厚み方向に曲げ加工がなされ、いわゆるディプレス部が形成されており、後述の封止樹脂によって一部分が覆われる構造となっている。また、リードフレーム２２の材質、リードフレーム２２の表面に被覆されるメッキ膜、半導体チップ１２の向き、金属細線１４の種類については前述の通りである。 First, as shown in step A of FIG. 5, the semiconductor chip 12, the semiconductor chip 12 is electrically connected to the semiconductor chip 12 by a metal pad 14, and a die pad 13 on which the semiconductor chip 12 is bonded and mounted by an adhesive, so-called die bonding material. A lead frame 22 provided with the lead terminals 15 is prepared. Although the die pad 13 is supported by the suspension leads, it is not shown in the cross section in FIG. Further, the suspension lead is bent in the thickness direction to form a so-called depressed portion, and a part of the suspension lead is covered with a sealing resin described later. The material of the lead frame 22, the plating film coated on the surface of the lead frame 22, the direction of the semiconductor chip 12, and the type of the fine metal wires 14 are as described above.
　次に、図５の工程Ｂでは、後の工程により頂面露出リード端子１７となるリード端子１５の頂面に樹脂付着防止ピン２３を接触させる。なお、従来の製造フローでは、この工程は存在しない。また、封止樹脂部１６に被覆される通常のリード端子１５の頂面には樹脂付着防止ピン２３を設けない。 Next, in the process B of FIG. 5, the resin adhesion preventing pin 23 is brought into contact with the top surface of the lead terminal 15 that becomes the top surface exposed lead terminal 17 in the subsequent process. Note that this process does not exist in the conventional manufacturing flow. Further, the resin adhesion preventing pin 23 is not provided on the top surface of the normal lead terminal 15 covered with the sealing resin portion 16.
　樹脂付着防止ピン２３は、樹脂封止時に、頂面露出リード端子１７の頂面に封止樹脂が回り込まないようにするマスクの役割を果たすためのものである。つまり、この樹脂付着防止ピン２３の存在によって頂面露出リード端子１７の頂面に封止樹脂バリが形成されるのを防止することができる。そして図５の工程Ｂは、最終的には本開示の半導体装置１１の頂面露出リード端子１７の構造を決する重要な工程となるのである。この樹脂付着防止ピン２３は、樹脂封止用金型に併設されており、封止樹脂を注入する前に頂面露出リード端子１７に接触し、封止樹脂が硬化した後に取り外しが出来る構造となっている。また、樹脂封止用金型の費用抑制などのため、必ずしも樹脂封止用金型に併設されるものでは無く、後述のように樹脂封止時の高温環境に耐性があり、樹脂封止硬化完了後もしくは個別ダイシング後に取り外し、あるいは消滅する材質であってもよい。つまり、樹脂付着防止ピン２３を任意の方法により除去できればよい。 The resin adhesion prevention pin 23 serves as a mask that prevents the sealing resin from entering the top surface of the top surface exposed lead terminal 17 during resin sealing. That is, the presence of the resin adhesion preventing pin 23 can prevent the sealing resin burr from being formed on the top surface of the top surface exposed lead terminal 17. Then, the process B in FIG. 5 is an important process that finally determines the structure of the top exposed lead terminal 17 of the semiconductor device 11 of the present disclosure. The resin adhesion prevention pin 23 is provided in the mold for resin sealing and has a structure that can be removed after the sealing resin is cured by contacting the top exposed lead terminal 17 before injecting the sealing resin. It has become. In addition, it is not necessarily attached to the resin sealing mold to reduce the cost of the resin sealing mold, and is resistant to the high temperature environment at the time of resin sealing as will be described later. The material may be removed or disappear after completion or after individual dicing. That is, the resin adhesion preventing pin 23 may be removed by any method.
　なお、本実施形態では、この樹脂付着防止ピン２３が接触している頂面露出リード端子１７には金属細線１４が接続され、電気的に有効な信号ピンとして図示しているが、例えば半導体装置１１の４隅のコーナー部に位置するリード端子、いわゆる補強ランドのみを頂面露出リード端子１７とし、樹脂付着防止ピン２３を接触させてもよい。すなわち、複数のリード端子１５のうち少なくとも１つの頂面に、樹脂付着防止ピン２３を接触させればよい。 In the present embodiment, the fine metal wires 14 are connected to the top surface exposed lead terminals 17 that are in contact with the resin adhesion preventing pins 23 and are shown as electrically effective signal pins. 11, only lead terminals located at the four corners, so-called reinforcing lands, may be used as the top exposed lead terminals 17, and the resin adhesion preventing pins 23 may be brought into contact with each other. That is, the resin adhesion preventing pin 23 may be brought into contact with at least one top surface of the plurality of lead terminals 15.
　次に、図５の工程Ｃで、封止樹脂を注入して、半導体チップ１２、金属細線１４、ダイパッド１３の一部、頂面露出リード端子１７の頂面の一部を除くすべてのリード端子１５の頂面を封止する封止樹脂部１６を形成する。 Next, in step C of FIG. 5, all lead terminals except for the semiconductor chip 12, the fine metal wires 14, part of the die pad 13, and part of the top face of the top exposed lead terminal 17 are injected with sealing resin. A sealing resin portion 16 for sealing the top surface of 15 is formed.
　最後に、図５の工程Ｄで、頂面露出リード端子１７に接触していた樹脂付着防止ピン２３を取り外し、ダイシングソー２５などにより個別に分割することにより半導体装置１１が完成する。この工程において、樹脂付着防止ピン２３を除去することにより、封止樹脂部１６に切り欠き部３０が形成される。 Finally, in step D of FIG. 5, the resin adhesion preventing pins 23 that have been in contact with the top exposed lead terminals 17 are removed and divided individually by a dicing saw 25 or the like to complete the semiconductor device 11. In this step, the notch portion 30 is formed in the sealing resin portion 16 by removing the resin adhesion preventing pin 23.
　半導体装置１１は、頂面方向から見ると封止樹脂部１６の樹脂領域よりも内側にリード端子１５が形成されている、いわゆるＱＦＮパッケージと呼ばれる樹脂封止型半導体装置である。すなわち、少なくとも１本以上のリード端子１５の頂面方向の一部分が封止樹脂部１６から露出している構造（頂面露出リード端子１７）を持つ樹脂封止型の半導体装置１１が完成する。 The semiconductor device 11 is a resin-encapsulated semiconductor device called a so-called QFN package in which the lead terminals 15 are formed inside the resin region of the encapsulating resin portion 16 when viewed from the top surface direction. That is, the resin-encapsulated semiconductor device 11 having a structure (a top exposed lead terminal 17) in which at least a part of at least one lead terminal 15 in the top surface direction is exposed from the sealing resin portion 16 is completed.
　なお、先に述べたとおり、半導体装置１１が樹脂封止されたあとにメッキ膜を被覆する、いわゆる後メッキ工法を用いれば、本開示の頂面露出リード端子１７の頂面側の露出面や底面側の露出面にメッキ膜が形成されるのはもちろんである。さらに、ダイシングソー２５による切断で金属素材が剥き出しとなっている頂面露出リード端子１７を含むすべてのリード端子１５の側面側にもメッキ膜が形成することが可能となるため、ハンダ濡れ性が飛躍的に向上する。 Note that, as described above, if a so-called post-plating method for covering the plating film after the semiconductor device 11 is sealed with resin is used, the exposed surface on the top surface side of the top surface exposed lead terminal 17 of the present disclosure, Of course, a plating film is formed on the exposed surface on the bottom side. Further, since the plating film can be formed on the side surfaces of all the lead terminals 15 including the top surface exposed lead terminals 17 where the metal material is exposed by cutting with the dicing saw 25, the solder wettability is improved. Improve dramatically.
　なお、本実施形態では、リードフレーム２２を備えている半導体装置１１の製造方法の例を示したが、本開示の製造方法はリードフレーム２２を用いる場合に限定されるものでない。本開示の基本的な概念である頂面露出リード端子１７の形状は、半導体チップを搭載しリード端子を持つ半導体装置全般に適用できるものであり、例えば、基板タイプ、ＴＡＢタイプ、セラミックタイプなど広く応用することが可能である。 In the present embodiment, an example of a manufacturing method of the semiconductor device 11 including the lead frame 22 has been described. However, the manufacturing method of the present disclosure is not limited to the case where the lead frame 22 is used. The shape of the top exposed lead terminal 17 that is a basic concept of the present disclosure is applicable to all semiconductor devices having a semiconductor chip mounted and having a lead terminal. For example, the substrate type, TAB type, ceramic type, etc. are widely used. It is possible to apply.
　＜第２の実施形態＞
　図６は、第２の実施形態に係る半導体装置と従来の半導体装置との製造フローを比較するための図である。なお、以下の説明において、実質的に同一の機能を有する構成要素については、第１の実施形態と同一の符号を付し、詳しい説明は省略する場合がある。 <Second Embodiment>
FIG. 6 is a diagram for comparing manufacturing flows of the semiconductor device according to the second embodiment and a conventional semiconductor device. In the following description, components having substantially the same function are denoted by the same reference numerals as those in the first embodiment, and detailed description may be omitted.
　図６の工程Ａ～工程Ｅにおいて、一点鎖線の左側が本実施形態の半導体装置の製造フローを示す断面図であり、右側が従来の半導体装置の製造フローを示す断面図である。 6A to 6E, the left side of the alternate long and short dash line is a cross-sectional view showing the manufacturing flow of the semiconductor device of the present embodiment, and the right side is a cross-sectional view showing the manufacturing flow of the conventional semiconductor device.
　まず、図６の工程Ａについては、前述の図５の工程Ａと同様であるため詳細を省略する。 First, Step A in FIG. 6 is the same as Step A in FIG.
　次に、図６の工程Ｂでは、樹脂付着防止蓋材２４をリード端子１５の頂面に接触させる。この樹脂付着防止蓋材２４は頂面露出リード端子１７の頂面に樹脂封止時に封止樹脂が回り込まないようにするマスクの役割を果たすためのものである。つまり、この樹脂付着防止蓋材２４の存在によって頂面露出リード端子１７の頂面に封止樹脂バリが形成されるのを防止することができる。そして図６の工程Ｂは、最終的には本開示の半導体装置１１の頂面露出リード端子１７の構造を決する重要な工程となるのである。この樹脂付着防止蓋材２４は、封止樹脂を注入する前に頂面露出リード端子１７となるリード端子１５に接触するように載置する。 Next, in step B of FIG. 6, the resin adhesion preventing lid member 24 is brought into contact with the top surface of the lead terminal 15. This resin adhesion preventing lid member 24 serves to serve as a mask that prevents the sealing resin from entering the top surface of the top exposed lead terminal 17 during resin sealing. That is, it is possible to prevent the sealing resin burr from being formed on the top surface of the top surface exposed lead terminal 17 due to the presence of the resin adhesion preventing lid member 24. Then, the process B in FIG. 6 is an important process that finally determines the structure of the top exposed lead terminal 17 of the semiconductor device 11 of the present disclosure. The resin adhesion prevention lid member 24 is placed so as to come into contact with the lead terminal 15 serving as the top exposed lead terminal 17 before injecting the sealing resin.
　なお、本実施形態では、この樹脂付着防止蓋材２４が接触している頂面露出リード端子１７には金属細線１４が接続され、電気的に有効な信号ピンとして図示しているが、例えば半導体装置１１の４隅のコーナー部に位置するリード端子、いわゆる補強ランドのみを頂面露出リード端子１７とし、樹脂付着防止蓋材２４を接触させてもよい。すなわち、複数のリード端子１５のうち少なくとも１つの頂面に、樹脂付着防止蓋材２４を接触させればよい。 In the present embodiment, the fine metal wire 14 is connected to the top surface exposed lead terminal 17 that is in contact with the resin adhesion preventing lid member 24 and is shown as an electrically effective signal pin. Only the lead terminals located at the four corners of the device 11, that is, so-called reinforcing lands, may be used as the top exposed lead terminals 17, and the resin adhesion preventing lid member 24 may be brought into contact therewith. That is, the resin adhesion prevention lid member 24 may be brought into contact with at least one top surface of the plurality of lead terminals 15.
　次に、図６の工程Ｃで、封止樹脂を注入して、半導体チップ１２、金属細線１４、ダイパッド１３の一部、頂面露出リード端子１７の頂面の一部を除くすべてのリード端子１５の頂面を封止する封止樹脂部１６を形成する。 Next, in step C of FIG. 6, all lead terminals except for the semiconductor chip 12, the fine metal wires 14, part of the die pad 13, and part of the top surface of the top surface exposed lead terminal 17 are injected with sealing resin. A sealing resin portion 16 for sealing the top surface of 15 is formed.
　次に、図６の工程Ｄで、ダイシングソー２５などにより個別に分割することにより、頂面露出リード端子１７に接触している樹脂付着防止蓋材２４が半導体装置１１の側面に現出する。 Next, in step D of FIG. 6, the resin adhesion prevention lid member 24 that is in contact with the top surface exposed lead terminal 17 appears on the side surface of the semiconductor device 11 by being divided individually by a dicing saw 25 or the like.
　最後に、図６の工程Ｅで、この樹脂付着防止蓋材２４を除去することにより、リード端子１５の頂面が露出する構造（頂面露出リード端子１７）ができる。この工程において、樹脂付着防止蓋材２４を除去することにより、封止樹脂部１６に切り欠き部３０が形成される。 Finally, in step E of FIG. 6, by removing the resin adhesion prevention lid member 24, a structure in which the top surface of the lead terminal 15 is exposed (top surface exposed lead terminal 17) can be formed. In this step, the notch portion 30 is formed in the sealing resin portion 16 by removing the resin adhesion preventing lid member 24.
　樹脂付着防止蓋材２４は樹脂封止時の高温環境に対して耐性がある材質であって、さらに個別に分割したのちに消滅する（取り外す場合等を含む）ものであることが好ましい。例えば、ダイシングソー２５の回転ダメージを軽減するために、頂面露出リード端子１７と同一の金属材料や、封止樹脂部１６と同一のエポキシ樹脂材料であってもよい。また、例えば、ハンダ材料２１と同一組成で形成された金属片であれば１７０℃前後の樹脂封止工程の加熱に耐性があり、しかもリフロー実装時にはハンダペースト材料とともに溶融することができる。そのため、良好なハンダフィレットの形成が期待できる。さらに、例えば、樹脂封止耐熱性を持つ水溶性材料であれば、樹脂封止工程の加熱に耐性があるだけではなく、図６の工程Ｄで分割する際に、樹脂付着防止蓋材２４がダイシングソー２５の冷却水に溶解することにより、消滅（除去）させることができる。 The resin adhesion preventing lid member 24 is preferably a material that is resistant to a high temperature environment at the time of resin sealing, and further disappears (including when removed) after being divided individually. For example, in order to reduce rotational damage of the dicing saw 25, the same metal material as the top surface exposed lead terminal 17 or the same epoxy resin material as the sealing resin portion 16 may be used. Further, for example, a metal piece formed with the same composition as the solder material 21 is resistant to heating in a resin sealing process at around 170 ° C., and can be melted together with the solder paste material during reflow mounting. Therefore, formation of a good solder fillet can be expected. Furthermore, for example, if it is a water-soluble material having resin-sealing heat resistance, it is not only resistant to heating in the resin-sealing process, but also when the resin adhesion prevention lid member 24 is divided in the process D of FIG. It can be eliminated (removed) by dissolving in the cooling water of the dicing saw 25.
　＜第３の実施形態＞
　図７は、第３の実施形態に係る半導体装置を備えた実装体の側面断面図である。なお、以下の説明において、実質的に同一の機能を有する構成要素については、第１の実施形態と同一の符号を付し、詳しい説明は省略する場合がある。 <Third Embodiment>
FIG. 7 is a side cross-sectional view of a mounting body including a semiconductor device according to the third embodiment. In the following description, components having substantially the same function are denoted by the same reference numerals as those in the first embodiment, and detailed description may be omitted.
　本実施形態において、封止樹脂部１６からその上面を露出した頂面露出リード端子１７は、頂面と底面とが平行状態を成さず、半導体装置１１の外周部では頂面と底面から成る厚さ方向の距離が外周部に向かうに連れてテーパ状に薄くなっていくという構造を特徴としている。 In the present embodiment, the top surface exposed lead terminal 17 whose top surface is exposed from the sealing resin portion 16 does not form a parallel state between the top surface and the bottom surface, and the top surface and the bottom surface are formed in the outer peripheral portion of the semiconductor device 11. It is characterized by a structure in which the distance in the thickness direction becomes thinner in a tapered shape as it goes toward the outer periphery.
　頂面露出リード端子１７の底面は半導体装置１１の底面に平行であるのに対して、頂面露出リード端子１７の頂面は半導体装置１１の底面に対して斜面となっている。この構造を有することにより、頂面露出リード端子１７の頂面側にハンダ材料２１が届き易くなり、濡れ拡がり面積の拡大および濡れ拡がり速度の向上が実現でき、ひいてはハンダフィレットが形成されやすいという効果が期待できる。 The bottom surface of the top surface exposed lead terminal 17 is parallel to the bottom surface of the semiconductor device 11, whereas the top surface of the top surface exposed lead terminal 17 is inclined with respect to the bottom surface of the semiconductor device 11. By having this structure, the solder material 21 can easily reach the top surface side of the top surface exposed lead terminal 17, the wet spread area can be increased and the wet spread speed can be increased, and as a result, a solder fillet is easily formed. Can be expected.
　これにより、頂面露出リード端子１７の頂面側は、ハンダ材料２１によりプリント基板１８の配線パターン１９に押し付けられるようにハンダ合金接続されるため実装強度を向上することができる。 Thereby, since the top surface side of the top surface exposed lead terminal 17 is connected to the solder alloy so as to be pressed against the wiring pattern 19 of the printed board 18 by the solder material 21, the mounting strength can be improved.
　なお、図３について説明したように、本実施形態における頂面露出リード１７においても、コーナー部もしくは側面部のいずれに設置してもよく、また、ハンダ接続信頼性をより高く維持するために、コーナー部と側面部のすべてのリード端子に適用してもよい。 As described with reference to FIG. 3, the top exposed lead 17 in the present embodiment may be installed at either the corner portion or the side surface portion, and in order to maintain higher solder connection reliability, You may apply to all the lead terminals of a corner part and a side part.
　＜第４の実施形態＞
　図８Ａおよび図８Ｂは、それぞれ第４の実施形態に係る半導体装置の一例の主要部を示す図であり、図８Ａおよび図８Ｂは、それぞれ半導体装置を頂面側から見た場合の平面図、図８Ｃは、図８Ａの半導体装置をVIIIｃ－VIIIｃ線で切った場合の断面図である。図８Ｄは、図８Ｂの半導体装置をVIIId－VIIId線で切った場合の断面図である。 <Fourth Embodiment>
8A and FIG. 8B are views showing main parts of an example of the semiconductor device according to the fourth embodiment, respectively, and FIG. 8A and FIG. 8B are plan views when the semiconductor device is viewed from the top surface side, respectively. 8C is a cross-sectional view of the semiconductor device of FIG. 8A taken along the line VIIIc-VIIIc. 8D is a cross-sectional view of the semiconductor device of FIG. 8B taken along line VIIId-VIIId.
　なお、以下の説明において、実質的に同一の機能を有する構成要素については、第１の実施形態と同一の符号を付し、詳しい説明は省略する場合がある。 In the following description, components having substantially the same function are denoted by the same reference numerals as those in the first embodiment, and detailed description may be omitted.
　第４の実施形態における封止樹脂部１６からその上面を露出した頂面露出リード端子１７は、頂面に溝部１７ａまたは凹部１７ａが形成されていることを特徴としている。溝部１７ａまたは凹部１７ａは、半導体装置１１の中心方向から半導体装置１１の外周部に向かう方向に伸びている。溝部１７ａまたは凹部１７ａは外周部に向かう方向に伸びていれば、図８Ａに示すように直線状であっても、図８Ｂに示すように曲線状であっても構わない。また、両方が同一の頂面露出リード端子１７に混在しても構わない。 The top surface exposed lead terminal 17 whose top surface is exposed from the sealing resin portion 16 in the fourth embodiment is characterized in that a groove portion 17a or a concave portion 17a is formed on the top surface. The groove portion 17 a or the recess portion 17 a extends from the center direction of the semiconductor device 11 toward the outer peripheral portion of the semiconductor device 11. As long as the groove part 17a or the recessed part 17a is extended in the direction which goes to an outer peripheral part, it may be linear as shown to FIG. 8A, or may be curvilinear as shown to FIG. 8B. Further, both may be mixed in the same top exposed lead terminal 17.
　この構造を有することにより、頂面露出リード端子１７の頂面側にハンダ材料２１が接触した際に、いわゆる毛細管現象により、ハンダ材料２１が溝部１７ａや凹部１７ａに沿って濡れ拡がることができる。その結果、濡れ拡がり面積の拡大および濡れ拡がり速度の向上が実現でき、ひいてはハンダフィレットが形成されやすいという効果が期待できる。 By having this structure, when the solder material 21 comes into contact with the top surface side of the top surface exposed lead terminal 17, the solder material 21 can spread along the groove portion 17a and the recess portion 17a by a so-called capillary phenomenon. As a result, it is possible to increase the wet spreading area and improve the wet spreading speed, and as a result, an effect that a solder fillet is easily formed can be expected.
　これにより、頂面露出リード端子１７の頂面側は、ハンダ材料２１によりプリント基板１８の配線パターン１９に押し付けられるようにハンダ合金接続されるため実装強度を向上することができる。 Thereby, since the top surface side of the top surface exposed lead terminal 17 is connected to the solder alloy so as to be pressed against the wiring pattern 19 of the printed board 18 by the solder material 21, the mounting strength can be improved.
　なお、図３について説明したように、本実施形態における頂面露出リード端子１７においても、コーナー部もしくは側面部のいずれに設置してもよい。また、ハンダ接続信頼性をより高く維持するために、コーナー部と側面部のすべてのリード端子に適用してもよい。また、第３の実施形態と組み合わせた構造としてもよい。 Note that, as described with reference to FIG. 3, the top-surface exposed lead terminal 17 in the present embodiment may be installed in either the corner portion or the side portion. Further, in order to maintain higher solder connection reliability, the present invention may be applied to all lead terminals in the corner portion and the side portion. Moreover, it is good also as a structure combined with 3rd Embodiment.
　＜第５の実施形態＞
　図９は、第５の実施形態に係る半導体装置を備えた実装体の側面断面図である。なお、以下の説明において、実質的に同一の機能を有する構成要素については、第１の実施形態と同一の符号を付し、詳しい説明は省略する場合がある。 <Fifth Embodiment>
FIG. 9 is a side cross-sectional view of a mounting body including a semiconductor device according to the fifth embodiment. In the following description, components having substantially the same function are denoted by the same reference numerals as those in the first embodiment, and detailed description may be omitted.
　第５の実施形態における封止樹脂部１６からその上面を露出した頂面露出リード端子１７は、半導体装置１１の外周部に近づくにつれて、プリント基板１８に向かって厚さ方向に湾曲した構造であることを特徴としている。 The top exposed lead terminal 17 whose upper surface is exposed from the sealing resin portion 16 in the fifth embodiment has a structure that is curved in the thickness direction toward the printed circuit board 18 as it approaches the outer peripheral portion of the semiconductor device 11. It is characterized by that.
　すなわち、頂面露出リード端子１７の端部は、半導体装置１１の底面（封止樹脂部１６の底面）よりもプリント基板１８により近い配置となる。このような構造により、頂面露出リード端子１７の底面とプリント基板１８との間隙、いわゆるスタンドオフを確保することができる。 That is, the end portion of the top surface exposed lead terminal 17 is disposed closer to the printed circuit board 18 than the bottom surface of the semiconductor device 11 (the bottom surface of the sealing resin portion 16). With such a structure, a gap between the bottom surface of the top surface exposed lead terminal 17 and the printed board 18, a so-called standoff can be secured.
　この構造では、頂面露出リード端子１７の底面が封止樹脂部１６の底面より突出した構造となる。そのため、プリント基板１８に半導体装置１１を実装する際の頂面露出リード端子１７とプリント基板１８上の配線パターン１９との接合において、頂面露出リード端子１７のスタンドオフ高さを高く確保することができる。そのため、ハンダ材料の厚みが必然的に増加し、より多くの歪を吸収できる構造となるため、接合強度の向上を図ることができる。 In this structure, the bottom surface of the top surface exposed lead terminal 17 protrudes from the bottom surface of the sealing resin portion 16. Therefore, the stand-off height of the top surface exposed lead terminal 17 is ensured to be high when the top surface exposed lead terminal 17 and the wiring pattern 19 on the printed circuit board 18 are joined when the semiconductor device 11 is mounted on the printed circuit board 18. Can do. Therefore, the thickness of the solder material inevitably increases and a structure capable of absorbing more strain can be obtained, so that the bonding strength can be improved.
　また、スタンドオフ高さを高くすることにより、リフロー実装時におけるプリント基板１８の反りの影響を受けること無くハンダ接合実装ができる。さらに、プリント基板１８の反りによる半導体装置１１自身の製品持ち上がり現象や製品浮き現象を防止できるため、頂面露出リード端子１７を含むすべてのリード端子１５のオープン不良を防ぐことができる。 Also, by increasing the standoff height, it is possible to perform solder joint mounting without being affected by warping of the printed circuit board 18 during reflow mounting. Furthermore, since the product lifting phenomenon and the product floating phenomenon of the semiconductor device 11 due to the warpage of the printed circuit board 18 can be prevented, open defects of all the lead terminals 15 including the top exposed lead terminals 17 can be prevented.
　なお、図３について説明したように、本実施形態における頂面露出リード端子１７においても、コーナー部もしくは側面部のいずれに設置してもよく、また、ハンダ接続信頼性をより高く維持するために、コーナー部と側面部のすべてのリード端子に適用してもよい。また、第４の実施形態と組み合わせた構造としてもよい。 As described with reference to FIG. 3, the top exposed lead terminal 17 in the present embodiment may be installed at either the corner or the side surface, and in order to maintain higher solder connection reliability. It may be applied to all the lead terminals in the corner portion and the side portion. Moreover, it is good also as a structure combined with 4th Embodiment.
　＜第６の実施形態＞
　図１０は、第６の実施形態に係る半導体装置を備えた実装体の側面断面図である。なお、以下の説明において、実質的に同一の機能を有する構成要素については、第１の実施形態と同一の符号を付し、詳しい説明は省略する場合がある。 <Sixth Embodiment>
FIG. 10 is a side cross-sectional view of a mounting body including a semiconductor device according to the sixth embodiment. In the following description, components having substantially the same function are denoted by the same reference numerals as those in the first embodiment, and detailed description may be omitted.
　第６実施形態における封止樹脂部１６からその上面を露出した頂面露出リード端子１７は、側面の露出が厚み方向に延伸した構造を特徴としている。 The top-surface exposed lead terminal 17 whose upper surface is exposed from the sealing resin portion 16 in the sixth embodiment is characterized by a structure in which the side surface is extended in the thickness direction.
　具体的に、半導体装置１１のコーナー部において、半導体装置１１の底面から上面にかけて封止樹脂部１６から露出する頂面露出リード端子１７が存在する。すなわち、封止樹脂部１６の上面と頂面露出リード端子１７の最上面は同じ高さであり、面一である。また、頂面露出リード端子１７は、半導体装置１１の厚み方向の断面図においてＬ字形状となっている。このような構造により、頂面露出リード端子１７の頂面に存在するハンダ材料２１がさらに厚み方向に濡れ上がることが可能となり、より肉厚が厚いハンダフィレットを形成することが可能となる。 Specifically, there is a top exposed lead terminal 17 exposed from the sealing resin portion 16 from the bottom surface to the top surface of the semiconductor device 11 at the corner portion of the semiconductor device 11. That is, the top surface of the sealing resin portion 16 and the top surface of the top surface exposed lead terminal 17 have the same height and are flush with each other. The top exposed lead terminal 17 is L-shaped in the cross-sectional view of the semiconductor device 11 in the thickness direction. With such a structure, the solder material 21 existing on the top surface of the top surface exposed lead terminal 17 can further wet in the thickness direction, and a thicker solder fillet can be formed.
　これにより、頂面露出リード端子１７の頂面側は、ハンダ材料２１によりプリント基板１８の配線パターン１９に押し付けられるようにハンダ合金接続されるため実装強度を向上することができる。 Thereby, since the top surface side of the top surface exposed lead terminal 17 is connected to the solder alloy so as to be pressed against the wiring pattern 19 of the printed board 18 by the solder material 21, the mounting strength can be improved.
　本実施形態は半導体装置のコーナー部に配置されるが、頂面露出リード端子１７の形状として、第３乃至第５の実施形態と組み合わせた構造としてもよい。 Although this embodiment is arranged at a corner portion of a semiconductor device, the shape of the top exposed lead terminal 17 may be a structure combined with the third to fifth embodiments.
　上記いずれの実施形態においても、従来のＱＦＮパッケージと同じく封止樹脂領域よりも内側にリード端子が形成されているため、半導体装置１１自身の小型化を維持しながらも、プリント基板１８とのハンダ接続強度が向上できるという、優れた性能を持つＱＦＮパッケージを提供することができる。 In any of the above embodiments, since the lead terminal is formed inside the sealing resin region as in the conventional QFN package, the semiconductor device 11 itself can be reduced in size and soldered to the printed circuit board 18. It is possible to provide a QFN package with excellent performance that connection strength can be improved.
　本開示は、半導体装置の実装体においてリード端子の頂面方向からハンダフィレットを形成することができ、強固なハンダ接続強度を保つことができるという効果を有する、そのため、微小なリード端子を持つ半導体装置とプリント基板とのハンダ接続強度を強固に保つのに有用であり、また大きな機械的ストレスや熱ストレスの負荷に充分に耐え得ることが可能な実装体として有用である。 The present disclosure has an effect that a solder fillet can be formed from the top surface direction of a lead terminal in a mounting body of a semiconductor device, and a strong solder connection strength can be maintained. Therefore, a semiconductor having a minute lead terminal This is useful for keeping the solder connection strength between the apparatus and the printed circuit board strong, and is useful as a mounting body that can sufficiently withstand a load of a large mechanical stress or thermal stress.
　　１１　　半導体装置
　　１２　　半導体チップ
　　１３　　ダイパッド
　　１４　　金属細線
　　１５　　リード端子
　　１６　　封止樹脂部
　　１７　　頂面露出リード端子
　　１７ａ　　溝部、凹部
　　１８　　プリント基板
　　１９　　配線パターン
　　２０　　実装体
　　２１　　ハンダ材料
　　２２　　リードフレーム
　　２３　　樹脂付着防止ピン（樹脂付着防止材料）
　　２４　　樹脂付着防止蓋材（樹脂付着防止材料）
　　２５　　ダイシングソー DESCRIPTION OF SYMBOLS 11 Semiconductor device 12 Semiconductor chip 13 Die pad 14 Metal fine wire 15 Lead terminal 16 Sealing resin part 17 Top surface exposed lead terminal 17a Groove part, recessed part 18 Printed circuit board 19 Wiring pattern 20 Mounting body 21 Solder material 22 Lead frame 23 Resin adhesion prevention pin ( Resin adhesion prevention material)
24 Resin adhesion prevention lid (resin adhesion prevention material)
25 Dicing saw

Claims (15)

  1. 　半導体チップと、
    　前記半導体チップと電気的に接続される複数のリード端子と、
    　前記半導体チップおよび前記複数のリード端子を封止する封止樹脂部とを備え、
    　前記複数のリード端子は、頂面から見て前記封止樹脂部の最外周の辺で構成される方形の封止樹脂領域よりも内側に形成されており、
    　前記複数のリード端子のうち少なくとも一つは、前記封止樹脂領域内において頂面が前記封止樹脂部から露出している頂面露出リード端子である
    ことを特徴とする半導体装置。     A semiconductor chip;
    A plurality of lead terminals electrically connected to the semiconductor chip;
    A sealing resin portion for sealing the semiconductor chip and the plurality of lead terminals;
    The plurality of lead terminals are formed inside a rectangular sealing resin region formed by an outermost peripheral side of the sealing resin portion as viewed from the top surface,
    At least one of the plurality of lead terminals is a top surface exposed lead terminal having a top surface exposed from the sealing resin portion in the sealing resin region.
  2. 　請求項１の半導体装置において、
    　前記半導体チップが載置されるダイパッドを備え、
    　前記封止樹脂部は、前記半導体チップおよび前記複数のリード端子、ならびに前記ダイパッドを封止する
    ことを特徴とする半導体装置。     The semiconductor device according to claim 1.
    A die pad on which the semiconductor chip is placed;
    The sealing resin portion seals the semiconductor chip, the plurality of lead terminals, and the die pad.
  3. 　請求項１の半導体装置において、
    　前記複数のリード端子の底面は前記封止樹脂部に覆われていない
    ことを特徴とする半導体装置。     The semiconductor device according to claim 1.
    A semiconductor device, wherein bottom surfaces of the plurality of lead terminals are not covered with the sealing resin portion.
  4. 　請求項１および２のいずれかの半導体装置において、
    　前記頂面露出リード端子は、当該半導体装置のコーナー部に位置する
    ことを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 and 2,
    The top exposed lead terminal is located at a corner portion of the semiconductor device.
  5. 　請求項４の半導体装置において、
    　前記頂面露出リード端子は、当該半導体装置の４つのコーナー部に配置されている
    ことを特徴とする半導体装置。     The semiconductor device according to claim 4.
    The top exposed lead terminal is arranged at four corners of the semiconductor device.
  6. 　請求項１から５のいずれか１つの半導体装置において、
    　前記頂面露出リード端子の、頂面、底面、および側面の少なくとも１つには、メッキ膜が被覆されている
    ことを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 5,
    At least one of the top surface, the bottom surface, and the side surface of the top surface exposed lead terminal is coated with a plating film.
  7. 　請求項１から６のいずれか１つの半導体装置において、
    　前記頂面露出リード端子の頂面は、当該半導体装置の中央部から外周部に向かって当該半導体装置の底面側に傾斜している
    ことを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 6,
    The top surface of the top surface exposed lead terminal is inclined toward the bottom surface side of the semiconductor device from the central portion toward the outer peripheral portion of the semiconductor device.
  8. 　請求項１から７のいずれか１つの半導体装置において、
    　前記頂面露出リード端子の頂面には溝部または凹部が形成されている
    ことを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 7,
    A semiconductor device, wherein a groove or a recess is formed on a top surface of the top surface exposed lead terminal.
  9. 　請求項８の半導体装置において、
    　前記溝部または前記凹部は、当該半導体装置の中央部から外周部に向かって形成されている
    ことを特徴とする半導体装置。     The semiconductor device according to claim 8.
    The groove portion or the concave portion is formed from the central portion toward the outer peripheral portion of the semiconductor device.
  10. 　請求項１から９のいずれか１つの半導体装置において、
    　前記頂面露出リード端子は、当該半導体装置の外周部において、当該半導体装置の底面よりも外側に湾曲した形状である
    ことを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 9,
    The semiconductor device according to claim 1, wherein the top exposed lead terminal has a shape that is curved outward from the bottom surface of the semiconductor device at an outer peripheral portion of the semiconductor device.
  11. 　請求項３および４のいずれかの半導体装置において、
    　前記頂面露出リード端子の最上面は、前記封止樹脂部の上面と同じ高さである
    ことを特徴とする半導体装置。     The semiconductor device according to any one of claims 3 and 4,
    The top surface of the top surface exposed lead terminal is the same height as the top surface of the sealing resin portion.
  12. 　請求項１から１１のいずれか１つの半導体装置と、
    　配線パターンを有するプリント基板と、
    　前記半導体装置の前記複数のリード端子と前記配線パターンとを接続するハンダ材料とを備え、
    　前記ハンダ材料は、前記半導体装置の前記頂面露出リード端子の頂面にも配置されている
    ことを特徴とする半導体装置の実装体。     A semiconductor device according to any one of claims 1 to 11,
    A printed circuit board having a wiring pattern;
    A solder material for connecting the plurality of lead terminals of the semiconductor device and the wiring pattern;
    The mounting body of a semiconductor device, wherein the solder material is also disposed on a top surface of the top surface exposed lead terminal of the semiconductor device.
  13. 　複数のリード端子と半導体チップとを準備する第１の工程と、
    　前記半導体チップと前記複数のリード端子とを金属細線により接合する第２の工程と、
    　前記複数のリード端子の少なくとも１つの頂面の一部に樹脂付着防止材料を載置する第３の工程と、
    　前記複数のリード端子および前記半導体チップおよび前記金属細線を封止樹脂により封止する第４の工程と、
    　前記樹脂付着防止材料を除去して、封止樹脂体を得る第５の工程と、
    　前記封止樹脂体を個別に分割することによって、半導体装置を得る第６の工程とを備えている
    ことを特徴とする半導体装置の製造方法。     A first step of preparing a plurality of lead terminals and a semiconductor chip;
    A second step of joining the semiconductor chip and the plurality of lead terminals with fine metal wires;
    A third step of placing a resin adhesion preventing material on a part of at least one top surface of the plurality of lead terminals;
    A fourth step of sealing the plurality of lead terminals, the semiconductor chip, and the fine metal wires with a sealing resin;
    A fifth step of removing the resin adhesion preventing material to obtain a sealing resin body;
    A semiconductor device manufacturing method comprising: a sixth step of obtaining a semiconductor device by dividing the sealing resin body individually.
  14. 　複数のリード端子と半導体チップとを準備する第１の工程と、
    　前記半導体チップと前記複数のリード端子とを金属細線により接合する第２の工程と、
    　前記複数のリード端子の少なくとも１つの頂面の一部に樹脂付着防止材料を載置する第３の工程と、
    　前記複数のリード端子および前記半導体チップおよび前記金属細線を封止樹脂で封止することによって成型される封止樹脂体を得る第４の工程と、
    　前記封止樹脂体を個別に分割する第５の工程と、
    　前記樹脂付着防止材料を除去することによって、半導体装置を得る第６の工程とを備えている
    ことを特徴とする半導体装置の製造方法。     A first step of preparing a plurality of lead terminals and a semiconductor chip;
    A second step of joining the semiconductor chip and the plurality of lead terminals with fine metal wires;
    A third step of placing a resin adhesion preventing material on a part of at least one top surface of the plurality of lead terminals;
    A fourth step of obtaining a sealing resin body molded by sealing the plurality of lead terminals, the semiconductor chip and the fine metal wires with a sealing resin;
    A fifth step of individually dividing the sealing resin body;
    A semiconductor device manufacturing method comprising: a sixth step of obtaining a semiconductor device by removing the resin adhesion preventing material.
  15. 　請求項１３および１４のいずれかの半導体装置の製造方法において、
    　前記第１の工程では、前記複数のリード端子と、前記半導体チップを載置するダイパッドと、前記ダイパッドを支持する吊りリードとを有するリードフレームを準備し、
    　前記第１の工程と前記第２の工程との間において、前記半導体チップを前記ダイパッド上に載置する第７の工程を備えている
    ことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device in any one of Claim 13 and 14,
    In the first step, a lead frame having the plurality of lead terminals, a die pad for mounting the semiconductor chip, and a suspension lead for supporting the die pad is prepared,
    A semiconductor device manufacturing method comprising a seventh step of placing the semiconductor chip on the die pad between the first step and the second step.
PCT/JP2015/000653 2014-02-27 2015-02-13 Resin-sealed semiconductor device, production method therefor, and mounting body therefor WO2015129185A1 (en)

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WO2023140046A1 (en) * 2022-01-20 2023-07-27 ローム株式会社 Semiconductor device

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