CN2641822Y - IC package assembly - Google Patents
IC package assembly Download PDFInfo
- Publication number
- CN2641822Y CN2641822Y CNU032644906U CN03264490U CN2641822Y CN 2641822 Y CN2641822 Y CN 2641822Y CN U032644906 U CNU032644906 U CN U032644906U CN 03264490 U CN03264490 U CN 03264490U CN 2641822 Y CN2641822 Y CN 2641822Y
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- substrate
- several
- viscose
- wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The utility model provides an IC package assembly for the convenient jointing of leading wires and the improvement of manufacturing capability, and comprises a substrate, a spacing layer, an integrated circuit, an adhesive layer and a plurality of leading wires; wherein the substrate is arranged with an upper surface with a plurality of a first jointing points, and a lower surface with a plurality of a second jointing points. The spacing layer is adhesive to the upper surface of the substrate by dint of adhesive glue. The integrated circuit is provided with a plurality of welded gaskets that are adhesive to the spacing layer by dint of adhesive glue. The spacing layer has a smaller area than that of the integrated circuit so that the clearance can be formed between the integrated circuit and the substrate. The leading wires are connected electrically via the welded gaskets of the integrated circuit on the first jointing point of the substrate. The adhesive layer is formed on the upper surface of the substrate for the sake of embracing the integrated circuit and leading wires.
Description
Technical field
The utility model belongs to semiconductor package, particularly a kind of integrated circuit package assembling.
Background technology
As shown in Figure 1, the package assembling of known integrated circuit includes substrate 10, integrated circuit 20, several wires 26 and adhesive layer 28.
Substrate is provided with upper surface 12 that forms several first contacts 16 and the lower surface 14 that forms several second contacts 18.
Only, there is following disappearance in above-mentioned known integrated circuit package assembling:
When integrated circuit 20 is attached on the upper surface 12 of substrate 10 by viscose 24,, will cause the situation of the glue that overflows, and make viscose 24 cover first contact 16 on the substrate 10 if the control of viscose amount was not at that time.So, will cause several wires 26 to go between to be bonded on the substrate 10 or lead 26 is come off during the lead-in wire bonding.
Summary of the invention
The purpose of this utility model provides a kind of bonding of being convenient to go between, promotes the integrated circuit package assembling of processing procedure ability.
The utility model comprises substrate, wall, integrated circuit, several wires and adhesive layer; Substrate is provided with upper surface that forms several first contacts and the lower surface that forms several second contacts; Wall is attached on the upper surface of substrate by viscose; Integrated circuit is provided with several weld pads and borrows viscose to be attached on the wall; The wall area is less than the integrated circuit area, so that be formed with the gap between integrated circuit and substrate; Several wires system is electrically connected the weld pad of integrated circuit to first contact of substrate; The sealing series of strata are formed on the upper surface of substrate, so as to enveloping integrated circuit and several wires.
Wherein:
Form the ball grid array Metal Ball on second contact of base lower surface.
Because the utility model comprises substrate, wall, integrated circuit, several wires and adhesive layer; Substrate is provided with upper surface that forms several first contacts and the lower surface that forms several second contacts; Wall is attached on the upper surface of substrate by viscose; Integrated circuit is provided with several weld pads and borrows viscose to be attached on the wall; The wall area is less than the integrated circuit area, so that be formed with the gap between integrated circuit and substrate; Several wires system is electrically connected the weld pad of integrated circuit to first contact of substrate; The sealing series of strata are formed on the upper surface of substrate, so as to enveloping integrated circuit and several wires.Integrated circuit is attached on the substrate by wall, makes between integrated circuit and substrate and forms the gap, makes the excessive glue of viscose can not cover first contact on the upper surface of base plate by the gap.So, in encapsulation process, can be convenient to the bonding that goes between, can improve its processing procedure ability, thereby reach the purpose of this utility model.
Description of drawings
Fig. 1, be known image sensor structure schematic sectional view.
Fig. 2, for the utility model structural representation cutaway view (not forming the adhesive layer state).
Fig. 3, be the utility model structural representation cutaway view.
Embodiment
As Fig. 2, shown in Figure 3, the utility model comprises substrate 30, wall 32, integrated circuit 34, several wires 36 and adhesive layer 38.
Adhesive layer 38 is to be formed on the upper surface 40 of substrate 30, so as to enveloping integrated circuit 34 and several wires 36.
As mentioned above, the utlity model has following advantage:
Claims (2)
1, a kind of integrated circuit package assembling, it comprises substrate, integrated circuit, several wires and adhesive layer; Substrate is provided with upper surface that forms several first contacts and the lower surface that forms several second contacts; Integrated circuit is provided with several weld pads; Several wires system is electrically connected the weld pad of integrated circuit to first contact of substrate; The sealing series of strata are formed on the upper surface of substrate, so as to enveloping integrated circuit and several wires; It is characterized in that described upper surface of base plate borrows viscose to stick together and be provided with the wall of area less than the integrated circuit area, integrated circuit borrows viscose to be attached on the wall, so that be formed with the gap between integrated circuit and substrate.
2, integrated circuit package assembling according to claim 1 is characterized in that forming on second contact of described base lower surface the ball grid array Metal Ball.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNU032644906U CN2641822Y (en) | 2003-06-20 | 2003-06-20 | IC package assembly |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNU032644906U CN2641822Y (en) | 2003-06-20 | 2003-06-20 | IC package assembly |
Publications (1)
Publication Number | Publication Date |
---|---|
CN2641822Y true CN2641822Y (en) | 2004-09-15 |
Family
ID=34297320
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNU032644906U Expired - Lifetime CN2641822Y (en) | 2003-06-20 | 2003-06-20 | IC package assembly |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN2641822Y (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101164162B (en) * | 2005-06-06 | 2010-06-09 | 罗姆股份有限公司 | Semiconductor device and semiconductor device manufacturing method |
CN102593079A (en) * | 2012-03-15 | 2012-07-18 | 南通富士通微电子股份有限公司 | Chip packaging structure and chip packaging method |
CN104183555A (en) * | 2013-05-28 | 2014-12-03 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
-
2003
- 2003-06-20 CN CNU032644906U patent/CN2641822Y/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101164162B (en) * | 2005-06-06 | 2010-06-09 | 罗姆股份有限公司 | Semiconductor device and semiconductor device manufacturing method |
CN102593079A (en) * | 2012-03-15 | 2012-07-18 | 南通富士通微电子股份有限公司 | Chip packaging structure and chip packaging method |
CN104183555A (en) * | 2013-05-28 | 2014-12-03 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
CN104183555B (en) * | 2013-05-28 | 2018-09-07 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CX01 | Expiry of patent term |
Expiration termination date: 20130620 Granted publication date: 20040915 |