CN2684375Y - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
- Publication number
- CN2684375Y CN2684375Y CN 03208179 CN03208179U CN2684375Y CN 2684375 Y CN2684375 Y CN 2684375Y CN 03208179 CN03208179 CN 03208179 CN 03208179 U CN03208179 U CN 03208179U CN 2684375 Y CN2684375 Y CN 2684375Y
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- China
- Prior art keywords
- chip
- wire
- contact
- lead
- carrier
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The utility model discloses a chip packaging structure, mainly composed of a carrier, a chip, one passive element at least, one first lead wire at least and a sealing glue. The utility model is characterized in that the passive element is arranged across the space between the power connection point and the grounding contact of the carrier. The both ends of the first lead wire can be directly connected with a welded gasket of the chip and a welded end of the passive element. Thus, the length of the first lead wire can be effectively shortened. The transmission path in which the signal is transmitted in the first lead wire is shortened, which causes the electric property of the chip to be raised and the wire arranging space of the adjacent lead wires to be increased. In addition, the structure also comprises one second lead wire at least. One end of the second lead wire can be arranged across the upper part of the passive element and can be welded on the connection point of the outermost periphery of the carrier.
Description
Technical field
The utility model relates to a kind of chip-packaging structure, and particularly relevant for a kind of chip-packaging structure with lead-in wire bonding kenel of passive component.
Background technology
Because development of semiconductor, under the market demand improves, make semiconductor industry constantly develop more accurate, electronic component faster, technology with present semiconductor packages, such as the technology of chip packaging, the making of chip carrier (chip carrier) and the assembling of passive component (passive component) etc., all in semiconductor industry, occupy indispensable status.
With regard to the technology of chip packaging, each cuts formed bare chip (die) by wafer (wafer), for example with lead-in wire bonding (wire bonding) or flip-chip welding modes such as (flip chip bonding), be disposed at the surface of a carrier (carrier), wherein carrier for example is lead frame (leadframe) or substrate (substrate), and chip has a plurality of welded gaskets, and the welded gasket of chip is able to be electrically connected to outside electronic installation via the transmission line of carrier and contact.In addition, utilize the chip of lead-in wire bonding, its welded gasket forms an adhesive material with chip, the coating that goes between again with after the contact of substrate is electrically connected, is used for protecting chip and lead-in wire, so promptly finishes a chip-packaging structure.
Please refer to Figure 1A and Figure 1B, wherein Figure 1A shows the part sectioned view of the chip-packaging structure of existing a kind of bonding kenel that goes between, and Figure 1B shows the schematic top plan view of the chip-packaging structure of existing a kind of bonding kenel that goes between.Chip-packaging structure 100 mainly is made of a carrier 110, a chip 120, a plurality of leads 134,136,138 and a sealing (not shown).The surface of carrier 110 has a chips welding district 112, and the back side 122 of chip 120 is attached in the chips welding district 112, and active surperficial 124 of chip 120 has a plurality of welded gaskets 126, it corresponds respectively to the lip-deep contact of carrier 110, and wherein contact order from inside to outside for example is ground contact 114, power supply contact 116 and signal contact 118 etc.In addition, each lead-in wire two ends of 134,136,138 is connected to respectively on one of the welded gasket 126 and pairing ground contact 114, power supply contact 116 and signal contact 118 of chip 120.
It should be noted that, in order effectively to improve the electrical characteristic of chip-packaging structure 100, normally utilize surface mounting technology (Surface Mount Technology, SMT) small passive element 130 is attached to the surface of carrier 110, be used for reducing the noise cross-talk (crosstalk) that signal is produced when switching, and keep signal transmitting quality.Wherein, passive component 130 for example is inductance element (inductor) or capacity cell (capacitor), and passive component 130 is cross-placed between the power supply contact 116 and ground contact 114 of carrier 110, and two welding ends 132a, the 132b of passive component 130 are connected to power supply contact 116 and ground contact 114 respectively.
Yet, when carrying out lead key closing process between chip 120 and the carrier 110, the lead-in wire 136 of the power supply contact 116 of corresponding welded gasket 126 that connects chip 120 and carrier 110 must stride across the top of passive component 130 earlier, is soldered on the surface of power supply contact 116 afterwards again.Because lead-in wire 136 must elongate camber line earlier, just can stride across the top of passive component 130, so 136 itself the length that cause relatively going between increase, and signal rows increases through 136 the transmission path of going between, to the electric property of chip 120 be reduced, and the laying space of the contiguous lead-in wire of influence.
The utility model content
Therefore, the purpose of this utility model is to provide a kind of chip-packaging structure, is used for shortening the length of lead-in wire, and increases the wiring space of lead-in wire.
Another purpose of the present utility model is to provide a kind of wire bond package structure, is used for shortening the length of lead-in wire, and increases the wiring space of lead-in wire.
For reaching above-mentioned purpose of the present utility model, the utility model provides a kind of chip-packaging structure, at least comprise a carrier, this carrier has a surface, a power supply contact and a ground contact, and the surface has a chips welding district, and power supply contact and ground contact all are disposed at the surface, and power supply contact and ground contact are positioned at the zone outside the chips welding district.In addition, chip configuration is in the surface of carrier, and chip has an active surface and a corresponding back side, and chip is pasted to the chips welding district with the back side, and chip also has a plurality of welded gaskets, and it is disposed at active surface.In addition, at least one passive component is cross-placed between the power supply contact and ground contact of carrier, and passive component has at least two welding endss, and it is electrically connected to power supply contact and ground contact respectively.Moreover the two ends of at least one first lead-in wire are connected to one of one of these welded gaskets of chip and these welding endss respectively.Moreover a sealing is coated chip, passive component and first lead-in wire.
Above-mentioned chip-packaging structure of the present utility model, wherein Yin Xian a end can be connected directly on the welding ends of passive component, therefore the length of lead-in wire can shorten effectively, and signal rows shortens through the transmission path of lead-in wire, to the electric property of chip be improved, and increase the wiring space of contiguous lead-in wire.
For reaching above-mentioned purpose of the present utility model, the utility model also provides a kind of wire bond package structure, be suitable for a chip is electrically connected to a carrier, the surface that it is characterized in that this carrier has a chips welding district, and chip has an active surface and a corresponding back side, and chip is pasted in the chips welding district with this back side, and this wire bond package structure comprises at least: a power supply contact is configured in the surface of carrier; One ground contact is configured in the surface of carrier; One signal contact is configured in the surface of carrier, and wherein power supply contact and ground contact are positioned at the same side outside the chips welding district, and signal contact be positioned at power supply contact and ground contact away from the outside in chips welding district; One passive component is cross-placed between the power supply contact and ground contact of carrier, and passive component has at least two welding endss, and it is electrically connected to power supply contact and ground contact respectively; A plurality of welded gaskets are disposed at the active surface of chip; One first lead-in wire is electrically connected one of one of those welded gaskets and those welding endss; And one second lead-in wire, be electrically connected another and signal contact of those welded gaskets, and second lead-in wire is across the top of passive component.Above-mentioned wire bond package structure of the present utility model, wherein Yin Xian a end can be connected directly on the welding ends of passive component, therefore the length of lead-in wire can shorten effectively, and signal rows shortens through the transmission path of lead-in wire, to the electric property of chip be improved, and increase the wiring space of contiguous lead-in wire.
For above-mentioned and other purpose of the present utility model, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A shows the part sectioned view of the chip-packaging structure of existing a kind of bonding kenel that goes between;
Figure 1B shows the schematic top plan view of the chip-packaging structure of existing a kind of bonding kenel that goes between;
The part sectioned view of the chip-packaging structure of a kind of bonding kenel that goes between of Fig. 2 A demonstration the utility model one preferred embodiment;
The schematic top plan view of the chip-packaging structure of a kind of bonding kenel that goes between of Fig. 2 B demonstration the utility model one preferred embodiment.
Description of reference numerals
100 chip-packaging structures, 110 carriers
112 chips welding districts, 114 ground contacts
116 power supply contacts, 118 signal contacts
120 chips, 122 back sides
124 active surperficial 126 welded gaskets
130 passive component 132a welding endss
132b welding ends 134 lead-in wires
136 lead-in wires, 138 lead-in wires
200 chip-packaging structures, 210 carriers
212 chips welding districts, 214 ground contacts
216 power supply contacts, 218 signal contacts
220 chips, 222 back sides
224 active surperficial 226a welded gaskets
226b welded gasket 226c welded gasket
230 passive component 232a welding endss
232b welding ends 234 first lead-in wires
236 first lead-in wires, 238 second lead-in wires
240 welding cover layers, 242 metal levels
Embodiment
Please refer to Fig. 2 A and 2B, wherein Fig. 2 A shows the part sectioned view of chip-packaging structure of a kind of bonding kenel that goes between of the utility model one preferred embodiment, and Fig. 2 B shows the schematic top plan view of chip-packaging structure of a kind of bonding kenel that goes between of the utility model one preferred embodiment.Chip-packaging structure 200 mainly is made of a carrier 210, a chip 220, a passive component 230, a plurality of first lead-in wire 234,236, at least one second lead-in wire, 238 and one sealing (not shown), wherein carrier 210 for example is a substrate, its surface has a chips welding district 212, and the back side 222 of chip 220 is attached in the chips welding district 212, and active surperficial 224 of chip 220 has a plurality of welded gaskets 226, it corresponds respectively to the contact on the carrier 210, and these contacts for example are ground contact 214, power supply contact 216 and signal contact 218 etc.In the present embodiment, shown in Fig. 2 B, wherein power supply contact 216 and ground contact 214 for example are positioned at the same side outside the chips welding district 212, and both are for example formed by a power ring (not shown) of the periphery that is surrounded on chips welding district 212 and the local line segment of a ground loop (not shown) respectively, and the part surface of the part surface of power ring and ground loop is exposed in the opening of a welding cover layer 240 of patterning, with power supply contact 216 or the ground contact 214 as the usefulness that connects first lead-in wire 234,236 or passive component 230.
Please refer to Fig. 2 A and 2B, signal contact 218 is positioned at the same side of power supply contact 216 and ground contact 214, and signal contact 218 is relatively away from chips welding district 212 and be positioned at power supply contact 216 and the outside of ground contact 214.In addition, signal contact 218 and chips welding district 212 can be exposed in the opening of welding cover layer 240 of patterning equally.
In addition, please refer to Fig. 2 A, passive component 230 is cross-placed between power supply contact 216 and the ground contact 214, and passive component 230 has at least two welding ends 232a, 232b, it utilizes surface mounting technology (SMT) and is welded on the surface of power supply contact 216 and ground contact 214 respectively, is used for effectively suppressing the mutual inductive couplings that is produced between first lead-in wire, 234,236 and second lead-in wire 238.Wherein, passive component 230 for example is small inductance element or capacity cell, and the welding ends 232a of passive component 230,232b surface also have a metal level 242, this metal level 242 is for example formed in the mode of electroplating, and the material of metal level 242 can be nickel, gold or other alloy, the weldability when being used for increasing follow-up lead key closing process between first lead-in wire 234,236 and welding ends 232a, the 232b.
It should be noted that, in order to shorten the length of lead-in wire 234,236, present embodiment directly is welded on an end of at least one first lead-in wire 236 on the welding ends 232a of passive component 230, wherein first lead-in wire, 236 two ends can corresponding be connected to a welded gasket 226a of chip 220 and the welding ends 232a away from chip 220 of passive component 220, and the two ends of another first lead-in wire 234 can corresponding be connected to that the welding ends 232b of the adjacent chips 220 of another welded gasket 226b of chip 220 and passive component 230 goes up or ground contact 214 on (not shown).Because outer field first lead-in wire 236 must not elongate camber line to stride across the top of passive component 230, but directly be welded on the welding ends 232a of passive component 230, therefore the length of outer field first lead-in wire 236 can shorten effectively, and signal rows shortens through the transmission path of first lead-in wire 236, to the electric property of chip 220 be improved, and increase the laying space of contiguous lead-in wire.In addition, the two ends of second lead-in wire 238 can correspondingly connect the another welded gasket 226c of chip 220 and the signal contact 218 of carrier 210 outermost, and second lead-in wire 238 also can be across the top of passive component 230, and can not touch arbitrary welding ends 232a, the 232b of passive component 230.
By above-mentioned explanation as can be known; chip-packaging structure of the present utility model bridges at least one passive component earlier between the power supply contact and ground contact of carrier; and two welding endss of passive component are electric connection of power supply contact and ground contact respectively; then corresponding connection one first goes between to a welding ends of a welded gasket of chip and passive component; then corresponding again connection one second goes between to another welded gasket and the signal contact of chip; can form a sealing afterwards again with chip; passive component and first; second lead-in wire coats; be used for protecting chip and first; second lead-in wire so can be finished a chip-packaging structure.
In sum, chip-packaging structure of the present utility model has following advantage:
(1) Yin Xian a end can be connected directly on the welding ends of passive component, and therefore the length of lead-in wire can shorten effectively, and signal rows shortens through the transmission path of lead-in wire, will the electric property of chip be improved, and increases the wiring space of contiguous lead-in wire.
(2) Yin Xian a end can be across the top of passive component and be welded on the contact of carrier outermost, and can not touch arbitrary welding ends of passive component.
Though the utility model discloses as above in conjunction with a preferred embodiment; so it is not to be used for limiting the utility model; those skilled in the art; in not breaking away from spirit and scope of the present utility model; when the change that can do a little and retouching, therefore protection range of the present utility model is with being as the criterion that claim was defined.
Claims (9)
1. chip-packaging structure comprises at least:
One carrier, have a surface, a power supply contact and a ground contact, and this surface has a chips welding district, and this power supply contact and this ground contact all are disposed at this surface, and this power supply contact and this ground contact are positioned at the same side outside this chips welding district;
One chip is disposed at this surface of this carrier, and this chip has an active surface and a corresponding back side, and this chip is pasted to this chips welding district with this back side, and this chip also has a plurality of welded gaskets, and it is disposed at this active surface;
At least one passive component is cross-placed between this power supply contact and this ground contact of this carrier, and this passive component has at least two welding endss, and it is electrically connected to this power supply contact and this ground contact respectively;
At least one first lead-in wire is electrically connected one of one of those welded gaskets of this chip and those welding endss; And
One sealing coats this chip, this passive component and this first lead-in wire.
2. chip-packaging structure as claimed in claim 1 is characterized in that this carrier also has a signal contact, and this signal contact be positioned at this power supply contact and this ground contact away from the outside in this chips welding district.
3. chip-packaging structure as claimed in claim 2 also comprises at least one second lead-in wire, and its two ends are connected to another and this signal contact of those welded gaskets of this chip respectively, and this second lead-in wire is across the top of this passive component.
4. chip-packaging structure as claimed in claim 3 is characterized in that this sealing also is covered in this second lead-in wire.
5. chip-packaging structure as claimed in claim 1 it is characterized in that the surface of those welding endss has a metal level, and the material of this metal level is selected from a kind of material by nickel, gold and group that these alloys are formed.
6. chip-packaging structure as claimed in claim 1, it is characterized in that this passive component be inductance element and capacity cell one of them.
7. wire bond package structure, be suitable for a chip is electrically connected to a carrier, the surface that it is characterized in that this carrier has a chips welding district, and this chip has an active surface and a corresponding back side, and this chip is pasted in this chips welding district with this back side, and this wire bond package structure comprises at least:
One power supply contact is configured in the surface of this carrier;
One ground contact is configured in the surface of this carrier;
One signal contact is configured in the surface of this carrier, and wherein this power supply contact and this ground contact are positioned at the same side outside this chips welding district, and this signal contact be positioned at this power supply contact and this ground contact away from the outside in this chips welding district;
One passive component is cross-placed between this power supply contact and this ground contact of this carrier, and this passive component has at least two welding endss, and it is electrically connected to this power supply contact and this ground contact respectively;
A plurality of welded gaskets are disposed at this active surface of this chip;
One first lead-in wire is electrically connected one of one of those welded gaskets and those welding endss; And
One second lead-in wire be electrically connected another and this signal contact of those welded gaskets, and this second lead-in wire is across the top of this passive component.
8. wire bond package structure as claimed in claim 7 it is characterized in that the surface of those welding endss has a metal level, and the material of this metal level is selected from a kind of material by nickel, gold and group that these alloys are formed.
9. wire bond package structure as claimed in claim 7, it is characterized in that this passive component be inductance element and capacity cell one of them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03208179 CN2684375Y (en) | 2003-08-25 | 2003-08-25 | Chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03208179 CN2684375Y (en) | 2003-08-25 | 2003-08-25 | Chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2684375Y true CN2684375Y (en) | 2005-03-09 |
Family
ID=34598671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03208179 Expired - Lifetime CN2684375Y (en) | 2003-08-25 | 2003-08-25 | Chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2684375Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386165A (en) * | 2011-10-28 | 2012-03-21 | 三星半导体(中国)研究开发有限公司 | Chip package and manufacturing method thereof |
| CN106158837A (en) * | 2015-04-23 | 2016-11-23 | 朋程科技股份有限公司 | Voltage regulating device |
| WO2020097767A1 (en) * | 2018-11-12 | 2020-05-22 | 北京比特大陆科技有限公司 | Circuit board and supercomputing equipment |
-
2003
- 2003-08-25 CN CN 03208179 patent/CN2684375Y/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386165A (en) * | 2011-10-28 | 2012-03-21 | 三星半导体(中国)研究开发有限公司 | Chip package and manufacturing method thereof |
| CN106158837A (en) * | 2015-04-23 | 2016-11-23 | 朋程科技股份有限公司 | Voltage regulating device |
| CN106158837B (en) * | 2015-04-23 | 2019-01-11 | 朋程科技股份有限公司 | Voltage regulating device |
| WO2020097767A1 (en) * | 2018-11-12 | 2020-05-22 | 北京比特大陆科技有限公司 | Circuit board and supercomputing equipment |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20130825 Granted publication date: 20050309 |