CN1206728C - Chip package and its making process - Google Patents
Chip package and its making process Download PDFInfo
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- CN1206728C CN1206728C CNB021598401A CN02159840A CN1206728C CN 1206728 C CN1206728 C CN 1206728C CN B021598401 A CNB021598401 A CN B021598401A CN 02159840 A CN02159840 A CN 02159840A CN 1206728 C CN1206728 C CN 1206728C
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- chip packaging
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
- H01L23/4922—Bases or plates or solder therefor having a heterogeneous or anisotropic structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A chip package includes a chip having a first surface provided with a first terminal and a second surface provided with at least one second terminal, the second surface being opposite to the first surface, a first substrate arranged on the first surface of the chip and having a first conductive via hole connected to the first terminal, a second substrate arranged on the second surface of the chip and having at least one second conductive via hole connected to the second terminal, and a resin molding part formed around the chip between the first substrate and the second substrate. And the present invention provides a chip package assembly including the chip package. Further, a method of manufacturing the chip package and an assembly including the chip package are provided. The chip package does not use a bonding wire and additional conductive lands, thereby reducing the size of the package and simplifying the manufacturing process.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, relate to a kind of Chip Packaging and make the method for this Chip Packaging, link by the substrate that will have conductive through hole on two surfaces of chip and make the microminiaturized and easier manufacturing of this Chip Packaging.
Background technology
As known for the skilled artisan, packaging semiconductor such as diode or transistor are installed in these potted elements on the printed circuit board (PCB) then.Structurally, the corresponding signal mode (signalpattern) that this encapsulation easily is connected to the terminal of semiconductor chip printed circuit board (PCB) is gone up and is used for protecting semiconductor chip not to be subjected to external stress, thereby improves the stability of this encapsulation.
For satisfying the trend of recent semiconductor product microminiaturization, also made the semiconductor die package microminiaturization.Therefore, introduced chip size packages.Fig. 1 is the schematic cross sectional views of the chip size packages of routine.The structure of the chip size packages 10 of Fig. 1 adopts ceramic substrate 1 and is applied to have the diode of two terminals.
With reference to figure 1, on ceramic substrate 1, form two through holes, the i.e. first through hole 2a and the second through hole 2b.Fill the first and second through hole 2a, 2b so that be electrically connected upper surface and the lower surface of the first and second through hole 2a, 2b with electric conducting material.Then, the upper surface at the first and second through hole 2a, 2b forms conductive welding disk on first and second respectively.On the lower surface of the first and second through hole 2a, 2b, form first and second times conductive welding disk 4a, 4b respectively.Conductive welding disk 3b on second is directly connected to lower surface at diode 5, promptly on the terminal that forms on the installed surface of the diode on the printed circuit board (PCB) 5, and conductive welding disk 3a on first is connected to by lead 7 on the another terminal that forms on the upper surface of diode 5.On the upper surface of the ceramic substrate 1 that comprises diode 5, form the molded item 9 that uses conventional resin so that protection diode 5 is not subjected to external stress.Thereby finish the manufacturing of encapsulation 10.
Fig. 2 is the perspective schematic view of the chip packaging array of routine.
As shown in Figure 2, by the Reflow Soldering connection Chip Packaging of making 10 is installed on the printed circuit board (PCB) 20.Be arranged on the corresponding signal mode of printed circuit board (PCB) 20 by encapsulating 10 last conductive welding disk 3a, 3b and following conductive welding disk 4a, 4b, be connected on the signal mode with scolder 15 diode package 10 electricity and be mechanically connected on the printed circuit board (PCB) 20 by going up conductive welding disk 3a, 3b and following conductive welding disk 4a, 4b then.
As illustrated in fig. 1 and 2, because diode has terminal usually on two opposite face, therefore should these terminals be interconnected by lead.Yet these leads need sizable space of the upper surface of chip, thereby have increased the height of whole encapsulation.In addition, owing on ceramic substrate, form two or three through holes consistent, need the same big zone of total diameter in addition with through hole with the quantity of chip terminal.And, interconnect in order not make the conductive welding disk that on the upper surface of through hole and lower surface, forms, with appointed interval conductive welding disk is separated from each other.Therefore, the size of substrate is being forced a restriction aspect the microminiaturization encapsulation.
Therefore, require a kind of size of energy minimization encapsulation and the encapsulation technology of simplifying its manufacture process.
Summary of the invention
Therefore, in view of the above problems, the present invention has been proposed, an object of the present invention is to provide a kind of stable Chip Packaging, be connected on two opposite faces of chip by the substrate that will have conductive through hole and form resin moulded pieces in the space between two substrates and make this chip array microminiaturization, easier manufacturing and improve its reliability.
Another object of the present invention provides a kind of Chip Packaging assembling parts, according to the structure of Chip Packaging, by innovative approach this Chip Packaging assembling parts is installed on the printed circuit board (PCB).
Another object of the present invention provides a kind of method of making this Chip Packaging.
According to an aspect of the present invention, comprise having the first surface that has the first terminal and have Chip Packaging at least one second terminal and the chip first surface opposing second surface by providing, and be arranged on the first surface of chip and have first substrate of first conductive through hole that is connected to the first terminal, and be arranged on the second surface of chip and second substrate with at least one second conductive through hole that is connected to second terminal is realized above and other objects of the present invention.
In a preferred embodiment according to the present invention, Chip Packaging further comprises the resin moulded pieces that the chip around between first substrate and second substrate forms.
Simultaneously, first substrate can have the size and dimension identical with second substrate, and resin moulded pieces can have the size and dimension identical with second substrate with first substrate, thereby further makes encapsulation microminiaturized.In addition, but the Chip Packaging hexahedral shape.
In addition, preferably, first and second substrates are made with printed circuit board (PCB).
In addition, preferably, each that can be in first and second conductive through holes that form first and second substrates at least one side of each substrate on the shape of approximate half-circular or at least one angle with the shape of approximate 1/4 circle at each substrate.
Preferably, Chip Packaging can be applied to the transistor unit that has the diode element of two terminals and have three terminals.Under the transistor unit situation, second substrate that is connected on the transistorized second surface comprises and two two second conductive through holes that terminal is corresponding.
According to a further aspect in the invention, provide a kind of Chip Packaging assembling parts that comprises Chip Packaging and printed circuit board (PCB).Chip Packaging comprises having the first surface that has the first terminal and have at least one second terminal and the chip first surface opposing second surface, is arranged on the first surface of chip and has first substrate of first conductive through hole that is connected to the first terminal and be arranged on the second surface of chip and have second substrate of at least one second conductive through hole that is connected to second terminal.Printed circuit board (PCB) is included in a plurality of signal modes of terminal that form and that be connected to Chip Packaging on the upper surface of printed circuit board (PCB) and a plurality of conductors that are used for first and second conductive through holes are connected to signal mode.Here, Chip Packaging is vertically mounted on the upper surface of printed circuit board (PCB) so that the outer surface of first and second substrates becomes the side.Preferably, this conductor is a scolder.
According to a further aspect in the invention, be provided for making the method for a plurality of Chip Packaging.The method comprising the steps of: prepare a plurality of chips, each chip has first surface that has a plurality of terminals and the second surface with a plurality of terminals, and second surface is relative with first surface; Prepare first substrate and second substrate, each has a plurality of through holes; The second surface of chip is attached on second substrate so that the terminal of the second surface of chip is connected to the conductive through hole of second substrate; The first surface of chip is attached on first substrate so that the terminal of the first surface of chip is connected on the conductive through hole of first substrate; And Chip Packaging cut be sawn into a plurality of unit Chip Packaging.
Preferably, the step that first and second surfaces of chip is connected in first and second substrates can be included in the upper surface of conductive through hole of first and second substrates or the upper surface of chip is coated with electroconductive binder; And chip is pressed on the upper surface of second substrate or first substrate is pressed on the first surface of chip.
Description of drawings
To be more readily understood above-mentioned and other purposes, feature and other advantages of the present invention from detailed description in conjunction with following accompanying drawing, wherein:
Fig. 1 is the cutaway view of conventional Chip Packaging;
Fig. 2 is the perspective schematic view of conventional chip packaging array;
Fig. 3 is the perspective view of Chip Packaging according to an embodiment of the invention;
Fig. 4 is the perspective schematic view of chip packaging array according to an embodiment of the invention;
Fig. 5 is the perspective schematic view of chip packaging array according to another embodiment of the present invention;
Fig. 6 a is the cutaway view of describing the method for making Chip Packaging of the present invention to 6d; And
Each of Fig. 7 a and 7b is according to another embodiment of the present invention, describes the schematic diagram of the substrate of difform through hole and use through hole.
Embodiment
Fig. 3 is the perspective view of Chip Packaging according to an embodiment of the invention.
With reference to figure 3, encapsulation 40 comprises chip 35 and two substrates, promptly at the first substrate 31a that forms on the upper surface of chip 35 and the second substrate 31b that forms on the lower surface of chip 35.The second terminal (not shown) that chip 35 is included in the first terminal (not shown) that forms on the upper surface and forms on lower surface.The first terminal and second terminal are usually toward each other.The first substrate 31a is connected on the upper surface of chip 35 here, and the second substrate 31b is connected on the lower surface of chip 35 with second terminal with the first terminal.
Forming the first conductive through hole 32a on the first substrate 31a and on the second substrate 31b, forming the second conductive through hole 32b respectively.Fill the first and second conductive through hole 32a and 32b so that the upper surface of the first and second through hole 32a, 32b is electrically connected to the lower surface of the first and second through hole 32a and 32b with electric conducting material.Here, with the appointed area of corresponding first and second substrate 31a of the terminal of chip 35 and 31b on form first and second conductive through hole 32a and the 32b.Therefore, by the first and second conductive through hole 32a and 32b the terminal of chip 35 is electrically connected to external equipment.The position of the first and second conductive through hole 32a and 32b without limits, this will further describe in Fig. 7.
Between the first substrate 31a and the second substrate 31b, be formed for protecting the resin moulded pieces 37 of chip 35.Here, the resin as resin moulded pieces 37 is identical with the resin of the molded item of conventional encapsulation.
The encapsulation of this embodiment of the present invention does not need the large-area any lead of requirement.In addition, owing to needn't on single ceramic substrate, form at least two through holes and at least two conductive welding disks, so the zone that does not need to be used to separate conductive welding disk, thereby the much the same compact package of size of realization and chip.
By Chip Packaging is installed on the printed circuit board (PCB), these characteristics of Chip Packaging of the present invention will be clearer.Fig. 4 is the perspective schematic view of chip packaging array 100 according to an embodiment of the invention.Chip Packaging 50 is installed on the printed circuit board (PCB) 110.Here, the Chip Packaging assembling parts refers to the assembly that comprises Chip Packaging and be used to install the printed circuit board (PCB) of Chip Packaging.
With reference to figure 4, printed circuit board (PCB) 110 is included in the signal mode (not shown) that forms on its upper surface.The signal mode of printed circuit board (PCB) 110 comprises the signal mode on the terminal that is connected to chip 35.Chip Packaging 50 is vertically mounted on the printed circuit board (PCB) 110 becomes the side so that be connected in upper surface and the first and second substrate 41a on the lower surface, the outer surface of 41b of chip 35.That is, be different from conventional installation method, the upper surface and lower surface and the printed circuit plate level that wherein have the Chip Packaging of terminal, Chip Packaging 50 of the present invention is rotated by 90 degrees, and then postrotational Chip Packaging 50 is installed on the printed circuit board (PCB) 110.In this Chip Packaging 50 on being installed in Chip Packaging 110, the first substrate 41a is relative with the second substrate 41b.Therefore, conductive through hole 42a, the 42b that forms on the first and second substrate 41a, 41b is positioned on the side of Chip Packaging assembling parts 100.Here, on printed circuit board (PCB) 110, be formed for and be connected to the welding assembly 115 of the first and second conductive through hole 42a, 42b with the corresponding signal mode of each terminal.As shown in Figure 3, because the first and second conductive through hole 32a, 32b are connected on the corresponding terminal of chip 35, Chip Packaging 50 is connected on the signal mode of printed circuit board (PCB) 110.
In the Chip Packaging assembling parts of Fig. 4, be the size of the suitable Chip Packaging 50 that obtains to be suitable for signal pattern interval, can change the size of Chip Packaging 50 by the thickness that adjustment is attached to the upper surface of Chip Packaging 50 and the first and second substrate 41a, 41b on the lower surface.Therefore, not changing or revising under the situation of signal mode or printed circuit board (PCB) 110, can use Chip Packaging 50 of the present invention.
Fig. 5 is the perspective schematic view of chip packaging array according to another embodiment of the present invention.The chip packaging array of this embodiment of the present invention is by encapsulating a transistor and packaged transistor 105 being installed in the Transistor packages array that forms on the printed circuit board (PCB).Form a terminal on the upper surface of transistor 105 and on the lower surface of transistor 105, forming two terminals.Therefore, the signal mode that the conductive through hole 102a of the first substrate 101a is connected to printed circuit board (PCB) 91 by scolder 115 is connected to a upper terminal of the upper surface of transistor 105 on the printed circuit board (PCB) 91.On the other hand, owing on the lower surface of transistor 105, form two lower terminal, need the another kind of method that two lower terminal is connected to printed circuit board (PCB) 91.
The lower surface that will have the transistor 105 of two lower terminal is attached on the second substrate 101b with two through hole 102b, 102c, and these two through holes are used to connect upper surface and the lower surface of the second substrate 101b.On the upper surface of the second substrate 101b with two conductive through hole 102b, 102c and lower surface, form conductive layer.On the upper surface of the second substrate 101b between conductive through hole 102b, 102c and lower surface, form non-conductive regional A, thereby two lower terminal of chip 105 are connected on the corresponding wired circuit of printed circuit board (PCB) 91.The conductive layer of the lower surface by the second substrate 101b is connected to two conductive through hole 102b, 102c on the wired circuit of printed circuit board (PCB) 91 through scolder 115b, 115c.
Fig. 6 a to 6d is a cutaway view of describing the method for making Chip Packaging of the present invention.
Shown in Fig. 6 a, prepare the first substrate 201a and the second substrate 201b.The a plurality of first conductive through hole 202a that on the first substrate 201a, form and separate by appointed interval, and a plurality of second through hole 202b that on the second substrate 201b, form and separate by appointed interval.Preferably, use the mount means of electroconductive binder as chip.Therefore, shown in Fig. 6 a, on conductive through hole 202a, 202b, be coated with electroconductive binder 203a, 203b.By using electroconductive binder 203a, 203b, be mechanically secured to chip terminal on the substrate and be electrically connected on the conductive through hole of substrate.
Shown in Fig. 6 b, a plurality of chips 205 are being installed on the upper surface of the second substrate 201b so that the lower terminal of chip 205 is connected on the corresponding conductive through hole 202b of second substrate.Afterwards, the first substrate 201a is installed on the chip 205 so that the upper terminal of chip 205 is connected on the corresponding conductive through hole 202a of the second substrate 201a.Here, can chip 205 be fixed on the first and second substrate 201a, the 201b, shown in Fig. 6 a by the above-mentioned electroconductive binder 203 that is coated on conductive through hole 202a, the 202b.
Shown in Fig. 6 c, fill space between the first substrate 201a and the second substrate 201b with resin, thereby form resin moulded pieces 207.Resin moulded pieces 207 is used for protecting chip 205.
The assembly of manufacturing is cut is sawn into and cuts into a plurality of Chip Packaging 200, shown in Fig. 6 d.
As mentioned above, use substrate to be easy to make these Chip Packaging 200 of the present invention with conductive through hole.
In Chip Packaging of the present invention, conductive through hole plays a part to be electrically connected on the signal mode of printed circuit board (PCB) by the terminal of welding with chip.This conductive through hole to its shape without limits.
Fig. 7 a and 7b represent can be used on the different shape of the through hole on the Chip Packaging 210,220 of the present invention and the substrate that uses through hole.
Shown in Fig. 7 a, on each angle of substrate 211, form conductive through hole 213.Initial substrate 211 ' on form former through hole 213 ' in, by initial substrate 211 ' the intersection region of line (scribleline) on form these conductive through holes 213 of former through hole 213 ' obtain.After the initial substrate 211 of Fig. 7 a ' cut is sawn into and cuts into a plurality of unit substrate 211, on each angle of single substrate 211, form the through hole 213 of 4 1/4 circles.This side that may also will have two 1/4 circular conductive through holes 213 at two 1/4 manholes of homonymy formation 213 of substrate 211 is installed on the printed circuit board (PCB).
Shown in Fig. 7 b, on two opposite sides of substrate 221, form conductive through hole 223.Initial substrate 221 ' on form former through hole 223 ' in, by initial substrate 221 ' the zone line of line on form these conductive through holes 223 of former through hole 223 ' obtain.After the initial substrate 221 of Fig. 7 b ' cut is sawn into and cuts into a plurality of unit substrate 221, on two opposite sides of single substrate 221, form 2 semi-circular through hole 223.This side that can form a semi-circular through hole 223 and will have a semi-circular through hole 223 on a side of substrate 221 is installed on the printed circuit board (PCB).
Under the situation of the conductive through hole that uses Fig. 7 a and 7b, when being revolved, the Chip Packaging of manufacturing turn 90 degrees and when being installed in postrotational Chip Packaging on the printed circuit board (PCB), conductive through hole more approaches the surface of printed circuit board (PCB), thereby is connected on the signal mode of printed circuit board (PCB) by welding step these conductive through holes with Fig. 7 a and 7b easilier.
As what see from top description, according to the present invention, be mounted on by the substrate that will have conductive through hole on two opposite faces of chip and and make the manufacture method that this Chip Packaging is more microminiaturized and more simplify this Chip Packaging by in the space of two substrates, forming resin moulded pieces.In addition, can improve the reliability of Chip Packaging, thereby make more stable encapsulation.
Although disclose the above embodiment of the present invention for the purpose of illustration, those of ordinary skill in the art has various changes, interpolation and replacement with recognizing under the situation that does not break away from disclosed scope and spirit of the present invention in the accessory claim book.
Claims (21)
1. Chip Packaging comprises:
Chip has first surface that has the first terminal and the second surface that has at least one second terminal, and second surface is relative with first surface;
First substrate is arranged on the first surface of described chip and has first conductive through hole that is connected to the first terminal
Second substrate is arranged on the second surface of described chip and has second conductive through hole that is connected to second terminal at least; With
Resin moulded pieces around the described chip formation between described first substrate and described second substrate.
2. Chip Packaging as claimed in claim 1, wherein said first substrate has identical size and shape with described second substrate, and described resin moulded pieces has identical size and shape with described first substrate and described second substrate.
3. Chip Packaging as claimed in claim 1, described Chip Packaging has hexahedral shape.
4. Chip Packaging as claimed in claim 1, wherein said two substrates are made by printed circuit board (PCB).
5. Chip Packaging as claimed in claim 1 wherein forms each of described first and second conductive through holes of described first and second substrates with semicircular shape at least one side of each substrate.
6. Chip Packaging as claimed in claim 1 wherein forms each of described first and second conductive through holes of described first and second substrates with the shape of 1/4 circle at least one angle of each substrate.
7. Chip Packaging as claimed in claim 1, wherein said chip is a diode element, and the described second surface of its chips comprises one second terminal, and described second substrate comprises one second conductive through hole.
8. Chip Packaging as claimed in claim 1, wherein said chip is a transistor unit, and the described second surface of its chips comprises two second independent terminals, and described second substrate comprises two second conductive through holes.
9. Chip Packaging assembling parts comprises:
Chip Packaging as claimed in claim 1,
And
Printed circuit board (PCB) comprises:
A plurality of signal modes of described terminal that form and that be connected to Chip Packaging on the upper surface of printed circuit board (PCB), and
A plurality of conductors are used for described first and second conductive through holes are connected to described signal mode,
Wherein said Chip Packaging vertically is installed on the upper surface of described printed circuit board (PCB) so that the outer surface of described first and second substrates becomes the side.
10. Chip Packaging assembling parts as claimed in claim 9, wherein said first substrate has identical size and shape with described second substrate, and described resin moulded pieces has identical size and shape with described first substrate and described second substrate.
11. Chip Packaging assembling parts as claimed in claim 9, described Chip Packaging has hexahedral shape.
12. Chip Packaging assembling parts as claimed in claim 9, wherein said two substrates are made by printed circuit board (PCB).
13. Chip Packaging assembling parts as claimed in claim 9 wherein forms each of described first and second conductive through holes of described first and second substrates with semicircular shape at least one side of each substrate.
14. Chip Packaging assembling parts as claimed in claim 9 wherein forms each of described first and second conductive through holes of described first and second substrates with the shape of 1/4 circle at least one angle of each substrate.
15. Chip Packaging assembling parts as claimed in claim 9, wherein said chip is a diode element, and the described second surface of its chips comprises one second terminal, and described second substrate comprises one second conductive through hole.
16. Chip Packaging assembling parts as claimed in claim 9, wherein said chip is a transistor unit, and the described second surface of its chips comprises two second independent terminals, and described second substrate comprises two second conductive through holes.
17. a method of making a plurality of Chip Packaging, described method comprises step:
Prepare a plurality of chips, each chip has first surface that has a plurality of terminals and the second surface that has a plurality of terminals, and second surface is relative with first surface;
Prepare first substrate and second substrate, each substrate has a plurality of through holes;
The second surface of chip is attached on second substrate so that the terminal of the second surface of chip is connected on the conductive through hole of second substrate;
The first surface of chip is attached on first substrate so that the terminal of the first surface of chip is connected on the conductive through hole of first substrate;
Between two substrates, form resin moulded pieces in the space; And
Chip assembly cut be sawn into and cut into a plurality of unit Chip Packaging.
18. the method for manufacturing Chip Packaging as claimed in claim 17, wherein the described step that the second surface of chip is attached on second substrate comprises substep:
On the upper surface of the conductive through hole of second substrate, be coated with electroconductive binder; And
Chip is pressed on the upper surface of second substrate.
19. the method for manufacturing Chip Packaging as claimed in claim 17, wherein the described step that the first surface of chip is attached on first substrate comprises substep:
On the first surface of chip, be coated with electroconductive binder; And
First substrate is pressed on the first surface of chip.
20. the method for manufacturing Chip Packaging as claimed in claim 17, wherein said chip is a diode element.
21. the method for manufacturing Chip Packaging as claimed in claim 17, wherein said chip is a transistor unit, and wherein on any one of described first and second surfaces of chip, form two terminals, and on any one of described first and second substrates, form two conductive through holes so that corresponding with two terminals.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0086347A KR100401975B1 (en) | 2001-12-27 | 2001-12-27 | Chip package and the method of fabricating the same |
| KR86347/2001 | 2001-12-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1433071A CN1433071A (en) | 2003-07-30 |
| CN1206728C true CN1206728C (en) | 2005-06-15 |
Family
ID=19717711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021598401A Expired - Fee Related CN1206728C (en) | 2001-12-27 | 2002-12-27 | Chip package and its making process |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6653725B2 (en) |
| JP (1) | JP2003197840A (en) |
| KR (1) | KR100401975B1 (en) |
| CN (1) | CN1206728C (en) |
| DE (1) | DE10260005A1 (en) |
| TW (1) | TW579585B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110349920A (en) * | 2019-06-27 | 2019-10-18 | 深圳第三代半导体研究院 | A kind of diode chip package structure and its packaging method |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6762076B2 (en) * | 2002-02-20 | 2004-07-13 | Intel Corporation | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
| US7087538B2 (en) * | 2004-08-16 | 2006-08-08 | Intel Corporation | Method to fill the gap between coupled wafers |
| US7284896B2 (en) * | 2005-04-15 | 2007-10-23 | Jiahn-Chang Wu | Light unit display |
| US7342308B2 (en) * | 2005-12-20 | 2008-03-11 | Atmel Corporation | Component stacking for integrated circuit electronic package |
| US7821122B2 (en) * | 2005-12-22 | 2010-10-26 | Atmel Corporation | Method and system for increasing circuitry interconnection and component capacity in a multi-component package |
| JP4503046B2 (en) | 2007-05-30 | 2010-07-14 | 株式会社東芝 | Manufacturing method of semiconductor device |
| US8053885B2 (en) * | 2009-01-12 | 2011-11-08 | Harvatek Corporation | Wafer level vertical diode package structure and method for making the same |
| JP2011023463A (en) * | 2009-07-14 | 2011-02-03 | Denso Corp | Semiconductor module |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3708722A (en) * | 1970-12-18 | 1973-01-02 | Erie Technological Prod Inc | Semiconductor device with soldered terminals and plastic housing and method of making the same |
| US4005457A (en) * | 1975-07-10 | 1977-01-25 | Semimetals, Inc. | Semiconductor assembly, method of manufacturing same, and bonding agent therefor |
| US4574297A (en) * | 1981-07-15 | 1986-03-04 | Rohm Company Limited | Encapsulated semiconductor with terminals having tabs to increase solder wetting |
| JP2713254B2 (en) * | 1995-07-13 | 1998-02-16 | 日本電気株式会社 | Package for integrated circuit, method of manufacturing the same, and method of converting pad arrangement |
| JPH1032224A (en) * | 1996-07-15 | 1998-02-03 | Shinko Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JP3604108B2 (en) * | 1997-02-17 | 2004-12-22 | 株式会社シチズン電子 | Manufacturing method of chip type optical semiconductor |
| US6300686B1 (en) * | 1997-10-02 | 2001-10-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor chip bonded to a thermal conductive sheet having a filled through hole for electrical connection |
| JPH11312710A (en) * | 1998-04-30 | 1999-11-09 | Murata Mfg Co Ltd | Method for connecting electronic component and connecting structure |
| KR20000026099A (en) * | 1998-10-17 | 2000-05-06 | 김영환 | Chip size semiconductor package and method for making the same |
-
2001
- 2001-12-27 KR KR10-2001-0086347A patent/KR100401975B1/en not_active IP Right Cessation
-
2002
- 2002-12-18 US US10/321,427 patent/US6653725B2/en not_active Expired - Fee Related
- 2002-12-19 JP JP2002368735A patent/JP2003197840A/en active Pending
- 2002-12-20 DE DE10260005A patent/DE10260005A1/en not_active Ceased
- 2002-12-23 TW TW091137078A patent/TW579585B/en not_active IP Right Cessation
- 2002-12-27 CN CNB021598401A patent/CN1206728C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110349920A (en) * | 2019-06-27 | 2019-10-18 | 深圳第三代半导体研究院 | A kind of diode chip package structure and its packaging method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003197840A (en) | 2003-07-11 |
| KR100401975B1 (en) | 2003-10-17 |
| US20030122230A1 (en) | 2003-07-03 |
| DE10260005A1 (en) | 2003-07-17 |
| TW200411855A (en) | 2004-07-01 |
| TW579585B (en) | 2004-03-11 |
| CN1433071A (en) | 2003-07-30 |
| KR20030056176A (en) | 2003-07-04 |
| US6653725B2 (en) | 2003-11-25 |
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