CN110349920A - A kind of diode chip package structure and its packaging method - Google Patents
A kind of diode chip package structure and its packaging method Download PDFInfo
- Publication number
- CN110349920A CN110349920A CN201910566691.4A CN201910566691A CN110349920A CN 110349920 A CN110349920 A CN 110349920A CN 201910566691 A CN201910566691 A CN 201910566691A CN 110349920 A CN110349920 A CN 110349920A
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- China
- Prior art keywords
- chip
- electrode
- metal
- backlight unit
- diode chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 25
- 238000004806 packaging method and process Methods 0.000 title claims description 21
- 239000002184 metal Substances 0.000 claims abstract description 57
- 229910052751 metal Inorganic materials 0.000 claims abstract description 57
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052802 copper Inorganic materials 0.000 claims abstract description 31
- 239000010949 copper Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 229910000831 Steel Inorganic materials 0.000 claims abstract description 23
- 239000010959 steel Substances 0.000 claims abstract description 23
- 238000005538 encapsulation Methods 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 4
- 238000009826 distribution Methods 0.000 claims abstract description 4
- 239000004033 plastic Substances 0.000 claims description 35
- 239000005022 packaging material Substances 0.000 claims description 26
- 239000003822 epoxy resin Substances 0.000 claims description 11
- 229920000647 polyepoxide Polymers 0.000 claims description 11
- 238000000605 extraction Methods 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- 239000011135 tin Substances 0.000 claims description 2
- 239000010426 asphalt Substances 0.000 claims 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 4
- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 238000002360 preparation method Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 3
- 238000005234 chemical deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Abstract
A kind of encapsulating structure of diode chip for backlight unit, comprising: electrode pattern, chip, layer, the substrate of vertical distribution from top to bottom, and it is coated on the plastic-sealed body of chip surrounding；The substrate includes: metal aperture, the horizontally disposed plate being spaced apart by metal aperture, the front copper electrode and back side copper electrode being arranged by the vertical symmetry that metal aperture connects；The front copper electrode and back side copper electrode diameter are greater than metal bore dia, and the electrode pattern forms hollow out plastic-sealed body using steel mesh or silk screen, form conductive metal layer acquisition by physically or chemically deposition on the hollow out plastic-sealed body.The present invention solves low, the at high cost technical problem of original small size diode chip package structure production efficiency, realizes the high efficiency, low cost encapsulation of small size diode chip for backlight unit, and lower material resistance is low in equal volume, excellent in heat dissipation effect.
Description
Technical field
The present invention relates to chip packages to interconnect field, relates more specifically to small-sized single chip encapsulation technology.
Background technique
As electronic product is towards the lightening hair of miniaturization, integrated direction development and the consumer electronics such as mobile phone
Exhibition trend.Entire consumer corresponding electronic component is also towards miniaturization.
Diode traditional at present is packaged by the processing that traditional routing plastic packaging form carries out product with one
Determine the diode of function.The characteristics of being limited to routing technique, the packaging technology is existing, and there are two problems: first is that needing to control one
Fixed loop height, bank across footpath etc. cause the area discrepancy of package body sizes and chip size excessive, will lead to accounting for for device
It is big with space；Second is that the process characteristic of routing needs to burn a metal ball in chip top electrode, then bank is elongated to pad position
Cutting is set, entire processing procedure feature production efficiency is low；Third is that the packaging technology of traditional routing collocation plastic packaging, existing equipment and ability are equal
It is to be processed using small size, such as 240mm*76.3mm, production efficiency is low to cause overall cost to rise.
Summary of the invention
In order to overcome the deficiencies of the prior art, the technical issues of solving original single small-sized package low efficiency at high cost, this
Invention provides a kind of encapsulating structure of diode chip for backlight unit, comprising:
Electrode pattern, chip, layer, the substrate of vertical distribution from top to bottom, and it is coated on the plastic-sealed body of chip surrounding；
The substrate includes: metal aperture, the horizontally disposed plate being spaced apart by metal aperture, hanging down by metal aperture connection
Straight symmetrically arranged front copper electrode and back side copper electrode；The front copper electrode and back side copper electrode length are straight greater than metal aperture
Diameter；
The electrode pattern forms hollow out plastic-sealed body using steel mesh or silk screen, in hollow out plastic-sealed body upper surface physics or
Chemical deposition forms conductive metal layer and obtains；
The electrode pattern include the one or more electrode columns being connected with chip upper surface and with it is one or more of
The connected horizontally disposed electrode plate in pole upper surface.
Preferably, the sheet material is epoxy resin, and the conductive metal layer material is copper, tin, silver；The solder packet
Containing conductive material.
Preferably, the metal aperture is metal throuth hole or metal blind hole.
Preferably, the encapsulation diameter is greater than 50 μm of the chip diameter.
A kind of packaging method of diode chip for backlight unit, comprising:
S1: preparing substrate, and the substrate includes the multiple front copper electrodes being arranged in pairs connected by multiple metal apertures
With multiple back side copper electrodes；
S2: piece is mounted on the front copper electrode；
S3: steel mesh or silk screen are covered into the chip, filling plastic packaging material to the chip；
S4: removing steel mesh or silk screen, forms conduction using either physically or chemically deposition on the chip upper layer of the plastic packaging
Metal layer；
S5: cutting forms single encapsulation diode chip for backlight unit.
Preferably, the step 3 includes:
S3.1: according to package dimension, shape, electrode pattern size, shape define size, the shape of steel mesh or silk screen；
S3.2: the steel mesh or silk screen are covered into the chip；
S3.2: plastic packaging material is filled to the chip to steel mesh or silk screen covering；
S3.3: the chip of baking-curing plastic packaging material filling.
Preferably, the step 5 includes:
S5.1 extraction electrode figure forms external electrode；
S5.2 etches the substrate conductive layer, forms single encapsulation diode electrode.
Preferably, the mounting method of the step 2 are as follows:
Using the conductive solder fixed chip that can make chip back electrode conduction.
Preferably, the substrate further includes the epoxy resin board separated by metal aperture, the metal aperture be metal throuth hole or
Metal blind hole, the plastic packaging material of the step 3 are liquid plastic packaging material, and the plastic packaging material is epoxy resin.
Preferably, the S4 includes:
The production of conductive metal sandwich circuit and the extraction of top electrodes are carried out using physically or chemically mode.
The present invention completes the integral-filled of plastic packaging material using steel mesh or screen printing mode, using physically or chemically mode into
Row conduction sandwich circuit completes the extractions of top electrodes, substitutes traditional routing processing method, efficiently solves traditional envelope
The dress technical problem that processing efficiency is low, at high cost realizes that low isometric lower material resistance, excellent in heat dissipation effect, chip size are small
Technical effect.
Detailed description of the invention
Fig. 1 is the double-sided substrate side view for the diode chip for backlight unit preparation method that embodiment two provides.
Fig. 2 is the chip attachment side view for the diode chip for backlight unit preparation method that embodiment two provides.
Fig. 3 is that the plastic packaging material for the diode chip for backlight unit preparation method that embodiment two provides fills side view.
Fig. 4 is the conductive metal layer side view for the diode chip for backlight unit preparation method that embodiment two provides.
Chip side view after the etching for the diode chip for backlight unit preparation method that Fig. 5 provides for embodiment two.
Fig. 6 is single encapsulation diode chip for backlight unit side view of the diode chip for backlight unit preparation method that embodiment two provides.
Copper electrode 1, through-hole/blind hole 2, epoxy resin board 3, chip 4, solder 5, plastic packaging material 6, conductive metal 7, electrode pattern
8
Specific embodiment
The following detailed description of specific implementation of the invention, it is necessary to it is indicated herein to be, implement to be only intended to this hair below
Bright further explanation, should not be understood as limiting the scope of the invention, and field person skilled in the art is according to above-mentioned
Some nonessential modifications and adaptations that summary of the invention makes the present invention, still fall within protection scope of the present invention.
Embodiment one
The present embodiment provides a kind of encapsulating structures of diode chip for backlight unit, comprising:
Electrode pattern, chip, layer, the substrate of vertical distribution from top to bottom, and it is coated on the plastic-sealed body of chip surrounding；
The substrate includes: metal aperture, the horizontally disposed plate being spaced apart by metal aperture, hanging down by metal aperture connection
Straight symmetrically arranged front copper electrode and back side copper electrode；The front copper electrode and back side copper electrode length are straight greater than metal aperture
Diameter,
The electrode pattern forms hollow out plastic-sealed body using steel mesh or silk screen, uses object in hollow out plastic-sealed body upper surface
Reason or chemical deposition form conductive metal layer and obtain,
The electrode pattern include two electrode columns being connected with chip upper surface and with described two electrode column upper surfaces
Connected horizontally disposed electrode plate.
In some preferred embodiments, the sheet material be epoxy resin, the conductive metal layer material be copper,
The materials such as tin, silver or its alloy；The solder includes conductive material.
In some preferred embodiments, the metal aperture is metal throuth hole or metal blind hole.
In some preferred embodiments, the encapsulation diameter is that the encapsulation diameter is 100 μm of 50- bigger than chip, or
50-500μm。
A kind of packaging method of diode chip for backlight unit, comprising:
S1: preparing substrate, and the substrate includes the multiple front copper electrodes being arranged in pairs connected by multiple metal apertures
With multiple back side copper electrodes；
S2: the pasting chip on the front copper electrode；
S3: steel mesh or silk screen are covered into the chip, filling plastic packaging material to the chip；
S4: removing steel mesh or silk screen, forms conduction using either physically or chemically deposition on the chip upper layer of the plastic packaging
Metal layer；
S5: cutting forms single encapsulation diode chip for backlight unit.
Specifically, the step 3 includes:
S3.1: according to package dimension, shape, electrode pattern size, shape define size, the shape of steel mesh or silk screen；
S3.2: the steel mesh or silk screen are covered into the chip；
S3.2: plastic packaging material is filled to the chip to steel mesh or silk screen covering；
S3.3: the chip of baking-curing plastic packaging material filling.
Specifically, the step 5 includes:
S51 extraction electrode figure forms external electrode；
S52 etches the substrate conductive layer, forms single encapsulation diode electrode.
Specifically, the mounting method of the step 2 are as follows:
Using the conductive solder fixed chip that can make chip back electrode conduction.
Specifically, the substrate further includes the epoxy resin board separated by metal aperture, the metal aperture be metal throuth hole or
Metal blind hole, the plastic packaging material of the step 3 are liquid plastic packaging material, and the plastic packaging material is epoxy resin.
Specifically, the S4 includes:
The production of conductive metal sandwich circuit and the extraction of top electrodes are carried out using physically or chemically mode.
Embodiment two
The present embodiment provides a kind of packaging methods of diode chip for backlight unit, as shown in figures 1 to 6.
S1 prepares large-sized double-sided substrate, substrate size 406mm*508mm.The two sides copper electrode 1 of this double-sided substrate
It is to be connected by metal aperture 2 (through-hole or blind hole), double-sided substrate includes epoxy resin board 3；
S2 completes the fixation position on above-mentioned double-sided substrate the attachment of chip 4, the fixed solder 5 using conduction of chip
It is processed, guarantees that chip back electrode can be with normally；
S3 has completed the dual platen of chip attachment, and the steel mesh for fixed design of arranging in pairs or groups completes liquid plastic packaging material around chip
And the filling of top section position, fixed design steel mesh are to block chip front side part, rest part hollow out is used for plastic packaging material
Filling.Baking-curing is carried out after the completion of plastic packaging material filling, obtains molding plastic packaging 6；
The cured plate containing chip of above-mentioned completion is powered on the surface of the material by way of physics or chemistry and is plated by S4
One layer of conductive metal 7 is realized conductive interconnections, and the upper partial electrode of chip is drawn, the external electrode as device；
S5 be directed to completed interconnection circuit board further according to actual product design by Conductive Layer Etch at demand
Electrode size and shape, obtain electrode pattern 8；
S6 cuts the plate of above-mentioned completion, forms single encapsulation diode component, the single encapsulation diode
Device architecture is as shown in Figure 6.
The encapsulating structure and its packaging method of diode chip for backlight unit provided by the invention, can get following technical effect:
1) preparation efficiency is high.It is packaged using plate grade size, it is bigger than conventional package processing procedure size, while plate of arranging in pairs or groups
Procedure for producing can effectively promote overall processing efficiency, reduce product cost；
2) preparation cost is low.The integral-filled equal instead of traditional plastic packaging processing procedure of plastic packaging material is completed using steel mesh mode of printing
Plastic packaging material is filled to mould inside using Molding equipment and completes plastic packaging processing procedure, it is expensive to reduce traditional large scale plastic packaging equipment
Production prices；
3) material resistance is reduced.Heat radiation performance.Conductive sandwich circuit is carried out using physically or chemically mode to complete
The extraction of top electrodes substitutes the extraction that traditional routing processing method realizes top electrodes, leads compared to traditional routing technique copper
Line is more advantageous to more greatly resistance, the heat radiation performance etc. for reducing material in equal volume；
4) single device encapsulation of smaller szie is realized.Under the premise of guaranteeing properties of product, single device size only compares core
Piece is unilateral greatly a bit, can reduce the processing dimension of encapsulation.
Although for illustrative purposes, it has been described that exemplary embodiments of the present invention, those skilled in the art
Member it will be understood that, can be in form and details in the case where the scope and spirit for not departing from invention disclosed in appended claims
On the change that carry out various modifications, add and replace etc., and all these changes all should belong to appended claims of the present invention
Protection scope, and each step in the claimed each department of product and method, can in any combination
Form is combined.Therefore, to disclosed in this invention the description of embodiment be not intended to limit the scope of the invention,
But for describing the present invention.Correspondingly, the scope of the present invention is not limited by embodiment of above, but by claim or
Its equivalent is defined.
Claims (10)
1. a kind of encapsulating structure of diode chip for backlight unit characterized by comprising
Electrode pattern, chip, layer, the substrate of vertical distribution from top to bottom, and it is coated on the plastic-sealed body of chip surrounding；
The substrate includes: metal aperture, the horizontally disposed plate being spaced apart by metal aperture, by the vertical right of metal aperture connection
Claim the front copper electrode and back side copper electrode of setting；The front copper electrode and back side copper electrode length are greater than metal bore dia,
The electrode pattern forms hollow out plastic-sealed body using steel mesh or silk screen, physically or chemically deposits on the hollow out plastic-sealed body
Conductive metal layer is formed to obtain,
The electrode pattern include the one or more electrode columns being connected with chip upper surface and with one or more of electrodes
The connected horizontally disposed electrode plate in column upper surface.
2. a kind of encapsulating structure of diode chip for backlight unit as described in claim 1, which is characterized in that the sheet material is asphalt mixtures modified by epoxy resin
Rouge, the conductive metal layer material are copper, tin, silver；The solder includes conductive material.
3. a kind of encapsulating structure of diode chip for backlight unit as described in claim 1, which is characterized in that the metal aperture is metal throuth hole
Or metal blind hole.
4. a kind of encapsulating structure of diode chip for backlight unit as described in claim 1, which is characterized in that the encapsulation diameter is greater than described
50 μm of chip diameter.
5. a kind of packaging method of diode chip for backlight unit characterized by comprising
S1: preparing substrate, and the substrate includes the multiple front copper electrodes being arranged in pairs connected by multiple metal apertures and more
A back side copper electrode；
S2: adornment chip is pasted on the front copper electrode；
S3: steel mesh or silk screen are covered into the chip, filling plastic packaging material to the chip；
S4: removing steel mesh or silk screen, forms conductive metal using either physically or chemically deposition on the chip upper layer of the plastic packaging
Layer；
S5: cutting forms single encapsulation diode chip for backlight unit.
6. a kind of packaging method of diode chip for backlight unit as claimed in claim 5, which is characterized in that the S3 includes:
S3.1: according to package dimension, shape, electrode pattern size, shape define size, the shape of steel mesh or silk screen；
S3.2: the steel mesh or silk screen are covered into the chip；
S3.2: plastic packaging material is filled to the chip to steel mesh or silk screen covering；
S3.3: the chip of baking-curing plastic packaging material filling.
7. a kind of packaging method of diode chip for backlight unit as claimed in claim 5, which is characterized in that the S5 includes:
S5.1 extraction electrode figure forms external electrode；
S5.2 etches the substrate conductive layer, forms single encapsulation diode electrode.
8. a kind of packaging method of diode chip for backlight unit as claimed in claim 5, which is characterized in that the mounting method of the S2
Are as follows:
Using the conductive solder fixed chip that can make chip back electrode conduction.
9. a kind of packaging method of diode chip for backlight unit as claimed in claim 5, which is characterized in that the substrate further includes golden
Belong to the epoxy resin board that hole separates, the metal aperture is metal throuth hole or metal blind hole, and the plastic packaging material of the S3 is liquid plastic packaging
Material, the plastic packaging material are epoxy resin.
10. a kind of packaging method of diode chip for backlight unit as claimed in claim 5, which is characterized in that the S4 includes:
The production of conductive metal sandwich circuit and the extraction of top electrodes are carried out using physically or chemically mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910566691.4A CN110349920A (en) | 2019-06-27 | 2019-06-27 | A kind of diode chip package structure and its packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910566691.4A CN110349920A (en) | 2019-06-27 | 2019-06-27 | A kind of diode chip package structure and its packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110349920A true CN110349920A (en) | 2019-10-18 |
Family
ID=68176818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910566691.4A Pending CN110349920A (en) | 2019-06-27 | 2019-06-27 | A kind of diode chip package structure and its packaging method |
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| Country | Link |
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| CN (1) | CN110349920A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112417729A (en) * | 2020-11-23 | 2021-02-26 | 复旦大学 | Ant colony algorithm-based SiC MOSFET packaging structure optimization method |
| CN113707632A (en) * | 2021-08-30 | 2021-11-26 | 中国振华集团永光电子有限公司（国营第八七三厂） | Three-terminal rectifying circuit module and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1206728C (en) * | 2001-12-27 | 2005-06-15 | 三星电机株式会社 | Chip package and its making process |
| JP2005340233A (en) * | 2004-05-24 | 2005-12-08 | Hitachi Kokusai Electric Inc | Electronic circuit substrate |
| US20090267230A1 (en) * | 2008-04-24 | 2009-10-29 | Mutual-Pak Technology Co., Ltd. | Package structure for integrated circuit device and method of the same |
| CN106653702A (en) * | 2015-11-04 | 2017-05-10 | 中国科学院深圳先进技术研究院 | Packaging structure of implanted chip and manufacturing method thereof |
| CN107093588A (en) * | 2017-04-21 | 2017-08-25 | 中航（重庆）微电子有限公司 | A kind of vertical encapsulating structure of chip double-side and method for packing |
| CN107968074A (en) * | 2016-10-19 | 2018-04-27 | 江西省昌大光电科技有限公司 | A kind of GaN base electronic device |
-
2019
- 2019-06-27 CN CN201910566691.4A patent/CN110349920A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1206728C (en) * | 2001-12-27 | 2005-06-15 | 三星电机株式会社 | Chip package and its making process |
| JP2005340233A (en) * | 2004-05-24 | 2005-12-08 | Hitachi Kokusai Electric Inc | Electronic circuit substrate |
| US20090267230A1 (en) * | 2008-04-24 | 2009-10-29 | Mutual-Pak Technology Co., Ltd. | Package structure for integrated circuit device and method of the same |
| CN106653702A (en) * | 2015-11-04 | 2017-05-10 | 中国科学院深圳先进技术研究院 | Packaging structure of implanted chip and manufacturing method thereof |
| CN107968074A (en) * | 2016-10-19 | 2018-04-27 | 江西省昌大光电科技有限公司 | A kind of GaN base electronic device |
| CN107093588A (en) * | 2017-04-21 | 2017-08-25 | 中航（重庆）微电子有限公司 | A kind of vertical encapsulating structure of chip double-side and method for packing |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112417729A (en) * | 2020-11-23 | 2021-02-26 | 复旦大学 | Ant colony algorithm-based SiC MOSFET packaging structure optimization method |
| CN112417729B (en) * | 2020-11-23 | 2023-04-18 | 复旦大学 | Ant colony algorithm-based SiC MOSFET packaging structure optimization method |
| CN113707632A (en) * | 2021-08-30 | 2021-11-26 | 中国振华集团永光电子有限公司（国营第八七三厂） | Three-terminal rectifying circuit module and manufacturing method thereof |
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Application publication date: 20191018 |