TWI262587B - Leadframe and the manufacturing method thereof - Google Patents

Abstract

The present invention discloses a leadframe and the manufacturing method thereof, which is working on both sides of metal plates locally to form a denser and precise alignment of circuit pitch; locally working on single surface of metal plate to form patternized grooves; filling into insulative material or material with different conductivity to isolate the metal plate as a plurality of conductive areas or areas with special electrical characteristics, and providing additional support strength for the circuit on the metal plate. The present invention could improve the manufacturing limitation of conventional leadframe, provide better heat dissipation, and have high lead number and versatile features.

Description

1262587 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a lead frame fabrication technique, and more particularly to a lead frame capable of having a plurality of conductive regions or special electrical regions and providing additional support strength of a metal plate line. And its production method. [Prior Art] According to the purpose of electronic packaging, it can be used as a transmission circuit signal, a transmission of electric energy, a heat dissipation path, and structural protection and support. In the post-semiconductor packaging process, lead frame and semi-conductor • The IC substrate is used as a bridge between the integrated circuit chip and the external circuit to transmit the internal electronic signals of the chip to the external system board. However, as the function of the chip circuit is improved, the input and output contacts of the chip are also greatly increased. The lead frame carrying the chip can only use four sides as pins, and cannot provide enough pins; and the lead frame can only be connected and simple. Another method is to use a printed circuit board (PCB) as a carrier for carrying the wafer, and supplemented by solder balls arranged in an array at the bottom instead of the traditional way of making the lead around the metal lead frame. The advantage of the packaging technology is that the number of pins can be increased under the same size area, and the package size is much smaller. However, as the power consumption of such package components is increasing, the heat dissipation problem of the package components becomes an insurmountable problem. But as the integration of the chip functions (SOC) simplifies the circuit design, some CSP-size packages turn to the use of leadframes for heat dissipation; they also breed the complexity of the line design between the CSP and the leadframe, such as QF N. An increase in the demand for packaged products is an obvious example. But up and down

[Invention, ΐ 方式 ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” The invention is made by using the applicable invention, the filling and the plating are performed on the main sides of the phase line frame, and the single-sided object is made to know that the other material of the wire is in the upper and lower materials. The hole technology is the same size as the circumference, and the time is engraved into the support frame. The material and the semiconductor are supported on the surface, so that it can be said to provide a wire. Or machining deep _ dense line spacing to create grooves, and then complete the problem of groove and packaging. A fabrication of a wire support structure is provided to provide packaging requirements. Providing a columnar conductor in which the lead frame is connected does not require the trouble of eliminating the winding as a printed circuit for a larger LGA (Land grid frame is manufactured by molding or penetrating and can accurately align with the groove/concave side The circuit, the manufacturing method of the frame, the manufacturing method of the circuit, and the wire of the pattern of the board to reduce the size of the board, the pin is not array)

Page 6 1262587 V. INSTRUCTIONS This solution is filled into the rack. This issue 'metal plate way to selective layer; then • to make in. The hair plate; for this type, the groove and the plug filler are mechanically machined in the groove; the number of guides is more effective (3) and the material that is not penetrated is one of the embodiments. The metal plate is formed with a through-groove groove design; and is formed in the patterned through groove or groove to form a wire having a plurality of conductive regions; forming a plurality of through-fill plugs on the metal plate to metal into the metal plate The board indicates that another metal plate is provided for the selection of a plurality of through-grooves to fill the deep-controlled forming or the upper/lower groove or the unfilled filling layer. The completion of the review further explains the situation as a lead frame. The manufacturing method provides etching, machining deep control molding or casting groove and lower/upper groove; forming a plurality of conductive etching and machining on the lower surface of the metal plate in the through groove and the lower/upper groove; In the deep control forming or casting, a plurality of upper/lower grooves are formed, and a lead frame for completing the circuit is manufactured by providing a metal name, mechanically deep-forming or praying and lower/upper grooves. And filling the through grooves and the lower/upper; then re-engraving and casting the metal plate to form a number on the upper surface of the metal, and selectively filling the through grooves and the upper/lower grooves And the production of the metal plate and the lower surface line. The structural features of the present invention and the understanding and understanding of the present invention are described in the preferred embodiments and as follows:

Page 7 1262587 V. Description of the Invention (4) One invention is a lead frame and a manufacturing method thereof, which are fabricated by selective etching, deep control forming technology or casting method, double-sided etching technology and filler filling technology. As a metal plate lead frame of a semiconductor carrier board, it has both good heat dissipation effect and can be applied to a high pin count semiconductor package to overcome the problems of the existing lead frame fabrication and packaging. Firstly, the present invention utilizes a through groove, an upper groove, a lower groove and a filling technique to form a metal lead frame, and therefore cannot be distinguished by a process point formed by a through groove, an upper concave 1 Ca, and a lower groove. The invention is limited. In the following, the flow path of the present invention will be described by taking the example of forming the through groove and the lower groove first. First, referring to the first (a) diagram, a patterned resist layer 12 and a patterned resist layer 14 are formed on the upper surface and the lower surface of a metal plate 10, and the patterned resist layer 12 is patterned. Please refer to the third figure for the pattern, and the pattern of the patterned resist layer 14 is shown in the fourth figure. At the same time, the patterned resist layer 12 and the patterned resist layer 14 are used as masks, and the metal plate 10 is etched to form the through grooves 16 and the lower grooves as shown in the first (b). 18. The etching method can be wet etching, mainly because the halogen is a wet etching solvent, and after forming the penetration of the metal carrier 10, it is easy to form a straight sidewall, which helps to form a finer line. Partially, and the exact position is obtained, and then the patterned resist layers 1 2, 14 are removed. The formation of the trough or the lower groove can also be made in a manner of deep control forming or casting. 'Continuously, the filling process is performed, and the support or the filler 20 is filled in the above-mentioned through groove 16 and the lower groove 18, and the filling 20 is flattened through a grinding step so that the filling 20 does not Covering the metal plate 10 will make the line or

Page 8 1262587 V. Description of the Invention (5) The portion covering the conductive layer, thus forming the line portion of the fine line portion and the lower surface, as shown in the first (c). Among them, the material of the filler 20 is a material such as resin, silver glue, copper glue, carbon ink or the like which is blocked or changed in electrical properties. Then, referring to the first (d), a patterned resist layer 2 2 and a patterned resist layer 24 are formed on the upper and lower surfaces of the metal plate 10, and then patterned to resist the residual layers 22 and 2. 4 is a mask to the metal plate 10 for 14 times to form a plurality of upper grooves 2 6 on the metal plate 10, and then remove the patterned resist 2 2, 4, forming a first (e) figure As shown, the pattern can be made by selective etching or deep-controlled molding. Then, in the above plurality of upper grooves 26, whether to select the packing support or the filling material 2, and after the filling of the support or the filling material 28, a polishing step is performed to planarize the filling to form the upper surface. The circuit, as shown in the first (Π) or first (f 2) diagram. Subsequently, a patterned anti-plating layer 3_0, 32 or a solder resist layer is formed on the upper and lower surfaces of the metal plate 10, as shown in the first (gl) diagram or the first (g2). The patterned resist layer 30, 3 2 or solder resist layer defines the location of a plurality of outer conductive layers. The patterned anti-plating layer 3 0, 3 2 or the solder resist layer is used as a mask, and a plurality of external P-electrode layers 34 for increasing the conductivity of the conductive region are formed on the upper and lower surfaces of the metal 110, and then the patterned anti-resistance is removed. The plating layer 30, 3 2, or the solder resist layer is not removed, and forms a structure as shown in the first (hi) diagram or the (h2) diagram. The conductive layer is selected from various metal surface treatments such as electroless tin plating, electroplating tin, electroless silver plating, electroplating silver, electroplated nickel gold, electroless nickel-plated palladium gold, and electroless nickel immersion gold.

Page 9 1262587 V. Description of the Invention (6) After the fabrication of the lead frame is completed, the step of mounting the wafer 48 can be performed. In the present embodiment, the center of the metal plate 10 is used as the mounting wafer predetermined area 5 and by The wire 50 connects the wafer 48 to the outer conductive layer 34 as an outer conductive contact, and finally covers the upper surface of the metal plate 10 with an encapsulant 52 to cover the wafer 48 and the wire 5. 0, the encapsulant 52 is usually an epoxy resin (e ρ ο X yresi η), thereby providing a mechanical protection against external forces, forming a first (1 1) diagram and a first (1 2) • The structure shown in the figure. Moreover, a receiving groove 5 4 may be formed in the center of the metal plate 10 to lower the overall package height, and then the step of mounting the wafer 48 is performed, and φ is formed as the first (j 1) image and the first (j 2 ). The structure shown in the figure. In the foregoing steps of filling the support 16 or the filler 20 in the through groove 16 and the lower groove 18 of the metal plate 1 , the filling process may be selected according to the electrical requirements of each area on the metal plate or Without inserting the support or filler 20, please refer to the second (a) diagram which is a schematic diagram of an embodiment in which a through groove 16 and a portion of the lower groove 18 are not filled with a support or a filler 20. Then, by using the same steps as described above, a plurality of upper grooves 26 are formed on the metal plate 10, and it is selected to be filled with the packing support or the groove 26 of the filling 28 to fill the support or the filling 2 8. The filler is planarized to form an upper surface circuit as shown in the second (b). Subsequently, a plurality of external electrical layers 34 are formed on the upper and lower surfaces of the metal plate 10, and the steps of mounting and encapsulating the liquid crystals 5 2 are performed, as shown in the second (cl) or the second (c2). The structure. - In addition to the above-described implementations, the present invention also exemplifies another embodiment in which the first or the upper groove or the groove is formed, and the filler is filled in the groove or the groove and planarized, and then On the metal plate, the lower surface

Page 10 1262587 V. INSTRUCTIONS (7) A plurality of conductive layers are formed in a predetermined area, and then upper/lower grooves and lines are formed. Here, the description will be made by first forming a lower groove or a through groove, and then sequentially filling the filler, forming a conductive layer, and forming an upper groove. First, please refer to the steps shown in the first (a) to the first (c) above to form the lower groove 18 and the through groove 16 which have been filled with the filler, as shown in the fifth (a) diagram. . , Continuation, please refer to the fifth (b) figure, forming a patterned anti-plating layer 3 6 , 3 8 on the upper and lower surfaces of the metal plate 10 , and the patterned anti-plating layer 3 6 , 3 8 is a plurality of The location of the outer conductive layer. In the splicing, the patterned anti-plating layer 3 6 , 38 is used as a mask to form a plurality of outer conductive layers 34 for increasing the conductivity of the conductive region on the upper and lower surfaces of the metal plate 10 , wherein the conductive layer 34 It is selected from various metal surface treatments such as electroless tin plating, electroplating tin, electroless silver plating, electroplating silver, electroplated nickel gold, electroless nickel-plated palladium gold, and electroless nickel immersion gold, and then removing the patterned resist layer 3 6 , 3 8, as shown in the fifth (c). A patterned resist layer 4 2, 4 4 is formed on the upper and lower sides of the metal plate 10 to define a position of the upper groove to pattern the resist layer 4 2, 4 4 and the outer conductive layer 34 as a cover. Curtain, the metal plate 10 is etched to form a groove as shown in the fifth (d), and then the patterned resist layer 4 2, 4 4 is moved, successively, and selectively filled, The upper groove 26 is filled with the support or the filler 2 8 to obtain a lead frame combining the techniques and advantages of the conventional lead frame and the printed circuit board, such as the fifth (e 1) diagram or the fifth e2). The figure shows. Subsequently, the wafer 48, the wire 5 2 is mounted and the encapsulant 5 2 is formed to form

Page 11 1262587 V. Description of the invention (8) If the fifth (f 1) diagram, the fifth (f 2 ) diagram, or the accommodating slot is first etched, the wafer 4 8 and the conductor 5 2 are mounted. The package colloid 52 is formed to form a structure having a fifth (f3) diagram and a fifth (f 4) diagram having the wafer 48 accommodating groove 54. Furthermore, the forming step of the accommodating groove 504 can also be incorporated in the forming step of the upper groove 26, and the process step will be changed to form a patterned anti-layer 4 on the upper and lower sides of the metal plate 10, respectively. 4 4, in order to define the position of the upper groove 26 and the receiving groove 52, and then to pattern the resist layer 4 2, 4 4 and the outer conductive layer 34 as a mask, the metal plate 10 is surnamed To form the groove_ and the receiving groove 5 4 as shown in the sixth figure, and then remove the patterned resist layer 4 2, 4 4, followed by selective filling process and wafer mounting, etc. The subsequent process steps are the same as previously described, and will not be described again here. Please refer to the seventh (a) and seventh (b) drawings, which are still another embodiment of the present invention. The embodiments are such that a plurality of lower grooves are not filled during the manufacturing process of the lead frame. When filling, a plurality of metal balls 5 6 are formed to replace the traditional solder ball as an interface for external connection, which reduces the reliability problem caused by bonding different metal interfaces, and can increase the overall The reliability of the components, and the reduction of the process of scraping the ball, can reduce the overall packaging process scrap rate and cost. In summary, the present invention is a lead frame and a method of manufacturing the same, which utilizes a double-sided etching technique to form a denser portion of a wire on a metal plate, and is combined with multiple etching, deep control molding, and filling. The plugging technology effectively solves the problem of conventional lead frame fabrication and packaging. The present invention can be summarized as follows:

Page 12 1262587 V. INSTRUCTIONS (9) I. The fabrication of filler materials and support structures makes the circuit diversified and can be widely applied to various semiconductor packaging needs. Second, a plurality of metal balls can be formed in advance to reduce the scrap rate and cost of the package, and improve the reliability of the package components. 3. Since the pins are filled with fillers, the problem of using the traditional lead frame to cover the glue to the upper surface (S Μ T Pad) during the filling can be completely avoided, and the package can be reduced. Process, increase yield and reduce costs. - Fourth, a lead frame can be formed with a receiving groove to reduce the overall package height. However, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the practice of the present invention. Equivalent changes and modifications of the process methods, features and spirits described in the claims are intended to be included within the scope of the invention.

Page 13 1262587 Brief Description of the Drawings [Simple Description of the Drawings] The first (a) to the first (j 2) drawings are cross-sectional views showing the construction steps of one embodiment of the present invention. The second (a) through second (c 2) drawings are cross-sectional views showing the construction steps of another embodiment of the present invention. The third figure is a schematic diagram of a patterned resist pattern on the surface of the metal plate of the first (b) figure. 'The fourth figure is a schematic diagram of the patterned anti-layer layer of the lower surface of the metal plate of the first (b) figure. The five (a) to fifth (f 4) drawings are another embodiment of the present invention. A cross-sectional view of each step is constructed. The sixth figure is a schematic diagram of the step of forming the accommodating groove in the upper groove etching step of the present invention. The seventh (a) and seventh (b) drawings form a plurality of metal balls, Schematic diagram of an embodiment of an interface for external connection. [Description of main component symbols] 10 0 metal plate 1 2 patterned resist layer ft patterned resist layer 1 6 through groove 1 8 lower groove 2 0 filler 2 2 patterning Resist layer

Page 14 1262587 Schematic description 2 4 patterned resist layer 6 upper groove 2 8 filler 3 0 patterned resist layer 3 2 patterned resist layer 34 conductive layer 3 6 patterned anti-plating layer - 3 8 Patterned plating layer _ 4 2 patterned resist layer φ ΐ patterned resist layer 4 8 wafer 5 0 wire 5 2 package colloid 5 4 accommodating groove 5 6 metal ball

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Claims (1)

1262587 VI. Patent Application No. 1 · A lead frame comprising: a metal plate having a patterned through groove and a non-perforated groove formed therein: and a filling material filled in the metal plate The patterned through groove or the groove is used for connecting and supporting the metal plate to be insulated into a plurality of conductive regions. 2. The lead frame of claim 1, wherein the filling material is an insulating material that is insulated from the metal plate into a plurality of electrically conductive regions. The lead frame of claim 1, wherein the filling material is a conductive material filled in a specific patterning groove and a groove of the metal plate to form a special region Electrical area. 4. The lead frame of claim 2, wherein the surface of the plurality of conductive regions of the metal plate is further subjected to a surface treatment to form a conductive layer. 5. The lead frame of claim 4, wherein the conductive layer is selected from the group consisting of electroless tin plating, electroplating tin, electric tin ore, tin-spraying, electroless silver plating, electroplating silver, electroplating nickel gold, and no electricity. Metal surface treatment of nickel-plated palladium and electroless nickel immersion gold. 6. The lead frame of claim 1, wherein the groove or the groove is formed by a plurality of wet etching, dry etching, casting or over-depth forming methods. 7. The lead frame of claim 1, wherein the groove or the groove is formed by selective etching. $. The lead frame of claim 1, wherein the groove or the groove is formed by several times of deep control molding. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The lead frame of claim 1, wherein one or more of the accommodating grooves are provided at a predetermined position on the metal plate for mounting one or more of the wafers. The lead frame of claim 1, wherein a surface of the metal plate or above the filling material may or may not be formed with a protective or solder mask layer. 1 . The lead frame according to claim 1 , wherein the filler material φ is a resin, a silver glue, an aluminum glue, a ceramic material, a copper glue, a carbon ink, or the like, which is a material that blocks or changes electrical properties. The lead frame of claim 1, wherein a plurality of metal balls (m e t a 1 b u m p ) are formed on the lower surface of the metal plate for external connection of the semiconductor elements. 1 4 · A method of manufacturing a lead frame, comprising the steps of: providing a metal plate; processing the metal plate to form a plurality of through grooves and lower/upper grooves; - selectively selecting the through grooves Filling a filler in the lower/upper groove; forming a plurality of conductive layers on the metal plate and the lower surface; and processing the metal plate to form a plurality of upper/lower grooves on the upper surface of the metal, and Optionally, the filler is filled in the upper/lower grooves. The method of manufacturing a lead frame according to the invention of claim 4, wherein the processing method is selected from the group consisting of several wet etching, dry etching, casting or deep-controlled molding. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; By. The method of manufacturing a lead frame according to claim 14, wherein the lower/upper groove or the through groove is finished by a plurality of deep-controlled forming methods. The method of manufacturing a lead frame according to claim 14, wherein the lower/upper groove or the through groove is formed by casting. The manufacturing method of the lead frame according to claim 14, wherein the 10 conductive layers are selected from the group consisting of electroless tin plating, electroplating tin, electroplating tin-lead, tin-lead lead, electroless silver plating, electroplating silver, electroplating nickel Various metal surfaces for electrical connection between semiconductor and lead frame, such as gold, electroless nickel-plated palladium and electroless nickel immersion gold. The manufacturing method of the lead frame according to claim 14, wherein the filling material is a resin, a silver glue, an aluminum glue, a ceramic material, a copper glue, a carbon ink, or the like, which is a material for blocking or changing electrical properties. . 2 1 · A method for manufacturing a lead frame, comprising the following steps: ~ providing a metal plate to process the metal plate to form a plurality of through grooves and lower/upper grooves; _ in the through grooves and under/ Selectively filling the filler in the upper groove; processing the metal plate to form a plurality of upper/lower grooves on the upper surface of the metal, and selectively filling the filler in the upper/lower grooves; And forming a plurality of conductive layers on the metal plate/lower surface. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The lead frame manufacturing method according to claim 2, wherein the lower/upper groove or the through groove is formed by a plurality of selective etching methods. The method of manufacturing a lead frame according to claim 2, wherein the lower/upper groove or the through groove is formed by several deep-depth forming methods. The manufacturing method of the lead frame according to Item 2, wherein the φ lower/upper groove or the through groove is formed by casting. The lead frame manufacturing method according to claim 2, wherein the conductive layer is selected from the group consisting of electroless tin plating, electroplating tin, electroplating tin-lead, tin-lead lead, electroless silver plating, electroplating silver, electroplating nickel Various metal surfaces for electrical connection between semiconductor and lead frame, such as gold, electroless nickel-plated palladium and electroless nickel immersion gold. The manufacturing method of the lead frame according to the above-mentioned patent application, wherein the filling material is a resin, a silver glue, an aluminum glue, a ceramic material, a copper glue, a carbon ink, or the like, which is a material for blocking or changing electrical properties. . The invention relates to a semiconductor package component, comprising: a metal plate having a patterned through groove and upper and lower groove designs formed thereon; a filler filled with the pattern of the metal plate The through slot or the upper and lower four slots are used to isolate the metal plate into one or a plurality of predetermined areas of the wafer and the plurality of conductive areas; Page 19 1262587 VI. Patent Application Scope One or a plurality of wafers are mounted on a predetermined area of the wafer on the metal plate and electrically connected to the conductive regions. The semiconductor package component of claim 28, wherein the surface of the plurality of conductive regions of the metal plate is further subjected to a surface treatment to form a conductive layer. The semiconductor package component of claim 28, wherein the conductive layer is selected from the group consisting of electroless tin plating, tin plating, tin-lead plating, tin-lead lead, electroless silver plating, electroplating silver, and electroplated nickel gold. Various electroless nickel/palladium gold and electroless nickel-plating gold, etc., are used for electrical connection between semiconductor and semiconductor package components. The semiconductor package component of claim 28, further comprising an encapsulant covering the wafer. The semiconductor package component of claim 28, wherein the recess or the via is formed by selective etching. The semiconductor package component of claim 28, wherein the groove or the through groove is formed by several times of deep control molding. The semiconductor package component of claim 28, wherein the groove or the through groove is formed by casting. The semiconductor package component of claim 28, wherein the conductive layer is selected from the group consisting of electroless tin plating, tin plating, tin-lead plating, tin-lead lead, electroless silver plating, electroplating silver, electroplated nickel gold, Various metal surface treatments for electrically connecting semiconductors and lead frames, such as electroless nickel-palladium gold and electroless nickel immersion gold. Page 20 1262587 VIII. Patent Application No. 3 6. The semiconductor package component of claim 28, wherein the filler material is resin, silver glue, aluminum glue, ceramic material, copper glue, carbon ink, etc. A variety of materials that block or change electrical properties. The semiconductor package component of claim 28, wherein the predetermined area of the wafer on the metal plate is further provided with one or more accommodating grooves for accommodating one or more wafers. The semiconductor package component of claim 28, wherein - one or more metal balls are formed on the lower surface of the metal plate for semi-conducting, and the components are externally connected. Page 21