CN106611747A - A die seal interconnection substrate and a manufacturing method thereof - Google Patents
A die seal interconnection substrate and a manufacturing method thereof Download PDFInfo
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- CN106611747A CN106611747A CN201510682387.8A CN201510682387A CN106611747A CN 106611747 A CN106611747 A CN 106611747A CN 201510682387 A CN201510682387 A CN 201510682387A CN 106611747 A CN106611747 A CN 106611747A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Abstract
The present invention discloses a die seal interconnection substrate and a manufacturing method thereof. The die seal interconnection substrate comprises an embedded reconfiguration circuit layer, an embossing reconfigurable circuit layer and a plurality of conductor posts and a chip which are sealed in a die seal core layer. The conductor posts are arranged on an external pad of the embedded reconfiguration circuit layer. The chip is in joint withthe embedded reconfiguration circuit layer. The die-seal core layer has an outer mating surface and an opposite component mounting surface, and the embedded reconfiguration circuit layer is embedded in the die sealing core layer by the mating surface. The lower surface of the embedded reconfiguration circuit layer is coplanar to the outer mating surface. The column top end surfaces of the conductor columns are coplanar to the component mounting surface. The embossing reconfiguration circuit layer is formed on the component mounting surface in an embossing mode and includes column top pads that are in joint with the column top end surfaces in an aligned mode. Thus the thickness of one flip chip die seal can be omitted; manufacturing of substrate plating lines is not needed; and an effect of substrate line micro-spacing and omitting of a substrate boring process can be reached.
Description
Technical field
The present invention is related to carry the wiring board of electronic building brick, particularly with regard to a kind of molding interconnection substrates and its manufacture method.
Background technology
In existing composite packing structure, chip is that chip bonding mode is engaged in a substrate, and chip is first placed on substrate and makees to be connected by projection and substrate, but this structure cannot effectively reduce the total height of chip-packaging structure.
Printed substrate (Printed Circuit Board;PCB) it is key part and component in every electronic product, a wherein purposes is, as the medium for carrying each micromodules such as chip and the transmission of inter-module message, to generally can be divided into multilayer circuit board, high density circuit board (HDI), high-level plate (HLC), soft board (FPC) and rigid-flex (Rigid-Flex PCB) etc..Generally the core layer material of the printed substrate is BT resins.
Fig. 1 is referred to, a kind of existing crystal-coated package structure 300 mainly seals the molding compound 340 of the chip 320 comprising a circuit base plate 310, a chip bonding in the chip 320 and of the circuit base plate 310.The circuit base plate 310 has a core 311, and the lower upper surface of the core 311 is respectively formed with a first line layer 312 and one second line layer 313, and is electrically conducted two line layer 312 and 313 with multiple plated-through-holes 314.Multiple projections 321 of the chip 320 are bonded to second line layer 313, and seal those projections 321 with a underfill 330.The molding compound 340 is formed on the circuit base plate 310 in molding mode, and thickness of the molding compound 340 on the circuit base plate 310 is provided as a flip molding thickness H0.And multiple external terminals 350 are located at the bottom surface of the circuit base plate 310 and are bonded to the first line layer 312.The making of those plated-through-holes 314 needs first to drill through the core 311 but not through the first line layer 312 or second line layer 313, the hole wall metal level in plating in through hole, fills up dielectric material or conductive materials in hole again.
The content of the invention
It is above-mentioned in order to solve the problems, such as, present invention is primarily targeted at providing a kind of molding interconnection substrates and its manufacture method, can with pre-plugged chip in substrate omitting a flip molding thickness, and the making of electroplating substrate line is not needed, and is reached the micro- spacing of base plate line and is omitted effect of substrate drilling processing procedure.
A time purpose of the invention is to provide a kind of molding interconnection substrates and its manufacture method, the existing substrate plated-through-hole of conductor pin replacement for arranging on connection pad in addition, is discontented with hole plating through line layer by solving the problems, such as to drill in root.
The object of the invention to solve the technical problems employs the following technical solutions to realize.The present invention discloses a kind of molding interconnection substrates, and comprising one formula reconfiguration line layer, multiple first conductor pins, one first chip, one first molding core layer and one first relief formula reconfiguration line layer are embedded into.This is embedded into formula reconfiguration line layer and is formed in a molding plane, and this is embedded into formula reconfiguration line layer and is embedded into connection pad in circuit, multiple outer connection pads and multiple first comprising multiple, and those are embedded into corresponding those the outer connection pads of connection with those connection pads in first.Those first conductor pins are arranged on those outer connection pads.First chip is engaged in this and is embedded in formula reconfiguration line layer and is electrically connected to those connection pads in first.The first molding core layer is formed in the molding plane, to seal first chip and those first conductor pins, the first molding core layer has an outer engagement face, this is embedded into formula reconfiguration line layer and is embedded into into the first molding core layer by the outer engagement face, those are embedded into circuit, multiple lower surface coplines of those outer connection pads and those connection pads in first are in the outer engagement face, wherein the first molding core layer separately have one relative to the outer engagement face first assembly mounting surface, those first conductor pins have multiple first capital end faces, copline is in the first assembly mounting surface.The first relief formula reconfiguration line layer is formed on the first assembly mounting surface, the first relief formula reconfiguration line layer includes connection pad in multiple first relief circuits, multiple first capital pads and multiple second, corresponding those the first capital pads of those the first relief connections and those connection pads in second, those the first capital pads are alignedly engaged in those the first capital end faces, and the first relief formula reconfiguration line layer is by the first assembly mounting surface relief outside the first molding core layer.The present invention separately discloses the manufacture method of above-mentioned molding interconnection substrates.
The object of the invention to solve the technical problems can also be applied to the following technical measures to achieve further.
In aforementioned molding interconnection substrates, the single layer structure that the first molding core layer can solidify to form for molding, to simplify the structure of substrate core.
In aforementioned molding interconnection substrates, first chip can have multiple projections, and those connection pads in first for being embedded into formula reconfiguration line layer are connected in chip bonding mode, therefore when the first molding core layer is formed, the position of those connection pads in first is fixed in advance gain effect, will not be affected by mould stream.
In aforementioned molding interconnection substrates, the height of those the first capital end faces to those outer connection pads of those the first conductor pins can be more than the chip rational height of first chip, so that first chip is entirely sealed in the first molding core layer.
In aforementioned molding interconnection substrates, a plating seed layer can be formed between those first conductor pins and those outer connection pads, be formed with the plating of sharp those the first conductor pins.
In aforementioned molding interconnection substrates, the plating seed layer can have more multiple seeds around those outer connection pad peripheries and remain ring, therefore when the first molding core layer is formed, the position of those outer connection pads is fixed in advance gain effect, will not be affected by mould stream.
In aforementioned molding interconnection substrates, this is embedded into the multiple superposed metal level that formula reconfiguration line layer can be reverse configuration, therefore this is embedded into formula reconfiguration line layer and its those outer connection pads for including and itself has barrier, splicing results when formation, it is not necessary to which the plating on surface that appears with extra electroplating process in those outer connection pads after substrate forming forms ni/au layers.
In aforementioned molding interconnection substrates, one second chip can have been additionally comprised, it is engageable in the first relief formula reconfiguration line layer and to be electrically connected to those connection pads in second.
In aforementioned molding interconnection substrates, multiple second conductor pins, one second molding core layer and one second relief formula reconfiguration line layer can be additionally comprised.Those second conductor pins are arranged on those the first capital pads.The second molding core layer is formed on the first assembly mounting surface, to seal second chip and those second conductor pins, the first relief formula reconfiguration line layer is embedded into into the second molding core layer, wherein the second molding core layer have one relative to the first assembly mounting surface the second component mounting surface, those second conductor pins have multiple second capital end faces, and copline is in the second component mounting surface.The second relief formula reconfiguration line layer is formed on the second component mounting surface, the second relief formula reconfiguration line layer includes connection pad in multiple second relief circuits, multiple second capital pads, multiple three, corresponding those the second capital pads of those the second relief connections and those connection pads in the 3rd, those the second capital pads are alignedly engaged in those the second capital end faces, and the second relief formula reconfiguration line layer is by the second component mounting surface relief outside the second molding core layer.Therefore, the molding interconnection substrates can be multilamellar core texture.
In aforesaid molding interconnection substrates, multiple external terminals can be additionally comprised, be arranged at those lower surfaces of those outer connection pads.
In aforesaid molding interconnection substrates, an electronic installation can be additionally comprised, it is engaged in the second relief formula reconfiguration line layer, the electronic installation has multiple first electrodes with multiple second electrodes, those first electrodes are engaged in those connection pads in the 3rd, and those second electrodes are engaged in those the second capital pads.
The manufacture method of the molding interconnection substrates that the present invention is provided, comprising：
Formation one is embedded into formula reconfiguration line layer in a molding plane, this is embedded into formula reconfiguration line layer and is embedded into connection pad in circuit, multiple outer connection pads and multiple first comprising multiple, those are embedded into corresponding those the outer connection pads of connection with those connection pads in first, and the molding plane is provided by a temporary transient support plate；
Multiple first conductor pins are set on those outer connection pads；
Engage one first chip and be embedded in formula reconfiguration line layer and be electrically connected to those connection pads in first in this；
One first molding core layer is formed in the molding plane, to seal first chip and those first conductor pins, the first molding core layer has an outer engagement face, this is embedded into formula reconfiguration line layer and is embedded into into the first molding core layer by the outer engagement face, and those are embedded into multiple lower surface coplines of circuit, those outer connection pads and those connection pads in first in the outer engagement face；
With the first planarization lapping mode make the first molding core layer separately have one relative to the outer engagement face first assembly mounting surface, those first conductor pins have multiple first capital end faces, and copline is in the first assembly mounting surface；And
One first relief formula reconfiguration line layer is formed on the first assembly mounting surface, the first relief formula reconfiguration line layer includes connection pad in multiple first relief circuits, multiple first capital pads and multiple second, corresponding those the first capital pads of those the first relief connections and those connection pads in second, those the first capital pads are alignedly engaged in those the first capital end faces, and the first relief formula reconfiguration line layer is by the first assembly mounting surface relief outside the first molding core layer.
In the manufacture method of aforesaid molding interconnection substrates, additionally comprise：
Multiple second conductor pins are set on those the first capital pads；
One second chip is engaged in the first relief formula reconfiguration line layer and those connection pads in second are electrically connected to；
One second molding core layer is formed on the first assembly mounting surface, to seal second chip and those second conductor pins, the first relief formula reconfiguration line layer is embedded into into the second molding core layer；
With the second planarization lapping mode make the second molding core layer have one relative to the first assembly mounting surface the second component mounting surface, those second conductor pins have multiple second capital end faces, and copline is in the second component mounting surface；And
One second relief formula reconfiguration line layer is formed on the second component mounting surface, the second relief formula reconfiguration line layer includes connection pad in multiple second relief circuits, multiple second capital pads, multiple three, corresponding those the second capital pads of those the second relief connections and those connection pads in the 3rd, those the second capital pads are alignedly engaged in those the second capital end faces, and the second relief formula reconfiguration line layer is by the second component mounting surface relief outside the second molding core layer.
By above-mentioned correspondence effect technological means partially or in whole, the present invention can be reached by the use of epoxy glue material as molding core layer, replace the core of the BT materials of original circuit base plate.Preferably, after being embedded into formula reconfiguration line layer and being formed, chip is connected by flip mode with formula reconfiguration line layer is embedded into, molding core layer is recycled by chip and is embedded into formula reconfiguration line layer and is buried in it, may achieve encapsulating structure thin type by this mode, and the purpose of encapsulating structure storehouse can be reached by the interior connection pad of the relief connection for extending.
Description of the drawings
Fig. 1：A kind of schematic cross-section of existing crystal-coated package structure.
Fig. 2：According to first specific embodiment of the present invention, the schematic cross-section and partial enlarged drawing of a kind of molding interconnection substrates.
Fig. 3 A to 3G：According to first specific embodiment of the present invention, the component diagram of each step in the processing procedure of the molding interconnection substrates is shown in.
Fig. 4：According to second specific embodiment of the present invention, the schematic cross-section of another kind of molding interconnection substrates.
Fig. 5 A to 5E：According to second specific embodiment of the present invention, the component diagram of each step in the back-end process of the molding interconnection substrates is shown in.
Fig. 6：According to second specific embodiment of the present invention, using the molding interconnection substrates schematic cross-section of a stacking-type microelectronic device is combined into.
Reference:
H0 flip molding thickness；The height of the conductor pins of H1 first；The chip rational height of the chips of H2 first；10 temporary transient support plates；20 external terminals；30 electronic installations；31 first electrodes；32 second electrodes；40 photoresistance patterns；51 times moulds；52 molds；60 grinding heads；100 molding interconnection substrates；101 molding planes；110 are embedded into formula reconfiguration line layer；110A bonding layers；110B barrier layers；110C agent structure layers；111 are embedded into circuit；112 outer connection pads；Connection pad in 113 first；120 first conductor pins；121 first capital end faces；122 plating seed layers；123 seeds remain ring；130 first chips；131 projections；132 solders；140 first molding core layers；141 outer engagement faces；142 first assembly mounting surfaces；150 first relief formula reconfiguration line layers；151 first relief circuits；152 first capital pads；Connection pad in 153 second；200 molding interconnection substrates；260 second conductor pins；261 second capital end faces；270 second chips；271 projections；280 second molding core layers；281 second component mounting surfaces；290 second relief formula reconfiguration line layers；291 second relief circuits；292 second capital pads；Connection pad in 293 the 3rd；300 crystal-coated package structures；310 circuit base plates；311 cores；312 first line layers；313 second line layers；314 plated-through-holes；320 chips；321 projections；330 underfills；340 molding compounds；350 external terminals.
Specific embodiment
Embodiments of the invention are described in detail below in conjunction with appended diagram, so it should be noted that, those diagrams are simplified schematic diagram, the basic framework or implementation of the present invention are only illustrated with illustrative method, therefore only show the component relevant with this case and syntagmatic, shown component is not done equal proportion and is drawn with the actual number implemented, shape, size in figure, some dimension scales and other relative dimensions ratios or has been exaggerated or has been simplified and process, to provide clearer description.The actual number implemented, shape and dimension scale are a kind of design of putting property of choosing, and detailed assembly layout is likely more complexity.
According to first specific embodiment of the present invention, a kind of molding interconnection substrates 100 are illustrated in the schematic cross-section and partial enlarged drawing of Fig. 2.A kind of molding interconnection substrates 100 are embedded into formula reconfiguration line layer 110, multiple first conductor pins 120, one first chip 130, one first molding core layer 140 and one first relief formula reconfiguration line layer 150 comprising one.
As shown in Figure 2, this is embedded into formula reconfiguration line layer 110 and is formed in a molding plane 101, the molding plane 101 can be provided (as shown in Figure 3A) by a temporary transient support plate 10, the body of the temporary transient support plate 10 is glass or silicon, shape can form photosensitive mucigel for panel or wafer, body surfaces.This is embedded into formula reconfiguration line layer 110 and is embedded into connection pad 113 in circuit 111, multiple outer connection pads 112 and multiple first comprising multiple, and those are embedded into circuit 111 and connect corresponding those outer connection pads 112 with those connection pads 113 in first.The spacing of those outer connection pads 112 should be greater than the spacing of those connection pads 113 in first and be that periphery is fanned out to kenel.Optionally, the lower surface of those outer connection pads 112 is available for engaging multiple external terminals 20, such as soldered ball.Alleged " reconfiguration line layer " is, using the vapour deposition of semiconductor crystal wafer or panel, plating and the line layer that formed of etch processes equipment, line structure need not to be electroplated in substrate circuit layer.But non-exclusively, this is embedded into formula reconfiguration line layer 110 and is also formed using the processing procedure that lifts off for making semiconductor subassembly." formation " alleged by here refers to that the solid-state opportunity of completing for being intended to formation is i.e. formation of the liquid vapor state thing in another solids or its definition surface on formed carrier or in defined plane.
Those first conductor pins 120 are arranged on those outer connection pads 112." setting " alleged by here refers to that " carrier is set " makes and is configured to object, and " arranging thing " is fixed on " carrier is set ", and the making opportunity of " arranging thing " is in the setting up procedure after " carrier is set " shaping；Or " arranging thing " is formed in before setting steps for indivedual making, i.e. formation of the liquid vapor state thing in solids, or connection of the solids in solids.Those first conductor pins 120 have a height H1, equivalent to the residual value that the thickness of the first molding core layer 140 deducts the thickness for being embedded into formula reconfiguration line layer 110.Those first conductor pins 120 are embedded into formula reconfiguration line layer 110 not through this.The material of those the first conductor pins 120 can be copper, and its shape can be cylinder, four sides cylinder, six or the multi-faceted column such as eight, wherein be preferable with cylinder, to reduce the unfavorable blocking effect that mould stream is filled.It is preferred that a plating seed layer 122 can be formed between those first conductor pins 120 and those outer connection pads 112, formed with the plating of sharp those the first conductor pins 120.It is particularly preferred that the plating seed layer 122 can have more multiple seeds around those peripheries of outer connection pad 112 remains ring 123, therefore when the first molding core layer 140 is formed, the position of those outer connection pads 112 is fixed in advance gain effect, will not be affected by mould stream.
As shown in Fig. 2 first chip 130 is engaged in this is embedded in formula reconfiguration line layer 110 and is electrically connected to those connection pads 113 in first." engagement " alleged by here refers to that " jointer " all first indivedual making is configured to object with " engaged thing ", then jointer is fixed on engaged thing, i.e. connection of the solids to solids.First chip 130 has a chip rational height H2.In a concrete structure, first chip 130 can have multiple projections 131, and those connection pads 113 in first for being embedded into formula reconfiguration line layer 110 are connected in chip bonding mode, using solder 132 those projections 131 are engaged with corresponding those connection pads 113 in first.Therefore when the first molding core layer 140 is formed, the position of those connection pads 113 in first is fixed in advance gain effect, will not be affected by mould stream.First chip 130 is specially semiconductor integrated circuit package.
It is as shown in Figure 2 again, the first molding core layer 140 is formed in the molding plane 101, to seal first chip 130 and those first conductor pins 120, the first molding core layer 140 has an outer engagement face 141, this is embedded into formula reconfiguration line layer 110 and is embedded into into the first molding core layer 140 by the outer engagement face 141, those are embedded into circuit 111, multiple lower surface coplines of those outer connection pads 112 and those connection pads 113 in first are in the outer engagement face 141, wherein the first molding core layer 140 separately have one relative to the outer engagement face 141 first assembly mounting surface 142, those first conductor pins 120 have multiple first capital end faces 121, copline is in the first assembly mounting surface 142.In the present embodiment, the single layer structure that the first molding core layer 140 can solidify to form for molding, to simplify the structure of substrate core.The first molding core layer 140 is formed using compression molding or transfer molding mode.The main material of the first molding core layer 140 can be thermoset epoxy glue material.
As shown in Figure 2, the first relief formula reconfiguration line layer 150 is formed on the first assembly mounting surface 142, the first relief formula reconfiguration line layer 150 includes connection pad 153 in multiple first relief circuits 151, multiple first capital pads 152 and multiple second, those the first relief circuits 151 connect corresponding those the first capital pads 152 with those connection pads 153 in second, those the first capital pads 152 are alignedly engaged in those the first capital end faces 121, and the first relief formula reconfiguration line layer 150 is by the relief of first assembly mounting surface 142 outside the first molding core layer 140.When need to install one on the first assembly mounting surface 142 be same as the chip of first chip 130 when, those in second connection pad 153 can be longitudinally aligned with those connection pads 113 in first.More specifically, the height H1 of those the first capital end faces 121 to those outer connection pads 112 of those the first conductor pins 120 can be more than the chip rational height H2 of first chip 130, so that first chip 130 is entirely sealed in the first molding core layer 140.Additionally, under the glue of those the first capital pads 152 and covering and the first molding core layer up and down of those outer connection pads 112 covers, those first conductor pins 120 are also without the surface exposed.
Therefore, a kind of molding interconnection substrates 100 that the present invention is provided can with pre-plugged first chip 130 in board structure omitting a flip molding thickness, and the making of electroplating substrate line is not needed, and is reached the micro- spacing of base plate line and is omitted effect of substrate drilling processing procedure.Additionally, with the existing substrate plated-through-hole of the replacement of the first conductor pin 120 arranged on those outer connection pads 112, electroplate discontented through line layer and hole by solving the problems, such as to drill in root.
It is as shown in Figure 2 again, this is embedded into the multiple superposed metal level that formula reconfiguration line layer 110 can be reverse configuration, it is according to metal level formation order, this is embedded into formula reconfiguration line layer 110 comprising bonding layer 110A, the barrier layer 110B just like nickel (Ni) and the agent structure layer 110C just like copper (Cu) just like golden (Au), the forming method for being embedded into formula reconfiguration line layer of the present invention is reverse configuration, is sequentially gold deposition, nickel deposition, patterned copper plating and dry-etching.Existing substrate circuit layer is copper wire layer, the electronickelling gold only on outer connection pad, and the forming method of existing substrate circuit layer is positive configuration, is sequentially patterned copper etching, the circuit, electronickelling and the plating gold that cover outside outer connection pad with welding resisting layer.Therefore, this be embedded into formula reconfiguration line layer 110 and its those outer connection pads 113 for including formed when itself there are barrier, splicing results, it is not necessary to the plating on surface that appears with extra electroplating process in those outer connection pads after substrate forming forms ni/au layers.
After with regard to the manufacture method explanation such as of above-mentioned molding interconnection substrates 100, Fig. 3 A to 3G are shown in the component diagram of each step in the processing procedure of the molding interconnection substrates.
First, as shown in Figure 3A, using deposition/patterning plating/dry-etching mode or lift off mode and form one and be embedded into formula reconfiguration line layer 110 in a molding plane 101, this is embedded into formula reconfiguration line layer 110 and is embedded into connection pad 113 in circuit 111, multiple outer connection pads 112 and multiple first comprising multiple, those are embedded into circuit 111 and connect corresponding those outer connection pads 112 with those connection pads 113 in first, and the molding plane 101 is provided by a temporary transient support plate 10.
Afterwards, as shown in Figure 3 B, a plating seed layer 122 is formed on the temporary transient support plate 10 in vapour deposition mode, and at least cover those outer connection pads 112.The plating seed layer 122 can be titanium/copper registered layers.Afterwards, a photoresistance pattern 40 is made to be formed on the plating seed layer 122 of the temporary transient support plate 10 using photolithography technology, the hole of the photoresistance pattern 40 exactly corresponds to those outer connection pads 112.
Afterwards, as shown in Figure 3 C, multiple first conductor pins 120 of setting are on those outer connection pads 112.The formation of those the first conductor pins 120 is using the copper plating in the hole of the photoresistance pattern 40.After the photoresistance pattern 40 is removed, recycle dry-etching that the position that appears of the plating seed layer 122 can be removed, and be retained in the lower section of those the first conductor pins 120 and the part plating seed layer 122 of those peripheries of outer connection pad 112.
Afterwards, as shown in Figure 3 D, engage one first chip 130 and be embedded in formula reconfiguration line layer 110 and be electrically connected to those connection pads 113 in first in this.The set-up mode of first chip 130 can be chip bonding.The projection 131 of first chip 130 is bonded to those connection pads 113 in first with solder 132.Relative to the molding plane 101 for relief those in first connection pad 113 can prevent the diffusion overflow of those solders 132.Non-exclusively, the projection 131 be also bonded using gold-gold bonding, Jin-stannum with the engagement of those connection pads 113 in first, anisotropic conductive film (ACF), anisotropic conductive body (ACP) or non-conductive colloid (NCP).
Afterwards, as shown in FIGURE 3 E, one first molding core layer 140 is formed in the molding plane 101, to seal first chip 130 and those first conductor pins 120, the first molding core layer 140 has an outer engagement face 141, limited by the molding plane 101 and formed, this is embedded into formula reconfiguration line layer 110 and is embedded into into the first molding core layer 140 by the outer engagement face 141, and those are embedded into circuit 111, those outer connection pads 112 with multiple lower surface coplines of those connection pads 113 in first in the outer engagement face 141.The formation of the first molding core layer 140 is first placed on the temporary transient support plate 10 once between the mold 52 of mould 51 and, and moulding compound material is formed in into the molding space between the lower mould 51 and the mold 52.The thickness that preliminarily forms of the first molding core layer 140 can be more than the height of those the first conductor pins 120, to seal those first conductor pins 120 and first chip 130.
Afterwards, as illustrated in Figure 3 F, using the upper surface of the spin finishing of a grinding head 60 first molding core layer 140, with the first planarization lapping mode make the first molding core layer 140 separately have one relative to the outer engagement face 141 first assembly mounting surface 142, those first conductor pins 120 have multiple first capital end faces 121, and copline is in the first assembly mounting surface 142.
Afterwards, as shown in Figure 3 G, one first relief formula reconfiguration line layer 150 is formed on the first assembly mounting surface 142, the first relief formula reconfiguration line layer 150 includes multiple first relief circuits 151, connection pad 153 in multiple first capital pads 152 and multiple second, those the first relief circuits 151 connect corresponding those the first capital pads 152 with those connection pads 153 in second, those the first capital pads 152 are alignedly engaged in those the first capital end faces 121, the first relief formula reconfiguration line layer 150 is by the relief of first assembly mounting surface 142 outside the first molding core layer 140.The forming method of the first relief formula reconfiguration line layer 150 can be identical with the forming method that this is embedded into formula reconfiguration line layer 110.Finally, after the temporary transient support plate 10 is peeled off, you can constitute molding interconnection substrates 100 as shown in Figure 2.
Therefore, in a kind of manufacture method of molding interconnection substrates that the present invention is disclosed, substrate circuit layer need not electroplate line structure, the processing procedure of substrate need not drill, hole wall plating, hole filling operation.Also, can coating chip in core layer.Circuit in the outer engagement face of substrate is preferably embedded into protection.
The molding interconnection substrates of the present invention, except being single-layer core structure, also can be multilamellar core texture.According to second specific embodiment of the present invention, a kind of molding interconnection substrates 200 are illustrated in the schematic cross-section of Fig. 4, wherein represented with the component figure number of the first specific embodiment with the component of function corresponding to the first specific embodiment same names, and repeat no more the identical structure of its thin portion.A kind of molding interconnection substrates 200 basically comprise one and are embedded into formula reconfiguration line layer 110, multiple first conductor pins 120, one first chip 130, one first molding core layer 140 and one first relief formula reconfiguration line layer 150.
As shown in Figure 4, this is embedded into formula reconfiguration line layer 110 and is formed in a molding plane 101, this is embedded into formula reconfiguration line layer 110 and is embedded into connection pad 113 in circuit 111, multiple outer connection pads 112 and multiple first comprising multiple, and those are embedded into circuit 111 and connect corresponding those outer connection pads 112 with those connection pads 113 in first.Those first conductor pins 120 are arranged on those outer connection pads 112.First chip 130 is engaged in this and is embedded in formula reconfiguration line layer 110 and is electrically connected to those connection pads 113 in first.The first molding core layer 140 is formed in the molding plane 101, to seal first chip 130 and those first conductor pins 120, the first molding core layer 140 has an outer engagement face 141, this is embedded into formula reconfiguration line layer 110 and is embedded into into the first molding core layer 140 by the outer engagement face 141, those are embedded into circuit 111, multiple lower surface coplines of those outer connection pads 112 and those connection pads 113 in first are in the outer engagement face 141, wherein the first molding core layer 140 separately have one relative to the outer engagement face 141 first assembly mounting surface 142, those first conductor pins 120 have multiple first capital end faces 121, copline is in the first assembly mounting surface 142.
It is as shown in Figure 4 again, the first relief formula reconfiguration line layer 150 is formed on the first assembly mounting surface 142, the first relief formula reconfiguration line layer 150 includes multiple first relief circuits 151, connection pad 153 in multiple first capital pads 152 and multiple second, those the first relief circuits 151 connect corresponding those the first capital pads 152 with those connection pads 153 in second, those the first capital pads 152 are alignedly engaged in those the first capital end faces 121, the first relief formula reconfiguration line layer 150 is by the relief of first assembly mounting surface 142 outside the first molding core layer 140.
It is engageable in the first relief formula reconfiguration line layer 150 and to be electrically connected to those connection pads 153 in second additionally, the molding interconnection substrates 200 can additionally comprise one second chip 270.Corresponding those connection pads 153 in second are bonded to using multiple projections 271 of second chip 270.
Again as shown in figure 4, the molding interconnection substrates 200 can additionally comprise multiple second conductor pins 260, one second molding core layer 280 and one second relief formula reconfiguration line layer 290.Those second conductor pins 260 are arranged on those the first capital pads 152.The second molding core layer 280 is formed on the first assembly mounting surface 142, to seal second chip 270 and those second conductor pins 260, the first relief formula reconfiguration line layer 150 is embedded into into the second molding core layer 280, wherein the second molding core layer 280 have one relative to the first assembly mounting surface 142 the second component mounting surface 281, those second conductor pins 260 have multiple second capital end faces 261, and copline is in the second component mounting surface 281.The second relief formula reconfiguration line layer 290 is formed on the second component mounting surface 281, the second relief formula reconfiguration line layer 290 includes connection pad 293 in multiple second relief circuits 291, multiple second capital pads 292, multiple three, those the second relief circuits 291 connect corresponding those the second capital pads 292 with those connection pads 293 in the 3rd, those the second capital pads 292 are alignedly engaged in those the second capital end faces 261, and the second relief formula reconfiguration line layer 290 is by the relief of the second component mounting surface 281 outside the second molding core layer 280.Therefore, the molding interconnection substrates 200 can be multilamellar core texture.
The manufacture method of above-mentioned molding interconnection substrates 200 further explained below, its key step is divided into FEOL and back-end process, FEOL can be as the first specific embodiment is with regard to the operating instruction of Fig. 3 A to 3G, repeat no more, back-end process is found in Fig. 5 A to 5E, and it is shown in the component diagram of each step in the back-end process of the molding interconnection substrates 200.
After hookup 3G, as shown in Figure 5A, before the temporary transient support plate 10 is not yet removed, multiple second conductor pins 260 can be set on those the first capital pads 152.The method to set up of those the second conductor pins 260 can be same as the method to set up of those the first conductor pins 120.
Afterwards, as shown in Figure 5 B, one second chip 270 is engaged in the first relief formula reconfiguration line layer 150 and be electrically connected to those connection pads 153 in second.The joint method of second chip 270 can be same as the joint method of first chip 130.
Afterwards, as shown in Figure 5 C, one second molding core layer 280 is formed on the first assembly mounting surface 142, to seal second chip 270 and those second conductor pins 260, the first relief formula reconfiguration line layer 150 is embedded into into the second molding core layer 280.The formation of the second molding core layer 280 using the space between the lower mould 51 and the mold 52 molding.The forming method of the second molding core layer 280 can be same as the forming method of the first molding core layer 140.
Afterwards, as shown in Figure 5 D, using the grinding head 60, with second planarization lapping mode make the second molding core layer 280 have one relative to the first assembly mounting surface 142 the second component mounting surface 281, those second conductor pins 260 have multiple second capital end faces 261, and copline is in the second component mounting surface 281.
Afterwards, as shown in fig. 5e, one second relief formula reconfiguration line layer 290 is formed on the second component mounting surface 281, the second relief formula reconfiguration line layer 290 includes multiple second relief circuits 291, multiple second capital pads 292, connection pad 293 in multiple three, those the second relief circuits 291 connect corresponding those the second capital pads 292 with those connection pads 293 in the 3rd, those the second capital pads 292 are alignedly engaged in those the second capital end faces 261, the second relief formula reconfiguration line layer 290 is by the relief of the second component mounting surface 281 outside the second molding core layer 280.The forming method of the second relief formula reconfiguration line layer 290 can be same as the forming method of the first relief formula reconfiguration line layer 150.When the component to be engaged is differed in first chip 130 on the second component mounting surface 281, quantity and the lengthwise position of those connection pads 293 in the 3rd can not correspond to the quantity and lengthwise position of those connection pads 113 in first.Finally, the temporary transient support plate 10 is peeled off, you can produce molding interconnection substrates 200 as shown in Figure 4.
Fig. 6 is the schematic cross-section that a stacking-type microelectronic device is combined into using the molding interconnection substrates 200.The molding interconnection substrates 200 can additionally comprise an electronic installation 30, such as ball grid array packages construction (BGA package), it is engageable in the second relief formula reconfiguration line layer 290, the electronic installation 30 has multiple first electrodes 31 and multiple second electrodes 32, those first electrodes 31 are engaged in those connection pads 293 in the 3rd, and those second electrodes 32 are engaged in those the second capital pads 292.Multiple external terminals 20 are engageable or are formed at those outer connection pads 112.And Jing suitably cuts, stack type encapsulation structure is just may make up.
Embodiment described above is only the preferred embodiment lifted to absolutely prove the present invention, protection scope of the present invention not limited to this.Equivalent substitute or conversion that those skilled in the art are made on the basis of the present invention, within protection scope of the present invention.Protection scope of the present invention is defined by claims.
Claims (13)
1. a kind of molding interconnection substrates, it is characterised in that include：
One is embedded into formula reconfiguration line layer, is formed in a molding plane, and this is embedded into formula reconfiguration line layer and is embedded into connection pad in circuit, multiple outer connection pads and multiple first comprising multiple, and those are embedded into corresponding those the outer connection pads of connection with those connection pads in first；
Multiple first conductor pins, are arranged on those outer connection pads；
One first chip, is engaged in this and is embedded in formula reconfiguration line layer and is electrically connected to those connection pads in first；
One first molding core layer, it is formed in the molding plane, to seal first chip and those first conductor pins, the first molding core layer has an outer engagement face, this is embedded into formula reconfiguration line layer and is embedded into into the first molding core layer by the outer engagement face, those are embedded into circuit, multiple lower surface coplines of those outer connection pads and those connection pads in first are in the outer engagement face, wherein the first molding core layer separately have one relative to the outer engagement face first assembly mounting surface, those first conductor pins have multiple first capital end faces, copline is in the first assembly mounting surface；And
One first relief formula reconfiguration line layer, it is formed on the first assembly mounting surface, the first relief formula reconfiguration line layer includes connection pad in multiple first relief circuits, multiple first capital pads and multiple second, corresponding those the first capital pads of those the first relief connections and those connection pads in second, those the first capital pads are alignedly engaged in those the first capital end faces, and the first relief formula reconfiguration line layer is by the first assembly mounting surface relief outside the first molding core layer.
2. molding interconnection substrates as claimed in claim 1, it is characterised in that the single layer structure that the first molding core layer solidify to form for molding.
3. molding interconnection substrates as claimed in claim 1, it is characterised in that first chip has multiple projections, and those connection pads in first for being embedded into formula reconfiguration line layer are connected in chip bonding mode.
4. molding interconnection substrates as claimed in claim 1, it is characterized in that, the height of those the first capital end faces to those outer connection pads of those the first conductor pins is more than the chip rational height of first chip, so that first chip is entirely sealed in the first molding core layer.
5. molding interconnection substrates as claimed in claim 1, it is characterised in that be formed with a plating seed layer between those first conductor pins and those outer connection pads.
6. molding interconnection substrates as claimed in claim 5, it is characterised in that the plating seed layer remains rings with more multiple seeds around those outer connection pad peripheries.
7. molding interconnection substrates as claimed in claim 1, it is characterised in that this is embedded into the multiple superposed metal level that formula reconfiguration line layer is reverse configuration.
8. molding interconnection substrates as described in any one of claim 1 to 7, it is characterised in that additionally comprised one second chip, are engaged in the first relief formula reconfiguration line layer and are electrically connected to those connection pads in second.
9. molding interconnection substrates as claimed in claim 8, it is characterised in that additionally comprise：
Multiple second conductor pins, are arranged on those the first capital pads；
One second molding core layer, it is formed on the first assembly mounting surface, to seal second chip and those second conductor pins, the first relief formula reconfiguration line layer is embedded into into the second molding core layer, wherein the second molding core layer have one relative to the first assembly mounting surface the second component mounting surface, those second conductor pins have multiple second capital end faces, and copline is in the second component mounting surface；And
One second relief formula reconfiguration line layer, it is formed on the second component mounting surface, the second relief formula reconfiguration line layer includes connection pad in multiple second relief circuits, multiple second capital pads, multiple three, corresponding those the second capital pads of those the second relief connections and those connection pads in the 3rd, those the second capital pads are alignedly engaged in those the second capital end faces, and the second relief formula reconfiguration line layer is by the second component mounting surface relief outside the second molding core layer.
10. molding interconnection substrates as claimed in claim 9, it is characterised in that additionally comprise multiple external terminals, be arranged at those lower surfaces of those outer connection pads.
11. molding interconnection substrates as claimed in claim 10, it is characterized in that, additionally comprise an electronic installation, it is engaged in the second relief formula reconfiguration line layer, the electronic installation has multiple first electrodes with multiple second electrodes, those first electrodes are engaged in those connection pads in the 3rd, and those second electrodes are engaged in those the second capital pads.
12. a kind of manufacture methods of molding interconnection substrates, it is characterised in that include：
Formation one is embedded into formula reconfiguration line layer in a molding plane, this is embedded into formula reconfiguration line layer and is embedded into connection pad in circuit, multiple outer connection pads and multiple first comprising multiple, those are embedded into corresponding those the outer connection pads of connection with those connection pads in first, and the molding plane is provided by a temporary transient support plate；
Multiple first conductor pins are set on those outer connection pads；
Engage one first chip and be embedded in formula reconfiguration line layer and be electrically connected to those connection pads in first in this；
One first molding core layer is formed in the molding plane, to seal first chip and those first conductor pins, the first molding core layer has an outer engagement face, this is embedded into formula reconfiguration line layer and is embedded into into the first molding core layer by the outer engagement face, and those are embedded into multiple lower surface coplines of circuit, those outer connection pads and those connection pads in first in the outer engagement face；
With the first planarization lapping mode make the first molding core layer separately have one relative to the outer engagement face first assembly mounting surface, those first conductor pins have multiple first capital end faces, and copline is in the first assembly mounting surface；And
One first relief formula reconfiguration line layer is formed on the first assembly mounting surface, the first relief formula reconfiguration line layer includes connection pad in multiple first relief circuits, multiple first capital pads and multiple second, corresponding those the first capital pads of those the first relief connections and those connection pads in second, those the first capital pads are alignedly engaged in those the first capital end faces, and the first relief formula reconfiguration line layer is by the first assembly mounting surface relief outside the first molding core layer.
The manufacture method of 13. molding interconnection substrates as claimed in claim 12, it is characterised in that additionally comprise：
Multiple second conductor pins are set on those the first capital pads；
One second chip is engaged in the first relief formula reconfiguration line layer and those connection pads in second are electrically connected to；
One second molding core layer is formed on the first assembly mounting surface, to seal second chip and those second conductor pins, the first relief formula reconfiguration line layer is embedded into into the second molding core layer；
With the second planarization lapping mode make the second molding core layer have one relative to the first assembly mounting surface the second component mounting surface, those second conductor pins have multiple second capital end faces, and copline is in the second component mounting surface；And
One second relief formula reconfiguration line layer is formed on the second component mounting surface, the second relief formula reconfiguration line layer includes connection pad in multiple second relief circuits, multiple second capital pads, multiple three, corresponding those the second capital pads of those the second relief connections and those connection pads in the 3rd, those the second capital pads are alignedly engaged in those the second capital end faces, and the second relief formula reconfiguration line layer is by the second component mounting surface relief outside the second molding core layer.
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| CN201510682387.8A CN106611747A (en) | 2015-10-21 | 2015-10-21 | A die seal interconnection substrate and a manufacturing method thereof |
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| CN201510682387.8A CN106611747A (en) | 2015-10-21 | 2015-10-21 | A die seal interconnection substrate and a manufacturing method thereof |
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| CN108538794A (en) * | 2018-03-26 | 2018-09-14 | 江苏长电科技股份有限公司 | Surface mount packages structure and preparation method thereof |
| CN109638009A (en) * | 2018-12-17 | 2019-04-16 | 华进半导体封装先导技术研发中心有限公司 | A kind of Multi-chip laminating fan-out package structure and its manufacturing method |
| CN111863689A (en) * | 2019-04-25 | 2020-10-30 | 深圳市环基实业有限公司 | Package carrier, package and process thereof |
| WO2023082443A1 (en) * | 2021-11-12 | 2023-05-19 | 深南电路股份有限公司 | Circuit board preparation method and circuit board |
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| US20080023805A1 (en) * | 2006-07-26 | 2008-01-31 | Texas Instruments Incorporated | Array-Processed Stacked Semiconductor Packages |
| CN104779176A (en) * | 2014-01-15 | 2015-07-15 | 矽品精密工业股份有限公司 | Method for manufacturing packaging structure embedded with chip |
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| US20080023805A1 (en) * | 2006-07-26 | 2008-01-31 | Texas Instruments Incorporated | Array-Processed Stacked Semiconductor Packages |
| CN104779176A (en) * | 2014-01-15 | 2015-07-15 | 矽品精密工业股份有限公司 | Method for manufacturing packaging structure embedded with chip |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108538794A (en) * | 2018-03-26 | 2018-09-14 | 江苏长电科技股份有限公司 | Surface mount packages structure and preparation method thereof |
| CN109638009A (en) * | 2018-12-17 | 2019-04-16 | 华进半导体封装先导技术研发中心有限公司 | A kind of Multi-chip laminating fan-out package structure and its manufacturing method |
| CN111863689A (en) * | 2019-04-25 | 2020-10-30 | 深圳市环基实业有限公司 | Package carrier, package and process thereof |
| WO2023082443A1 (en) * | 2021-11-12 | 2023-05-19 | 深南电路股份有限公司 | Circuit board preparation method and circuit board |
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Application publication date: 20170503 |