TWI575691B - Semiconductor package having pillar top interconnection (pti) - Google Patents

Description

Pole top interconnect (PTI) semiconductor package construction

The present invention relates to semiconductor package construction, and more particularly to a semiconductor package structure for a top-of-column interconnect (PTI).

The purpose of the semiconductor package structure is to protect the package of the semiconductor wafer, the expansion of the pitch of the bonding terminals, and the redefinition of the bonding pads. In addition to being bonded to an external printed circuit board, the semiconductor package structure is also expected to be bonded to a bottom semiconductor package structure for application of a three-dimensional package stack (POP), which is generally adopted in a system package (Sytem-In-Package, SIP). ) Products and intensive micro memory products. The bonding terminal of the package structure is generally a solder ball, and the solder ball is fixed to the substrate in the package structure by a reflow step. The conventional substrate (or IC carrier board) is a micro printed circuit board, and the main system is prepreg. A substrate (prepreg, or prepreg) consists of a substrate core and a printed circuit is formed on the surface. The circuit forming process of the conventional substrate uses a printed circuit board process, including a substrate drilling step. When the upper and lower surfaces of the substrate are bonded to the solder balls, the corresponding packaging process requires multiple ball reflow steps.

1 is a schematic cross-sectional view of a bottom semiconductor package structure of a conventional three-dimensional package stack (POP). The conventional bottom semiconductor package structure 500 mainly includes a substrate 510, a mold sealing layer 520, and a plurality of solder balls 540 as POP intermediate connections. A wafer 550 and a plurality of terminals 560 such as solder balls. The substrate 510 is a circuit board formed by using a printed circuit board process, and includes a wiring structure 511 and upper and lower solder resist layers 512 and 513. The wafer 550 and the solder balls 540 are disposed on the substrate 510. The wafer 550 is provided with a flip chip bond. The underfill 553 should be filled between the wafer 550 and the substrate 510 to seal the solder balls. A crystal bump 551 is formed on the substrate 510 to seal the wafer 550. The protruding terminal 560 is provided with a lower surface of the substrate 510. The mold seal layer 520 has an upper surface 521 that is defined by a molding die. There are two methods for setting the solder balls 540. One method is to first fix the solder balls 540 and then form the mold layer 520 to cover the solder balls 540. Another method is to first The mold layer 520 is formed and then drilled by the upper surface 521 to form a plurality of drill holes 523, and then the solder balls 540 are disposed in the holes 523. In both of the above methods, multiple ball reflow steps are required. Since the wiring structure 511 of the substrate 510 is formed by a printed circuit board process, the line pitch is limited by the printed circuit board process and is not integrated into the wafer level or panel level packaging process. The multi-channel balling step and the drilling step of fabricating a conventional package structure will cause process variations such as substrate warpage, poor solder ball bonding, and cracks in the terminal interface.

US Patent No. 7,851,894 B1 "System and method for shielding of package on package (PoP) assemblies" discloses a bottom package structure of a three-dimensional package stack (POP). The solder balls are used on both sides of the substrate, and the solder balls on the upper surface are The mold seal is coated, and the mold seal is formed to have holes for exposing the solder balls, and the holes are usually formed by drilling.

In order to solve the above problems, the main object of the present invention is to provide a column top interconnection (PTI) semiconductor package structure, which can replace the conventional circuit substrate in structure, and omits the printed circuit board of the conventional circuit substrate in a full package process. Process. For the application of the three-dimensional package stack (POP), the process variation caused by the multi-channel balling step and the drilling step for fabricating the conventional package structure can be removed.

A second object of the present invention is to provide a pillar-top interconnect (PTI) semiconductor package structure, which can omit the dielectric layer on the conventional sealant and the solder resist layer covered by the conventional substrate surface, and reduce the conventional Molding interference caused by high and low surface profiles on the substrate.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a pillar top interconnect (PTI) semiconductor package structure comprising a first mold layer and a second mold layer. The first molding layer is embedded with a reconfiguration line structure. The second molding layer is embedded with a plurality of conductor posts and a wafer, and the second molding layer is formed on the first molding layer. Wherein, the conductor pillars have a plurality of column top faces which are exposed coplanarly on one of the polishing faces of the second mold layer or slightly protruded from an etched surface of the second mold layer. The second mold seal layer is formed with a flip chip thickness between the polished surface (or the etched surface) and the wafer. In another preferred embodiment, the reconfiguration line structure, the conductor posts and the wafer system can be buried in the same molding layer to reduce the package thickness such that the package thickness is no more than twice the height of the flip chip bonding.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing semiconductor package structure, the wafer is flip-chip bonded to a plurality of fan-in pads of the reconfigured line structure, and the conductor posts are disposed on a plurality of fan-out pads of the reconfigured line structure, and the fan-in The mat and the fan-out mats are specifically coplanar. Therefore, the distance between the conductor columns may be greater than the distance between the fan-in pads to facilitate bonding the solder balls or connecting the upper layer reconfiguration lines. By the coplanar fan-inserted mats and the fan-out mats, the conductor posts can be provided in conformity with the set reference plane of the wafer.

In the above semiconductor package structure, the first mold layer may be further embedded with a plurality of external pads, the reconfiguration line structure is a three-dimensional circuit structure and connected to the external pads, and a plurality of external protruding terminals are coupled to the Some external pads. Therefore, the external pads are also embedded in the first molding layer to prevent falling off.

In the foregoing semiconductor package structure, the second mold layer may form a filling gap between the wafer and the first mold layer, and the thickness of the crystal is not greater than the filling gap. Therefore, the bottom of the wafer can be omitted from the formation of the underfill, and the second mold layer is not easy to form a gas trap at the bottom of the wafer.

In the foregoing semiconductor package structure, an embossed reconfiguration circuit layer may be further formed on the polishing surface to connect the top end surfaces of the pillars to change the contact position of the POP stack and is not easy to fall off.

By the above technical means, the present invention provides an innovative structure which can be connected to the solder balls of the top package structure of the POP stack by having coplanar column top end faces of the conductor posts such as copper posts. Process variations due to multiple ball placement steps and borehole drilling can be directly excluded.

T, T'‧‧‧ flip chip thickness

S‧‧‧fill gap

10, 30, 40‧‧‧ top stacking structure

11, 31, 41‧‧‧ solder balls

100‧‧‧Semiconductor package construction

110‧‧‧First molding layer

120‧‧‧Second molding layer

121‧‧‧Grinding surface

121A‧‧ ‧ cover

130‧‧‧Reconfigure line structure

131‧‧‧Fan

132‧‧‧Fan mat

133‧‧‧External mat

140‧‧‧Conductor column

141‧‧‧ top end of the column

150‧‧‧ wafer

151‧‧‧Bumps

152‧‧‧ solder

I60‧‧‧External terminal

200‧‧‧Semiconductor package construction

222‧‧‧etched surface

270‧‧‧embossed reconfiguration circuit layer

300‧‧‧Semiconductor package construction

370‧‧‧embossed reconfiguration circuit layer

400‧‧‧Semiconductor package construction

422‧‧‧etched surface

470‧‧‧embossed reconfiguration circuit layer

500‧‧‧Bottom semiconductor package structure of three-dimensional package stack

510‧‧‧Substrate

511‧‧‧Line structure

512‧‧‧ solder mask

513‧‧‧ solder mask

520‧‧‧Mold sealant

521‧‧‧ upper surface

523‧‧‧Drilling

540‧‧‧ solder balls

550‧‧‧ wafer

551‧‧‧Flip-chip bumps

553‧‧‧ underfill

560‧‧‧External terminal

Figure 1: Schematic cross-sectional view of a bottom semiconductor package structure of a conventional three-dimensional package stack (POP).

2 is a cross-sectional view showing a semiconductor package structure of a pillar top interconnection (PTI) in accordance with a first embodiment of the present invention.

3A to 3D are views showing a cross-sectional view of an element in a main process step in accordance with a first embodiment of the present invention.

4 is a cross-sectional view showing the semiconductor package structure in a three-dimensional package stack application according to a first embodiment of the present invention.

Figure 5 is a cross-sectional view showing a cross-sectional view of an element in a die-cut etching step of a semiconductor package structure of another column top interconnection (PTI) in accordance with a second embodiment of the present invention.

Figure 6 is a cross-sectional view showing another semiconductor package structure of a pillar top interconnect (PTI) in accordance with a second embodiment of the present invention.

Figure 7 is a cross-sectional view showing another semiconductor package structure of a pillar top interconnection (PTI) in a three-dimensional package stack application in accordance with a third embodiment of the present invention.

Figure 8 is a cross-sectional view showing another semiconductor package structure of a column top interconnect (PTI) in a three-dimensional package stack application in accordance with a fourth embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, which are to be understood The basic architecture or implementation method of the present invention is only shown in the elements and combinations related to the present invention. The components shown in the drawings are not drawn in proportion to the actual number, shape and size of the actual implementation, and certain size ratios and other related dimensions. The ratio is either exaggerated or simplified to provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

In accordance with a first embodiment of the present invention, a top package interconnect (PTI) semiconductor package structure 100 is illustrated in cross-sectional view in FIG. 2 and a cross-sectional view of elements in the main process steps of FIGS. 3A through 3D. A pillar top interconnect (PTI) semiconductor package structure 100 mainly includes a first mold layer 110 and a second mold layer 120. The semiconductor package structure 100 can be fabricated using a substrate-free wafer level packaging process or a panel level packaging process, and the conventional printed circuit board process can be omitted.

Referring to FIG. 2 , the first mold layer 110 is embedded with a reconfiguration line structure 130 . The material of the first mold layer 110 may be a thermosetting mold epoxy glue. The method of forming the first mold layer 110 may be compression molding or transfer molding. The reconfiguration line structure 130 includes one or more layers of reconfiguration lines. The reconfiguration circuit layer is a microcircuit layer formed by using a semiconductor wafer deposition apparatus, the reconfiguration wiring layer does not need to be formed on the substrate, and the thickness thinning and the fine pitch of the reconfiguration wiring layer are superior to the conventional ones. The circuit layer of the printed circuit board, and the formation of the re-distribution circuit layer can be formed by a process of first deposition, pattern plating, and etching, or a process of direct pattern deposition, which does not require a conventional plating circuit structure of the printed circuit board. The material of the reconfiguration circuit layer may include copper, aluminum, gold, platinum, nickel, tin or Combinations of the foregoing, such as gold/nickel/copper. In this embodiment, the reconfiguration line structure 130 is a multi-layered three-dimensional line structure, and includes a plurality of fan-in pads 131 and a plurality of fan-out pads 132. The fan-in pads 131 and the fan-out pads 132 are Specifically, it is coplanar. The fan-out pads 132 and the fan-in pads 131 may be the same layer of one of the lines of the reconfiguration line structure 130, or may be an additional layered portion (not shown). The first molding layer 110 provides a completely horizontal molding plane, a raised metal pad and a solder resist layer.

Referring to FIG. 2 , the second molding layer 120 is embedded with a plurality of conductor posts 140 and a wafer 150 . The second molding layer 120 is formed on the first molding layer 110 . The material of the second mold layer 120 may be a thermosetting mold epoxy material, which may be the same or different from the material of the first mold layer 110. The method of forming the second mold layer 120 may be compression molding or transfer molding. The conductive pillars 140 can be copper pillars. The wafer 150 can be an active component including an integrated circuit, and the substrate of the wafer 150 is a semiconductor. The bottom and top surfaces of the wafer 150 are also covered by the second mold layer 120. In the present embodiment, the wafer 150 is flip-chip bonded to the fan-in pads 131 of the reconfigured line structure 130. Specifically, the wafer 150 is provided with a plurality of bumps 151, such as copper stud bumps, and The bumps 151 and the corresponding fan-in pads 131 are bonded by the solder 152 with the active surface of the wafer 150 facing the relocation line structure 130. The fan-shaped pads 140 are disposed on the fan-out pads 132 of the reconfigurable line structure 130 , wherein the fan-in pads 131 and the fan-out pads 132 are coplanar. The conductor posts 140 are extended as the longitudinal connection of the fan-out pads 132 in the longitudinal direction of the polishing surface 121, so that the substrate and the package drill can be omitted. Hole work. Therefore, the distance between the conductor posts 140 may be greater than the distance between the fan-in pads 131 to facilitate bonding the solder balls or connecting the upper layer reconfiguration lines. The common conductors 131 and the fan-out pads 132 can provide the conductive pillars 140 in conformity with the setting reference surface of the wafer 150.

The plurality of column top surfaces 141 are exposed to be coplanar to one of the polishing faces 121 of the second molding layer 120. The second molding layer 120 is on the polishing surface 121. A chip thickness T (as shown in FIG. 2) is formed between the wafer 150 and the chip thickness T is not greater than the height of the bumps 151, and is less than about 200 microns. Therefore, the wafer 150 does not have a surface exposed on the polishing surface 121.

Referring to FIG. 2, in addition to the reconfiguration line structure 130 being a three-dimensional line structure, the first molding layer 110 may be further embedded with a plurality of external pads 133, and the reconfiguration line structure 130 is connected to the plurality of external pads 133. The external pads 133 are bonded to the plurality of external pads 133 by a plurality of, for example, solder balls. Therefore, the external pads 133 are also embedded in the first molding layer 110 to prevent falling off. The protrusion terminals 160 protrude from the first molding layer 110 to serve as contacts for external connection.

Referring to FIG. 2 , the second mold layer 120 may form a filling gap S between the wafer 150 and the first mold layer 110 , and the thickness T of the crystal is not greater than the filling gap S. The filling gap S may be not less than the height of the bumps 151. Therefore, the bottom of the wafer 150 can be omitted from the formation of the conventional underfill, and the second mold layer 120 is not easy to form a gas trap at the bottom of the wafer 150.

The column top surfaces 141 of the conductor posts 140 are provided with a solder ball 11 The junction or the connection of a reconfiguration line layer. FIG. 4 is a schematic cross-sectional view of the semiconductor package structure 100 in a three-dimensional package stack application. A plurality of solder balls 11 of the top stacked package structure 10 of the BGA package type are bonded to the column top end faces 141 of the conductor posts 140. In another variant embodiment, the semiconductor package structure may further comprise an embossed reconfiguration circuit layer (not shown) formed on the polishing surface 121 to connect the column top end faces 141.

3A through 3D are schematic cross-sectional views of the components of the semiconductor package structure 100 in a main process step.

Referring to FIG. 3A, in the first molding step of the wafer level packaging process or the panel level packaging process, the dummy carrier (not shown) is patterned on a wafer type or a panel type. The first molding layer 110 is formed by the sealing method. The first molding layer 110 is embedded with the reconfigurable circuit structure 130. The reconfiguring circuit structure 130 can include the fan-in mats 131 and the fan-outs. Pad 132 and the outer pads 133. Thereafter, in the plating step of the wafer level packaging process or the panel level packaging process, the conductor posts 140 are formed on the fan-out pads 132 by electroplating.

Referring to FIG. 3B, in the flip chip bonding step of the wafer level packaging process or the panel level packaging process, a plurality of wafers 150 are disposed on the first molding layer 110, and the bumps of the wafers 150 are 151 is bonded to the plurality of fan-in pads 131 of the reconfigured line structure 130 via corresponding solder 152. The heights of the wafers 150 are less than the height of the conductor posts 140.

Referring to FIG. 3C, in the second molding step of the wafer level packaging process or the panel level packaging process, the second molding layer 120 is formed by molding. On the first mold layer 110. The second mold layer 120 is used to embed the conductor posts 140 and the wafer 150. In this step, the second mold layer 120 has a mold cover 121A defined by the mold, which is higher than the top end faces 141 of the conductor posts 140, that is, the second mold layer 120. The thickness of the mold is greater than the plating height of the conductor posts 140.

Referring to FIG. 3D, in the planarization polishing step of the wafer level packaging process or the panel level packaging process, the mold cover 121A of the second mold layer 120 is ground to reduce the second mold layer 120. The thickness is formed, and the abrasive surface 121 of the second mold layer 120 is formed. The column top end faces 141 of the conductor posts 140 are exposed coplanar to the polishing surface 121 of the second mold layer 120, and the second mold layer 120 is on the polishing surface 121 and the wafer 150. A cuvette thickness is formed between the layers. Therefore, the back surface of the wafer 150 is not exposed to the polishing surface 121, and the surface characteristics of the polishing surface 121 may be different from the surface characteristics of the mold cover 121A. For example, the polishing surface 121 and the exposed column top surface 141 may be simultaneously It becomes more rough to facilitate component joining. Finally, the semiconductor package structure 100 as shown in FIG. 2 can be fabricated through a ball bonding step and a singulation step of a wafer level packaging process or a panel level packaging process.

Accordingly, the present invention discloses a post-top interconnect (PTI) semiconductor package structure 100 that is structurally replaceable to a conventional circuit substrate and that omits the printed circuit board process of the conventional circuit substrate in a full package process. For the application of the three-dimensional package stack (POP), the process variation caused by the multi-channel balling step and the drilling step for fabricating the conventional package structure can be removed. In addition, the dielectric layer on the conventional encapsulant and the conventional substrate table can be omitted. The surface is covered with a solder resist layer to reduce the mold flow interference caused by the high and low surface profile on the conventional substrate.

In accordance with a second embodiment of the present invention, a post-top interconnect (PTI) semiconductor package structure 200 illustrates a cross-sectional schematic view of a cross-sectional view of the device in the mold etch step of FIG. 5 and a cross-sectional view of FIG. Elements having the same names and functions as those of the first embodiment are denoted by the component numbers of the first embodiment, and the details of the details are omitted. A pillar top interconnect (PTI) semiconductor package structure 200 includes a first mold layer 110 and a second mold layer 120. The semiconductor package structure 200 is also fabricated using a substrate-free wafer-level packaging process or a panel-level packaging process. The conventional printed circuit board process can be omitted, and the main process steps in the 3A to 3D drawings can be used. The die-cut etch step can be performed after the planarization grinding step of Figure 3D.

Referring to FIGS. 5 and 6, the first mold layer 110 is embedded with a reconfiguration line structure 130. The second mold layer 120 is embedded with a plurality of conductor posts 140 and a wafer 150. The second mold layer 120 is formed on the first mold layer 110. The conductive pillars 140 have a plurality of pillar top surfaces 141 which are exposed on the second molding layer 120 and protrude from the etching surface 222 of the second molding layer 120. The second mold layer 120 is formed with a flip-chip thickness T' between the etched surface 222 and the wafer 150 (as shown in FIG. 6). The "microprojection" may be such that the height of the conductive pillars 140 protruding from the etched surface 222 is below 50 micrometers. In addition, the etching surface 222 of FIG. 5 may be formed by performing a die etching step on the polishing surface 121 of FIG. 3D, such as dry etching or for a molding gel. Chemical etching.

Referring to FIGS. 5 and 6, the first molding layer 110 is further embedded with a plurality of external pads 133. The reconfiguration circuit structure 130 is a three-dimensional circuit structure and connects the external pads 133, and a plurality of external protrusions. Terminals 160 are bonded to the outer pads 133 (as shown in FIG. 6). More specifically, the second mold layer 120 is formed with a filling gap S between the wafer 150 and the first mold layer 110, and the thickness T' of the flip chip is not greater than the filling gap S.

Preferably, the semiconductor package structure 200 further includes an embossed reconfiguration circuit layer 270 formed on the etched surface 222 to connect the column top end surfaces 141 for changing the contact position of the POP stack. And not easy to fall off.

Accordingly, the present invention discloses a post-top interconnect (PTI) semiconductor package structure 200 that is structurally replaceable to a conventional circuit substrate and that omits the printed circuit board process of the conventional circuit substrate in a full package process. For the application of the three-dimensional package stack (POP), the process variation caused by the multi-channel balling step and the drilling step for fabricating the conventional package structure can be removed. The column top end faces 141 of the etched surface 222 will have a better mechanical bonding effect on the bonding pads of the corresponding bonding balls or the embossed rewiring circuit layer 270.

In accordance with a third embodiment of the present invention, a top-of-the-column interconnect (PTI) semiconductor package structure 300 is illustrated in a cross-sectional view of the FIG. 7 in a three-dimensional package stack application, wherein the same name is used in relation to the first embodiment. The elements of the function are denoted by the component numbers of the first embodiment, and the details of the details thereof will not be described again. A pillar top interconnect (PTI) semiconductor package structure 300 includes a mold layer 110.

Referring to FIG. 7 , the mold layer 110 is embedded with a reconfigurable line structure 130 , a plurality of conductor posts 140 , and a wafer 150 . Wherein, the conductor pillars 140 have a plurality of column top end faces 141 which are exposed coplanarly to one of the polishing faces 121 of the mold compound layer 110 (as shown in FIG. 7), or in different embodiments, The top end faces 141 of the posts are microprojected on one of the etched faces 422 of the mold layer 110 (as shown in FIG. 8). Moreover, the mold layer 110 is formed on the wafer 150 with a flip chip thickness (longitudinal colloidal thickness between the rubbing surface 121 and the back surface of the wafer 150), and the mold layer 110 is on the wafer 150. A direction toward the reconfiguration line structure 130 is formed with a filling gap S which is not greater than the filling gap S.

Referring to FIG. 7 , the wafer 150 is flip-chip bonded to the plurality of fan-in pads 131 of the reconfigured line structure 130 , and the conductor posts 140 are disposed on the plurality of fan-out pads 132 of the reconfigurable line structure 130 . The fan-in pads 131 and the fan-out pads 132 are coplanar.

More specifically, the reconfiguration line structure 130 is a single layer circuit structure, and a plurality of, for example, solder ball protrusion terminals 160 are bonded to the plurality of outer surfaces of the fan-out pads 132 that are not covered by the molding layer 110. . In a preferred embodiment, the semiconductor package structure 300 can further include an embossed reconfiguration circuit layer 370 formed on the mold layer 110 to non-depressively connect the column top end faces 141. The embossed reconfiguration circuit layer 370 is a reconfigurable ball pad comprising a plurality of matrix arrangements. Some of the reconfigured ball pads located at the periphery are aligned and overlaid on the tops of the columns On the end surface 141, the remaining re-arranged ball pads are disposed on the polishing surface 121 in an inner ring matrix arrangement to obtain a good fixing force.

In addition, in a three-dimensional package stack (POP) application, a BGA type top stack package structure 30 can be bonded to the reconfigured ball pads of the embossed reconfiguration line layer 370 by solder balls 31 at the bottom thereof. .

In accordance with a fourth embodiment of the present invention, a top-of-the-column interconnect (PTI) semiconductor package construction 400 is illustrated in a cross-sectional view of FIG. 8 in a three-dimensional package stack application, wherein the same name is used in relation to the first embodiment. The elements of the function are denoted by the component numbers of the first embodiment, and the details of the details thereof will not be described again. A post-top interconnect (PTI) semiconductor package structure 400 includes one or more layers of molding compound 110. In the illustration of Fig. 8, the two layers of the molding compound layer 110 are simply shown, and the actual product may be a molding layer containing 4 layers, 6 layers, 8 layers or more.

Referring to FIG. 8, each layer of the molding layer 110 is embedded with a reconfigurable wiring structure 130, a plurality of conductor pillars 140, and a wafer 150. The conductive pillars 140 have a plurality of pillar top surfaces 141 which are exposed coplanarly on one of the surface of the mold layer or slightly etched on one of the etched surfaces 422 of the mold layer; In an example, the top end faces 141 of the pillars are exposed in a coplanar manner to the etched surface 422 of the mold layer 110. Moreover, the mold layer 110 is formed on the wafer 150 with a flip-chip thickness T' (ie, a longitudinal colloidal thickness between the etched surface 422 and the back surface of the wafer 150), and the mold layer 110 is A filling gap S is formed in the direction of the wafer 150 toward the rearrangement line structure 130. The thickness of the flip chip T is not Greater than the filling gap S.

Referring to FIG. 8 , the wafer 150 is flip-chip bonded to the plurality of fan-in pads 131 of the reconfigured line structure 130 , and the conductor posts 140 are disposed on the plurality of fan-out pads 132 of the reconfigurable line structure 130 . The fan-in pads 131 and the fan-out pads 132 are embedded in the mold layer 110 in a coplanar manner.

In this embodiment, the re-arrangement line structure 130 is a single-layer structure, and the plurality of protrusion terminals 160 are bonded to the bottommost molding layer 110. The fan-out pads 132 are not covered by the molding layer 110. a plurality of outer surfaces.

Referring to FIG. 8 again, the semiconductor package structure 400 can further include an embossed reconfiguration circuit layer 470 formed on the etched surface 422 of the topmost mold layer 110 to connect the non-recessed portions. Column top surface 141. The embossed reconfiguration circuit layer 470 is a reconfigurable ball pad comprising a plurality of matrix arrangements. A portion of the reconfigurable ball pads located at the periphery are aligned and overlaid on the top end faces 141 of the columns, and the remaining reconfigured ball pads are disposed on the etched surface 422 in an inner ring matrix arrangement. Good fixation.

In addition, in a three-dimensional package stack (POP) application, a BGA type top stack package structure 40 can be bonded to the reconfigured ball pads of the embossed reconfiguration line layer 470 by solder balls 41 at the bottom thereof. .

Accordingly, the present invention provides a pillar top interconnect (PTI) semiconductor package structure 100, 200, 300, 400 that can be fabricated in a substrate-free wafer level packaging process or a panel level packaging process, and the conventional substrate can be omitted. Printed circuit board process. And improved the existing fan-out wafer level package structure (or fan-out panel, etc.) Grade-package construction), which enhances the bond strength of the solder joint strength of the top stacked package structure or the embossed reconfigurable circuit layer, thus achieving a fan-out wafer/panel grade package (FOWLP/FOPLP) and stereo The good integration of the package stack (POP) eliminates process variations caused by the multiple ball placement steps and drilling steps of the conventional package construction.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes made in the claims of the present invention are still within the scope of the present invention.

T‧‧‧ flip chip thickness

S‧‧‧fill gap

100‧‧‧Semiconductor package construction

110‧‧‧First molding layer

120‧‧‧Second molding layer

121‧‧‧Grinding surface

130‧‧‧Reconfigure line structure

131‧‧‧Fan

132‧‧‧Fan mat

133‧‧‧External mat

140‧‧‧Conductor column

141‧‧‧ top end of the column

150‧‧‧ wafer

151‧‧‧Bumps

152‧‧‧ solder

160‧‧‧External terminal

Claims (8)

A pillar top interconnect (PTI) semiconductor package structure comprising: a first mold layer, a reconfigured line structure; and a second mold layer, a plurality of conductor posts and a wafer The second molding layer is formed on the first molding layer; wherein the conductive pillars have a plurality of column top surfaces that are exposed coplanar to one of the second molding layers a grinding surface, the second molding layer is formed with a coating thickness between the polishing surface and the wafer; wherein the wafer is provided with a plurality of columnar bumps, and the above-mentioned columnar bumps are flip-chip bonded to the substrate The plurality of fan-in pads of the reconfigured line structure; and the semiconductor package structure further includes an embossed reconfigurable circuit layer formed on the polishing surface to connect the top end faces of the columns. The pillar package interconnection (PTI) semiconductor package structure of claim 1, wherein the conductor pillars are disposed on a plurality of fan-out pads of the reconfiguration line structure, the fan-in pads and the The fan-out mats are coplanar. The semiconductor package structure of the pillar top interconnection (PTI) according to claim 2, wherein the first mold layer is further embedded with a plurality of external pads, and the reconfiguration circuit structure is a three-dimensional circuit structure. Connecting the external pads, a plurality of external protruding terminals are coupled to the external pads. The semiconductor package structure of a column top interconnect (PTI) according to claim 1, wherein the second mold layer is formed between the wafer and the first mold layer. Filling the gap, the thickness of the flip chip is not greater than the fill gap. A pillar top interconnect (PTI) semiconductor package construction comprising: a first mold seal layer is embedded with a re-arrangement line structure; and a second mold seal layer is embedded with a plurality of conductor posts and a wafer, and the second mold seal layer is formed on the first mold layer On the sealant layer, wherein the conductor pillars have a plurality of pillar top faces that are exposed coplanarly on the second mold seal layer and protrude from one of the etched surfaces of the second mold seal layer. The second mold layer is formed with a flip chip thickness between the etched surface and the wafer; wherein the wafer is provided with a plurality of columnar bumps, and the re-arrangement is performed by flip chip bonding via the pillar bumps a plurality of fan-in pads of the line structure; and the semiconductor package structure further includes an embossed reconfiguration circuit layer formed on the etched surface to connect the top end faces of the columns. The pillar package interconnection (PTI) semiconductor package structure of claim 5, wherein the conductor pillars are disposed on a plurality of fan-out pads of the reconfiguration line structure, the fan-in pads and the The fan-out mats are coplanar. The semiconductor package structure of the pillar top interconnection (PTI) according to claim 6, wherein the first mold layer is further embedded with a plurality of external pads, and the reconfiguration circuit structure is a three-dimensional circuit structure. Connecting the external pads, a plurality of external protruding terminals are coupled to the external pads. The semiconductor package structure of a column top interconnect (PTI) according to claim 5, 6 or 7, wherein the second mold layer is formed between the wafer and the first mold layer. Filling the gap, the thickness of the flip chip is not greater than the fill gap.