KR101095055B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR101095055B1 KR101095055B1 KR20100054798A KR20100054798A KR101095055B1 KR 101095055 B1 KR101095055 B1 KR 101095055B1 KR 20100054798 A KR20100054798 A KR 20100054798A KR 20100054798 A KR20100054798 A KR 20100054798A KR 101095055 B1 KR101095055 B1 KR 101095055B1
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- hole
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- etching
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- interlayer insulating
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical & Material Sciences (AREA)
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Abstract
According to the present invention, a TSV mask is used to form through silicon vias in a semiconductor substrate, but the semiconductor substrate is etched using an anisotropic etching method, and then bulbous holes are formed using an isotropic etching method. Therefore, due to the shape of the protruding bulb-shaped hole, thermal stress is transmitted to the through silicon via to reduce the stress of the metal material of the through silicon via, thereby preventing the defect caused by the stress. Provide a method.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a through substrate via (TSV).
Three-dimensional lamination technology among packaging technologies of semiconductor integrated circuits has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance, and the three-dimensional lamination package has a plurality of chips having the same storage capacity. A stacked package, which is commonly referred to as a stack chip package.
Here, the technology of the laminated chip package can reduce the manufacturing cost of the package by a simplified process, and also has advantages such as mass production, while wiring space for electrical connection inside the package is increased due to the increase in the number and size of the stacked chips. There is a shortcoming.
That is, the conventional laminated chip package is manufactured in a structure in which a plurality of chips are attached to the chip attaching region of the substrate so as to be electrically connected between the bonding pads of each chip and the conductive circuit pattern of the substrate so as to enable wire bonding. This requires a circuit pattern area of the substrate to which the wires are connected, resulting in an increase in the size of the semiconductor package.
In view of this, a structure using through silicon vias (TSV) has been proposed as an example of a stack package. After forming through silicon vias in each chip at the wafer stage, the through silicon vias vertically intersect the chips. Looking at the structure of the physical and electrical connection to make a conventional manufacturing process briefly as follows.
1 is a cross-sectional view illustrating a process of forming a through silicon via according to the prior art.
The through-silicon via 16 is formed by burying an electrolytic material, that is, a
Next, the backside of the wafer is back ground to expose the
The wafer is then sawed and separated into individual chips, and then at least two or more chips are stacked vertically on the substrate for signal exchange through conductive metals of through silicon vias. Thereafter, the stack package is completed by molding the upper surface of the substrate including the stacked chips and mounting solder balls on the lower surface of the substrate.
Even after manufacturing the through silicon via (TSV) through the other manufacturing process is exposed to the continuous heat (Thermal) there is a problem that the metal material in the through silicon via is stressed (stress), a failure occurs.
In order to solve the above-mentioned problems, the present invention uses a TSV mask and forms an anisotropic etching method to form a through silicon via (TSV) in the semiconductor substrate. Afterwards, the bulb-shaped hole is formed by using an isotropic etching method to transfer heat stress to the through-silicon via to the surrounding silicon via, thereby reducing the stress of the metal material of the through-silicon via. Provided is a method of manufacturing a semiconductor device that can be reduced.
The present invention provides a method of forming an interlayer insulating film on a semiconductor substrate, etching the interlayer insulating film using a mask for forming a through substrate via (TSV) to form a first hole, and forming a first hole in the lower portion of the first hole. Etching the interlayer insulating layer to form a first bulb-type hole, further etching the first bulb-type hole to form a second hole, and an oxide film and a barrier metal film on the entire surface including the second hole. And sequentially depositing a metal film to form a through substrate via (TSV).
Preferably, the metal film is characterized in that it contains copper (Cu).
Preferably, the first hole is formed by an anisotropic etching of the interlayer insulating film.
Preferably, the first bulb-shaped hole is formed by isotropic etching the exposed interlayer insulating layer below the first hole.
Preferably, the second hole is formed by an anisotropic etching of the exposed interlayer insulating layer below the first bulb-shaped hole until the semiconductor substrate is exposed.
Preferably, the barrier metal layer may include a structure in which titanium (Ti) and titanium nitride (TiN) are stacked.
Preferably, after forming the second hole, etching the exposed semiconductor substrate under the second hole to form a second bulb-type hole and further etching the second bulb-type hole to form a third hole. Forming a hole is characterized in that it further comprises.
Preferably, the second bulb-shaped hole is formed using an isotropic etching method.
Preferably, the third hole is formed by an anisotropic etching of the semiconductor substrate.
Preferably, the barrier metal layer is formed using a chemical vapor deposition (CVD) method.
In the present invention, a TSV mask is used to form through silicon vias (TSV) on a semiconductor substrate, and the semiconductor substrate is etched using an anisotropic etching method, and then an isotropic etching method is used. By forming a bulb-shaped hole, the shape of the protruding bulb-shaped hole transmits a stress caused by heat to the through-silicon via, thereby reducing the stress of the metal material of the through-silicon via.
1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.
2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.
2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
Referring to FIG. 2A, an
Next, after the photoresist film is formed on the
As shown in FIG. 2B, the
Referring to FIG. 2C, the lower portion of the exposed
As illustrated in FIG. 2D, the first bulb-
Referring to FIG. 2E, a lower portion of the exposed
As shown in FIG. 2F, after forming the second bulb-
Here, an anisotropic etching process and an isotropic etching process may be repeatedly performed by using a TSV mask.
2G and 2H, a
Next, a
In the present invention, a TSV mask is used to form through silicon vias (TSV) on a semiconductor substrate, and the semiconductor substrate is etched using an anisotropic etching method, and then an isotropic etching method is used. By forming a bulb-shaped hole, the shape of the protruding bulb-shaped hole transmits a stress caused by heat to the through-silicon via, thereby reducing the stress of the metal material of the through-silicon via.
It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.
Claims (10)
Etching the interlayer insulating layer using a mask for forming a through substrate via (TSV) to form a first hole;
Etching the interlayer insulating layer below the first hole to form a first bulb-shaped hole;
Further etching the first bulb-shaped hole to form a second hole; And
Sequentially depositing an oxide film, a barrier metal film, and a metal film on the entire surface including the second hole to form a through substrate via (TSV).
Method for manufacturing a semiconductor device comprising a.
The metal film comprises a copper (Cu) manufacturing method of a semiconductor device.
The first hole is a method of manufacturing a semiconductor device, characterized in that formed by an anisotropic etching of the interlayer insulating film.
And the first bulb-shaped hole is formed by isotropic etching the exposed interlayer insulating layer under the first hole.
And the second hole is formed by an anisotropic etching of the exposed interlayer insulating layer under the first bulb-shaped hole until the semiconductor substrate is exposed.
The barrier metal layer may include a structure in which titanium (Ti) and titanium nitride (TiN) are stacked.
After forming the second hole,
Etching the exposed semiconductor substrate below the second hole to form a second bulb-shaped hole; And
And further etching the second bulb-shaped hole to form a third hole.
The second bulb-type hole is a method of manufacturing a semiconductor device, characterized in that formed using an isotropic etching method.
The third hole is a method of manufacturing a semiconductor device, characterized in that formed by the anisotropic (An-isotropic) etching of the semiconductor substrate.
The barrier metal film is formed using a chemical vapor deposition (CVD) method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR20100054798A KR101095055B1 (en) | 2010-06-10 | 2010-06-10 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
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KR20100054798A KR101095055B1 (en) | 2010-06-10 | 2010-06-10 | Method for manufacturing semiconductor device |
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KR20110135075A KR20110135075A (en) | 2011-12-16 |
KR101095055B1 true KR101095055B1 (en) | 2011-12-20 |
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KR20100054798A KR101095055B1 (en) | 2010-06-10 | 2010-06-10 | Method for manufacturing semiconductor device |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9337125B2 (en) | 2012-09-12 | 2016-05-10 | Samsung Electronics Co., Ltd. | Integrated circuit devices including a via structure and methods of fabricating integrated circuit devices including a via structure |
KR20170071421A (en) | 2015-12-15 | 2017-06-23 | 솔브레인 주식회사 | Composition for plating copper and method of forming copper wire using the same |
KR20190071591A (en) | 2017-12-14 | 2019-06-24 | 솔브레인 주식회사 | Composition for plating cobalt and method for forming a methal wiring using the same |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101411734B1 (en) * | 2013-01-08 | 2014-06-25 | 앰코 테크놀로지 코리아 주식회사 | Fabricating method of semiconductor device having through silicon via and semiconductor device therof |
KR101617382B1 (en) | 2014-06-24 | 2016-05-02 | 서울시립대학교 산학협력단 | Through Silicon Via electroplating filling solution and Method for suppressing -SiC layer extrusion in Through Silicon Via using the filling solution |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004200547A (en) | 2002-12-20 | 2004-07-15 | Seiko Epson Corp | Semiconductor chip, semiconductor wafer, semiconductor device and method for manufacturing the same, and circuit board and electronic component |
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2010
- 2010-06-10 KR KR20100054798A patent/KR101095055B1/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004200547A (en) | 2002-12-20 | 2004-07-15 | Seiko Epson Corp | Semiconductor chip, semiconductor wafer, semiconductor device and method for manufacturing the same, and circuit board and electronic component |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9337125B2 (en) | 2012-09-12 | 2016-05-10 | Samsung Electronics Co., Ltd. | Integrated circuit devices including a via structure and methods of fabricating integrated circuit devices including a via structure |
KR20170071421A (en) | 2015-12-15 | 2017-06-23 | 솔브레인 주식회사 | Composition for plating copper and method of forming copper wire using the same |
KR20190071591A (en) | 2017-12-14 | 2019-06-24 | 솔브레인 주식회사 | Composition for plating cobalt and method for forming a methal wiring using the same |
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KR20110135075A (en) | 2011-12-16 |
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