KR101095055B1

KR101095055B1 - Method for manufacturing semiconductor device

Info

Publication number: KR101095055B1
Application number: KR20100054798A
Authority: KR
Inventors: 성민철
Original assignee: 주식회사 하이닉스반도체
Priority date: 2010-06-10
Filing date: 2010-06-10
Publication date: 2011-12-20
Also published as: KR20110135075A

Abstract

According to the present invention, a TSV mask is used to form through silicon vias in a semiconductor substrate, but the semiconductor substrate is etched using an anisotropic etching method, and then bulbous holes are formed using an isotropic etching method. Therefore, due to the shape of the protruding bulb-shaped hole, thermal stress is transmitted to the through silicon via to reduce the stress of the metal material of the through silicon via, thereby preventing the defect caused by the stress. Provide a method.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a through substrate via (TSV).

Three-dimensional lamination technology among packaging technologies of semiconductor integrated circuits has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance, and the three-dimensional lamination package has a plurality of chips having the same storage capacity. A stacked package, which is commonly referred to as a stack chip package.

Here, the technology of the laminated chip package can reduce the manufacturing cost of the package by a simplified process, and also has advantages such as mass production, while wiring space for electrical connection inside the package is increased due to the increase in the number and size of the stacked chips. There is a shortcoming.

That is, the conventional laminated chip package is manufactured in a structure in which a plurality of chips are attached to the chip attaching region of the substrate so as to be electrically connected between the bonding pads of each chip and the conductive circuit pattern of the substrate so as to enable wire bonding. This requires a circuit pattern area of the substrate to which the wires are connected, resulting in an increase in the size of the semiconductor package.

In view of this, a structure using through silicon vias (TSV) has been proposed as an example of a stack package. After forming through silicon vias in each chip at the wafer stage, the through silicon vias vertically intersect the chips. Looking at the structure of the physical and electrical connection to make a conventional manufacturing process briefly as follows.

1 is a cross-sectional view illustrating a process of forming a through silicon via according to the prior art.

Vertical holes 12 are formed in the bonding pad adjacent portions of each chip 26 at the wafer level, and an insulating film (not shown) is formed on the surface of the vertical holes 12.

The through-silicon via 16 is formed by burying an electrolytic material, that is, a conductive metal 14, through the electroplating process in the vertical hole 12 with the seed metal film formed on the insulating film.

Next, the backside of the wafer is back ground to expose the conductive metal 14 embedded in the through silicon via 16.

The wafer is then sawed and separated into individual chips, and then at least two or more chips are stacked vertically on the substrate for signal exchange through conductive metals of through silicon vias. Thereafter, the stack package is completed by molding the upper surface of the substrate including the stacked chips and mounting solder balls on the lower surface of the substrate.

Even after manufacturing the through silicon via (TSV) through the other manufacturing process is exposed to the continuous heat (Thermal) there is a problem that the metal material in the through silicon via is stressed (stress), a failure occurs.

In order to solve the above-mentioned problems, the present invention uses a TSV mask and forms an anisotropic etching method to form a through silicon via (TSV) in the semiconductor substrate. Afterwards, the bulb-shaped hole is formed by using an isotropic etching method to transfer heat stress to the through-silicon via to the surrounding silicon via, thereby reducing the stress of the metal material of the through-silicon via. Provided is a method of manufacturing a semiconductor device that can be reduced.

The present invention provides a method of forming an interlayer insulating film on a semiconductor substrate, etching the interlayer insulating film using a mask for forming a through substrate via (TSV) to form a first hole, and forming a first hole in the lower portion of the first hole. Etching the interlayer insulating layer to form a first bulb-type hole, further etching the first bulb-type hole to form a second hole, and an oxide film and a barrier metal film on the entire surface including the second hole. And sequentially depositing a metal film to form a through substrate via (TSV).

Preferably, the metal film is characterized in that it contains copper (Cu).

Preferably, the first hole is formed by an anisotropic etching of the interlayer insulating film.

Preferably, the first bulb-shaped hole is formed by isotropic etching the exposed interlayer insulating layer below the first hole.

Preferably, the second hole is formed by an anisotropic etching of the exposed interlayer insulating layer below the first bulb-shaped hole until the semiconductor substrate is exposed.

Preferably, the barrier metal layer may include a structure in which titanium (Ti) and titanium nitride (TiN) are stacked.

Preferably, after forming the second hole, etching the exposed semiconductor substrate under the second hole to form a second bulb-type hole and further etching the second bulb-type hole to form a third hole. Forming a hole is characterized in that it further comprises.

Preferably, the second bulb-shaped hole is formed using an isotropic etching method.

Preferably, the third hole is formed by an anisotropic etching of the semiconductor substrate.

Preferably, the barrier metal layer is formed using a chemical vapor deposition (CVD) method.

In the present invention, a TSV mask is used to form through silicon vias (TSV) on a semiconductor substrate, and the semiconductor substrate is etched using an anisotropic etching method, and then an isotropic etching method is used. By forming a bulb-shaped hole, the shape of the protruding bulb-shaped hole transmits a stress caused by heat to the through-silicon via, thereby reducing the stress of the metal material of the through-silicon via.

1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.
2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, an interlayer insulating layer 210 is formed on the semiconductor substrate 200. In this case, the interlayer insulating film 210 may be formed of an oxide film.

Next, after the photoresist film is formed on the interlayer insulating film 210, the photoresist pattern 220 is formed by an exposure and development process using a mask for forming a through substrate via (TSV).

As shown in FIG. 2B, the interlayer insulating layer 210 is etched using the photoresist pattern 220 as a mask to form a first hole 230. In this case, it is preferable to perform an anisotropic etching process to form the first hole 230.

Referring to FIG. 2C, the lower portion of the exposed first hole 230 is etched to form a first bulb type hole 240. In this case, it is preferable to perform an isotropic etching process to form the first bulb-shaped hole 240.

As illustrated in FIG. 2D, the first bulb-shaped hole 240 is additionally etched until the semiconductor substrate 200 is exposed to form the second hole 250.

Referring to FIG. 2E, a lower portion of the exposed second hole 250 is etched to form a second bulb type hole 260. In this case, it is preferable to perform an isotropic etching process to form the second bulb-shaped hole 260.

As shown in FIG. 2F, after forming the second bulb-shaped hole 260, the lower portion of the second bulb-shaped hole 260 is etched to form the third hole 270.

Here, an anisotropic etching process and an isotropic etching process may be repeatedly performed by using a TSV mask.

2G and 2H, a liner oxide layer 280 is deposited on the entire surface including the third hole 270. In this case, the liner oxide layer 280 is configured to insulate the silicon (Si) of the semiconductor substrate 200 and the metal material deposited in a subsequent process from each other.

Next, a barrier metal layer 290 and a copper (Cu) material 300 are sequentially deposited on the entire surface including the liner oxide layer 280. In this case, the barrier metal layer 290 is preferably formed by using a chemical vapor deposition (CVD) method, and the diffusion barrier layer for preventing the diffusion of the copper (Cu) material 300 and improving the cohesion (adhision) Can play a role. Here, the barrier metal layer preferably includes a structure in which titanium (Ti) and titanium nitride layer (TiN) are stacked.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims

Forming an interlayer insulating film on the semiconductor substrate;
Etching the interlayer insulating layer using a mask for forming a through substrate via (TSV) to form a first hole;
Etching the interlayer insulating layer below the first hole to form a first bulb-shaped hole;
Further etching the first bulb-shaped hole to form a second hole; And
Sequentially depositing an oxide film, a barrier metal film, and a metal film on the entire surface including the second hole to form a through substrate via (TSV).
Method for manufacturing a semiconductor device comprising a.

Claim 2 has been abandoned due to the setting registration fee.

The method of claim 1,
The metal film comprises a copper (Cu) manufacturing method of a semiconductor device.

Claim 3 was abandoned when the setup registration fee was paid.

The method of claim 1,
The first hole is a method of manufacturing a semiconductor device, characterized in that formed by an anisotropic etching of the interlayer insulating film.

Claim 4 was abandoned when the registration fee was paid.

The method of claim 1,
And the first bulb-shaped hole is formed by isotropic etching the exposed interlayer insulating layer under the first hole.

Claim 5 was abandoned upon payment of a set-up fee.

The method of claim 1,
And the second hole is formed by an anisotropic etching of the exposed interlayer insulating layer under the first bulb-shaped hole until the semiconductor substrate is exposed.

Claim 6 was abandoned when the registration fee was paid.

The method of claim 1,
The barrier metal layer may include a structure in which titanium (Ti) and titanium nitride (TiN) are stacked.

Claim 7 was abandoned upon payment of a set-up fee.

The method of claim 1,
After forming the second hole,
Etching the exposed semiconductor substrate below the second hole to form a second bulb-shaped hole; And
And further etching the second bulb-shaped hole to form a third hole.

Claim 8 was abandoned when the registration fee was paid.

The method of claim 7, wherein
The second bulb-type hole is a method of manufacturing a semiconductor device, characterized in that formed using an isotropic etching method.

Claim 9 was abandoned upon payment of a set-up fee.

The method of claim 7, wherein
The third hole is a method of manufacturing a semiconductor device, characterized in that formed by the anisotropic (An-isotropic) etching of the semiconductor substrate.

Claim 10 was abandoned upon payment of a setup registration fee.

The method of claim 1,
The barrier metal film is formed using a chemical vapor deposition (CVD) method.