TWI611530B - Thermally enhanced face-to-face semiconductor assembly with heat spreader and method of making the same - Google Patents

Abstract

The face-to-face semiconductor package of the present invention is characterized in that the embedding device is electrically coupled to and stacked on the heat dissipation gain type device, wherein the embedding device has the first semiconductor element, and the first semiconductor element is in the sealing material. Surrounded by a series of vertical connectors, the heat sinking type device has a second semiconductor wafer, and the second semiconductor wafer is received in a recess of the heat conducting plate. The first and second semiconductor wafers are placed face to face on opposite sides of the first routing circuit and further electrically connected to the vertical connectors by the first routing circuit. The heat conducting plate has a heat sink to provide a means for heat dissipation of the second semiconductor wafer. The first routing circuit provides primary fan-out routing for the first and second semiconductor wafers, while the vertical connectors provide electrical contacts for the next level of connection.

Description

Heat dissipation gain type face-to-face semiconductor package with heat sink and manufacturer law

The present invention relates to a face-to-face semiconductor package and a method of fabricating the same, and more particularly to a face-to-face semiconductor package in which two semiconductor devices are surface-contacted by a dual routing circuit, and an external contact is provided in one of the devices. Terminal.

The market trend for multimedia devices is tended to be more rapid and thinner design requirements. One such method is to face-to-face the two wafers so that the shortest routing distance between the two wafers is achieved. Since the stacked wafers can be directly transferred to each other to reduce the delay, the signal integrity of the group can be greatly improved, and additional energy consumption can be saved. Therefore, the face-to-face semiconductor package can exhibit almost all of the advantages of 3D IC stacking, and it is not necessary to form a cost-perfect via in the stacked wafer. A stacked wafer assembly having a face-to-face arrangement is disclosed, for example, in U.S. Patent Application Serial No. 2014/0210107. However, since the bottom wafer is unprotected and the thickness of the bottom wafer must be thinner than the solder balls for external connection, the assembly is not reliable and cannot be practically applied. U.S. Patent Nos. 8,008,121, 8,519,537 and 8,558,395 disclose various types of interposer assembly structures having interposers disposed between wafers disposed face to face. Although it does not need to be in the heap Tantalum vias (TSVs) are formed in the stacked wafers, but the vias used in the interposer to provide electrical routing between the wafers can result in complex processes, low production yields, and high costs. In addition, since the semiconductor wafer is liable to cause performance deterioration at a high operating temperature, if the face-to-face stacked wafer is not properly dissipated, the thermal environment of the element is deteriorated, resulting in an immediate failure in operation.

For the above reasons and other reasons described below, there is an urgent need to develop a new face-to-face semiconductor package to achieve high package density, better signal integrity, and high heat dissipation.

SUMMARY OF THE INVENTION A primary object of the present invention is to provide a face-to-face semiconductor package in which two semiconductor devices are surface-contacted together by a dual routing circuit to improve interconnection efficiency between two semiconductor devices, thereby ensuring excellent performance of the group. Electrical performance.

Another object of the present invention is to provide a face-to-face semiconductor package, wherein the set of systems provides external contact terminals in the device by forming vertical connectors, so that no additional solder balls are required to surround the peripheral edges of the package. The size of the group can be reduced.

A further object of the present invention is to provide a face-to-face semiconductor package that attaches a heat conducting plate to a semiconductor wafer, and the heat conducting plate has a heat sink and a routing circuit disposed on the heat sink The heat generated by the semiconductor wafer can be directly and/or indirectly dissipated by the heat sink, thereby effectively improving the thermal performance of the assembly.

According to the above and other objects, the present invention provides a heat dissipation gain type face-to-face semiconductor package that electrically couples an embedding device to a heat dissipation gain type device, wherein the embedding device includes a first semiconductor wafer and a first route. The circuit, a series of vertical connectors and a sealing material, and the heat dissipation type device comprises a second semiconductor wafer and a heat conducting plate. In a preferred embodiment, the first semiconductor wafer Electrically coupled to the top side of the first routing circuit, surrounded by the vertical connectors, and embedded in the sealing material; the second semiconductor wafer is electrically coupled to the first routing circuit by the first bumps The bottom side is electrically connected to the first semiconductor wafer face-to-face by the first routing circuit; the first routing circuit provides a primary fan-out route to the first semiconductor chip and the second semiconductor wafer and the shortest The interconnecting distance; the heat conducting plate is thermally coupled to the second semiconductor wafer received in the recess of the heat conducting plate to provide a heat dissipation path for the second semiconductor wafer.

In another aspect, the present invention provides a heat dissipation gain type face-to-face semiconductor package provided with a heat sink, comprising: a buried device comprising a first semiconductor wafer, a sealing material, and a series of vertical connections And a first routing circuit, the first routing circuit is disposed on a first surface of the sealing material, wherein (i) the first semiconductor wafer is embedded in the sealing material and electrically coupled to the first routing circuit, and (ii) the vertical connectors are laterally covered by the sealing material and surround the first semiconductor wafer, wherein the vertical connectors are electrically coupled to the first routing circuit and extend to or extend beyond one of the sealing materials And a heat dissipation type device comprising a heat sink, a second routing circuit and a second semiconductor chip, wherein the second routing circuit is disposed on the heat sink, and the second semiconductor wafer is contacted by a thermal contact The device is thermally coupled to the heat sink; wherein the embedding device is stacked on the heat dissipation gain type device, and the second semiconductor chip is electrically coupled to the first routing circuit by a series of first bumps, and the first The routing circuit maintains the distance, and the second routing circuit is electrically coupled to the first routing circuit by a series of second bumps and is kept at a distance from the first routing pad.

In still another aspect, the present invention provides another heat dissipation gain type face-to-face semiconductor package provided with a heat sink, comprising: a buried device comprising a first semiconductor wafer, a sealing material, and a series of vertical a first routing circuit is disposed on the first surface of the sealing material, wherein the (i) the first semiconductor wafer is embedded in the sealing material and electrically coupled to the first routing circuit, And (ii) the vertical connectors are laterally covered by the sealing material and surround the first semiconductor wafer, wherein the vertical connectors are electrically coupled to the first routing circuit and extend to or extend beyond one of the sealing materials a second surface; and a heat dissipation type device comprising a heat sink and a second semiconductor wafer thermally coupled to the heat sink by a heat conducting contact and located in a recess of the heat sink The buried semiconductor device is stacked on the heat dissipation gain type device, and the second semiconductor chip is electrically coupled to the first routing circuit by a series of bumps and is kept at a distance from the first routing circuit.

In another aspect, the present invention provides a method for fabricating a heat dissipation gain type face-to-face semiconductor package provided with a heat sink, comprising the steps of: providing a buried device comprising a first semiconductor wafer, a seal a first routing circuit is disposed on the first surface of the sealing material, wherein the first semiconductor wafer is embedded in the sealing material and electrically coupled to the material, the first routing circuit, and the first routing circuit. a first routing circuit, and (ii) the vertical connectors surround the first semiconductor chip and are electrically coupled to the first routing circuit; and by a series of first bumps located at the first routing circuit, The second semiconductor wafer is electrically coupled to the first routing circuit of the embedding device; a heat conducting plate is provided, which comprises a heat sink; and the embedding device is stacked on the heat conducting plate, and the heat conducting contact is used to make the first The semiconductor wafer is thermally conductive to the heat sink.

Unless specifically described or the words "subsequent" are used between steps, or steps that must occur sequentially, the order of the above steps is not limited to the above, and may be varied or rearranged depending on the desired design.

The face-to-face semiconductor package of the present invention and its method of fabrication have many advantages. For example, electrically coupling the first and second semiconductor wafers face to face to opposite sides of the first routing circuit provides a shortest interconnect distance between the first and second semiconductor wafers. The formation of a vertical connector in the sealing material is particularly advantageous because the vertical connector surrounding the first semiconductor wafer can provide a dense connection. The electrical connection between the opposite sides of the sealing material allows a denser smaller solder ball to be attached to the top side of the sealing material for external connection, avoiding the use of large external solder balls that need to span the height of the embedding device. Furthermore, it is advantageous to insert the second semiconductor wafer into the recess of the heat conducting plate because the heat sink of the heat conducting plate can dissipate heat from the second semiconductor wafer and serve as a support platform for the embedded device to be stacked thereon.

The above and other features and advantages of the present invention will become more apparent from the detailed description of the preferred embodiments.

110, 120, 210, 220, 310, 320, 330, 410, 510, 520, 530, 610‧‧‧ semiconductor group

10‧‧‧ sacrificial carrier

111‧‧‧Support plate

113‧‧‧Barrier layer

20‧‧‧buried device

21‧‧‧First routing circuit

212‧‧‧Route line

213‧‧‧First dielectric layer

214‧‧‧ first blind hole

215‧‧‧First wire

217‧‧‧First metallized blind hole

22‧‧‧First semiconductor wafer

223‧‧‧Bumps

23, 32‧‧‧ Heat sink

24‧‧‧Vertical connectors

242‧‧‧ solder balls

241‧‧‧First solder ball

243‧‧‧second solder ball

244‧‧‧ Conductive blind holes

245‧‧‧Metal column

246‧‧‧ solder balls

25‧‧‧ Sealing material

251‧‧‧ first surface

253‧‧‧ second surface

254, 284‧‧ ‧ openings

256‧‧‧blind hole

26‧‧‧External routing circuit

262‧‧‧External wires

27, 37‧‧‧ Thermal contact parts

28‧‧‧ solder mask

29‧‧‧Electrical components

30‧‧‧heating gain type device

305, 322‧‧ ‧ pocket

31‧‧‧heat conducting plate

32‧‧‧ Heat sink

33‧‧‧Second routing circuit

321‧‧‧Depression

331‧‧‧Second dielectric layer

332‧‧‧ second blind hole

333‧‧‧second wire

334‧‧‧Second metallization blind hole

335‧‧‧ Third dielectric layer

336‧‧‧ third blind hole

337‧‧‧ Third wire

338‧‧‧3rd metallization blind hole

36‧‧‧Second semiconductor wafer

41‧‧‧First bump

43‧‧‧second bump

47‧‧‧ underfill

48‧‧‧Resin

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a routing line formed on a sacrificial carrier in a first embodiment of the present invention, with reference to the accompanying drawings; FIG. 2 is a cross-sectional view showing a first dielectric layer and a first blind via hole in the first embodiment of the present invention; FIG. 3 is a first embodiment of the present invention; FIG. 4 is a cross-sectional view showing the first semiconductor wafer in FIG. 3 in the first embodiment of the present invention; FIG. 5 is a first embodiment of the present invention, wherein the first solder ball is attached to the structure of FIG. Figure 6 is a cross-sectional view showing the sealing material formed on the structure of Figure 5 in the first embodiment of the present invention; Figure 7 is a cross-sectional view showing the opening of the structure of Figure 6 in the first embodiment of the present invention; In a first embodiment of the invention, a cross-sectional view of the sacrificial carrier is removed from the structure of FIG. 7; FIG. 9 is a cross-sectional view of the heat sink according to the first embodiment of the present invention; and FIG. 10 is a view of the first embodiment of the present invention. a cross-sectional view of the second dielectric layer and the second blind via formed on the structure; Figure 11 is a cross-sectional view showing the second lead in the structure of Figure 10 in the first embodiment of the present invention; Figure 12 is a third embodiment of the present invention, wherein the third dielectric layer and the third blind via are formed in the structure of Figure 11 FIG. 13 is a cross-sectional view showing the third conductive line formed on the structure of FIG. 12 in the first embodiment of the present invention; FIG. 14 is a cross-sectional view showing the second semiconductor wafer connected to the structure of FIG. 13 in the first embodiment of the present invention; Figure 15 is a cross-sectional view showing the first and second bumps of the structure of Figure 14 in a first embodiment of the present invention; Figure 16 is a first embodiment of the present invention, and the structure of Figure 8 is stacked on the structure of Figure 15 Figure 17 is a cross-sectional view showing the structure of Figure 8 electrically coupled to the structure of Figure 15 in the first embodiment of the present invention; Figure 18 is a second embodiment of the present invention, and Figure 17 is connected to the second structure. FIG. 19 is a cross-sectional view of a face-to-face semiconductor package in a first embodiment of the present invention; FIG. 20 is a second embodiment of the present invention; FIG. 4 is a cross-sectional view showing the structure of the solder ball; FIG. 21 is a second embodiment of the present invention. Figure 20 is a cross-sectional view showing the structure of the heat sink; Figure 22 is a cross-sectional view of the structure of Figure 21 in the second embodiment of the present invention; Figure 23 is a second embodiment of the present invention, removed from the structure of Figure 22 Figure 24 is a cross-sectional view of the top portion of the sealing material; Figure 24 is a cross-sectional view of the sacrificial carrier plate removed from the structure of Figure 23 in the second embodiment of the present invention; Figure 25 is a cross-sectional view of the structure of Figure 24 in the second embodiment of the present invention. 15 is a cross-sectional view of the semiconductor; FIG. 26 is a cross-sectional view of the second embodiment of the present invention, wherein the structure of FIG. 24 is electrically coupled to the structure of FIG. Figure 27 is a cross-sectional view showing another aspect of the face-to-face semiconductor package in a second embodiment of the present invention; Figure 28 is a cross-sectional view showing the structure of the seal member in the structure of Figure 4 in the third embodiment of the present invention; In the third embodiment of the present invention, a cross-sectional view of the blind hole is formed on the structure of FIG. 28; FIG. 30 is a cross-sectional view showing the conductive blind hole and the external wire formed on the structure of FIG. 29 in the third embodiment of the present invention; In a third embodiment, a cross-sectional view of the solder resist layer is formed on the structure of FIG. 30; FIG. 32 is a cross-sectional view of the sacrificial carrier board removed from the structure of FIG. 31 in the third embodiment of the present invention; FIG. 33 is a third embodiment of the present invention. FIG. 32 is a cross-sectional view showing the second semiconductor wafer in a structure; FIG. 34 is a cross-sectional view showing the structure of FIG. 33 stacked on the structure of FIG. 13 in the third embodiment of the present invention; FIG. 35 is a third embodiment of the present invention. The structure of FIG. 33 is connected to the structure of FIG. 13 to fabricate a cross-sectional view of the face-to-face semiconductor package; FIG. 36 is a cross-sectional view of the face-to-face semiconductor package in the third embodiment of the present invention; In the third embodiment of the present invention, the other side faces half FIG. 38 is a cross-sectional view showing a first routing circuit formed on a sacrificial carrier board in a fourth embodiment of the present invention; FIG. 39 is a fourth embodiment of the present invention, and FIG. 38 is connected to the structure. FIG. 40 is a cross-sectional view showing the structure of the first semiconductor wafer in FIG. 39 in the fourth embodiment of the present invention; FIG. 41 is a view showing the structure of the sealing material in the structure of FIG. 40 in the fourth embodiment of the present invention; Figure 42 is a cross-sectional view showing the top region of the sealing material removed from the structure of Figure 41 in a fourth embodiment of the present invention; 43 is a cross-sectional view showing the external routing circuit and the solder resist layer formed on the structure of FIG. 42 in the fourth embodiment of the present invention; and FIG. 44 is a cross-sectional view showing the sacrificial carrier plate removed from the structure of FIG. 43 in the fourth embodiment of the present invention; 45 is a cross-sectional view showing the second semiconductor wafer in FIG. 44 in a fourth embodiment of the present invention; and FIG. 46 is a cross-sectional view showing the second dielectric layer formed on the heat sink in the fourth embodiment of the present invention; Figure 47 is a cross-sectional view showing the second conductor formed in the structure of Figure 46 in the fourth embodiment of the present invention; Figure 48 is a fourth embodiment of the present invention, wherein the third dielectric layer and the third blind are formed on the structure of Figure 47. Figure 49 is a cross-sectional view showing a third wire in the structure of Figure 48 in the fourth embodiment of the present invention; Figure 50 is a fourth embodiment of the present invention, and Figure 45 is stacked on the structure of Figure 49. FIG. 51 is a cross-sectional view showing the structure of FIG. 45 connected to the structure of FIG. 49 for fabricating the face-to-face semiconductor package; FIG. 52 is a face-to-face view of the fifth embodiment of the present invention; A cross-sectional view of a semiconductor package; Fig. 53 is a fifth embodiment of the present invention FIG. 54 is a cross-sectional view of a further face-to-face semiconductor package in a fifth embodiment of the present invention; and FIG. 55 is a front view of the sixth embodiment of the present invention A cross-sectional view of a semiconductor package.

In the following, an embodiment will be provided to explain in detail embodiments of the invention. The advantages and effects of the present invention will be more apparent by the disclosure of the present invention. The drawings attached hereto are simplified and are used for illustration. Number, shape and size of components shown in the drawing Modifications can be made based on actual conditions, and the configuration of components can be more complicated. Other variations and modifications can be made without departing from the spirit and scope of the invention as defined in the invention.

[Example 1]

1-18 are diagrams showing a method of fabricating a face-to-face semiconductor package according to a first embodiment of the present invention, including a first routing circuit 21, a first semiconductor wafer 22, a series of vertical connectors 24, and a The sealing material 25 and a heat conducting plate 31 and a second semiconductor wafer 36.

1 is a cross-sectional view of the routing line 212 formed on the sacrificial carrier 10, wherein the routing lines 212 are formed by metal deposition and metal patterning processes. In this figure, the sacrificial carrier 10 has a single layer structure. The sacrificial carrier 10 is typically made of copper, aluminum, iron, nickel, tin, stainless steel, tantalum or other metal or alloy, but may be made of any other electrically conductive or non-conductive material. In this embodiment, the sacrificial carrier 10 is made of a ferrous material. The routing lines 212 are typically made of copper and may be patterned by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or combinations thereof, or formed by thin film deposition followed by a metal patterning step. In the case of a sacrificial carrier 10 having electrical conductivity, it is typically deposited by metal plating to form routing lines 212. Metal patterning techniques include wet etching, electrochemical etching, laser assisted etching, and combinations thereof, and an etch mask (not shown) is used to define routing lines 212.

2 is a cross-sectional view of the first dielectric layer 213 and the first blind via 214, wherein the first dielectric layer 213 is on the sacrificial carrier 10 and the routing line 212, and the first blind via 214 is in the first dielectric layer 213. in. The first dielectric layer 213 can be deposited by lamination or coating, and contacts the sacrificial carrier 10 and the routing line 212, and the first dielectric layer 213 is covered by the upper side and extends laterally to the sacrificial carrier. 10 and routing line 212. The first dielectric layer 213 typically has a thickness of 50 microns and may be made of epoxy, glass epoxy, polyimine, or the like. After depositing the first dielectric layer 213, the first blind vias 214 may be formed by various techniques, such as laser drilling, plasma etching, and Photographic technology, and usually has a diameter of 50 microns. Pulsed lasers can be used to improve laser drilling performance. Alternatively, a scanning laser beam can be used with a metal reticle. The first blind via 214 extends through the first dielectric layer 213 and is aligned with selected portions of the routing line 212.

Referring to FIG. 3, a first conductive line 215 is formed on the first dielectric layer 213 by a metal deposition and metal patterning process. The first wire 215 extends upward from the routing line 212 and fills the first blind hole 214 to form a first metallization blind hole 217 that directly contacts the routing line 212 while extending laterally over the first dielectric layer 213. Thus, the first wire 215 can provide horizontal signal routing in the X and Y directions and a vertical route through the first blind hole 214 to serve as an electrical connection for the routing line 212.

The first wire 215 can be deposited as a single layer or multiple layers by various techniques such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof. For example, first, by immersing the structure in an activator solution, the first dielectric layer 213 is reacted with electroless copper to generate a catalyst, and then a thin copper layer is coated as a seed layer by electroless plating, and then electroplated. A second copper layer of a desired thickness is formed on the seed layer. Alternatively, the seed layer may be formed by a sputtering method such as a titanium/copper seed layer film before the electroplated copper layer is deposited on the seed layer. Once the desired thickness is achieved, the coating can be patterned using various techniques to form a first wire 215 that includes wet etching, electrochemical etching, laser assisted etching, and combinations thereof, and using an etch mask (not shown) ) to define the first wire 215.

This stage has been completed by the process of forming the first routing circuit 21 on the sacrificial carrier 10. In the figure, the first routing circuit 21 is a multi-layer build-up circuit including a routing line 212, a first dielectric layer 213, and a first conductive line 215.

4 is a cross-sectional view of the first semiconductor wafer 22 electrically coupled to the first routing circuit 21. The first semiconductor wafer 22 (shown as a bare wafer) can be electrically coupled to the first wire 215 of the first routing circuit 21 via the bump 223 by hot pressing, reflow, or thermal ultrasonic bonding, wherein the bump Block 223 contacts first semiconductor wafer 22 and first routing circuit 21.

FIG. 5 is a cross-sectional view showing the first solder ball 241 attached to the first routing circuit 21. The first solder ball 241 is electrically connected to the first wire 215 of the first routing circuit 21 and is in contact with the first wire 215.

6 is a cross-sectional view showing the formation of the sealing material 25 on the first routing circuit 21, the first semiconductor wafer 22, and the first solder ball 241, wherein the sealing material 25 can be coated by, for example, resin-glass, resin-glass coating, or Formed by a molding method. The sealing material 25 covers the first routing circuit 21, the first semiconductor wafer 22 and the first solder ball 241 from above, and surrounds and covers the sidewalls of the first semiconductor wafer 22 and the first solder ball 241.

FIG. 7 is a cross-sectional view showing the opening 254 in the sealing member 25. The openings 254 are aligned with the first solder balls 241 to expose selected portions of the first solder balls 241 from above.

FIG. 8 is a cross-sectional view of the sacrificial carrier 10 removed. The sacrificial carrier 10 can be removed by various means to expose the first routing circuit 21 from below, including wet etching and electrochemistry using an acidic solution (such as ferric chloride or copper sulfate solution) or an alkaline solution (such as an ammonia solution). Chemical etching is performed after etching or mechanical means such as drilling or end milling. In this embodiment, the sacrificial carrier 10 made of a ferrous material can be removed by a chemical etching solution, wherein the chemical etching solution is selective between copper and iron to avoid removal of the sacrificial carrier 10. The copper routing line 212 is etched. Accordingly, the first routing circuit 21 adjacent to the first surface 251 of the sealing material 25 and the first solder ball 241 exposed from the second surface 253 of the self-sealing material 25 can provide electrical contacts for the next stage of connection.

9 is a cross-sectional view of the heat sink 32. The heat sink 32 can be made of any material having a high thermal conductivity, such as copper, aluminum, stainless steel, tantalum, ceramic, graphite or other metal or alloy material, and is formed with a recess 321 . The heat sink 32 can have a thickness ranging from 0.5 to 2.0 mm. In this embodiment, the heat sink 32 has a thickness of 1.0 mm.

10 is a cross-sectional view of the second dielectric layer 331 and the second blind via 332, wherein the second dielectric layer 331 is laminated/coated on the selected portion outside the recess 321 of the heat sink 32, and the second blind The hole 332 is in the second dielectric layer 331. The second dielectric layer 331 is in contact with the heat sink 32 and may be made of epoxy resin, glass epoxy, polyimide, or the like, and typically has a thickness of 50 microns. The second blind via 332 extends through the second dielectric layer 331 to expose selected portions of the heat sink 32 from above. As described for the first blind via 214, the second blind via 332 can also be formed by a variety of techniques, such as laser drilling, plasma etching, and lithography, and typically has a diameter of 50 microns.

Referring to FIG. 11, a second wire 333 is formed on the second dielectric layer 331 by a metal deposition and metal patterning process. The second wire 333 extends upward from the heat sink 32 and fills the second blind hole 332 to form a second metallization blind hole 334 that directly contacts the heat sink 32 while extending laterally on the second dielectric layer 331. .

12 is a cross-sectional view of the third dielectric layer 335 and the third via 336, wherein the third dielectric layer 335 is laminated/coated on the second dielectric layer 331 and the second conductive line 333, and The three blind vias 336 are in the third dielectric layer 335. The third dielectric layer 335 contacts the second dielectric layer 331 and the second conductive line 333. The third dielectric layer 335 can be made of epoxy resin, glass epoxy, polyimide, or the like, and typically has a thickness of 50 microns. The third blind via 336 extends through the third dielectric layer 335 to expose selected portions of the second lead 333 from above. As described for the first blind via 214 and the second blind via 332, the third blind via 336 can also be formed by various techniques, such as laser drilling, plasma etching, and lithography, and typically has a diameter of 50 microns. .

13 is a cross-sectional view showing the formation of a third wire 337 on the third dielectric layer 335, wherein the third wire 337 is formed by a metal deposition and metal patterning process. The third wire 337 extends upward from the second wire 333 and fills the third blind hole 336 to form a third metallization blind hole 338 that directly contacts the second wire 333 while extending laterally to the third dielectric layer 335. on.

At this stage, the fabrication of the heat conducting plate 31 is completed, which has a recess 305 and includes a heat sink 32 and a second routing circuit 33. In the figure, the second routing circuit 33 is a multi-layer build-up circuit comprising a second dielectric layer 331, a second conductive line 333, a third dielectric layer 335 and a third conductive line 337, and by a second The metallized blind hole 334 is electrically coupled to the heat sink 32 to serve as a ground connection. The pocket 305 extends through the second routing circuit 33 to expose a selected portion of the heat sink 32 from above.

FIG. 14 is a cross-sectional view of the second semiconductor wafer 36 attached to the heat conducting plate 31. The second semiconductor wafer 36 (shown as a bare wafer) is inserted into the recess 305 of the heat conducting plate 31 in a face-up manner, and the heat sink 32 of the second semiconductor wafer 36 and the heat conducting plate 31 is made by the heat conducting contact 37. Thermal conduction. Here, the heat conductive contact 37 may be made of an organic resin or solder mixed with metal particles. At this stage, the fabrication of the heat dissipation type device 30 is completed, which includes a heat sink 32, a second routing circuit 33, and a second semiconductor wafer 36.

FIG. 15 is a cross-sectional view showing the first bump 41 and the second bump 43 attached to the heat dissipation gain type device 30. The first bump 41 and the second bump 43 are respectively in contact with and electrically coupled to the second semiconductor wafer 36 and the second routing circuit 33 of the heat conducting plate 31.

Figure 16 is a cross-sectional view showing the structure of Figure 8 stacked on the heat dissipation type device 30 of Figure 15. In this figure, the first semiconductor wafer 22 is disposed face down, and the second semiconductor wafer 36 is disposed to face upward.

17 is a cross-sectional view of the second semiconductor wafer 36 and the second routing circuit 33 electrically coupled to the first routing circuit 21. The first bump 41 and the second bump 43 are in contact with and electrically coupled to the routing line 212 of the first routing circuit 21 to provide a first routing circuit 21 and a second semiconductor chip 36 and a first routing circuit 21 and The electrical connection between the two routing circuits 33.

FIG. 18 is a cross-sectional view showing the second solder ball 243 attached to the first solder ball 241. The second solder ball 243 fills the opening 254 of the sealing material 25 and is in contact with the first solder ball 241. Accordingly, the first solder ball 241 and the first The second solder balls 243 can collectively function as a vertical connector 24 that extends upwardly from the first routing circuit 21 to the second surface 253 of the over-sealing material 25.

Accordingly, as shown in FIG. 17, the completed face-to-face semiconductor package 110 includes a buried device 20 and a heat dissipation gain type device 30. The embedding device 20 is electrically coupled and stacked on the heat dissipation gain type device 30 by a series of first bumps 41 and a series of second bumps 43. In the figure, the embedding device 20 includes a first routing circuit 21, a first semiconductor wafer 22, a series of vertical connectors 24, and a sealing material 25. The heat dissipation gain device 30 includes a heat sink 32. A second routing circuit 33 and a second semiconductor wafer 36.

The first semiconductor wafer 22 is electrically coupled to the first routing circuit 21 in a flip chip manner and embedded in the sealing material 25 . The vertical connector 24 surrounds the first semiconductor wafer 22 and is electrically coupled to the first routing circuit 21 and is laterally covered by the sealing material 25. The second semiconductor wafer 36 is electrically connected to the heat sink 32, and is electrically coupled to the first routing circuit 21 by the first bump 41, and the second semiconductor wafer 36 and the first routing circuit 21 are The first bumps 41 are spaced apart. Accordingly, the first routing circuit 21 can provide a primary fanout route and a shortest interconnect distance between the first semiconductor wafer 22 and the second semiconductor wafer 36. The second routing circuit 33 is disposed on the heat sink 32 and is grounded to the heat sink 32 while being electrically coupled to the first routing circuit 21 by the second bumps 43 and the second routing circuit 33 and the first routing circuit 21 The second bumps 43 are spaced apart.

19 is a cross-sectional view of another face-to-face semiconductor package 120 in which no second routing circuit is disposed between the first routing circuit 21 and the heat sink 32. The face-to-face semiconductor package 120 is similar in structure to that shown in FIG. 18 except that the second routing circuit is not disposed on the heat sink 32 of the heat dissipation gain type device 30. In this embodiment, the second semiconductor wafer 36 is disposed in the recess 322 of the heat sink 32, and the second bump 43 is selectively brought into contact with the first routing circuit 21 and the heat sink 32 to electrically couple the heat sink 32. Connected to the first The routing circuit 21 is configured to form a ground connection.

[Embodiment 2]

20-26 are views showing a method of fabricating a face-to-face semiconductor package in which another heat sink is attached to a first semiconductor wafer in a second embodiment of the present invention.

For the purpose of brief description, any description of the same application in the above-described embodiment 1 is hereby made, and the same description is not repeated.

Figure 20 is a cross-sectional view showing the solder ball 242 attached to the first routing circuit 21 of Figure 4 . The solder balls 242 are disposed on edge regions of the outer surface of the first routing circuit 21 and are in contact with the first wires 215 to serve as vertical connectors 24 surrounding the first semiconductor wafer 22.

21 is a cross-sectional view of the heat sink 23 attached to the first semiconductor wafer 22. The heat sink 23 can be made of any material having a high thermal conductivity such as metal, alloy, tantalum, ceramic or graphite. The heat sink 23 is attached to the inactive surface of the first semiconductor wafer 22 by the heat conducting contact 27.

22 is a cross-sectional view showing the formation of the sealing member 25 on the first routing circuit 21, the vertical connecting member 24, and the heat sink 23. The sealing material 25 covers the first routing circuit 21, the vertical connecting member 24 and the heat sink 23 from above, and is wrapped around the same shape and covers the sidewalls of the first semiconductor wafer 22, the vertical connecting member 24 and the heat sink 23.

Figure 23 is a cross-sectional view showing the top region of the sealing material 25 removed to reveal the vertical connector 24 and the heat sink 23 from above. In this figure, the first surface 251 of the sealing material 25 is adjacent to the first routing circuit 21, and the second surface 253 thereof is substantially coplanar with the exposed surfaces of the vertical connecting member 24 and the heat sink 23.

Figure 24 is a cross-sectional view showing the sacrificial carrier 10 removed to reveal the first routing circuit 21 from below. Accordingly, the fabrication of the embedding device 20 has been completed, which includes a first routing circuit 21, a first semiconductor wafer 22, a series of vertical connectors 24, a sealing material 25, and a heat sink 23.

25 is a cross-sectional view of the embedding device 20 of FIG. 24 stacked on the heat dissipation gain type device 30 of FIG. In this figure, the first semiconductor wafer 22 is disposed face down, and the second semiconductor wafer 36 is disposed to face upward.

26 is a cross-sectional view of the embedding device 20 electrically coupled to the heat dissipation gain type device 30. The second semiconductor chip 36 and the second routing circuit 33 of the heat dissipation type device 30 are electrically coupled to the first routing circuit 21 of the embedding device 20 by the first bump 41 and the second bump 43 respectively.

Accordingly, as shown in FIG. 26, the completed face-to-face semiconductor package 210 includes a buried device 20 and a heat dissipation gain type device 30. In the figure, the embedding device 20 includes a first routing circuit 21, a first semiconductor wafer 22, a series of vertical connectors 24, a sealing material 25 and a heat sink 23, and the heat dissipation gain type device 30 includes A heat sink 32, a second routing circuit 33 and a second semiconductor wafer 36.

The first semiconductor wafer 22 is embedded in the sealing material 25, and the second semiconductor wafer 36 is received in the recess 305 of the heat conducting plate 31. The first semiconductor wafer 22 and the second semiconductor wafer 36 are electrically coupled to each other in a surface-to-surface manner by the first routing circuit 21 therebetween, and are electrically connected to the heat sinks 23 and 32, respectively. The vertical connector 24 extends from the first routing circuit 21 to the second surface 253 of the sealing material 25 and surrounds the first semiconductor wafer 22 to provide an electrical contact for the next level of connection by the second surface 253 of the sealing material 25. The second routing circuit 33 laterally surrounds the second semiconductor wafer 36 and is electrically coupled to the heat sink 32 and the first routing circuit 21 to form a ground connection.

27 is a cross-sectional view of another face-to-face semiconductor package 220 in which no second routing circuit is provided between the first routing circuit 21 and the heat sink 32. The face-to-face semiconductor package 220 is similar in structure to that shown in FIG. 26 except that the second routing circuit is not disposed on the heat sink 32 of the heat conducting plate 31. In this embodiment, the second semiconductor wafer 36 is disposed in the recess 322 of the heat sink 32, and the second bump 43 is selectively brought into contact with the first routing circuit 21 and the heat sink 32 to electrically couple the heat sink 32. Connected to the first routing circuit 21 to form a ground connection.

[Example 3]

28-35 are diagrams showing a method of fabricating a face-to-face semiconductor package having an external routing circuit in a third embodiment of the present invention.

For the purpose of brevity, the description of any of the above embodiments that can be used for the same application is the same, and the same description is not repeated.

Figure 28 is a cross-sectional view showing the formation of the sealing material 25 on the first routing circuit 21 and the first semiconductor wafer 22 of Figure 4 . The sealing material 25 covers the first routing circuit 21 and the first semiconductor wafer 22 from above, and is wrapped around the same shape and covers the sidewall of the first semiconductor wafer 22.

29 is a cross-sectional view showing the formation of the blind hole 256 in the sealing material 25. The blind holes 256 are aligned with the selected portions of the first wires 215 of the first routing circuit 21 and extend through the sealing material 25 between the first surface 251 and the second surface 253 of the sealing material 25.

30 is a cross-sectional view showing the formation of conductive vias 244 in blind vias 256 and forming external leads 262 on sealing material 25. The conductive vias 244 may be formed by a metal deposition process in the blind vias 256 that is in contact with the first leads 215 of the first routing circuit 21 as a vertical connector 24 surrounding the first semiconductor wafer 22. The external wires 262 are formed on the second surface 253 of the sealing material 25 by a metal deposition and metal patterning process, and are electrically coupled to the conductive vias 244.

This stage has been completed to form the outer routing circuit 26 on the second surface 253 of the sealing material 25. In the figure, the external routing circuit 26 includes an outer lead 262 that extends laterally over the second surface 253 of the sealing material 25 and that is in contact with and electrically coupled to the vertical connector 24 in the sealing material 25.

31 is a cross-sectional view showing the formation of the solder resist layer 28, which is formed on the sealing material 25 and the external routing circuit 26, and filled in the remaining space of the blind via 256. The solder resist layer 28 is composed of The sealing material 25 and the external routing circuit 26 are covered above and fill the remaining space of the blind holes 256. Additionally, the solder mask 28 has an opening 284 to expose selected portions of the outer lead 262 from above.

32 is a cross-sectional view showing the sacrificial carrier 10 removed to reveal the first routing circuit 21 from below. Accordingly, the fabrication of the embedding device 20 has been completed, which includes a first routing circuit 21, a first semiconductor wafer 22, a series of vertical connectors 24, a sealing material 25, an external routing circuit 26, and a solder mask. 28.

33 is a cross-sectional view of the second semiconductor wafer 36 electrically coupled to the first routing circuit 21. The second semiconductor wafer 36 is flip-chip connected to the first routing circuit 21 by a series of first bumps 41, wherein the first bumps 41 are in contact with the routing line 212 of the first routing circuit 21. The underfill 47 may be optionally filled in the gap between the first routing circuit 21 and the second semiconductor wafer 36.

Figure 34 is a cross-sectional view showing the structure of Figure 33 superposed on the heat conducting plate 31 of Figure 13. Before the stacking step, the heat conducting contact 37 is applied to the recess 305 of the heat conducting plate 31, and a series of second bumps 43 are attached to the second routing circuit 33 of the heat conducting plate 31.

35 is a cross-sectional view of the thermally conductive plate 31 attached to the second semiconductor wafer 36 and electrically coupled to the first routing circuit 21. The second semiconductor wafer 36 is inserted into the recess 305 of the heat conducting plate 31, and the second semiconductor wafer 36 is thermally connected to the heat sink 32 of the heat conducting plate 31 by the heat conducting contact 37. At the same time, the second routing circuit 33 of the heat conducting board 31 is electrically coupled to the first routing circuit 21 by the second bumps 43. Optionally, a gap 48 between the first routing circuit 21 and the second routing circuit 33 and between the first routing circuit 21 and the second semiconductor wafer 36 is filled, and the resin 48 also fills the second semiconductor in the recess 305. The gap between the wafer 36 and the sidewall of the recess 305.

Accordingly, as shown in FIG. 35, the completed face-to-face semiconductor package 310 includes a buried device 20 and a heat dissipation gain type device 30. In the figure, the embedding device 20 includes a first routing circuit 21, a first semiconductor wafer 22, a series of vertical connectors 24, a sealing material 25, and an external route. The circuit 26 and a solder resist layer 28 include a heat sink 32, a second routing circuit 33 and a second semiconductor wafer 36.

The first semiconductor wafer 22 and the second semiconductor wafer 36 are disposed on opposite sides of the first routing circuit 21, and are electrically coupled to each other in a face-to-face manner by the first routing circuit 21 therebetween. The first semiconductor wafer 22 is embedded in the sealing material 25 and surrounded by the vertical connecting member 24, and the second semiconductor wafer 36 is received in the recess 305 of the heat conducting plate 31 and thermally conductive with the heat sink 32. The second routing circuit 33 of the heat conducting board 31 is electrically coupled to the heat sink 32 and the first routing circuit 21 to form a ground connection. The first routing circuit 21 is electrically coupled to the external routing circuit 26 by a vertical connector 24 in the sealing material 25.

36 is a cross-sectional view of another face-to-face semiconductor package 320 in which no second routing circuit is provided between the first routing circuit 21 and the heat sink 32. The face-to-face semiconductor package 320 is similar in structure to that shown in FIG. 35 except that the second routing circuit is not disposed on the heat sink 32 of the heat conducting plate 31. In this embodiment, the second semiconductor wafer 36 is disposed in the recess 322 of the heat sink 32, and the second bump 43 is selectively brought into contact with the first routing circuit 21 and the heat sink 32 to electrically couple the heat sink 32. Connected to the first routing circuit 21 to form a ground connection.

37 is a cross-sectional view of another face-to-face semiconductor package 330 in which an electrical component 29 is embedded in a sealing material 25. In this aspect, the face-to-face semiconductor package 330 is fabricated in a manner similar to the face-to-face semiconductor package 310, except that the embedding device 20 further includes an electrical component 29, such as a passive component or decoupling. A decoupling capacitor electrically coupled to the first routing circuit 21 and embedded by the sealing material 25.

[Example 4]

38-51 are diagrams showing a method of fabricating a face-to-face semiconductor package having a metal post as a vertical connector in a fourth embodiment of the present invention.

For the purpose of brevity, the description of any of the above embodiments that can be used for the same application is the same, and the same description is not repeated.

38 is a cross-sectional view of the first routing circuit 21 detachably attached to the sacrificial carrier 10. In the figure, the sacrificial carrier 10 is a two-layer structure comprising a support plate 111 and a barrier layer 113 deposited on the support plate 111. The first routing circuit 21 is formed on the barrier layer 113 by the steps shown in FIGS. 1-3. The barrier layer 113 may have a thickness of 0.001 to 0.1 mm, and may be a metal layer, wherein the metal layer may resist chemical etching when chemically removing the support plate 111, and may remove the metal without affecting the routing line 212. Floor. For example, when the support plate 111 and the routing line 212 are made of copper, the barrier layer 113 may be made of tin or nickel. Further, in addition to the metal material, the barrier layer 113 may be a dielectric layer such as a peelable laminate film. In this embodiment, the support plate 111 is a copper plate, and the barrier layer 113 is a nickel layer having a thickness of 5 micrometers.

39 is a cross-sectional view of a series of metal posts 245 deposited on the first routing circuit 21. The metal posts 245 are located in the edge regions of the outer surface of the first routing circuit 21 and are in contact with the first wires 215 to serve as the vertical connectors 24.

40 is a cross-sectional view of the first semiconductor wafer 22 electrically coupled to the first routing circuit 21 from above. Here, the first semiconductor wafer 22 is electrically coupled to the first routing circuit 21 by the bumps 223 and surrounded by the vertical connecting members 24.

41 is a cross-sectional view showing the formation of the sealing material 25 on the first routing circuit 21, the first semiconductor wafer 22, and the vertical connector 24. The sealing material 25 covers the first routing circuit 21, the first semiconductor wafer 22 and the vertical connecting member 24 from above, and is wrapped around the same shape and covers the sidewalls of the first semiconductor wafer 22 and the vertical connecting member 24.

Figure 42 is a cross-sectional view showing the top region of the sealing material 25 removed to reveal the vertical connector 24 from above. In this figure, the first surface 251 of the sealing material 25 is adjacent to the first routing circuit 21 and its second surface 253 is substantially coplanar with the exposed surface of the vertical connector 24.

43 is a cross-sectional view showing the formation of the outer lead 262 on the sealing member 25 and forming the solder resist layer 28 on the sealing member 25 and the outer lead 262. The outer leads 262 extend laterally on the second surface 253 of the sealing material 25 and contact the vertical connectors 24. This stage has been completed to form the outer routing circuit 26 on the second surface 253 of the sealing material 25. In addition, the solder resist layer 28 covers the sealing material 25 and the external routing circuit 26 from above and has an opening 284 to expose selected portions of the outer conductor 262 from above.

44 is a cross-sectional view of the sacrificial carrier 10 removed. Here, the support plate 111 made of copper can be removed by an alkaline etching solution, and then the barrier layer 113 made of nickel can be removed by an acidic etching solution to expose the first routing circuit from below. twenty one. In another aspect in which the barrier layer 113 is a peelable laminate film, the barrier layer 113 can be removed by mechanical peeling or plasma ashing. Accordingly, the fabrication of the embedding device 20 has been completed, which includes a first routing circuit 21, a first semiconductor wafer 22, a series of vertical connectors 24, a sealing material 25, an external routing circuit 26, and a solder mask. 28.

45 is a cross-sectional view of the second semiconductor wafer 36 electrically coupled to the first routing circuit 21. The second semiconductor wafer 36 is flip-chip connected to the first routing circuit 21 by a series of first bumps 41, wherein the first bumps 41 are in contact with the routing line 212 of the first routing circuit 21.

46 is a cross-sectional view of the second dielectric layer 331 and the second blind via 332, wherein the second dielectric layer 331 is laminated/coated on the heat sink 32, and the second blind via 332 is in the second dielectric layer In the electrical layer 331. The second dielectric layer 331 contacts the heat sink 32 and covers a selected portion of the heat sink 32 from above. The second blind via 332 extends through the second dielectric layer 331 to expose selected portions of the heat sink 32 from above.

47 is a cross-sectional view showing the second conductive line 333 formed on the second dielectric layer 331 by a metal deposition and metal patterning process. The second wire 333 extends upward from the heat sink 32 and fills the second blind hole 332, to form a second metallization blind via 334 that directly contacts the heat sink 32 while laterally extending over the second dielectric layer 331.

48 is a cross-sectional view of the third dielectric layer 335 and the third via 336, wherein the third dielectric layer 335 is laminated/coated on the second dielectric layer 331 / the second conductive line 333, and The three blind vias 336 are in the third dielectric layer 335. The third dielectric layer 335 contacts the second dielectric layer 331 / the second wire 333 and covers the second dielectric layer 331 / the second wire 333 from above. The third blind via 336 extends through the third dielectric layer 335 to expose selected portions of the second lead 333 from above.

49 is a cross-sectional view showing the formation of a third wire 337 on the third dielectric layer 335, wherein the third wire 337 is formed by a metal deposition and metal patterning process. The third wire 337 extends upward from the second wire 333 and fills the third blind hole 336 to form a third metallization blind hole 338 that directly contacts the second wire 333 while extending laterally to the third dielectric layer 335. on.

At this stage, the fabrication of the heat conducting plate 31 is completed, which has a recess 305 and includes a heat sink 32 and a second routing circuit 33. The pocket 305 extends through the second routing circuit 33 and a selected portion of the heat sink 32 emerges from the recess 305 from above. In the figure, the second routing circuit 33 includes a second dielectric layer 331, a second conductive line 333, a third dielectric layer 335, and a third conductive line 337.

Figure 50 is a cross-sectional view showing the structure of Figure 45 superimposed on the heat conducting plate 31 of Figure 49. Before the stacking step, the heat conducting contact 37 is applied to the recess 305 of the heat conducting plate 31, and a series of second bumps 43 are attached to the second routing circuit 33 of the heat conducting plate 31.

51 is a cross-sectional view showing the embedding device 20 and the second semiconductor wafer 36 attached to the heat conducting plate 31. The second semiconductor wafer 36 is inserted into the recess 305 of the heat conducting plate 31, and the second semiconductor wafer 36 is thermally connected to the heat sink 32 of the heat conducting plate 31 by the heat conducting contact 37. At the same time, the second routing circuit 33 of the heat conducting board 31 is electrically coupled to the first routing circuit 21 by the second bumps 43.

Accordingly, as shown in FIG. 51, the completed face-to-face semiconductor package 410 includes a The buried device 20 and a heat dissipation type device 30 are provided. In the figure, the embedding device 20 includes a first routing circuit 21, a first semiconductor wafer 22, a series of vertical connectors 24, a sealing material 25, an external routing circuit 26, and a solder mask 28. The heat dissipation gain type device 30 includes a heat sink 32, a second routing circuit 33, and a second semiconductor wafer 36.

The first routing circuit 21 provides the shortest interconnection distance between the first semiconductor wafer 22 and the second semiconductor wafer 36. The vertical connectors 24 embedded in the sealing material 25 provide electrical connection between the first routing circuit 21 and the external routing circuit 26 at opposite sides of the sealing material 25. The heat sink 32 provides a heat dissipation path for the second semiconductor wafer 36. The second routing circuit 33 is electrically coupled to the heat sink 32 and the first routing circuit 21 to form a ground connection.

[Example 5]

52-54 are cross-sectional views showing other face-to-face semiconductor packages in accordance with a fifth embodiment of the present invention.

In the present embodiment, the face-to-face semiconductor packages 510, 520, 530 are prepared in a manner similar to that described in Embodiment 3, except that the vertical connectors 24 are formed in different manners.

In the face-to-face semiconductor package 510 shown in FIG. 52, the vertical connector 24 includes a combination of conductive vias 244 and metal posts 245. The metal posts 245 contact the first wire 215 and the conductive blind holes 244 extend from the metal post 245 to the outer wire 262.

In the face-to-face semiconductor package 520 shown in FIG. 53, the vertical connector 24 includes a combination of conductive vias 244 and solder balls 246. The conductive blind vias 244 extend from the first routing circuit 21 to the external leads 262, and the solder balls 246 contact the conductive vias 244 and fill the remaining space of the blind vias 256 of the sealing material 25, while the solder balls 246 extend further upwardly beyond the outer The outer surface of the routing circuit 26.

In the face-to-face semiconductor package 530 shown in FIG. 54, the vertical connector 24 includes a conductive via 244, a combination of a metal post 245 and a solder ball 246. The metal posts 245 contact the first wires 215. Conductive blind via 244 extends from metal post 245 to outer lead 262. The solder balls 246 contact the conductive blind vias 244 and fill the remaining space of the blind vias 256 of the encapsulant 25 while the solder balls 246 extend further upward beyond the outer surface of the external routing circuitry 26.

[Embodiment 6]

Figure 55 is a cross-sectional view showing another face-to-face semiconductor package in accordance with a sixth embodiment of the present invention.

In the present embodiment, the face-to-face semiconductor package 610 is prepared in a manner similar to that described in Embodiment 3, except that the sealing material 25 of the embedding device 20 does not include the external routing circuit 26. And the vertical connectors 24 are formed into different aspects.

The embedding device 20 is made by depositing solder balls 246 in the blind holes 256 of the sealing material 25 of FIG. 29 and subsequently removing the sacrificial carrier 10. Accordingly, the solder balls 246 contact the first routing circuit 21 and fill the blind holes 256 of the sealing material 25 as the vertical connectors 24.

The above semiconductor package is merely illustrative, and the present invention can be implemented by other various embodiments. In addition, the above embodiments may be used in combination with each other or in combination with other embodiments based on design and reliability considerations. The embedding device can include a plurality of first semiconductor wafers and can be electrically coupled to the plurality of second semiconductor wafers, and the second semiconductor wafer can use a recess alone or share a recess with the other second semiconductor wafers. For example, a recess can accommodate a single second semiconductor wafer, and the thermally conductive plate can include a plurality of recesses arranged in an array to accommodate a plurality of second semiconductor wafers. Alternatively, a plurality of second semiconductor wafers can be placed in a single recess. In addition, the embedding device can use a heat conducting plate by itself or share a heat conducting plate with other embedding devices. For example, a single buried device can be stacked on a heat conducting plate. Alternatively, a plurality of embedding devices are stacked on a heat conducting plate. For example, four buried devices arranged in a 2x2 array may be stacked on a heat conducting plate, and the selective second routing circuit of the heat conducting plate may include an additional conductive Line to connect additional embedding devices. Similarly, the heat conducting plate can be placed in a buried device alone or in conjunction with other heat conducting plates.

As shown in the above embodiment, the present invention constructs a unique face-to-face semiconductor package comprising a first semiconductor wafer, a first routing circuit, a sealing material, a series of vertical connectors, and a second semiconductor wafer. , a thermal pad, and an optional external routing circuit. The first semiconductor wafer is embedded in the sealing material, and the second semiconductor wafer is disposed in the recess of the heat conducting plate instead of being embedded in the sealing material. In the face-to-face semiconductor package of the present invention, a space between the first routing circuit and the second semiconductor wafer and between the first routing circuit and the heat conducting plate may be filled with a resin, and the resin may fill the cavity of the heat conducting plate. A gap between the second semiconductor wafer and the sidewall of the recess. For convenience of the following description, the direction in which the first surface of the sealing material faces is defined as the first direction, and the direction in which the second surface of the sealing material faces is defined as the second direction.

The active surfaces of the first and second semiconductor wafers face the first routing circuit and are electrically connected to each other in a face-to-face manner by a first routing circuit therebetween. The first and second semiconductor wafers can be wafers that are packaged or unpackaged. For example, the first and second semiconductor wafers can be bare wafers, or wafer level packaged dies, and the like. Alternatively, the first and second semiconductor wafers can be stacked wafers. In a preferred embodiment, the embedding device for electrically coupling the first semiconductor wafer to the first routing circuit can be formed by electrically coupling the first semiconductor wafer to the first routing circuit. The first routing circuit is detachably mounted on a sacrificial carrier; a sealing material and a vertical connector are provided on the first routing circuit; and the sacrificial carrier is removed from the first routing circuit. Here, the first semiconductor wafer can be electrically coupled to the first routing circuit by bumps by a conventional flip chip bonding process (such as hot pressing or reflow soldering, etc.), and no metallized blind via contacts the first Semiconductor wafer. Similarly, after the sacrificial carrier is removed, the second semiconductor wafer can also be electrically coupled to the first routing circuit by the bump, and the metallized blind via contacts the second semiconductor by using a conventional flip chip bonding process. Wafer. In addition, a heat sink can be provided before the sealing material is provided. Attached to the inactive surface of the first semiconductor wafer. Accordingly, the heat generated by the first semiconductor wafer can be dissipated by the heat sink.

The first routing circuit can provide a shortest interconnect distance between the first and second semiconductor wafers, and is preferably a build-up circuit without a core layer. Specifically, the first routing circuit can be a multi-layer routing circuit detachably connected to the sacrificial carrier board, including a routing line, a dielectric layer and a wire, wherein the routing line is located on the sacrificial carrier board, and the dielectric is The layer is located on the routing line and the sacrificial carrier, and the wire extends from a selected portion of the routing line and fills the blind hole of the dielectric layer to form a metallized blind hole while extending laterally on the dielectric layer. Accordingly, after the sacrificial carrier is removed, the routing line and the dielectric layer have an exposed surface facing the first aspect, and the exposed surfaces are substantially coplanar with each other. If more signal routing is required, the first routing circuit can further include additional dielectric layers, additional blind vias, and additional traces. In the present invention, the first routing circuit can be formed directly on the sacrificial carrier board, or the first routing circuit can be separately formed, and then the first routing circuit can be detachably attached to the sacrificial carrier board to complete the sacrificial load. The step of forming a first routing circuit on the board.

After the sealing material is formed, the sacrificial carrier that provides a strong supporting force to the embedding device can be removed from the first routing circuit by chemical etching or mechanical peeling. The sacrificial carrier can be made of any conductive or non-conductive material such as copper, nickel, chromium, tin, iron, stainless steel, tantalum, glass, graphite, plastic film, or other metallic or non-metallic materials. In the aspect of removing the sacrificial carrier by chemical etching, the sacrificial carrier is typically made of a chemically removable material. To avoid etching the sacrificial carrier to the routing line that contacts the sacrificial carrier, the sacrificial carrier can be made of nickel, chrome, tin, iron, stainless steel, or other selective etching solution (not routed to copper) The line reacts) the material removed. Alternatively, the routing wires can be made of any stabilizing material to avoid etching when the sacrificial carrier is removed. For example, when the sacrificial carrier is made of copper, the routing line can be a gold routing line. In addition, the sacrificial carrier may also be a multi-layer structure having a barrier layer and a support plate, and the first routing circuit is formed on the barrier layer of the sacrificial carrier. Due to the first routing circuit and the support plate The barrier layer is isolated from each other by the barrier layer. Therefore, even if the routing line and the support board of the first routing circuit are made of the same material, the first routing circuit is not damaged when the support board is removed. Routing line. Here, the barrier layer may be a metal layer, and the metal layer does not act on chemical etching when chemically removing the support plate, and may be removed using an etching solution that does not react to the routing line. For example, a nickel layer, a chromium layer or a titanium layer may be formed on the surface of the support plate made of copper or aluminum as a barrier layer, and a routing line made of copper or aluminum may be deposited on the nickel layer, chromium. On the layer or on the titanium layer. Accordingly, the nickel, chrome or titanium layer protects the routing lines from etching when the support plate is removed. Alternatively, the barrier layer can be a dielectric layer that can be removed by, for example, mechanical stripping or plasma ashing. For example, the release layer can be used as a barrier layer between the support plate and the first routing circuit, and the support plate can be removed together with the release layer by mechanical peeling.

The vertical connectors extending through the sealing material can include metal posts, solder balls, conductive blind holes, or combinations thereof that provide electrical contacts for the next level of connection. The vertical connector can be electrically connected to the first routing circuit before or after the sealing material is provided. In a preferred embodiment, the vertical connectors are located in an edge region of the first routing circuit and extend from the first routing circuit toward the second direction or beyond the second surface of the sealing material. Accordingly, the vertical connector can have a first end in contact with the first routing circuit and an opposite second end adjacent the second surface of the sealing material.

The heat conducting plate includes a heat sink and a selective second routing circuit. The heat sink can provide a heat dissipation path for the second semiconductor wafer attached to the heat sink by a thermally conductive contact such as an organic resin or solder mixed with metal particles. The optional second routing circuit laterally surrounds the second semiconductor wafer and may be a build-up circuit. Preferably, the second routing circuit is a multi-layer build-up circuit, which may include at least one dielectric layer and wires that fill the blind holes in the dielectric layer and extend laterally on the dielectric layer. The dielectric layer and the wire are continuously formed in turns and can be formed repeatedly if desired. For the ground connection, the second routing circuit can be electrically coupled to the heat sink via a metallized blind hole in contact with the heat sink. The heat sink may have a recess for accommodating the second semiconductor wafer, and the heat sink may be disposed on the heat sink. The first routing circuit of the embedding device can be electrically coupled to form a ground connection by, for example, a bump (which is in contact with the heat sink and the first routing circuit). In another thermally conductive plate aspect in which the second routing circuit is disposed on the heat sink, the recess of the heat conducting plate extends through the second routing circuit to reveal a selected portion of the heat sink. In this aspect, the second routing circuit can be electrically coupled to the first routing circuit by bumps (rather than directly by the build-up process). Preferably, the height of the bump in contact with the second routing circuit or the heat sink is less than the height of the second semiconductor wafer and the bump (which contacts the second semiconductor wafer). More specifically, the height of the second semiconductor wafer and the bump (which contacts the second semiconductor wafer and the first routing circuit) can be substantially equal to the depth of the recess plus the bump (which contacts the heat conducting plate and the first route) The height of the circuit).

The optional external routing circuit is formed on the second surface of the sealing material and may be a build-up circuit electrically connected to the vertical connection. More specifically, the embedding device may further include wires that are in contact with and electrically connected to the vertical connectors of the sealing material, and the wires extend laterally further on the second surface of the sealing material. In addition, if more signal routing is desired, the external routing circuitry can be a multi-layer routing circuit that includes one or more dielectric layers, blind vias in the dielectric layer, and additional traces. The outermost wire of the external routing circuit can accommodate conductive contacts, such as solder balls, for electrical and mechanical connection with the next set of components or another electronic component.

The term "overlay" means incomplete and complete coverage in the vertical and / or lateral directions. For example, in a state where the pockets face upward, the heat sink is covered under the second semiconductor wafer, regardless of whether another component such as a thermally conductive contact is located between the second semiconductor wafer and the heat sink.

The words "attached to" and "attached to" include contact and non-contact with a single or multiple components. For example, the heat sink is attached to the inactive surface of the second semiconductor wafer regardless of whether the heat sink is separated from the second semiconductor wafer by a thermally conductive contact.

The terms "electrical connection" and "electrical coupling" mean direct or indirect electrical connection. For example, the vertical connectors are in direct contact and electrically connected to the first routing circuit, while the second semiconductor wafer is spaced from the first routing circuit and electrically coupled to the first routing circuit by the first bumps.

The "first direction" and "second direction" do not depend on the orientation of the semiconductor body. Anyone familiar with the art can easily understand the direction in which they actually refer. For example, the first surface of the sealing material faces in a first direction and the second surface of the sealing material faces in a second direction, regardless of whether the semiconductor body is inverted. Therefore, the first and second directions are opposite to each other and perpendicular to the side direction. Furthermore, in the state where the pocket is facing downward, the first direction is the upward direction, and the second direction is the downward direction; in the state where the pocket is upward, the first direction is the downward direction, and the second direction is the downward direction. Up direction.

The semiconductor package of the present invention has a number of advantages. For example, placing the first and second semiconductor wafers face to face on opposite sides of the first routing circuit provides the shortest interconnection distance between the first semiconductor wafer and the second semiconductor wafer. The first routing circuit can provide a first stage of fanout routing/interconnection to the first and second semiconductor wafers, and the vertical connector can provide an electrical connection for external connection or routing of the next level of routing circuitry. Since the first and second semiconductor chips are electrically coupled to the first routing circuit by the bumps instead of being directly coupled to the first routing circuit by the build-up process, the simplified process step can reduce the manufacturing cost. . The external routing circuit can provide terminal pads densely distributed throughout the area to add external electrical contacts for the next level of assembly. The heat sink can provide heat dissipation, electromagnetic shielding, and moisture barrier of the second semiconductor wafer, and provides mechanical support on which the embedding device is stacked. The semiconductor group system prepared by this method is high in reliability, low in cost, and is very suitable for mass production and production.

The manufacturing method of the present invention has high applicability, and combines various mature electrical and mechanical connection technologies in a unique and progressive manner. Furthermore, the manufacturing method of the present invention can be carried out without expensive tools. Therefore, compared to the traditional technology, this production method can greatly increase the yield, yield, efficiency and cost-effectiveness.

The embodiments described herein are illustrative, and the elements or steps that are well known in the art may be simplified or omitted in order to avoid obscuring the features of the present invention. Similarly, in order to make the drawings clear, the drawings may also omit redundant or non-essential components and component symbols.

110‧‧‧Semiconductor group

20‧‧‧buried device

21‧‧‧First routing circuit

22‧‧‧First semiconductor wafer

24‧‧‧Vertical connectors

241‧‧‧First solder ball

243‧‧‧second solder ball

25‧‧‧ Sealing material

251‧‧‧ first surface

253‧‧‧ second surface

31‧‧‧heat conducting plate

32‧‧‧ Heat sink

33‧‧‧Second routing circuit

36‧‧‧Second semiconductor wafer

37‧‧‧ Thermal contact parts

41‧‧‧First bump

43‧‧‧second bump

Claims (20)

A heat dissipation gain type face-to-face semiconductor package having a heat sink, comprising: a buried device comprising a first semiconductor wafer, a sealing material, a series of vertical connecting members and a first routing circuit, the first a routing circuit is disposed on the first surface of the sealing material, wherein (i) the first semiconductor wafer is embedded in the sealing material and electrically coupled to the first routing circuit, and (ii) the vertical connections The member is laterally covered by the sealing material and surrounds the first semiconductor wafer, wherein the vertical connecting members are electrically coupled to the first routing circuit and extend to or extend beyond one of the opposite second surfaces of the sealing material; And a heat dissipation type device comprising a heat sink, a second routing circuit and a second semiconductor chip, the second routing circuit is disposed on the heat sink, and the second semiconductor wafer is contacted by a thermal contact The device is thermally coupled to the heat sink; wherein the embedding device is stacked on the heat dissipation gain type device, and the second semiconductor chip is electrically coupled to the first route by a series of first bumps Circuit, and And maintaining a distance from the first routing circuit, and the second routing circuit is electrically coupled to the first routing circuit by a series of second bumps, and is kept at a distance from the first routing circuit. The heat dissipation gain type face-to-face semiconductor package according to claim 1, wherein the embedding device further comprises an external routing circuit disposed on the second surface of the sealing material and electrically coupled Connected to the vertical connectors in the sealing material. The heat dissipation gain type face-to-face semiconductor package according to claim 1, wherein the vertical connectors comprise metal pillars, solder balls, conductive blind holes or a combination thereof. The heat dissipation gain type face-to-face semiconductor package of claim 1, wherein the second routing circuit is electrically coupled to the heat sink. The heat dissipation gain type face-to-face semiconductor package according to claim 1, wherein the heat conduction contact member comprises an organic resin or solder mixed with metal particles. The heat dissipation gain type face-to-face semiconductor package of claim 1, wherein the embedding device further comprises another heat sink attached to one of the inactive surfaces of the first semiconductor wafer. The heat dissipation gain type face-to-face semiconductor package according to claim 1, further comprising: a resin filled in a space between the embedding device and the heat dissipation gain type device. A heat dissipation gain type face-to-face semiconductor package having a heat sink, comprising: a buried device comprising a first semiconductor wafer, a sealing material, a series of vertical connecting members and a first routing circuit, the first a routing circuit is disposed on the first surface of the sealing material, wherein (i) the first semiconductor wafer is embedded in the sealing material and electrically coupled to the first routing circuit, and (ii) the vertical connections The member is laterally covered by the sealing material and surrounds the first semiconductor wafer, wherein the vertical connecting members are electrically coupled to the first routing circuit and extend to or extend beyond one of the opposite second surfaces of the sealing material; And a heat dissipation type device comprising a heat sink and a second semiconductor wafer, wherein the second semiconductor wafer is thermally conductive to the heat sink by a heat conducting contact and located in a recess of the heat sink; The embedding device is stacked on the heat dissipation gain type device, and the second semiconductor chip is electrically coupled to the first routing circuit by a series of bumps and is kept away from the first routing circuit. . The heat dissipation gain type face-to-face semiconductor package according to claim 8, wherein the embedding device further comprises an external routing circuit disposed on the second surface of the sealing material and electrically coupled Connected to the vertical connectors in the sealing material. The heat dissipation gain type face-to-face semiconductor package of claim 8, wherein the vertical connectors comprise metal posts, solder balls, conductive blind holes or a combination thereof. The heat dissipation gain type face-to-face semiconductor package of claim 8, wherein the embedding device further comprises another heat sink attached to one of the inactive surfaces of the first semiconductor wafer. The heat dissipation gain type face-to-face semiconductor package according to claim 8, further comprising: a resin filled in a space between the embedding device and the heat dissipation gain type device. A method for fabricating a heat dissipation gain type face-to-face semiconductor package having a heat sink, comprising: providing a buried device comprising a first semiconductor wafer, a sealing material, a series of vertical connecting members and a first routing circuit The first routing circuit is disposed on a first surface of the sealing material, wherein (i) the first semiconductor wafer is embedded in the sealing material and electrically coupled to the first routing circuit, and (ii) the a vertical connection member surrounds the first semiconductor chip and is electrically coupled to the first routing circuit; the second semiconductor wafer is electrically coupled to the second semiconductor chip by a series of first bumps located at the first routing circuit The first routing circuit of the embedding device; providing a heat conducting plate comprising a heat sink; and stacking the embedding device on the heat conducting plate, and the second semiconductor chip is formed by a heat conducting contact It is thermally conductive with the heat sink. The manufacturing method of claim 13, wherein the heat conducting plate further comprises a second routing circuit located on the heat sink, and the step of stacking the plugging device on the heat conducting plate comprises The second routing circuit is electrically coupled to the first routing circuit by a series of second bumps located at the first routing circuit. The manufacturing method of claim 13, wherein the step of providing the embedding device comprises: providing the first routing circuit on a sacrificial carrier, wherein the first routing circuit is detachably Connected to the sacrificial carrier; electrically coupling the first semiconductor wafer to the first routing circuit; providing the sealing material laterally surrounding the first semiconductor wafer and covering the first routing circuit; forming The vertical connectors; and removing the sacrificial carrier from the first routing circuit. The manufacturing method of claim 13, wherein the embedding device further comprises an external routing circuit disposed on the second surface of the sealing material and electrically coupled to the sealing material The vertical connectors. The manufacturing method of claim 16, wherein the step of providing the embedding device comprises: providing the first routing circuit on a sacrificial carrier, wherein the first routing circuit is detachably Connected to the sacrificial carrier; electrically coupling the first semiconductor chip to the first routing circuit; Providing the sealing material laterally surrounding the first semiconductor wafer and covering the first routing circuit; forming the vertical connecting members; forming the external routing circuit on the second surface of the sealing material, and making the external portion A routing circuit is electrically coupled to the vertical connectors; and the sacrificial carrier is removed from the first routing circuit. The manufacturing method of claim 13, wherein the embedding device further comprises another heat sink attached to one of the inactive surfaces of the first semiconductor wafer. The manufacturing method of claim 14, wherein the second routing circuit is electrically coupled to the heat sink. The manufacturing method of claim 13, further comprising: filling a space between the embedding device and the heat conducting plate and between the embedding device and the second semiconductor wafer.