TW201940026A - Wiring board with embedded component and integrated stiffener, method of making the same and face-to-face semiconductor assembly using the same - Google Patents

Abstract

A wiring board includes an electronic component laterally surrounded by a stiffener, and a third routing circuitry disposed beyond the space laterally surrounded by the stiffener and extends over the stiffener. The electronic component includes a first routing circuitry, an encapsulant, an array of vertical connecting elements and a second routing circuitry integrated together. The mechanical robustness of the stiffener can prevent the wiring board from warping. The embedded semiconductor device is electrically coupled to the first routing circuitry and surrounded by the vertical connecting elements in electrical connection with the first and second routing circuitries. The first routing circuitry provides primary fan-out routing for another semiconductor device to be assembled on the wiring board, whereas the third routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the electronic component with the stiffener.

Description

Circuit board with embedded component and reinforcing layer, manufacturing method thereof and face-to-face semiconductor assembly

The invention relates to a circuit board, in particular to a circuit board with embedded components and a reinforcing layer, a method for manufacturing the same and a semiconductor assembly facing the surface.

The market trend of multimedia devices tends to be faster and thinner. One method is to embed electronic components (such as resistors and capacitors) in the circuit board, so that the electrical performance of the circuit board can be improved. When the memory chip or logic chip is embedded in the circuit board, another component can be connected to the circuit board to form a chip-on-chip 3D stacked structure. U.S. Patent Nos. 8,453,323, 8,525,337, 8,618,652, and 8,836,114 disclose various circuit boards with embedded components based on this purpose. However, in addition to the problem of difficult to control warping, there are other characteristics (such as design flexibility) that have not yet been resolved.

For the above reasons and other reasons described below, there is an urgent need to develop a new type of circuit board with embedded components to address routing requirements and ensure ultra-high package density, high signal integrity, thinness, and low warpage.

The main object of the present invention is to provide a circuit board, which is provided with a first routing circuit, an embedded semiconductor element, a sealing material, a series of vertical connectors and a second routing circuit in a space surrounded by the reinforcing layer laterally, To avoid warping in the central area of the circuit board, it can improve production yield and device-level reliability.

The circuit board of the present invention may further include a third routing circuit, which is located outside the space surrounded laterally by the reinforcement layer, and is electrically connected to the first routing circuit through the second routing circuit and the vertical connection member, so that the circuit board The warping phenomenon in the outermost area is well controlled, and the first, second and third routing circuits can exhibit a high degree of routing flexibility. For example, the first routing circuit can be constructed as a primary fan-out circuit with a very high routing density, and the third routing circuit can be constructed as a further fan-out routing with a thick width / pitch to facilitate board assembling at the next level. ).

According to the above and other objectives, the present invention provides a circuit board, which includes a first routing circuit, a first semiconductor element, a sealing material, a series of vertical connectors, a second routing circuit, a reinforcing layer, and a third Routing circuit. Here, the first routing circuit, the first semiconductor element, the sealing material, the vertical connection member and the second routing circuit are integrated into an electrical component, and the reinforcing layer surrounds the electrical component. In a preferred embodiment, the reinforcing layer has an inner side wall surface adjacent to the outer edge of the electrical component, and can provide a high-modulus bending-resistant platform for the circuit board; the first semiconductor component is placed on the first route in a flip-chip manner. On the circuit and buried in the sealing material and surrounded by the vertical connection; the first routing circuit is adjacent to one side of the sealing material and provides a primary fan-out routing for the second semiconductor component assembled subsequently, and Provide the shortest routing distance between the first and second semiconductor components; the second routing circuit is adjacent to the other side of the sealing material and provides electrical contacts for the next level routing circuit connection; the vertical connection is located on the first routing circuit And the second routing circuit, and provides an electrical connection between the first routing circuit and the second routing circuit; the third routing circuit is adjacent to the second routing circuit and extends laterally to the reinforcement layer, and the third routing circuit can The electrical components are mechanically bonded to the reinforcement layer, while providing further fan-out routing, wherein the pad spacing and pad size of the third routing circuit can meet the next-level assembly.

In another aspect, the present invention provides a circuit board including: an electrical component including a first semiconductor component, a sealing material, a series of vertical connectors, a first routing circuit and a second routing A circuit in which (i) the first semiconductor element and the vertical connectors are electrically coupled to the first routing circuit, (ii) the sealing material laterally covers the first semiconductor element and the vertical connectors, and Having a first surface facing the first routing circuit and a second surface opposite to the first surface, and (iii) the second routing circuit is disposed on the second surface of the sealing material, and is passed through the second surface Some vertical connectors are electrically connected to the first routing circuit; a reinforcing layer laterally surrounds the electric component, and an inner sidewall surface of the reinforcing layer is adjacent to a peripheral edge of the electric component; and a third The routing circuit is disposed on the second routing circuit and extends laterally on the reinforcement layer, wherein the third routing circuit is electrically coupled to the second routing circuit. In addition, the present invention also provides a face-to-face semiconductor assembly including the above-mentioned circuit board and a second semiconductor element. The first semiconductor element and the second semiconductor element are interposed therebetween. The first routing circuits are electrically coupled to each other face to face.

In yet another aspect, the present invention provides a method for manufacturing a circuit board, which includes the following steps: providing an electrical component on a sacrificial carrier board, the electrical component including a semiconductor component, a sealing material, a series of vertical A connector, a first routing circuit and a second routing circuit, wherein (i) the first routing circuit is detachably connected to the sacrificial carrier board and is adjacent to a first surface of the sealing material; ii) the semiconductor element and the vertical connectors are embedded in the sealing material, and are electrically coupled to the first routing circuit, and (iii) the second routing circuit is disposed on one of the sealing materials instead of the second On the surface, and electrically connected to the first routing circuit through the vertical connecting members; providing a reinforcing layer, which laterally surrounds the electrical component and the sacrificial carrier board; forming a third routing circuit, which is arranged on the The second routing circuit extends laterally on the reinforcement layer, wherein the third routing circuit is electrically coupled to the second routing circuit; and the sacrificial carrier board is removed from the first routing circuit.

The order of the above steps is not limited to those listed above, and can be changed or re-arranged according to the required design, unless the word "next" is specifically described or used between steps, or the steps must occur sequentially.

The method for manufacturing a circuit board of the present invention has many advantages. For example, before the third routing circuit is formed, the method of combining the sacrificial carrier board and the electrical components with the reinforcing layer is particularly advantageous because the sacrificial carrier board and the reinforcing layer can jointly provide a stable A platform for the formation of a third routing circuit. The method of forming a sealing material on the first routing circuit can provide another high-modulus bending-resistant platform for the circuit board, thereby the mechanical strength of the sealing material and the reinforcing layer can avoid warping after removing the sacrificial carrier board. In addition, when a multilayer routing circuit needs to be formed, a three-step process to form an interconnect substrate can avoid serious bending problems.

The above and other features and advantages of the present invention can be made clearer by the following detailed description of the preferred embodiments.

In the following, an embodiment will be provided to explain the implementation of the present invention in detail. The advantages and effects of the present invention will be more significant by the content disclosed by the present invention. The attached drawings are simplified and used for illustration. The number, shape and size of the components shown in the drawings can be modified according to the actual situation, and the configuration of the components may be more complicated. The present invention can also be practiced or applied in other aspects, and various changes and adjustments can be made without departing from the spirit and scope defined by the present invention.

[Example 1]

1-17 is a diagram of a method for manufacturing a circuit board in a first embodiment of the present invention, which includes a first routing circuit, a first semiconductor element, a series of vertical connectors, a sealing material, and a second routing Circuit, a reinforcement layer and a third routing circuit.

1 and 2 are a cross-sectional view and a top perspective view of a routing layer 211 formed on the sacrificial carrier 10, respectively. The routing layer 211 is formed by a metal deposition and metal patterning process. In this figure, the sacrificial carrier board 10 has a single-layer structure, and the routing layer 211 includes a bonding pad 212 and a stacking pad 213. The sacrificial carrier plate 10 is generally made of copper, aluminum, iron, nickel, tin, stainless steel, silicon, or other metals or alloys, but any other conductive or non-conductive material may be used. The thickness of the sacrificial carrier plate 10 is preferably in the range of 0.1 to 2.0 mm. In this embodiment, the sacrificial carrier plate 10 is made of an iron-containing material and has a thickness of 1.0 mm. The routing layer 211 is generally made of copper and can be patterned and deposited by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof, or formed by thin film deposition followed by a metal patterning step. As for the sacrificial carrier 10 having conductivity, it is generally deposited by metal plating to form the routing layer 211. The metal patterning technology includes wet etching, electrochemical etching, laser-assisted etching, and combinations thereof, and uses an etching mask (not shown) to define the routing layer 211.

3 and 4 are a cross-sectional view and a top perspective view of alternately forming multiple dielectric layers 214 and multiple wire layers 216 alternately. The dielectric layers 214 can be generally deposited by lamination or coating, and can be made of epoxy resin, glass epoxy resin, polyimide, or the like. The wire layers 216 extend laterally on the dielectric layer 214 and include metallized blind holes 218 in the dielectric layer 214. Accordingly, the wire layers 216 can be electrically coupled to each other through the metallized blind holes 218, and the innermost wire layer 216 is electrically coupled to the routing layer 211 through the metallized blind holes 218.

Each wire layer 216 may be deposited as a single layer or multiple layers by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof. For example, first, the structure is immersed in an activator solution to cause a dielectric reaction between the dielectric layer 214 and electroless copper, and then a thin copper layer is coated by electroless plating as a seed layer, and then electroplated. A second copper layer of a desired thickness is formed on the seed layer. Alternatively, before depositing the electroplated copper layer on the seed layer, the seed layer may be formed as a titanium / copper seed layer film by sputtering. Once the desired thickness is achieved, the coating layer can be patterned using various techniques to form the wire layer 216, which includes wet etching, electrochemical etching, laser-assisted etching, and combinations thereof, and uses an etching mask (not shown) To define the wire layer 216.

Accordingly, at this stage, the fabrication of the first routing circuit 21 can be completed on the sacrificial carrier board 10. In this figure, the first routing circuit 21 includes a routing layer 211, a dielectric layer 214, and a wire layer 216.

FIG. 5 is a cross-sectional view of an array-type vertical connection member 23 formed on the first routing circuit 21. In this figure, the vertical connecting members 23 are shown as metal pillars, and the first ends 231 thereof are in contact with and are electrically connected to the outermost wire layer 216 of the first routing circuit 21.

FIG. 6 is a cross-sectional view of the first semiconductor element 25 electrically coupled to the first routing circuit 21. The first semiconductor element 25 (shown as a bare chip) can be electrically coupled to the first routing circuit 21 with the active surface 251 facing the first routing circuit 21 by thermal pressing, reflow soldering, or thermal ultrasonic bonding technology, and is electrically coupled to the first routing circuit 21 by The outermost conductive layer 216 of the first routing circuit 21.

FIG. 7 is a cross-sectional view of the sealing material 27 formed on the vertical connecting member 23, the first semiconductor element 25, and the first routing circuit 21. The sealing material 27 can be formed by, for example, resin-glass lamination, resin-glass coating, or molding. Formed by molding. The sealing material 27 covers the vertical connecting member 23, the first semiconductor element 25, and the first routing circuit 21 from above, and surrounds and uniformly covers and covers the sidewalls of the vertical connecting member 23 and the first semiconductor element 25.

FIG. 8 is a cross-sectional view of the vertical connecting member 23 exposed from above. The upper region of the sealing material 27 can be removed by grinding to expose the second end 233 of the vertical connecting member 23. In this figure, the exposed surfaces of the vertical connectors 23 are substantially coplanar with the outer surface of the sealing material 27 above.

FIG. 9 is a cross-sectional view of the routing layer 291 formed on the sealing material 27. The routing layer 291 is formed by a metal pattern deposition method described below, and is electrically coupled to the vertical connection member 23. First, the top surface of the structure can be metallized by various techniques (such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof) to form a single-layer or multi-layer conductive layer (usually a copper layer). The conductive layer may be made of Cu, Ni, Ti, Au, Ag, Al, a combination thereof, or other suitable conductive materials. Generally, a seed layer is formed on the topmost surface of the structure before the conductive layer is plated to a desired thickness. The seed layer can be formed by a diffusion resistance layer and a plating bus layer. The diffusion resistance layer is used to offset oxidation or erosion of the conductive layer (such as copper). In most examples, the diffusion barrier layer can also be used as an adhesion enhancement layer for the underlying material, and can be formed by physical vapor deposition (PVD). For example, Ti can be formed by sputtering to a thickness of about 0.01 μm to 0.1 μm Or TiW layer. However, the diffusion barrier layer can also be made of other materials, such as TaN or other suitable materials, and its thickness is not limited to the above range. The plating carrier layer is usually made of the same material as the conductive layer and has a thickness ranging from about 0.1 μm to 1 μm. For example, when the conductive layer is copper, the plating carrier layer is preferably a copper thin film made by physical vapor deposition or electroless plating. However, the electroplated support layer can also be made of other suitable materials, such as silver, gold, chromium, nickel, tungsten, or a combination thereof, and its thickness is not limited to the above range.

After the seed layer is deposited, a photoresist layer (not shown) is formed on the seed layer. The photoresist layer can be formed by a wet process (such as a spin coating process) or a dry process (such as a lamination dry film). After the photoresist layer is formed, the photoresist layer is patterned to form openings, and then the openings are filled with a covering metal (such as copper) to form a routing layer 291. After the metal is plated, the exposed seed layer is removed through an etching process to form conductive wires that are electrically isolated from each other.

FIG. 10 is a cross-sectional view of the dielectric layers 294 and the wiring layers 296 alternately formed. The dielectric layer 294 contacts the sealing material 27 and the routing layer 291, is covered from above and extends laterally on the sealing material 27 and the routing layer 291. The wire layer 296 extends laterally on the dielectric layer 294 and includes a metallized blind hole 298 in the dielectric layer 294. Accordingly, the wire layer 296 can be electrically coupled to the routing layer 291 through the metallized blind hole 298.

At this stage, the production of the second routing circuit 29 has been completed, and it is electrically connected to the first routing circuit 21 through the vertical connection member 23. In this figure, the second routing circuit 29 includes a routing layer 291, a dielectric layer 294, and a wire layer 296.

FIG. 11 is a cross-sectional view of the panel size structure of FIG. 10 cut into individual pieces. As shown in the figure, separate the panel size structure into individual pieces along the cutting line "L".

FIG. 12 is a cross-sectional view of an individual unit, wherein the individual unit includes a sacrificial carrier board 10 and an electrical component 20 located on the sacrificial carrier board 10. The electrical component 20 includes a first routing circuit 21, a vertical connection member 23, a first semiconductor device 25, a sealing member 27, and a second routing circuit 29. In this figure, the first routing circuit 21 and the second routing circuit 29 are multi-layer build-up circuits, which are respectively located on opposite sides of the sealing material 27 and are electrically connected to each other by a vertical connection member 23. The first routing circuit 21 is detachably connected to the sacrificial carrier board 10 and is adjacent to the first surface 271 of the sealing material 27. The first routing circuit 21 includes a bonding pad 212 and a bonding pad 213 that are in contact with the sacrificial carrier board 10. The first semiconductor element 25 is embedded in the sealing material 27 and is electrically coupled to the first routing circuit 21. The vertical connecting members 23 are buried in the sealing material 27 and surround the first semiconductor element 25, and extend from the first routing circuit 21 to the second surface 272 of the sealing material 27. The second routing circuit 29 is disposed on the second surface 272 of the sealing material 27 and is electrically coupled to the vertical connecting member 23.

FIG. 13 is a cross-sectional view of the temporary carrier film 30 attached to the electrical component 20. The temporary carrier film 30 can provide a temporary fixing force to an individual unit having the sacrificial carrier board 10 and the electrical component 20. In this figure, the temporary carrier film 30 can be brought into contact with the second routing circuit 29 so that individual single pieces can be firmly fixed on the temporary carrier film 30 by the viscosity of the temporary carrier film 30.

FIG. 14 is a cross-sectional view of forming the reinforcing layer 40. The reinforcing layer 40 may be formed by molding, printing, or other methods (such as lamination of epoxy resin or polyimide). The reinforcing layer 40 covers the sacrificial carrier board 10 and the temporary carrier film 30 from above, and simultaneously covers, surrounds, and covers the sidewalls of the sacrificial carrier board 10 and the electrical components 20 side by side. 20 extends laterally to the peripheral edge of the structure.

FIG. 15 is a cross-sectional view of the third routing circuit 51 with the temporary carrier film 30 removed, wherein the third routing circuit 51 is electrically coupled to the electrical component 20. The temporary carrier film 30 is removed from the electrical component 20 and the reinforcement layer 40, and then a third routing circuit 51 is formed on the electrical component 20 and the reinforcement layer 40. The third routing circuit 51 extends laterally beyond the peripheral edge of the second routing circuit 29 and extends to a surface of the reinforcing layer 40. In this figure, the third routing circuit 51 is a multilayer build-up circuit, which includes multiple dielectric layers 514 and multiple wire layers 516 formed alternately and alternately. The dielectric layer 514 covers the electrical element 20 and the reinforcing layer 41 from below. The wire layer 516 extends laterally on the dielectric layer 514 and extends laterally beyond the peripheral edge of the second routing circuit 29. In addition, the wire layer 516 includes a metallized blind hole 518 in the dielectric layer 514. Accordingly, the wire layers 516 can be electrically coupled to each other through the metallized blind holes 518, and the innermost wire layer 516 is electrically coupled to the wire layers 296 of the second routing circuit 29 through the metallized blind holes 518.

FIG. 17 is a sectional view with the sacrificial carrier 10 removed. The sacrificial carrier board 10 can be removed in various ways to reveal the first routing circuit 21 from above, including wet etching and electrolysis using an acidic solution (such as ferric chloride, copper sulfate solution) or an alkaline solution (such as ammonia solution). Etching, or chemical etching after mechanical means (such as drilling or end milling). In this embodiment, the sacrificial carrier 10 made of an iron-containing material can be removed by a chemical etching solution, wherein the chemical etching solution is selective between copper and iron to avoid removing the sacrificial carrier 10 As a result, the copper routing layer 211 is etched. Therefore, the exposed surface 203 of the first routing circuit 21 and a portion of the inner wall surface 409 of the reinforcing layer 40 together form a cavity 405.

Accordingly, as shown in FIG. 17, the completed circuit board 100 includes a first routing circuit 21, a vertical connection 23, a first semiconductor element 25, a sealing material 27, a second routing circuit 29, a reinforcing layer 40, and a third routing The circuit 51, wherein the first routing circuit 21, the second routing circuit 29 and the third routing circuit 51 are all multi-layer build-up circuits without a core layer.

The first routing circuit 21, the vertical connection 23, the first semiconductor element 25, the sealing material 27, and the second routing circuit 29 are laterally surrounded by the reinforcing layer 40. The first routing circuit 21, the sealing material 27 and the peripheral edges of the second routing circuit 29 are bonded to the inner sidewall surface 409 of the reinforcing layer 40. The first semiconductor element 25 and the vertical connection member 23 are buried in a sealing material 27 and electrically connected to the first routing circuit 21. The first routing circuit 21 abuts the first surface 271 of the sealing material 27 and is exposed from the recess 405. The second routing circuit 29 is adjacent to the second surface 272 of the sealing material 27 and is electrically connected to the first routing circuit 21 through the vertical connecting member 23. The third routing circuit 51 is disposed on the second routing circuit 29 and extends laterally to the peripheral edge of the circuit board 100. Accordingly, the area of the exposed surface 203 of the first routing circuit 21 is smaller than the surface area of the third routing circuit 51 (ie, the area of the lower surface of the dielectric layer 214).

The third routing circuit 51 is electrically coupled to the second routing circuit 29 through the metallized blind hole 518 of the third routing circuit 51, and the third routing circuit 51 includes a wire layer 516 extending beyond the peripheral edge of the electrical component 20. . Thereby, the third routing circuit 51 can not only provide a further fan-out circuit structure, but also can mechanically join the electrical component 20 and the reinforcing layer 40.

The reinforcing layer 40 surrounds the peripheral edges of the first routing circuit 21, the sealing material 27, and the second routing circuit 29, and extends laterally to the peripheral edge of the circuit board 100 to provide mechanical support and prevent the circuit board 100 from warping . The inner wall surface 409 of the reinforcing layer 40 extends upward beyond the exposed surface 203 of the first routing circuit 21 to surround the cavity 405.

FIG. 18 is a cross-sectional view of a face-to-face semiconductor assembly connected to a second semiconductor element 61 on the circuit board 100 shown in FIG. 17, wherein the second semiconductor element 61 is illustrated as a wafer. The second semiconductor element 61 is located in the recess 405 and is placed on the first routing circuit 21 through the bump 613 in a flip-chip manner. Accordingly, the second semiconductor element 61 can be electrically connected to the first semiconductor element 25 face to face through the first routing circuit 21 between the first semiconductor element 25 and the second semiconductor element 61.

FIG. 19 is a cross-sectional view of a heat-dissipating base 81 further provided on the face-to-face semiconductor group shown in FIG. 18. The heat sink 81 can be made of any material with high thermal conductivity, such as metal, alloy, silicon, ceramic or graphite, which is attached to the non-active surface of the second semiconductor element 61 and extends laterally to the reinforcing layer 40. Accordingly, the heat generated by the second semiconductor element 61 can be dissipated through the heat sink 81.

20 is a cross-sectional view of a third semiconductor element 63 and a solder ball 75 selectively provided on the face-to-face semiconductor group shown in FIG. 19. The third semiconductor element 63 is placed on the wire layer 516 of the third routing circuit 51 in a flip-chip manner through the bump 633. The solder ball 75 is placed on the wire layer 516 of the third routing circuit 51 and surrounds the third semiconductor element 63.

FIG. 21 is a cross-sectional view of the second semiconductor element 61, the third semiconductor element 63, and the fourth semiconductor element 65 on the wiring board 100 shown in FIG. 17 facing the semiconductor assembly. The second semiconductor element 61 is disposed in the cavity 405 of the circuit board 100 and is electrically coupled to the bonding pad 212 of the first routing circuit 21. The third semiconductor element 63 is connected on the wire layer 516 of the third routing circuit 51 in a flip-chip manner. The fourth semiconductor element 65 is disposed on the second semiconductor element 61 and is electrically coupled to the bonding pad 213 of the first routing circuit 21. A plurality of solder balls 75 can be selectively placed on the wire layer 516 of the third routing circuit 51 so that the solder balls 75 surround the third semiconductor element 63.

[Example 2]

22-28 are diagrams of a method for manufacturing a circuit board according to a second embodiment of the present invention. The second routing circuit is electrically coupled to the vertical connector through a metallized blind hole in the sealing material.

For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated herein, and it is not necessary to repeat the same description.

22 is a cross-sectional view of a blind hole 273 formed in the sealing material 27 of the structure of FIG. 7. The blind hole 273 can be formed by various techniques, including laser drilling, plasma etching, and lithography. The blind hole 273 usually has a diameter of 50 microns. Pulse lasers can be used to improve laser drilling performance. Alternatively, a scanning laser beam can be used with a metal mask. The blind holes 273 are aligned with selected portions of the vertical connecting member 23 so that the vertical connecting member 23 is exposed from above.

FIG. 23 is a cross-sectional view of the routing layer 291 formed on the sealing material 27, wherein the routing layer 291 is electrically coupled to the vertical connection member 23 through the metallized blind hole 293. The routing layer 291 extends upward from the vertical connection member 23 and fills the blind hole 273 to form a metallized blind hole 293 directly contacting the vertical connection member 23 and extends laterally on the second surface 272 of the sealing material 27. Therefore, the routing layer 291 can provide horizontal signal routing in the X and Y directions and vertical routing through the blind hole 273 as electrical connections of the vertical connection member 23.

FIG. 24 is a cross-sectional view of the dielectric layers 294 and the wire layers 296 alternately formed. The dielectric layer 294 contacts the sealing material 27 and the routing layer 291, is covered from above and extends laterally on the sealing material 27 and the routing layer 291. The wire layer 296 extends laterally on the dielectric layer 294 and includes a metallized blind hole 298 in the dielectric layer 294. Accordingly, the wire layer 296 can be electrically coupled to the routing layer 291 through the metallized blind hole 298.

At this stage, the production of the second routing circuit 29 has been completed, and it is electrically connected to the first routing circuit 21 through the vertical connection member 23. In this figure, the second routing circuit 29 includes a routing layer 291, a dielectric layer 294, and a wire layer 296.

FIG. 25 is a cross-sectional view of the panel size structure of FIG. 24 cut into individual pieces. As shown in the figure, separate the panel size structure into individual pieces along the cutting line "L".

FIG. 26 is a cross-sectional view of an individual unit, wherein the individual unit includes a sacrificial carrier board 10 and an electrical component 20 located on the sacrificial carrier board 10. The electrical component 20 includes a first routing circuit 21, a vertical connection member 23, a first semiconductor device 25, a sealing member 27, and a second routing circuit 29.

FIG. 27 is a cross-sectional view of the reinforcing layer 40 bonded to the peripheral edges of the sacrificial carrier board 10, the first routing circuit 21, the sealing material 27, and the second routing circuit 29. In this figure, the top surface of the reinforcement layer 40 and the outer surface of the sacrificial carrier board 10 are substantially coplanar, and the bottom surface of the reinforcement layer 40 is substantially coplanar with the outer surface of the second routing circuit 29 wire layer 296.

FIG. 28 is a cross-sectional view of a circuit board 200 with the sacrificial carrier board 10 removed and a third routing circuit 51 deposited to electrically couple the electrical component 20. The sacrificial carrier 10 made of copper can be removed by an alkaline etching solution. The third routing circuit 51 extends laterally beyond the peripheral edge of the second routing circuit 29 and extends to the surface of the reinforcing layer 40. In this figure, the third routing circuit 51 is a multilayer build-up circuit, which includes multiple dielectric layers 514 and multiple wire layers 516 formed alternately and alternately. After the third routing circuit 51 is formed, the sacrificial carrier board 10 is removed to form a cavity 405.

FIG. 29 is a cross-sectional view of a semiconductor assembly facing the second semiconductor element 61 on the first routing circuit 21. The second semiconductor element 61 (shown as a chip) is electrically coupled to the first routing circuit 21 through a bump 613 on the first routing circuit 21.

[Example 3]

FIG. 30 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, which is provided with a heat sink attached to the first semiconductor element.

For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated herein, and it is not necessary to repeat the same description.

The circuit board 300 is similar to the structure shown in FIG. 17. The only difference is that the electrical component 20 further includes a heat sink 26 attached to the non-active surface of the first semiconductor component 25. The heat sink 26 can be made of any material with high thermal conductivity (such as metal, alloy, silicon, ceramic, or graphite), and is thermally conducted to the second routing circuit 29. Accordingly, the heat generated by the first semiconductor element 25 can be dissipated through the heat sink 26, the second routing circuit 29, and the third routing circuit 51.

[Example 4]

FIG. 31 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention, in which a heating layer is provided with additional vertical connecting members.

For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated herein, and it is not necessary to repeat the same description.

The circuit board 400 is similar to the structure shown in FIG. 17. The only difference is that the circuit board 400 further includes an additional vertical connection member 41, which is located in the reinforcement layer 40 and is formed by an additional metallization blind in the dielectric layer 514. The hole 519 is electrically coupled to the third routing circuit 51. In this embodiment, the additional vertical connecting members 41 in the reinforcing layer 40 are shown as metal pillars.

32 is a cross-sectional view of a semiconductor assembly facing the second semiconductor element 61, the third semiconductor element 63, the fourth semiconductor element 65, and the fifth semiconductor element 67 on the wiring board 400 shown in FIG. 31. The second semiconductor element 61 is electrically coupled to the first routing circuit 21 in a flip-chip manner. The third semiconductor element 63 is connected to the third routing circuit 51 in a flip-chip manner. The fourth semiconductor element 65 is disposed on the second semiconductor element 61 and is electrically coupled to the first routing circuit 21. The fifth semiconductor element 67 is disposed on the fourth semiconductor element 65 and the reinforcing layer 40, and is electrically coupled to the vertical connecting member 41 of the reinforcing layer 40. In addition, a solder ball 75 may be connected to the third routing circuit 51 and surround the third semiconductor element 63.

The above-mentioned circuit boards and assemblies are merely illustrative examples, and the present invention can be implemented through various other embodiments. In addition, the above embodiments may be mixed and used with each other or with other embodiments based on design and reliability considerations. For example, the reinforcing layer may include a plurality of recesses arranged in an array shape, and each recess corresponds to an electrical component. In addition, the third routing circuit may include additional wires to receive and connect additional electrical components.

As shown in the above embodiment, the present invention constructs a unique circuit board that can exhibit better reliability, which includes a first routing circuit, a first semiconductor element, a series of vertical connectors, a sealing material, a second routing circuit, Strengthen the layer and the third routing circuit. For the convenience of the following description, the direction facing the first surface of the sealing material is defined as the first direction, and the direction facing the second surface of the sealing material is defined as the second direction. The first routing circuit is disposed adjacent to the first surface of the sealing material, and the second routing circuit is disposed adjacent to the second surface of the sealing material.

The first semiconductor element may be a packaged or unpackaged wafer. For example, the first semiconductor element may be a bare wafer, or a wafer-level package die. Alternatively, the first semiconductor element may be a stacked wafer. In a preferred embodiment, the first semiconductor element is electrically coupled to the first routing circuit (the first routing circuit is detachably connected to a sacrificial carrier board), and is vertically connected by the connecting member. Laterally surround, then provide a sealing material on the first routing circuit, and then form a second routing circuit on the sealing material to form an electrical component on the sacrificial carrier board. In this aspect, the first semiconductor element may be electrically coupled to the first routing circuit through a bump, and an active surface thereof faces the first routing circuit. Preferably, the electrical component and the sacrificial carrier are integrally prepared in a panel size, and then cut into individual single pieces. In addition, a heat sink can be attached to the first semiconductor element before the sealing material is provided. Accordingly, the heat generated by the first semiconductor element can be dissipated outward through the heat sink.

The thickness of the vertical connection member in the sealing material may be substantially equal to or less than the thickness of the sealing material, and the vertical connection member may provide electrical contacts for connecting lower-level routing circuits. More specifically, the vertical connectors are located between the first routing circuit and the second routing circuit, and opposite ends of the vertical connectors are electrically coupled to the first routing circuit and the second routing circuit, respectively.

The reinforcing layer surrounds the peripheral edges of the first routing circuit, the sealing material and the second routing circuit, and can be made of any material with sufficient mechanical strength to provide mechanical support for the circuit board and avoid warping of the circuit board. In a preferred embodiment, the reinforcing layer is directly bonded to the peripheral edge of the electrical component and the sacrificial carrier board, and extends laterally to the peripheral edge of the circuit board. In addition, an additional vertical connection member may be formed in the reinforcement layer to provide another semiconductor element or a heat sink that is electrically connected to the reinforcement layer from the first direction.

The first routing circuit, the second routing circuit, and the third routing circuit may be layer-added routing circuits without a core layer. The first routing circuit and the second routing circuit are disposed in a space surrounded by the inner wall surface of the reinforcing layer, and the third routing circuit is disposed outside the space surrounded by the inner wall surface of the reinforcing layer and extends laterally to the surface of the reinforcing layer. on. More specifically, the third routing circuit extends laterally beyond the peripheral edges of the first and second routing circuits, and the surface area of the third routing circuit is larger than the surface area of the first routing circuit and the surface area of the second routing circuit. Preferably, the third routing circuit extends to the peripheral edge of the circuit board, and substantially has an added surface area of the second routing circuit and the reinforcing layer.

The first routing circuit may include at least one dielectric layer and at least one wire layer, wherein the wire layer includes a metallized blind hole in the dielectric layer and extends laterally on the dielectric layer. The dielectric layer and the wire layer are alternately formed, and can be formed repeatedly if necessary. For example, the first routing circuit may include a routing layer, a dielectric layer, and a wire layer, wherein the routing layer is on a sacrificial carrier board, the dielectric layer is located on the routing layer and the sacrificial carrier board, and the wire layer is selected by the routing layer. It partially extends and fills the blind holes in the dielectric layer to form metallized blind holes, while extending laterally on the dielectric layer. If more signal routing is needed, the first routing circuit may further include an additional dielectric layer and an additional wire layer. In addition, the first routing circuit may optionally include one or more passive components embedded therein. In the present invention, the first routing circuit may be formed directly on the sacrificial carrier board, or the first routing circuit may be separately formed, and then the first routing circuit may be detachably attached to the sacrificial carrier board to complete the sacrificial carrier board. The step of forming a first routing circuit on the board. In the first routing circuit, the routing layer may include bonding pads that match the chip I / O pads. In addition, the routing line may optionally further include a stacking pad to provide an electrical contact to another semiconductor element (such as a plastic package or another semiconductor assembly). Therefore, the first routing circuit may be a multilayer routing circuit, and an exposed surface of the first routing circuit may have a bonding pad and a selective overlapping pad. Accordingly, in a preferred embodiment, the first routing circuit can provide a first-level fan-out routing / interconnection for the second semiconductor component to be placed on the exposed surface of the first routing circuit. The bonding pad, the selective overlapping pad, and the dielectric layer adjacent to the sacrificial carrier board may have surfaces facing the first direction and being substantially coplanar with each other. In addition, the reinforcing layer may extend in a first direction beyond the exposed surface of the first routing circuit, and after removing the sacrificial carrier board, a cavity is formed to expose the first routing circuit. Accordingly, the second semiconductor element can be placed in the cavity, and the second semiconductor element can be electrically coupled to the bonding pad exposed by the cavity.

The second routing circuit may include a routing layer that extends laterally on the second surface of the sealing material and is electrically coupled to the vertical connection member, while being thermally conducted to a selective heat sink on the non-active surface of the first semiconductor element. In addition, the second routing circuit may further include at least one dielectric layer and at least one wire layer, wherein the wire layer includes a metallized blind hole in the dielectric layer and extends laterally on the dielectric layer. The dielectric layer and the wire layer are alternately formed, and can be formed repeatedly if necessary. The innermost wire layer adjacent to the routing layer in the second routing circuit can be electrically coupled to the routing layer through a metalized blind hole in contact with the routing layer, and the outermost layer in the second routing circuit adjacent to the third routing circuit The wire layer can provide electrical contacts for the connection of lower-level routing circuits. Accordingly, the second routing circuit can provide an electrical connection between the vertical connection member and the third routing circuit.

The third routing circuit may be formed on the second routing circuit and extend laterally onto the surface of the reinforcement layer to provide further fan-out routing / interconnection. Since the third routing circuit can be electrically coupled to the second routing circuit of the electrical component through the metallized blind hole of the third routing circuit, the electrical connection between the second routing circuit and the third routing circuit does not require soldering. material. In addition, the interface between the reinforcement layer and the third routing circuit and between the second routing circuit and the third routing circuit does not require the use of soldering materials or adhesives. More specifically, the third routing circuit may include at least one dielectric layer and at least one wire layer, wherein the wire layer includes a metallized blind hole in the dielectric layer and extends laterally on the dielectric layer. The dielectric layer and the wire layer are alternately formed, and can be formed repeatedly if necessary. For example, the third routing circuit may include a dielectric layer and a wire layer, wherein the dielectric layer covers the electrical component and the reinforcing layer from the second direction, and the wire layer extends from the second routing circuit (and is optionally self-reinforcing). The additional vertical connections in the layer extend through the dielectric layer to form metallized blind holes, while extending laterally over the dielectric layer. If more signal routing is needed, the third routing circuit may further include an additional dielectric layer and an additional wire layer. According to this, the third routing circuit can contact and be electrically coupled to the second routing circuit of the electrical component to form a signal route, and the third routing circuit can be further electrically coupled to the additional vertical layer in the reinforcement layer. Connectors for signal routing or ground connection. The outermost wire layer of the third routing circuit can contain conductive contacts, such as bumps, solder balls, for electrical transmission and mechanical connection with the next-level assembly or another electronic component.

The invention also provides a face-to-face semiconductor assembly, which is a bonding pad for electrically coupling a second semiconductor element to the circuit board. More specifically, the second semiconductor element can be placed in a cavity of the circuit board, and various connection media (such as bumps) can be provided on the circuit board bonding pads to electrically connect the second semiconductor element to the circuit board. Accordingly, the first semiconductor element and the second semiconductor element can be electrically connected to each other by a first routing circuit therebetween, and the second semiconductor element can be further connected by a first routing circuit, a vertical connection, and a second routing circuit. Is electrically connected to the third routing circuit. In the face-to-face semiconductor assembly, the first routing circuit can provide the shortest interconnection distance between the first semiconductor element and the second semiconductor element. The second semiconductor element may be a packaged or unpackaged wafer. For example, the second semiconductor element may be a bare wafer, or a wafer-level package die. Alternatively, the second semiconductor element may be a stacked wafer.

In addition, an additional semiconductor element can be further provided, and the conductive element, such as a solder ball, can be used to electrically couple the additional semiconductor element to the stack pad of the circuit board. For example, the additional semiconductor element may be disposed above the second semiconductor element and electrically coupled to the bonding pad of the circuit board. Alternatively, a heat sink can be attached to the non-active surface of the second semiconductor element.

The term "coverage" means incomplete and complete coverage in vertical and / or lateral directions. For example, in the state where the cavity is upward, the second routing circuit covers the first routing circuit below, regardless of whether another component such as the first semiconductor component, the vertical connection member, and the sealing material is located in the first routing circuit and the second routing circuit. between.

The terms "connected to" and "attached to" include contact and non-contact with a single or multiple components. For example, the selective heat sink can be attached to the second semiconductor element, whether the heat sink contacts the second semiconductor element or is separated from the second semiconductor element by a thermally conductive adhesive or solder ball.

The terms "electrically connected" and "electrically coupled" mean directly or indirectly electrically connected. For example, in a preferred embodiment, the second routing circuit is directly in contact with and electrically connected to the vertical connector, and the third routing circuit is at a distance from the vertical connector and is electrically connected to the second routing circuit through the second routing circuit. Vertical connection.

The "first direction" and "second direction" do not depend on the orientation of the circuit board, and anyone who is familiar with this technique can easily understand the actual direction it refers to. For example, the first surface of the sealing material faces the first direction, and the second surface of the sealing material faces the second direction, which has nothing to do with whether the circuit board is inverted. Therefore, the first and second directions are opposite to each other and perpendicular to the side direction. Moreover, in the state where the cavity is upward, the first direction is an upward direction, and the second direction is a downward direction; in the state where the cavity is downward, the first direction is a downward direction, and the second direction is an upward direction. direction.

The circuit board of the present invention has many advantages. For example, the first semiconductor element is electrically coupled to the first routing circuit through a conventional flip-chip bonding process such as hot pressing or reflow, which can avoid the use of an adhesive carrier as a temporary bonding in a stackable system process. , You will encounter problems with location accuracy. The first routing circuit can provide a first-level fan-out / interconnection so that the second semiconductor element can be placed thereon, and the second routing circuit on the sealing material can provide a second-level fan-out / interconnection. The second routing circuit and the third routing circuit on the reinforcement layer can provide a third-level fan-out / interconnect and provide electrical contacts for the assembly of the next-level board. Thereby, the second semiconductor element with the fine pads can be electrically coupled to one side of the first routing circuit, wherein the pad pitch on the side is consistent with the second semiconductor element, and the third routing circuit can be connected via the first The two routing circuits and the vertical connection elements are electrically coupled to the other side of the first routing circuit to further enlarge the pad size and pad spacing of the second semiconductor element. The reinforcement layer can provide a bending-resistant platform for the third routing circuit to be formed thereon, so as to prevent the circuit board from warping. The circuit board prepared by this method has high reliability, low price, and is very suitable for mass production.

The manufacturing method of the present invention has high applicability, and uses various mature electrical and mechanical connection technologies in a unique and progressive way. In addition, the manufacturing method of the present invention can be implemented without expensive tools. Therefore, compared with the traditional technology, this production method can greatly improve the yield, yield, efficiency and cost effectiveness.

The embodiments described herein are for illustrative purposes, and the embodiments may simplify or omit elements or steps that are well known in the technical field, so as not to obscure the features of the present invention. Similarly, to make the drawings clear, the drawings may omit repeated or unnecessary components and component symbols.

100, 200, 300, 400‧‧‧ circuit boards

10‧‧‧ sacrificial carrier board

20‧‧‧ Electrical components

21‧‧‧First routing circuit

211, 291‧‧‧ routing layer

212‧‧‧Joint pad

213‧‧‧ Overlay pad

214, 294, 514‧‧‧ dielectric layers

216, 296, 516‧‧‧ wire layer

218, 293, 298, 518, 519‧‧‧ metallized blind holes

23, 41‧‧‧ vertical connector

231‧‧‧ the first end

233‧‧‧second end

25‧‧‧First semiconductor element

251‧‧‧active face

253, 613‧‧‧ bump

26, 81‧‧‧ Radiator

27‧‧‧sealing material

271‧‧‧First surface

272‧‧‧Second Surface

273‧‧‧ blind hole

29‧‧‧Second routing circuit

30‧‧‧Temporary carrier film

40‧‧‧Enhancement

405‧‧‧Dent

409‧‧‧ inside wall surface

51‧‧‧Third routing circuit

61‧‧‧Second semiconductor element

63‧‧‧Third semiconductor element

65‧‧‧ Fourth semiconductor element

67‧‧‧Fifth semiconductor element

75‧‧‧solder ball

L‧‧‧ cutting line

With reference to the accompanying drawings, the present invention can be more clearly understood through the detailed description of the following preferred embodiments, in which:

1 and 2 are respectively a cross-sectional view and a top perspective view of a routing layer formed on a sacrificial carrier board in a first embodiment of the present invention;

3 and 4 are a cross-sectional view and a top perspective view of the first embodiment of the present invention, wherein a multilayer dielectric layer and a multilayer wire layer are formed on the structure of FIGS.

5 is a cross-sectional view of a vertical connecting member formed on the structure of FIG. 4 in a first embodiment of the present invention;

FIG. 6 is a cross-sectional view of a first semiconductor element on the structure of FIG. 5 in a first embodiment of the present invention; FIG.

7 is a cross-sectional view of a sealing material formed on the structure of FIG. 6 in a first embodiment of the present invention;

8 is a cross-sectional view of a top region of the sealing material removed from the structure of FIG. 7 in a first embodiment of the present invention;

9 is a cross-sectional view of a routing layer formed on the structure of FIG. 8 in a first embodiment of the present invention;

10 is a cross-sectional view of a first embodiment of the present invention, a dielectric layer and a wire layer are formed on the structure of FIG. 9 to complete a second routing circuit on the sealing material;

FIG. 11 is a cross-sectional view of the panel dimensional structure of FIG. 10 after cutting in the first embodiment of the present invention; FIG.

12 is a cross-sectional view of a structure corresponding to the cut-off unit of FIG. 11 in a first embodiment of the present invention;

13 is a cross-sectional view of a temporary carrier film provided on the structure of FIG. 12 in a first embodiment of the present invention;

14 is a cross-sectional view of a reinforcing layer provided on the structure of FIG. 13 in a first embodiment of the present invention;

15 is a cross-sectional view of the first embodiment of the present invention, with the temporary carrier film removed from the structure of FIG. 4 and a third routing circuit formed;

FIG. 16 is a cross-sectional view of the top region of the reinforcing layer removed from the structure of FIG. 15 in the first embodiment of the present invention; FIG.

17 is a cross-sectional view of the first embodiment of the present invention, removing the sacrificial carrier board from the structure of FIG. 16 to complete the production of the circuit board;

18 is a cross-sectional view of a second semiconductor element facing a semiconductor assembly on a circuit board of FIG. 17 in a first embodiment of the present invention;

19 is a cross-sectional view of a heat sink provided on the semiconductor assembly in FIG. 18 in a first embodiment of the present invention;

20 is a cross-sectional view of a third semiconductor element and a solder ball provided on the semiconductor assembly in FIG. 19 in a first embodiment of the present invention;

21 is a cross-sectional view of the semiconductor assembly with the other side facing the first embodiment of the present invention;

22 is a cross-sectional view of a blind hole formed on the structure of FIG. 7 in a second embodiment of the present invention;

23 is a cross-sectional view of a routing layer formed on the structure of FIG. 22 in a second embodiment of the present invention;

FIG. 24 is a cross-sectional view of forming a dielectric layer and a wire layer on the structure of FIG. 23 to complete a second routing circuit on the sealing material in a second embodiment of the present invention; FIG.

25 is a cross-sectional view of the panel dimensional structure of FIG. 24 after being cut in a second embodiment of the present invention;

26 is a cross-sectional view of a structure corresponding to the cut-off unit of FIG. 24 in a second embodiment of the present invention;

27 is a cross-sectional view of a reinforcing layer formed on the structure of FIG. 26 in a second embodiment of the present invention;

FIG. 28 is a cross-sectional view of forming a third routing circuit on the structure of FIG. 27 and removing a sacrificial carrier board to form a cavity in the second embodiment of the present invention;

FIG. 29 is a cross-sectional view of a second semiconductor element facing a semiconductor assembly on a circuit board of FIG. 28 in a second embodiment of the present invention; FIG.

30 is a cross-sectional view of another circuit board in a third embodiment of the present invention;

31 is a cross-sectional view of another circuit board in a fourth embodiment of the present invention; and

32 is a cross-sectional view of a second semiconductor element, a third semiconductor element, a fourth semiconductor element, a fifth semiconductor element, and a solder ball provided in the structure of FIG. 31 in a fourth embodiment of the present invention.

Claims (11)

A circuit board includes: An electrical component includes a first semiconductor component, a sealing material, a series of vertical connectors, a first routing circuit, and a second routing circuit. The first semiconductor component has an active surface, and each of these Each of the vertical connectors has a first end and a second end, wherein (i) the sealing material laterally covers the first semiconductor element and the vertical connectors, and has a first surface facing the first routing circuit. And a second surface opposite to the first surface, (ii) the first routing circuit extends to the first surface of the sealing material, the active surface of the first semiconductor element, and the vertical connectors On the first ends so that the first semiconductor element and the vertical connectors are electrically coupled to the first routing circuit, and (iii) the second routing circuit is disposed on the second of the sealing material On the surface and on the second ends of the vertical connectors, so that the second routing circuit is electrically connected to the first routing circuit through the vertical connectors; A reinforcing layer laterally surrounding the electrical component, and an inner sidewall surface of the reinforcement layer is adjacent to a peripheral edge of the electrical component; and A third routing circuit is disposed on the second routing circuit and extends laterally on the reinforcement layer, wherein the third routing circuit is electrically coupled to the second routing circuit. The circuit board according to item 1 of the patent application scope, wherein the third routing circuit includes at least one wire layer extending laterally beyond a peripheral edge of the second routing circuit. The circuit board described in item 1 of the patent application scope further includes additional vertical connectors located in the reinforcing layer, wherein the additional vertical connectors are electrically coupled to the third routing circuit. The circuit board according to item 1 of the scope of patent application, wherein the first routing circuit has an exposed surface facing away from the first surface of the sealing material. The circuit board according to item 4 of the scope of patent application, wherein a portion of the inner wall surface of the reinforcing layer forms a recess with the exposed surface of the first routing circuit. A face-to-face semiconductor assembly includes: The circuit board as described in any one of claims 1 to 4 of the scope of patent application; and A second semiconductor element is electrically coupled to the first semiconductor element face to face through the first routing circuit between the first semiconductor element and the second semiconductor element. The face-to-face semiconductor assembly as described in item 6 of the scope of patent application, wherein a portion of the inner side wall surface of the reinforcing layer forms a recess with a surface of the first routing circuit, and the second semiconductor element is disposed In the cavity. The face-to-face semiconductor assembly according to item 6 of the patent application scope further includes: a heat sink, which is attached to a non-active surface of the second semiconductor element and extends laterally to the reinforcing layer. A method for manufacturing a circuit board includes: An electrical component is provided on a sacrificial carrier board. The electrical component includes a semiconductor component, a sealing material, a series of vertical connectors, a first routing circuit and a second routing circuit. (I) the first The routing circuit is detachably connected to the sacrificial carrier board and is adjacent to a first surface of the sealing material. (Ii) The semiconductor element and the vertical connectors are embedded in the sealing material, and are electrically conductive. Coupled to the first routing circuit, and (iii) the second routing circuit is disposed on an opposite second surface of the sealing material, and is electrically connected to the first routing circuit through the vertical connectors; Providing a reinforcing layer that surrounds the electrical component and the sacrificial carrier board laterally; Forming a third routing circuit, which is disposed on the second routing circuit and extends laterally on the reinforcement layer, wherein the third routing circuit is electrically coupled to the second routing circuit; and The sacrificial carrier board is removed from the first routing circuit. According to the manufacturing method described in item 9 of the scope of patent application, the step of providing the electrical component on the sacrificial carrier board includes: Providing the first routing circuit on the sacrificial carrier board, wherein the first routing circuit is detachably connected to the sacrificial carrier board; Electrically coupling the semiconductor element to the first routing circuit; Forming the vertical connections; Providing the sealing material on the first routing circuit; and The second routing circuit is formed on the sealing material. The manufacturing method according to item 9 of the scope of patent application, wherein the step of forming the third routing circuit includes: electrically coupling the third routing circuit to an additional vertical connection member in the reinforcing layer.