TWI704848B - Wiring board with embedded component and integrated stiffener, method of making the same and face-to-face semiconductor assembly using the same - Google Patents

Wiring board with embedded component and integrated stiffener, method of making the same and face-to-face semiconductor assembly using the same Download PDF

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TWI704848B
TWI704848B TW108107521A TW108107521A TWI704848B TW I704848 B TWI704848 B TW I704848B TW 108107521 A TW108107521 A TW 108107521A TW 108107521 A TW108107521 A TW 108107521A TW I704848 B TWI704848 B TW I704848B
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routing circuit
routing
circuit
layer
semiconductor element
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TW108107521A
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TW201940026A (en
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文強 林
王家忠
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鈺橋半導體股份有限公司
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

A wiring board includes an electronic component laterally surrounded by a stiffener, and a third routing circuitry disposed beyond the space laterally surrounded by the stiffener and extends over the stiffener. The electronic component includes a first routing circuitry, an encapsulant, an array of vertical connecting elements and a second routing circuitry integrated together. The mechanical robustness of the stiffener can prevent the wiring board from warping. The embedded semiconductor device is electrically coupled to the first routing circuitry and surrounded by the vertical connecting elements in electrical connection with the first and second routing circuitries. The first routing circuitry provides primary fan-out routing for another semiconductor device to be assembled on the wiring board, whereas the third routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the electronic component with the stiffener.

Description

具有嵌埋式元件及加強層之線路板、其製法及其面朝 面半導體組體 Circuit board with embedded components and reinforcement layer, its manufacturing method and its facing Faceted semiconductor assembly

本發明是關於一種線路板，尤指一種具有嵌埋式元件及加強層之線路板、其製法及面朝面半導體組體。 The present invention relates to a circuit board, in particular to a circuit board with embedded components and strengthening layers, its manufacturing method and a facing semiconductor assembly.

多媒體裝置之市場趨勢係傾向於更迅速且更薄型化之設計需求。其中一種方法是將電子元件(如電阻器、電容器)嵌埋於線路板中，使線路板的電性效能可獲得改善。當記憶體晶片或邏輯晶片嵌埋於線路板中時，可將另一元件接置於線路板上，以形成疊晶(chip-on-chip)的3D堆疊結構。美國專利案號8,453,323、8,525,337、8,618,652及8,836,114即是基於此目的而揭露各種具有嵌埋式元件之線路板。然而，此作法除了有難以控制的彎翹問題外，還有其他特性問題(如設計靈活度)尚未解決。 The market trend of multimedia devices is toward faster and thinner design requirements. One of the methods is to embed electronic components (such as resistors and capacitors) in the circuit board to improve the electrical performance of the circuit board. When the memory chip or logic chip is embedded in the circuit board, another component can be connected to the circuit board to form a chip-on-chip 3D stacked structure. US Patent Nos. 8,453,323, 8,525,337, 8,618,652, and 8,836,114 are based on this purpose to disclose various circuit boards with embedded components. However, in addition to the difficult-to-control bending problem with this approach, there are other characteristic problems (such as design flexibility) that have not been resolved.

為了上述理由及以下所述之其他理由，目前亟需發展一種具有嵌埋式元件之新式線路板，以解決路由要求，並確保超高封裝密度、高信號完整度、薄型化且低彎翹。 For the above reasons and other reasons described below, there is an urgent need to develop a new circuit board with embedded components to solve routing requirements and ensure ultra-high packaging density, high signal integrity, thinness and low warpage.

本發明之主要目的係提供一種線路板，其係將第一路由電路、嵌埋式半導體元件、密封材、一系列垂直連接件及第二路由電路設置於被加強層側向環繞之空間內，以避免線路板中央區域發生彎翹，俾可改善生產良率及元件級(device-level)可靠度。 The main purpose of the present invention is to provide a circuit board, which arranges the first routing circuit, the embedded semiconductor element, the sealing material, a series of vertical connectors and the second routing circuit in a space laterally surrounded by a reinforcing layer, In order to avoid bending and warping in the central area of the circuit board, the production yield and device-level reliability can be improved.

本發明之線路板更可包括第三路由電路，其位於加強層所側向環繞之空間外，並藉由第二路由電路及垂直連接件，電性連接至第一路由電路，以使線路板最外區域之彎翹現象獲得良好控制，且可藉由第一、第二及第三路由電路展現高度的路由靈活度。例如，可將第一路由電路建構為具有極高路由密度之初級扇出電路，而第三路由電路則建構成具有粗寬度/間距的進一步扇出路由，以利於下一級的板封裝(board assembling)。 The circuit board of the present invention may further include a third routing circuit, which is located outside the space laterally surrounded by the reinforcement layer, and is electrically connected to the first routing circuit through the second routing circuit and the vertical connector, so that the circuit board The warping phenomenon in the outermost area is well controlled, and a high degree of routing flexibility can be demonstrated by the first, second and third routing circuits. For example, the first routing circuit can be constructed as a primary fan-out circuit with extremely high routing density, and the third routing circuit can be constructed as a further fan-out routing with a thick width/pitch to facilitate the next level of board assembling. ).

依據上述及其他目的，本發明提供一種線路板，其包括一第一路由電路、一第一半導體元件、一密封材、一系列垂直連接件、一第二路由電路、一加強層及一第三路由電路。在此，第一路由電路、第一半導體元件、密封材、垂直連接件及第二路由電路整合成一電性元件，且該加強層環繞該電性元件。於一較佳具體實施例中，加強層具有鄰近電性元件外側邊緣之內側壁表面，且可對線路板提供高模數抗彎平台；第一半導體元件以覆晶方式接置於第一路由電路上，並封埋於密封材中，且被垂直連 接件所環繞；第一路由電路鄰接於密封材之一側，且對後續組裝其上的第二半導體元件提供初級的扇出路由，並提供第一及第二半導體元件間之最短路由距離；第二路由電路鄰接於密封材之另一側，並提供用於下一級路由電路連接之電性接點；垂直連接件位於第一路由電路與第二路由電路之間，並提供第一路由電路與第二路由電路間之電性連接；第三路由電路鄰接第二路由電路並側向延伸至加強層上，且第三路由電路可將電性元件與加強層機械接合，同時提供進一步的扇出路由，其中第三路由電路的墊間距及墊尺寸可符合下一級組體。 According to the above and other objectives, the present invention provides a circuit board, which includes a first routing circuit, a first semiconductor element, a sealing material, a series of vertical connectors, a second routing circuit, a reinforcement layer and a third Routing circuit. Here, the first routing circuit, the first semiconductor element, the sealing material, the vertical connecting member and the second routing circuit are integrated into an electrical element, and the reinforcing layer surrounds the electrical element. In a preferred embodiment, the reinforcement layer has an inner sidewall surface adjacent to the outer edge of the electrical element, and can provide a high-modulus bending platform for the circuit board; the first semiconductor element is connected to the first route by flip chip On the circuit, and encapsulated in the sealing material, and connected vertically Surrounded by the connector; the first routing circuit is adjacent to one side of the sealing material, and provides a primary fan-out routing for the second semiconductor element subsequently assembled on it, and provides the shortest route between the first and second semiconductor elements; The second routing circuit is adjacent to the other side of the sealing material and provides electrical contacts for the connection of the next-level routing circuit; the vertical connector is located between the first routing circuit and the second routing circuit and provides the first routing circuit Electrical connection with the second routing circuit; the third routing circuit is adjacent to the second routing circuit and extends laterally to the reinforcement layer, and the third routing circuit can mechanically join the electrical components with the reinforcement layer, while providing further fan Outgoing routing, where the pad spacing and pad size of the third routing circuit can match the next-level assembly.

於另一態樣中，本發明提供一種線路板，其包括：一電性元件，其包含一第一半導體元件、一密封材、一系列垂直連接件、一第一路由電路及一第二路由電路，其中(i)該第一半導體元件及該些垂直連接件電性耦接至該第一路由電路，(ii)該密封材側向覆蓋該第一半導體元件及該些垂直連接件，並具有面向該第一路由電路之一第一表面及相反於該第一表面之一第二表面，且(iii)該第二路由電路設於該密封材之該第二表面上，並藉由該些垂直連接件，電性連接至該第一路由電路；一加強層，其側向環繞該電性元件，且該加強層之內側壁表面鄰近於該電性元件之外圍邊緣；以及一第三路由電路，其設於該第二路由電路上，並側向延伸於該加強層上，其中該第三路由電路電性耦接至該第二路由電路。此外，本發明亦提供一種面朝面(face-to-face)半導體組體，其包括上述之線路板及一第二半導體元件，該第一半導體元件與該第二半導體元件藉由兩者間之第一路由電路，面朝面地相互電性耦接。 In another aspect, the present invention provides a circuit board, which includes: an electrical component including a first semiconductor component, a sealing material, a series of vertical connectors, a first routing circuit and a second routing A circuit, wherein (i) the first semiconductor element and the vertical connectors are electrically coupled to the first routing circuit, (ii) the sealing material laterally covers the first semiconductor element and the vertical connectors, and Having a first surface facing the first routing circuit and a second surface opposite to the first surface, and (iii) the second routing circuit is provided on the second surface of the sealing material, and The vertical connectors are electrically connected to the first routing circuit; a reinforcement layer, which laterally surrounds the electrical element, and the inner sidewall surface of the reinforcement layer is adjacent to the peripheral edge of the electrical element; and a third A routing circuit is arranged on the second routing circuit and extending laterally on the reinforcement layer, wherein the third routing circuit is electrically coupled to the second routing circuit. In addition, the present invention also provides a face-to-face semiconductor assembly, which includes the above-mentioned circuit board and a second semiconductor element, the first semiconductor element and the second semiconductor element The first routing circuits are electrically coupled to each other face to face.

於再一態樣中，本發明提供一種線路板之製作方法，其包括以下步驟：提供一電性元件於一犧牲載板上，該電性元件包含一半導體元件、一密封材、一系列垂直連接件、一第一路由電路及一第二路由電路，其中(i)該第一路由電路可拆分式地接置於該犧牲載板上，並鄰接該密封材之一第一表面，(ii)該半導體元件及該些垂直連接件嵌埋於該密封材中，且電性耦接至該第一路由電路，且(iii)該第二路由電路設於該密封材之一相反第二表面上，並藉由該些垂直連接件電性連接至該第一路由電路；提供一加強層，其側向環繞該電性元件及該犧牲載板；形成一第三路由電路，其設於該第二路由電路上，並側向延伸於該加強層上，其中該第三路由電路電性耦接至該第二路由電路；以及從該第一路由電路移除該犧牲載板。 In yet another aspect, the present invention provides a method for manufacturing a circuit board, which includes the following steps: providing an electrical component on a sacrificial carrier, the electrical component including a semiconductor component, a sealing material, a series of vertical Connector, a first routing circuit and a second routing circuit, wherein (i) the first routing circuit is detachably connected to the sacrificial carrier plate and adjacent to a first surface of the sealing material, ( ii) The semiconductor element and the vertical connectors are embedded in the sealing material, and are electrically coupled to the first routing circuit, and (iii) the second routing circuit is provided on one of the sealing materials opposite to the second On the surface, and electrically connected to the first routing circuit by the vertical connectors; providing a reinforcing layer that laterally surrounds the electrical component and the sacrificial carrier; forming a third routing circuit, which is set in On the second routing circuit and laterally extending on the reinforcement layer, wherein the third routing circuit is electrically coupled to the second routing circuit; and the sacrificial carrier board is removed from the first routing circuit.

除非特別描述或步驟間使用”接著”字詞，或者是必須依序發生之步驟，上述步驟之順序並無限制於以上所列，且可根據所需設計而變化或重新安排。 Unless specifically described or the word "following" is used between steps, or steps that must occur sequentially, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design.

本發明之線路板製作方法具有許多優點。舉例來說，於形成第三路由電路前，將犧牲載板及電性元件與加強層結合之作法是特別具有優勢的，其原因在於，該犧牲載板與該加強層可共同提供一穩定的平台，供第三路由電路之形成。於第一路由電路上形成密封材之作法可對線路板提供另一高模數之抗彎平台，藉此密封材及加強層之機械強度可避免移除犧牲載板後出現彎翹現象。此外，當需形成多層路由電路時，藉由三階段步驟以形成互連基板之作法可避免發生嚴重的彎曲問題。 The circuit board manufacturing method of the present invention has many advantages. For example, before forming the third routing circuit, it is particularly advantageous to combine the sacrificial carrier board and the electrical components with the reinforcing layer. The reason is that the sacrificial carrier board and the reinforcing layer can provide a stable Platform for the formation of the third routing circuit. The method of forming the sealing material on the first routing circuit can provide another high-modulus flexural platform for the circuit board, so that the mechanical strength of the sealing material and the reinforcing layer can avoid warping after the sacrificial carrier is removed. In addition, when a multilayer routing circuit needs to be formed, a three-stage method of forming an interconnect substrate can avoid serious bending problems.

本發明之上述及其他特徵與優點可藉由下述較佳實施例之詳細敘述更加清楚明瞭。 The above and other features and advantages of the present invention can be more clearly understood by the detailed description of the following preferred embodiments.

100、200、300、400:線路板 100, 200, 300, 400: circuit board

10:犧牲載板 10: Sacrifice carrier board

20:電性元件 20: Electrical components

21:第一路由電路 21: The first routing circuit

211、291:路由層 211, 291: routing layer

212:接合墊 212: Bonding pad

213:疊接墊 213: Stacking Pad

214、294、514:介電層 214, 294, 514: Dielectric layer

216、296、516:導線層 216, 296, 516: wire layer

218、293、298、518、519:金屬化盲孔 218, 293, 298, 518, 519: metalized blind holes

23、41:垂直連接件 23, 41: vertical connector

231:第一端 231: first end

233:第二端 233: second end

25:第一半導體元件 25: The first semiconductor component

251:主動面 251: Active Side

253、613:凸塊 253, 613: bump

26、81:散熱座 26, 81: heat sink

27:密封材 27: Sealing material

271:第一表面 271: First Surface

272:第二表面 272: second surface

273:盲孔 273: Blind Hole

29:第二路由電路 29: Second routing circuit

30:暫時載膜 30: Temporary film loading

40:加強層 40: Strengthening layer

405:凹穴 405: dent

409:內側壁表面 409: inner wall surface

51:第三路由電路 51: Third routing circuit

61:第二半導體元件 61: second semiconductor element

63:第三半導體元件 63: The third semiconductor element

65:第四半導體元件 65: Fourth semiconductor element

67:第五半導體元件 67: Fifth semiconductor element

75:焊球 75: solder ball

L:切割線 L: cutting line

參考隨附圖式，本發明可藉由下述較佳實施例之詳細敘述更加清楚明瞭，其中：圖1及2分別為本發明第一實施態樣中，於犧牲載板上形成路由層之剖視圖及頂部立體示意圖；圖3及4分別為本發明第一實施態樣中，圖1及2結構上形成多層介電層及多層導線層以於犧牲載板上完成第一路由電路製作之剖視圖及頂部立體示意圖；圖5為本發明第一實施態樣中，圖4結構上形成垂直連接件之剖視圖；圖6為本發明第一實施態樣中，圖5結構上接置第一半導體元件之剖視圖；圖7為本發明第一實施態樣中，圖6結構上形成密封材之剖視圖；圖8為本發明第一實施態樣中，自圖7結構移除密封材頂部區域之剖視圖；圖9為本發明第一實施態樣中，圖8結構上形成路由層之剖視圖；圖10為本發明第一實施態樣中，圖9結構上形成介電層及導線層以於密封材上完成第二路由電路製作之剖視圖；圖11為本發明第一實施態樣中，圖10之面板尺寸結構切割後之剖視圖； 圖12為本發明第一實施態樣中，對應於圖11切離單元之結構剖視圖；圖13為本發明第一實施態樣中，圖12結構上提供暫時載膜之剖視圖；圖14為本發明第一實施態樣中，圖13結構上提供加強層之剖視圖；圖15為本發明第一實施態樣中，自圖4結構移除暫時載膜並形成第三路由電路之剖視圖；圖16為本發明第一實施態樣中，自圖15結構移除加強層頂部區域之剖視圖；圖17為本發明第一實施態樣中，自圖16結構移除犧牲載板以完成線路板製作之剖視圖；圖18為本發明第一實施態樣中，第二半導體元件接置於圖17線路板上之面朝面半導體組體之剖視圖；圖19為本發明第一實施態樣中，圖18面朝面半導體組體上提供散熱座之剖視圖；圖20為本發明第一實施態樣中，圖19面朝面半導體組體上提供第三半導體元件及焊球之剖視圖；圖21為本發明第一實施態樣中，另一面朝面半導體組體之剖視圖；圖22為本發明第二實施態樣中，圖7結構上形成盲孔之剖視圖；圖23為本發明第二實施態樣中，圖22結構上形成路由層之剖視圖；圖24為本發明第二實施態樣中，圖23結構上形成介電層及導線層以於密封材上完成第二路由電路製作之剖視圖； 圖25為本發明第二實施態樣中，圖24之面板尺寸結構切割後之剖視圖；圖26為本發明第二實施態樣中，對應於圖24切離單元之結構剖視圖；圖27為本發明第二實施態樣中，圖26結構上形成加強層之剖視圖；圖28為本發明第二實施態樣中，圖27結構上形成第三路由電路並移除犧牲載板以形成凹穴，進而完成線路板製作之剖視圖；圖29為本發明第二實施態樣中，第二半導體元件接置於圖28線路板上之面朝面半導體組體之剖視圖；圖30為本發明第三實施態樣中，另一線路板之剖視圖；圖31為本發明第四實施態樣中，再一線路板之剖視圖；以及圖32為本發明第四實施態樣中，圖31結構上提供第二半導體元件、第三半導體元件、第四半導體元件、第五半導體元件及焊球之剖視圖。 With reference to the accompanying drawings, the present invention can be more clearly understood by the detailed description of the following preferred embodiments, in which: Figures 1 and 2 are respectively the first embodiment of the present invention in which the routing layer is formed on the sacrificial carrier Cross-sectional view and top perspective schematic view; Figures 3 and 4 are respectively a cross-sectional view of the first embodiment of the present invention, where a multilayer dielectric layer and a multilayer wire layer are formed on the structure of Figures 1 and 2 to complete the production of the first routing circuit on the sacrificial carrier And a top perspective schematic view; FIG. 5 is a cross-sectional view of the vertical connector formed on the structure of FIG. 4 in the first embodiment of the present invention; FIG. 6 is the first embodiment of the present invention in which the first semiconductor element is connected to the structure of FIG. 7 is a cross-sectional view of the sealing material formed on the structure of FIG. 6 in the first embodiment of the present invention; FIG. 8 is a cross-sectional view of the top area of the sealing material removed from the structure of FIG. 7 in the first embodiment of the present invention; 9 is a cross-sectional view of the routing layer formed on the structure in FIG. 8 in the first embodiment of the present invention; FIG. 10 is the first embodiment of the present invention in which a dielectric layer and a wire layer are formed on the sealing material A cross-sectional view of the completion of the second routing circuit; FIG. 11 is a cross-sectional view of the panel size structure of FIG. 10 after cutting in the first embodiment of the present invention; 12 is a cross-sectional view of the structure of the cut-off unit corresponding to FIG. 11 in the first embodiment of the present invention; FIG. 13 is a cross-sectional view of the temporary carrier film provided on the structure of FIG. 12 in the first embodiment of the present invention; In the first embodiment of the present invention, FIG. 13 is a cross-sectional view of the reinforcement layer provided on the structure; FIG. 15 is a cross-sectional view of the first embodiment of the present invention in which the temporary carrier film is removed from the structure of FIG. 4 and the third routing circuit is formed; FIG. This is a cross-sectional view of the top area of the reinforcing layer removed from the structure in FIG. 15 in the first embodiment of the present invention; FIG. 17 is the first embodiment of the present invention in which the sacrificial carrier is removed from the structure in FIG. 16 to complete the circuit board production. Fig. 18 is a cross-sectional view of the facing semiconductor assembly on the circuit board of Fig. 17 in the first embodiment of the present invention; Fig. 19 is the first embodiment of the present invention, Fig. 18 A cross-sectional view of a heat sink provided on the facing semiconductor assembly; FIG. 20 is a cross-sectional view of a third semiconductor element and solder balls provided on the facing semiconductor assembly in the first embodiment of the present invention; In the first embodiment, the other side is a cross-sectional view of the semiconductor assembly; FIG. 22 is a cross-sectional view of the blind hole formed in the structure of FIG. 7 in the second embodiment of the present invention; FIG. 23 is the second embodiment of the present invention 22 is a cross-sectional view of the routing layer formed on the structure; FIG. 24 is a cross-sectional view of the second embodiment of the present invention, the dielectric layer and the wire layer are formed on the structure of FIG. 23 to complete the second routing circuit on the sealing material; 25 is a cross-sectional view of the panel size structure of FIG. 24 after cutting in the second embodiment of the present invention; FIG. 26 is a cross-sectional view of the structure of the cut-off unit corresponding to FIG. 24 in the second embodiment of the present invention; In the second embodiment of the present invention, the cross-sectional view of the reinforcement layer formed on the structure in FIG. 26; FIG. 28 is the second embodiment of the present invention in which the third routing circuit is formed on the structure in FIG. 27 and the sacrificial carrier is removed to form the cavity. Then complete the cross-sectional view of the circuit board production; FIG. 29 is a cross-sectional view of the facing semiconductor assembly on the circuit board of FIG. 28 in the second embodiment of the present invention; FIG. 30 is the third embodiment of the present invention Fig. 31 is a cross-sectional view of another circuit board in the fourth embodiment of the present invention; and Fig. 32 is a cross-sectional view of another circuit board in the fourth embodiment of the present invention. Cross-sectional views of the semiconductor element, the third semiconductor element, the fourth semiconductor element, the fifth semiconductor element and the solder balls.

在下文中，將提供一實施例以詳細說明本發明之實施態樣。本發明之優點以及功效將藉由本發明所揭露之內容而更為顯著。在此說明所附之圖式係簡化過且做為例示用。圖式中所示之元件數量、形狀及尺寸可依據實際情況而進行修改，且元件的配置可能更為複雜。本發明中也可進行其他方面之實踐或應用，且不偏離本發明所定義之精神及範疇之條件下，可進行各種變化以及調整。 Hereinafter, an example will be provided to illustrate the implementation aspects of the present invention in detail. The advantages and effects of the present invention will be more obvious through the content disclosed by the present invention. The drawings attached to this description are simplified and used as examples. The number, shape, and size of the components shown in the drawings can be modified according to actual conditions, and the configuration of the components may be more complicated. The present invention can also be practiced or applied in other aspects, and various changes and adjustments can be made without departing from the spirit and scope defined by the present invention.

[實施例1] [Example 1]

圖1-17為本發明第一實施態樣中，一種線路板之製作方法圖，其包括一第一路由電路、一第一半導體元件、一系列垂直連接件、一密封材、一第二路由電路、一加強層及一第三路由電路。 1-17 is a diagram of a manufacturing method of a circuit board in the first embodiment of the present invention, which includes a first routing circuit, a first semiconductor element, a series of vertical connectors, a sealing material, and a second routing Circuit, a reinforcement layer and a third routing circuit.

圖1及2分別為犧牲載板10上形成路由層211之剖視圖及頂部立體示意圖，其中路由層211係藉由金屬沉積及金屬圖案化製程形成。於此圖中，該犧牲載板10為單層結構，且路由層211包括接合墊212及疊接墊213。該犧牲載板10通常由銅、鋁、鐵、鎳、錫、不鏽鋼、矽或其他金屬或合金製成，但亦可使用任何其他導電或非導電材料製成。犧牲載板10之厚度較佳於0.1至2.0毫米之範圍。於本實施態樣中，該犧牲載板10係由含鐵材料所製成，且厚度為1.0毫米。路由層211通常由銅所製成，且可經由各種技術進行圖案化沉積，如電鍍、無電電鍍、蒸鍍、濺鍍或其組合，或者藉由薄膜沉積而後進行金屬圖案化步驟而形成。就具導電性之犧牲載板10而言，一般是藉由金屬電鍍方式沉積，以形成路由層211。金屬圖案化技術包括濕蝕刻、電化學蝕刻、雷射輔助蝕刻及其組合，並使用蝕刻光罩(圖未示)，以定義出路由層211。 1 and 2 are respectively a cross-sectional view and a top perspective schematic view of a routing layer 211 formed on the sacrificial carrier 10, wherein the routing layer 211 is formed by metal deposition and metal patterning processes. In this figure, the sacrificial carrier 10 has a single-layer structure, and the routing layer 211 includes a bonding pad 212 and a stacking pad 213. The sacrificial carrier 10 is usually made of copper, aluminum, iron, nickel, tin, stainless steel, silicon or other metals or alloys, but it can also be made of any other conductive or non-conductive materials. The thickness of the sacrificial carrier 10 is preferably in the range of 0.1 to 2.0 mm. In this embodiment, the sacrificial carrier 10 is made of iron-containing material and has a thickness of 1.0 mm. The routing layer 211 is usually made of copper, and can be patterned and deposited by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof, or formed by thin film deposition followed by a metal patterning step. For the conductive sacrificial carrier 10, it is generally deposited by metal plating to form the routing layer 211. Metal patterning techniques include wet etching, electrochemical etching, laser-assisted etching, and combinations thereof, and use an etching mask (not shown) to define the routing layer 211.

圖3及4分別為交替輪流形成多層介電層214及多層導線層216之剖視圖及頂部立體示意圖。該些介電層214一般可藉由層壓或塗佈方式沉積而成，其可由環氧樹脂、玻璃環氧樹脂、聚醯亞胺、或其類似物所製成。該些導線層216側向延伸於介電層214上，並包含有位於介電層214中之金屬化盲孔218。據此，導線層216可藉由金屬化盲孔218相互電性耦接，且最內層的導線層216藉由金屬化盲孔218電性耦接至路由層211。 3 and 4 are respectively a cross-sectional view and a top perspective schematic view of alternately forming a multilayer dielectric layer 214 and a multilayer wire layer 216. The dielectric layers 214 can generally be deposited by laminating or coating, which can be made of epoxy resin, glass epoxy resin, polyimide, or the like. The wire layers 216 extend laterally on the dielectric layer 214 and include metalized blind holes 218 in the dielectric layer 214. Accordingly, the wire layers 216 can be electrically coupled to each other through the metalized blind holes 218, and the innermost wire layer 216 is electrically coupled to the routing layer 211 through the metalized blind holes 218.

每一導線層216可藉由各種技術沉積為單層或多層，如電鍍、無電電鍍、蒸鍍、濺鍍或其組合。舉例來說，首先藉由將該結構浸入活化劑溶液中，使介電層214與無電鍍銅產生觸媒反應，接著以無電電鍍方 式被覆一薄銅層作為晶種層，然後以電鍍方式將所需厚度之第二銅層形成於晶種層上。或者，於晶種層上沉積電鍍銅層前，該晶種層可藉由濺鍍方式形成如鈦/銅之晶種層薄膜。一旦達到所需之厚度，即可使用各種技術圖案化被覆層，以形成導線層216，其包括濕蝕刻、電化學蝕刻、雷射輔助蝕刻及其組合，並使用蝕刻光罩(圖未示)，以定義出導線層216。 Each wire layer 216 can be deposited as a single layer or multiple layers by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof. For example, firstly by immersing the structure in an activator solution, the dielectric layer 214 and electroless copper are reacted as a catalyst, and then electroless plating is used. In this way, a thin copper layer is used as the seed layer, and then a second copper layer of required thickness is formed on the seed layer by electroplating. Alternatively, before depositing an electroplated copper layer on the seed layer, the seed layer may be sputtered to form a seed layer film such as titanium/copper. Once the required thickness is reached, various techniques can be used to pattern the coating layer to form the wire layer 216, including wet etching, electrochemical etching, laser-assisted etching and combinations thereof, and an etching mask (not shown) , To define the wire layer 216.

據此，此階段便可於犧牲載板10上完成第一路由電路21之製作。於此圖中，該第一路由電路21包括路由層211、介電層214及導線層216。 Accordingly, at this stage, the fabrication of the first routing circuit 21 can be completed on the sacrificial carrier 10. In this figure, the first routing circuit 21 includes a routing layer 211, a dielectric layer 214, and a wire layer 216.

圖5為形成陣列式垂直連接件23於第一路由電路21上之剖視圖。於此圖中，該些垂直連接件23是繪示成金屬柱，其第一端231接觸且電性連接至第一路由電路21之最外層導線層216。 FIG. 5 is a cross-sectional view of forming an array type vertical connector 23 on the first routing circuit 21. In this figure, the vertical connectors 23 are shown as metal pillars, the first ends 231 of which are in contact with and electrically connected to the outermost wire layer 216 of the first routing circuit 21.

圖6為第一半導體元件25電性耦接至第一路由電路21之剖視圖。第一半導體元件25(繪示成裸晶片)可藉由熱壓、迴焊、或熱超音波接合技術，以主動面251朝向第一路由電路21之方式，經由凸塊253電性耦接至第一路由電路21之最外層導線層216。 FIG. 6 is a cross-sectional view of the first semiconductor device 25 being electrically coupled to the first routing circuit 21. The first semiconductor device 25 (shown as a bare chip) can be electrically coupled to the first routing circuit 21 through the bumps 253 by hot pressing, reflow, or thermal ultrasonic bonding technology, with the active surface 251 facing the first routing circuit 21 The outermost wire layer 216 of the first routing circuit 21.

圖7為形成密封材27於垂直連接件23、第一半導體元件25及第一路由電路21上之剖視圖，其中該密封材27可藉由如樹脂-玻璃層壓、樹脂-玻璃塗佈或模製(molding)方式形成。該密封材27由上方覆蓋垂直連接件23、第一半導體元件25及第一路由電路21，且環繞、同形披覆並覆蓋垂直連接件23及第一半導體元件25之側壁。 7 is a cross-sectional view of forming a sealing material 27 on the vertical connector 23, the first semiconductor element 25 and the first routing circuit 21, wherein the sealing material 27 can be laminated by resin-glass, resin-glass coating or mold Formed by molding. The sealing material 27 covers the vertical connector 23, the first semiconductor element 25 and the first routing circuit 21 from above, and surrounds, covers and covers the side walls of the vertical connector 23 and the first semiconductor element 25.

圖8為垂直連接件23由上方顯露之剖視圖。可藉由研磨方式，將密封材27之上部區域移除，以顯露垂直連接件23之第二端233。於此圖中，該些垂直連接件23之外露表面於上方與密封材27之外表面呈實質上共平面。 FIG. 8 is a cross-sectional view of the vertical connecting member 23 exposed from above. The upper area of the sealing material 27 can be removed by grinding to reveal the second end 233 of the vertical connecting member 23. In this figure, the exposed surfaces of the vertical connecting members 23 are substantially coplanar with the outer surface of the sealing material 27 above.

圖9為形成路由層291於密封材27上之剖視圖，其中路由層291係藉由如下所述之金屬圖案化沉積法形成，並電性耦接至垂直連接件23。首先，可藉由各種技術(如電鍍、無電電鍍、蒸鍍、濺鍍或其組合)，對結構頂面進行金屬化，以形成單層或多層的導電層(通常為銅層)。該導電層可由Cu、Ni、Ti、Au、Ag、Al、其組合或其他合適的導電材料製成。一般而言，會於電鍍導電層至所需厚度前先於結構的最頂面形成晶種層，其中晶種層可由一擴散阻層及一電鍍載層(plating bus layer)所構成。該擴散阻層係用於抵消導電層(如銅)的氧化或侵蝕。於大多數的實例中，擴散阻層亦可做為下層材料的黏著加強層，並可藉由物理氣相沉積法(PVD)形成，例如，可濺鍍形成厚度約0.01μm至0.1μm的Ti或TiW層。然而，擴散阻層亦可由其他材料製成，如TaN或其他適用的材料，其厚度並不限於上述範圍。電鍍載層通常係由相同於導電層的材料製成，其厚度範圍約為0.1μm至1μm。舉例說明，若導電層為銅時，電鍍載層較佳為物理氣相沉積法或無電電鍍法所製成之銅薄膜。然而，電鍍載層亦可由其他適用的材料製成，如銀、金、鉻、鎳、鎢或其組合，其厚度並不限於上述範圍。 9 is a cross-sectional view of forming a routing layer 291 on the sealing material 27, wherein the routing layer 291 is formed by a metal patterned deposition method as described below, and is electrically coupled to the vertical connector 23. First, various techniques (such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof) can be used to metalize the top surface of the structure to form a single-layer or multi-layer conductive layer (usually a copper layer). The conductive layer can be made of Cu, Ni, Ti, Au, Ag, Al, combinations thereof, or other suitable conductive materials. Generally, a seed layer is formed on the top surface of the structure before the conductive layer is electroplated to a desired thickness. The seed layer may be composed of a diffusion barrier layer and a plating bus layer. The diffusion resistance layer is used to offset the oxidation or erosion of the conductive layer (such as copper). In most cases, the diffusion barrier layer can also be used as an adhesion enhancement layer for the underlying material, and can be formed by physical vapor deposition (PVD). For example, it can be sputtered to form Ti with a thickness of about 0.01 μm to 0.1 μm. Or TiW layer. However, the diffusion barrier layer can also be made of other materials, such as TaN or other suitable materials, and its thickness is not limited to the above range. The electroplating carrier layer is usually made of the same material as the conductive layer, and its thickness ranges from about 0.1 μm to 1 μm. For example, if the conductive layer is copper, the electroplating support layer is preferably a copper film made by physical vapor deposition or electroless plating. However, the electroplating carrier layer can also be made of other suitable materials, such as silver, gold, chromium, nickel, tungsten or a combination thereof, and its thickness is not limited to the above range.

於沉積晶種層後，於晶種層上形成光阻層(圖未示)。該光阻層可藉由濕式製程(如旋塗製程)或乾式製程(如壓合乾膜)而形成。於形成光阻層後，再對光阻層進行圖案化，以形成開孔，隨後於開孔中填滿披覆金屬(如銅)，進而形成路由層291。鍍上金屬後，再透過蝕刻製程，以移除顯露的晶種層，進而形成彼此電隔離的導線。 After depositing the seed layer, a photoresist layer (not shown) is formed on the seed layer. The photoresist layer can be formed by a wet process (such as a spin coating process) or a dry process (such as a dry film laminating). After the photoresist layer is formed, the photoresist layer is patterned to form openings, and then the openings are filled with cladding metal (such as copper) to form a routing layer 291. After the metal is plated, an etching process is performed to remove the exposed seed layer, thereby forming conductive lines electrically isolated from each other.

圖10為交替輪流形成介電層294及導線層296之剖視圖。介電層294接觸密封材27及路由層291，並由上方覆蓋且側向延伸於密封材27及路由層291上。導線層296側向延伸於該介電層294上，並包含有位於介 電層294中之金屬化盲孔298。據此，導線層296可藉由金屬化盲孔298，電性耦接至路由層291。 10 is a cross-sectional view of alternately forming the dielectric layer 294 and the wire layer 296 in turn. The dielectric layer 294 contacts the sealing material 27 and the routing layer 291, is covered from above and extends laterally on the sealing material 27 and the routing layer 291. The wire layer 296 extends laterally on the dielectric layer 294 and includes Metalized blind holes 298 in the electrical layer 294. Accordingly, the wire layer 296 can be electrically coupled to the routing layer 291 by metalizing the blind via 298.

此階段已完成第二路由電路29之製作，其藉由垂直連接件23，電性連接至第一路由電路21。於此圖中，第二路由電路29包含有路由層291、介電層294及導線層296。 At this stage, the production of the second routing circuit 29 has been completed, which is electrically connected to the first routing circuit 21 through the vertical connection member 23. In this figure, the second routing circuit 29 includes a routing layer 291, a dielectric layer 294, and a wire layer 296.

圖11為將圖10之面板尺寸結構切割成個別單件之剖視圖。如圖所示，沿著切割線“L”，將面板尺寸結構單離成個別單件。 Figure 11 is a cross-sectional view of the panel size structure of Figure 10 cut into individual pieces. As shown in the figure, along the cutting line "L", separate the panel size structure into individual pieces.

圖12為個別單件之剖視圖，其中該個別單件包括一犧牲載板10及位於該犧牲載板10上之一電性元件20。該電性元件20包含第一路由電路21、垂直連接件23、第一半導體元件25、密封件27及第二路由電路29。於此圖中，第一路由電路21及第二路由電路29為多層增層電路，其分別位於密封材27之相反兩側，並藉由垂直連接件23相互電性連接。第一路由電路21係可拆分式地接置於犧牲載板10上，並鄰接於密封材27之第一表面271。該第一路由電路21包含有與犧牲載板10接觸之接合墊212及疊接墊213。第一半導體元件25嵌埋於密封材27中，且電性耦接至第一路由電路21。該些垂直連接件23封埋於密封材27中，並環繞第一半導體元件25，且由第一路由電路21延伸至密封材27之第二表面272。第二路由電路29設於密封材27之第二表面272上，並電性耦接至垂直連接件23。 FIG. 12 is a cross-sectional view of an individual unit. The individual unit includes a sacrificial carrier 10 and an electrical component 20 on the sacrificial carrier 10. The electrical component 20 includes a first routing circuit 21, a vertical connector 23, a first semiconductor component 25, a sealing component 27 and a second routing circuit 29. In this figure, the first routing circuit 21 and the second routing circuit 29 are multi-layer build-up circuits, which are respectively located on opposite sides of the sealing material 27 and are electrically connected to each other by vertical connectors 23. The first routing circuit 21 is detachably connected to the sacrificial carrier 10 and adjacent to the first surface 271 of the sealing material 27. The first routing circuit 21 includes a bonding pad 212 and a stacking pad 213 that are in contact with the sacrificial carrier 10. The first semiconductor element 25 is embedded in the sealing material 27 and is electrically coupled to the first routing circuit 21. The vertical connectors 23 are embedded in the sealing material 27 and surround the first semiconductor element 25, and extend from the first routing circuit 21 to the second surface 272 of the sealing material 27. The second routing circuit 29 is provided on the second surface 272 of the sealing material 27 and is electrically coupled to the vertical connector 23.

圖13為暫時載膜30貼附至電性元件20之剖視圖。該暫時載膜30可對具有犧牲載板10及電性元件20之個別單件提供暫時固定力。於此圖中，可使暫時載膜30接觸第二路由電路29，以藉由暫時載膜30之黏性，使個別單件穩固地固定於暫時載膜30上。 FIG. 13 is a cross-sectional view of the temporary carrier film 30 attached to the electrical device 20. The temporary carrier film 30 can provide a temporary fixing force to individual single pieces having the sacrificial carrier board 10 and the electrical components 20. In this figure, the temporary carrier film 30 can be brought into contact with the second routing circuit 29, so that the individual single pieces can be firmly fixed on the temporary carrier film 30 by virtue of the adhesiveness of the temporary carrier film 30.

圖14為形成加強層40之剖視圖。該加強層40可藉由模製(molding)、印刷或其他方法(如環氧樹脂或聚醯亞胺之層壓)形成。該加強 層40是由上方覆蓋犧牲載板10及暫時載膜30，同時側向覆蓋、環繞且同形披覆犧牲載板10及電性元件20之側壁，並由犧牲載板10及電性元件20側向延伸至結構的外圍邊緣。 FIG. 14 is a cross-sectional view of forming the reinforcing layer 40. The reinforcing layer 40 can be formed by molding, printing or other methods (such as laminating epoxy resin or polyimide). Should strengthen The layer 40 covers the sacrificial carrier 10 and the temporary carrier film 30 from above, and at the same time laterally covers, surrounds and covers the sidewalls of the sacrificial carrier 10 and the electrical components 20 in the same shape, and is formed by the sacrificial carrier 10 and the electrical components 20 Extends to the outer edge of the structure.

圖15為移除暫時載膜30並形成第三路由電路51之剖視圖，其中第三路由電路51係電性耦接至電性元件20。將暫時載膜30從電性元件20及加強層40移除，接著於電性元件20及加強層40上形成第三路由電路51。該第三路由電路51側向延伸超過第二路由電路29之外圍邊緣，並延伸至加強層40之一表面上。於此圖中，該第三路由電路51為多層增層電路，其包括交替輪流形成之多層介電層514及多層導線層516。介電層514由下方覆蓋電性元件20及加強層41。導線層516側向延伸於介電層514上，並側向延伸超過第二路由電路29之外圍邊緣。此外，導線層516包括位於介電層514中之金屬化盲孔518。據此，導線層516可藉由金屬化盲孔518相互電性耦接，而最內層導線層516藉由金屬化盲孔518電性耦接至第二路由電路29之導線層296。 15 is a cross-sectional view of removing the temporary carrier film 30 and forming a third routing circuit 51, wherein the third routing circuit 51 is electrically coupled to the electrical element 20. The temporary carrier film 30 is removed from the electrical element 20 and the reinforcement layer 40, and then a third routing circuit 51 is formed on the electrical element 20 and the reinforcement layer 40. The third routing circuit 51 extends laterally beyond the peripheral edge of the second routing circuit 29 and extends to a surface of the reinforcement layer 40. In this figure, the third routing circuit 51 is a multilayer build-up circuit, which includes a multilayer dielectric layer 514 and a multilayer wire layer 516 alternately formed. The dielectric layer 514 covers the electrical element 20 and the reinforcement layer 41 from below. The wire layer 516 laterally extends on the dielectric layer 514 and laterally extends beyond the peripheral edge of the second routing circuit 29. In addition, the wire layer 516 includes metalized blind vias 518 in the dielectric layer 514. Accordingly, the wire layers 516 can be electrically coupled to each other through the metalized blind holes 518, and the innermost wire layer 516 is electrically coupled to the wire layer 296 of the second routing circuit 29 through the metalized blind holes 518.

圖17為移除犧牲載板10之剖視圖。可藉由各種方式移除犧牲載板10，以由上方顯露第一路由電路21，包括使用酸性溶液(如氯化鐵、硫酸銅溶液)或鹼性溶液(如氨溶液)之濕蝕刻、電化學蝕刻、或於機械方式(如鑽孔或端銑)後再進行化學蝕刻。於此實施態樣中，由含鐵材料所製成之犧牲載板10可藉由化學蝕刻溶液移除，其中化學蝕刻溶液於銅與鐵間具有選擇性，以避免移除犧牲載板10時導致銅路由層211遭蝕刻。因此，第一路由電路21之外露表面203與加強層40內側壁表面409之一部分共同形成一凹穴405。 FIG. 17 is a cross-sectional view of the sacrificial carrier board 10 removed. The sacrificial carrier 10 can be removed in various ways to expose the first routing circuit 21 from above, including wet etching and electrochemical treatment using acidic solutions (such as ferric chloride, copper sulfate solution) or alkaline solutions (such as ammonia solution) Learn to etch, or perform chemical etching after mechanical means (such as drilling or end milling). In this embodiment, the sacrificial carrier 10 made of iron-containing material can be removed by a chemical etching solution, wherein the chemical etching solution is selective between copper and iron to avoid removing the sacrificial carrier 10 As a result, the copper routing layer 211 is etched. Therefore, the exposed surface 203 of the first routing circuit 21 and a portion of the inner sidewall surface 409 of the reinforcing layer 40 jointly form a cavity 405.

據此，如圖17所示，已完成之線路板100包括第一路由電路21、垂直連接件23、第一半導體元件25、密封材27、第二路由電路29、加 強層40及第三路由電路51，其中第一路由電路21、第二路由電路29及第三路由電路51皆為不具有核心層之多層增層電路。 Accordingly, as shown in FIG. 17, the completed circuit board 100 includes a first routing circuit 21, a vertical connector 23, a first semiconductor element 25, a sealing material 27, a second routing circuit 29, and The strong layer 40 and the third routing circuit 51, wherein the first routing circuit 21, the second routing circuit 29 and the third routing circuit 51 are all multilayer build-up circuits without a core layer.

第一路由電路21、垂直連接件23、第一半導體元件25、密封材27及第二路由電路29被加強層40側向包圍。第一路由電路21、密封材27及與第二路由電路29的外圍邊緣接合至加強層40之內側壁表面409。第一半導體元件25及垂直連接件23封埋於密封材27中，並電性連接至第一路由電路21。第一路由電路21鄰接密封材27之第一表面271，並從凹穴405顯露。第二路由電路29鄰接密封材27之第二表面272，並藉由垂直連接件23電性連接至第一路由電路21。第三路由電路51設於第二路由電路29上，並側向延伸至線路板100之外圍邊緣。據此，第一路由電路21之外露表面203面積即小於第三路由電路51之表面面積(即，介電層214下表面的面積)。 The first routing circuit 21, the vertical connecting member 23, the first semiconductor element 25, the sealing material 27 and the second routing circuit 29 are laterally surrounded by the reinforcing layer 40. The peripheral edges of the first routing circuit 21, the sealing material 27 and the second routing circuit 29 are joined to the inner sidewall surface 409 of the reinforcing layer 40. The first semiconductor element 25 and the vertical connecting member 23 are encapsulated in the sealing material 27 and electrically connected to the first routing circuit 21. The first routing circuit 21 is adjacent to the first surface 271 of the sealing material 27 and is exposed from the cavity 405. The second routing circuit 29 is adjacent to the second surface 272 of the sealing material 27 and is electrically connected to the first routing circuit 21 through the vertical connector 23. The third routing circuit 51 is disposed on the second routing circuit 29 and extends laterally to the peripheral edge of the circuit board 100. Accordingly, the area of the exposed surface 203 of the first routing circuit 21 is smaller than the surface area of the third routing circuit 51 (ie, the area of the lower surface of the dielectric layer 214).

第三路由電路51藉由第三路由電路51之金屬化盲孔518，電性耦接至第二路由電路29，且第三路由電路51包含有延伸超過電性元件20外圍邊緣之導線層516。藉此，第三路由電路51不僅可提供進一步的扇出線路結構，其亦可使電性元件20與加強層40機械接合。 The third routing circuit 51 is electrically coupled to the second routing circuit 29 through the metalized blind via 518 of the third routing circuit 51, and the third routing circuit 51 includes a wire layer 516 extending beyond the peripheral edge of the electrical element 20 . In this way, the third routing circuit 51 can not only provide a further fan-out circuit structure, but also mechanically connect the electrical element 20 and the reinforcement layer 40.

加強層40環繞於第一路由電路21、密封材27及第二路由電路29之外圍邊緣，並側向延伸至線路板100之外圍邊緣，用以提供機械支撐並避免線路板100發生彎翹狀況。加強層40之內側壁表面409向上延伸超過第一路由電路21之外露表面203，以環繞凹穴405。 The reinforcing layer 40 surrounds the outer edges of the first routing circuit 21, the sealing material 27 and the second routing circuit 29, and extends laterally to the outer edge of the circuit board 100 to provide mechanical support and avoid warping of the circuit board 100 . The inner sidewall surface 409 of the reinforcement layer 40 extends upwardly beyond the exposed surface 203 of the first routing circuit 21 to surround the cavity 405.

圖18為第二半導體元件61接置於圖17所示線路板100上之面朝面半導體組體剖視圖，其中該第二半導體元件61係繪示成一晶片進行說明。第二半導體元件61係位於凹穴405內，並以覆晶方式透過凸塊613而接置於第一路由電路21上。據此，第二半導體元件61可藉由第一半導體元 件25與第二半導體元件61間之第一路由電路21，而與第一半導體元件25面朝面地相互電性連接。 18 is a cross-sectional view of the face-to-face semiconductor assembly with the second semiconductor element 61 connected to the circuit board 100 shown in FIG. 17, wherein the second semiconductor element 61 is shown as a chip for illustration. The second semiconductor element 61 is located in the cavity 405 and is connected to the first routing circuit 21 through bumps 613 in a flip chip manner. Accordingly, the second semiconductor element 61 can be The first routing circuit 21 between the component 25 and the second semiconductor element 61 is electrically connected to the first semiconductor element 25 face to face.

圖19為圖18所示之面朝面半導體組體上更設置散熱座81之剖視圖。散熱座81可由任何具有高導熱性之材料製成，如金屬、合金、矽、陶瓷或石墨，其貼附於第二半導體元件61之非主動面上，並側向延伸至加強層40上。據此，第二半導體元件61所產生的熱可藉由散熱座81散出。 19 is a cross-sectional view of the facing semiconductor assembly shown in FIG. 18 with a heat sink 81 further provided. The heat sink 81 can be made of any material with high thermal conductivity, such as metal, alloy, silicon, ceramic or graphite, which is attached to the inactive surface of the second semiconductor element 61 and extends laterally to the reinforcing layer 40. Accordingly, the heat generated by the second semiconductor element 61 can be dissipated by the heat sink 81.

圖20為圖19所示之面朝面半導體組體上更設置第三半導體元件63並選擇性設置焊球75之剖視圖。第三半導體元件63以覆晶方式，透過凸塊633而接置於第三路由電路51之導線層516上。焊球75接置於第三路由電路51之導線層516上，並環繞第三半導體元件63。 20 is a cross-sectional view of the face-to-face semiconductor assembly shown in FIG. 19 with a third semiconductor element 63 and optionally solder balls 75 disposed thereon. The third semiconductor element 63 is connected to the conductive layer 516 of the third routing circuit 51 through bumps 633 in a flip chip manner. The solder ball 75 is connected to the wire layer 516 of the third routing circuit 51 and surrounds the third semiconductor element 63.

圖21為圖17所示之線路板100上接置第二半導體元件61、第三半導體元件63及第四半導體元件65之另一面朝面半導體組體的剖視圖。第二半導體元件61設置於線路板100之凹穴405內，並電性耦接至第一路由電路21之接合墊212。第三半導體元件63以覆晶方式接置於第三路由電路51之導線層516上。第四半導體元件65設置於第二半導體元件61上，並電性耦接至第一路由電路21之疊接墊213。可選擇性地將複數焊球75接置於第三路由電路51之導線層516上，使焊球75環繞第三半導體元件63。 21 is a cross-sectional view of the circuit board 100 shown in FIG. 17 with the second semiconductor element 61, the third semiconductor element 63 and the fourth semiconductor element 65 connected to the other side facing the semiconductor assembly. The second semiconductor element 61 is disposed in the cavity 405 of the circuit board 100 and is electrically coupled to the bonding pad 212 of the first routing circuit 21. The third semiconductor element 63 is connected to the wire layer 516 of the third routing circuit 51 in a flip chip manner. The fourth semiconductor element 65 is disposed on the second semiconductor element 61 and is electrically coupled to the overlap pad 213 of the first routing circuit 21. A plurality of solder balls 75 can be selectively connected to the wire layer 516 of the third routing circuit 51 so that the solder balls 75 surround the third semiconductor element 63.

[實施例2] [Example 2]

圖22-28為本發明第二實施態樣之線路板製作方法圖，其第二路由電路是藉由密封材中之金屬化盲孔，電性耦接至垂直連接件。 22-28 are diagrams of the circuit board manufacturing method of the second embodiment of the present invention. The second routing circuit is electrically coupled to the vertical connector through the metalized blind hole in the sealing material.

為了簡要說明之目的，上述實施例1中任何可作相同應用之敘述皆併於此，且無須再重複相同敘述。 For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated herein, and the same description is not required to be repeated.

圖22為於圖7結構之密封材27中更形成盲孔273之剖視圖。可藉由各種技術形成盲孔273，其包括雷射鑽孔、電漿蝕刻及微影技術，且 盲孔273通常具有50微米之直徑。可使用脈衝雷射提高雷射鑽孔效能。或者，可使用掃描雷射光束，並搭配金屬光罩。該些盲孔273對準垂直連接件23之選定部位，以由上方顯露垂直連接件23。 22 is a cross-sectional view of a blind hole 273 further formed in the sealing material 27 of the structure in FIG. 7. Blind holes 273 can be formed by various techniques, including laser drilling, plasma etching, and lithography, and The blind holes 273 usually have a diameter of 50 microns. Pulse laser can be used to improve the efficiency of laser drilling. Alternatively, a scanning laser beam can be used with a metal mask. The blind holes 273 are aligned with selected positions of the vertical connecting member 23 to expose the vertical connecting member 23 from above.

圖23為形成路由層291於密封材27上之剖視圖，其中路由層291是藉由金屬化盲孔293，電性耦接至垂直連接件23。該路由層291自垂直連接件23向上延伸，並填滿盲孔273，以形成直接接觸垂直連接件23之金屬化盲孔293，且側向延伸於密封材27之第二表面272上。因此，路由層291可提供X及Y方向的水平信號路由以及穿過盲孔273的垂直路由，以作為垂直連接件23的電性連接。 FIG. 23 is a cross-sectional view of forming a routing layer 291 on the sealing material 27, wherein the routing layer 291 is electrically coupled to the vertical connector 23 through a metalized blind hole 293. The routing layer 291 extends upward from the vertical connection member 23 and fills the blind hole 273 to form a metalized blind hole 293 directly contacting the vertical connection member 23 and extends laterally on the second surface 272 of the sealing material 27. Therefore, the routing layer 291 can provide horizontal signal routing in the X and Y directions and vertical routing through the blind holes 273 to serve as electrical connections for the vertical connectors 23.

圖24為交替輪流形成介電層294及導線層296之剖視圖。介電層294接觸密封材27及路由層291，並由上方覆蓋且側向延伸於密封材27及路由層291上。導線層296側向延伸於該介電層294上，並包含有位於介電層294中之金屬化盲孔298。據此，導線層296可藉由金屬化盲孔298，電性耦接至路由層291。 24 is a cross-sectional view of alternately forming the dielectric layer 294 and the conductive layer 296 in turn. The dielectric layer 294 contacts the sealing material 27 and the routing layer 291, is covered from above and extends laterally on the sealing material 27 and the routing layer 291. The wire layer 296 extends laterally on the dielectric layer 294 and includes a metalized blind hole 298 in the dielectric layer 294. Accordingly, the wire layer 296 can be electrically coupled to the routing layer 291 by metalizing the blind via 298.

此階段已完成第二路由電路29之製作，其藉由垂直連接件23，電性連接至第一路由電路21。於此圖中，第二路由電路29包含有路由層291、介電層294及導線層296。 At this stage, the production of the second routing circuit 29 has been completed, which is electrically connected to the first routing circuit 21 through the vertical connection member 23. In this figure, the second routing circuit 29 includes a routing layer 291, a dielectric layer 294, and a wire layer 296.

圖25為將圖24之面板尺寸結構切割成個別單件之剖視圖。如圖所示，沿著切割線“L”，將面板尺寸結構單離成個別單件。 Figure 25 is a cross-sectional view of the panel size structure of Figure 24 being cut into individual pieces. As shown in the figure, along the cutting line "L", separate the panel size structure into individual pieces.

圖26為個別單件之剖視圖，其中該個別單件包括一犧牲載板10及位於該犧牲載板10上之一電性元件20。該電性元件20包含第一路由電路21、垂直連接件23、第一半導體元件25、密封件27及第二路由電路29。 FIG. 26 is a cross-sectional view of an individual unit, where the individual unit includes a sacrificial carrier 10 and an electrical component 20 on the sacrificial carrier 10. The electrical component 20 includes a first routing circuit 21, a vertical connector 23, a first semiconductor component 25, a sealing component 27 and a second routing circuit 29.

圖27為加強層40接合至犧牲載板10、第一路由電路21、密封材27及第二路由電路29外圍邊緣之剖視圖。於此圖中，加強層40之頂面 與犧牲載板10之外表面呈實質上共平面，而加強層40之底面則與第二路由電路29導線層296的外表面呈實質上共平面。 27 is a cross-sectional view of the reinforcement layer 40 being bonded to the sacrificial carrier 10, the first routing circuit 21, the sealing material 27, and the peripheral edge of the second routing circuit 29. In this figure, the top surface of the reinforcement layer 40 It is substantially coplanar with the outer surface of the sacrificial carrier 10, and the bottom surface of the reinforcement layer 40 is substantially coplanar with the outer surface of the wire layer 296 of the second routing circuit 29.

圖28為移除犧牲載板10並沉積第三路由電路51以電性耦接電性元件20之線路板200剖視圖。由銅製成之犧牲載板10可藉由鹼性蝕刻溶液來移除。第三路由電路51側向延伸超過第二路由電路29之外圍邊緣，並延伸至加強層40表面上。於此圖中，該第三路由電路51為多層增層電路，其包括交替輪流形成之多層介電層514及多層導線層516。於形成第三路由電路51後，移除犧牲載板10，以形成凹穴405。 FIG. 28 is a cross-sectional view of the circuit board 200 with the sacrificial carrier board 10 removed and the third routing circuit 51 deposited to electrically couple the electrical components 20. The sacrificial carrier 10 made of copper can be removed by an alkaline etching solution. The third routing circuit 51 extends laterally beyond the peripheral edge of the second routing circuit 29 and extends to the surface of the reinforcement layer 40. In this figure, the third routing circuit 51 is a multilayer build-up circuit, which includes a multilayer dielectric layer 514 and a multilayer wire layer 516 alternately formed. After the third routing circuit 51 is formed, the sacrificial carrier 10 is removed to form the cavity 405.

圖29為第二半導體元件61接置於第一路由電路21上之面朝面半導體組體剖視圖。該第二半導體元件61(繪示成晶片)藉由第一路由電路21上之凸塊613，電性耦接至第一路由電路21。 FIG. 29 is a cross-sectional view of the facing semiconductor assembly with the second semiconductor element 61 connected to the first routing circuit 21. The second semiconductor element 61 (shown as a chip) is electrically coupled to the first routing circuit 21 through bumps 613 on the first routing circuit 21.

[實施例3] [Example 3]

圖30為本發明第三實施態樣之線路板剖視圖，其設有散熱座貼附於第一半導體元件上。 30 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, which is provided with a heat sink attached to the first semiconductor element.

為了簡要說明之目的，上述實施例1中任何可作相同應用之敘述皆併於此，且無須再重複相同敘述。 For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated herein, and the same description is not required to be repeated.

該線路板300類似於圖17所示結構，差異處僅在於，電性元件20更包括一散熱座26貼附至第一半導體元件25之非主動面上。該散熱座26可由任何具有高導熱率之材料(如金屬、合金、矽、陶瓷或石墨)製成，並熱導通至第二路由電路29。據此，第一半導體元件25所產生的熱可藉由散熱座26、第二路由電路29及第三路由電路51散出。 The circuit board 300 is similar to the structure shown in FIG. 17. The only difference is that the electrical component 20 further includes a heat sink 26 attached to the inactive surface of the first semiconductor component 25. The heat sink 26 can be made of any material with high thermal conductivity (such as metal, alloy, silicon, ceramic or graphite), and is thermally connected to the second routing circuit 29. Accordingly, the heat generated by the first semiconductor element 25 can be dissipated by the heat sink 26, the second routing circuit 29, and the third routing circuit 51.

[實施例4] [Example 4]

圖31為本發明第四實施態樣之線路板剖視圖，其加熱層中設有額外的垂直連接件。 Fig. 31 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention, with additional vertical connectors provided in the heating layer.

為了簡要說明之目的，上述實施例1中任何可作相同應用之敘述皆併於此，且無須再重複相同敘述。 For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated herein, and the same description is not required to be repeated.

該線路板400類似於圖17所示結構，差異處僅在於，線路板400更包括額外的垂直連接件41，其位於加強層40內，並藉由位於介電層514中的額外金屬化盲孔519，電性耦接至第三路由電路51。於此實施態樣中，該加強層40中的額外垂直連接件41是繪示成金屬柱。 The circuit board 400 is similar to the structure shown in FIG. 17, the only difference is that the circuit board 400 further includes an additional vertical connector 41, which is located in the reinforcement layer 40, and is blinded by additional metalization in the dielectric layer 514 The hole 519 is electrically coupled to the third routing circuit 51. In this embodiment, the additional vertical connectors 41 in the reinforcing layer 40 are shown as metal pillars.

圖32為第二半導體元件61、第三半導體元件63、第四半導體元件65及第五半導體元件67接置於圖31所示線路板400上之面朝面半導體組體剖視圖。第二半導體元件61以覆晶方式，電性耦接至第一路由電路21。第三半導體元件63以覆晶方式，接置於第三路由電路51上。第四半導體元件65設於第二半導體元件61上，並電性耦接至第一路由電路21。第五半導體元件67設於第四半導體元件65及加強層40上，並電性耦接至加強層40之垂直連接件41。此外，更可選擇於第三路由電路51上接置焊球75，其環繞第三半導體元件63。 FIG. 32 is a cross-sectional view of the facing semiconductor assembly where the second semiconductor element 61, the third semiconductor element 63, the fourth semiconductor element 65, and the fifth semiconductor element 67 are placed on the circuit board 400 shown in FIG. 31. The second semiconductor element 61 is electrically coupled to the first routing circuit 21 in a flip chip manner. The third semiconductor element 63 is connected to the third routing circuit 51 in a flip chip manner. The fourth semiconductor element 65 is disposed on the second semiconductor element 61 and is electrically coupled to the first routing circuit 21. The fifth semiconductor element 67 is disposed on the fourth semiconductor element 65 and the reinforcement layer 40, and is electrically coupled to the vertical connector 41 of the reinforcement layer 40. In addition, a solder ball 75 may be connected to the third routing circuit 51 to surround the third semiconductor element 63.

上述之線路板及組體僅為說明範例，本發明尚可透過其他多種實施例實現。此外，上述實施例可基於設計及可靠度之考量，彼此混合搭配使用或與其他實施例混合搭配使用。舉例來說，加強層可包括多個排列成陣列形狀之凹穴，且每一凹穴對應一電性元件。此外，第三路由電路亦可包括額外的導線，以接收並連接額外電性元件。 The above-mentioned circuit board and assembly are only illustrative examples, and the present invention can be implemented by other various embodiments. In addition, the above-mentioned embodiments can be mixed and matched with each other or used with other embodiments based on considerations of design and reliability. For example, the reinforcement layer may include a plurality of cavities arranged in an array shape, and each cavity corresponds to an electrical element. In addition, the third routing circuit may also include additional wires to receive and connect additional electrical components.

如上述實施態樣所示，本發明建構出一種可展現較佳可靠度之獨特線路板，其包括第一路由電路、第一半導體元件、一系列垂直連接件、密封材、第二路由電路、加強層及第三路由電路。為方便下文描述，在此將密封材第一表面所面向的方向定義為第一方向，而密封材第二表面 所面向的方向定義為第二方向。第一路由電路係設置鄰接於密封材之第一表面，而第二路由電路則設置鄰接於密封材之第二表面。 As shown in the above embodiments, the present invention constructs a unique circuit board that can exhibit better reliability, which includes a first routing circuit, a first semiconductor element, a series of vertical connectors, a sealing material, a second routing circuit, Strengthen the layer and the third routing circuit. For the convenience of the following description, the direction facing the first surface of the sealing material is defined as the first direction, and the second surface of the sealing material The facing direction is defined as the second direction. The first routing circuit is arranged adjacent to the first surface of the sealing material, and the second routing circuit is arranged adjacent to the second surface of the sealing material.

第一半導體元件可為已封裝或未封裝之晶片。舉例來說，該第一半導體元件可為裸晶片，或是晶圓級封裝晶粒等。或者，該第一半導體元件可為堆疊晶片。於一較佳實施態樣中，該第一半導體元件係電性耦接至第一路由電路(第一路由電路係可拆分式地接置於一犧牲載板上)，並被垂直連接件側向環繞，隨後於第一路由電路上提供密封材，再於密封材上形成第二路由電路，以於犧牲載板上形成電性元件。此於態樣中，該第一半導體元件可藉由凸塊電性耦接至第一路由電路，且其主動面係朝向第一路由電路。較佳為，該電性元件與犧牲載板是整體一起以面板尺寸製備，接著再切割成個別單件。此外，可於提供密封材前，將一散熱座貼附至第一半導體元件。據此，第一半導體元件所產生的熱可藉由該散熱座向外散逸。 The first semiconductor element can be a packaged or unpackaged chip. For example, the first semiconductor device may be a bare chip, or a wafer-level package die. Alternatively, the first semiconductor element may be a stacked wafer. In a preferred embodiment, the first semiconductor element is electrically coupled to the first routing circuit (the first routing circuit is detachably connected to a sacrificial carrier), and is vertically connected Surround it laterally, and then provide a sealing material on the first routing circuit, and then form a second routing circuit on the sealing material to form electrical components on the sacrificial carrier. In this aspect, the first semiconductor element can be electrically coupled to the first routing circuit by bumps, and its active surface faces the first routing circuit. Preferably, the electrical component and the sacrificial carrier are integrally prepared in the size of the panel, and then cut into individual pieces. In addition, a heat sink can be attached to the first semiconductor element before the sealing material is provided. Accordingly, the heat generated by the first semiconductor element can be dissipated to the outside through the heat sink.

密封材中之垂直連接件厚度可實質上相等於或小於密封材厚度，且垂直連接件可提供用於連接下級路由電路之電性接點。更具體地說，該些垂直連接件位於第一路由電路與第二路由電路之間，且垂直連接件之相反兩端分別電性耦接至第一路由電路及第二路由電路。 The thickness of the vertical connector in the sealing material can be substantially equal to or less than the thickness of the sealing material, and the vertical connector can provide electrical contacts for connecting the lower-level routing circuit. More specifically, the vertical connectors are located between the first routing circuit and the second routing circuit, and opposite ends of the vertical connectors are electrically coupled to the first routing circuit and the second routing circuit, respectively.

加強層環繞於第一路由電路、密封材及第二路由電路的外圍邊緣，且可由任何具有足夠機械強度之材料製成，以提供線路板機械支撐，並避免線路板彎翹。於一較佳實施態樣中，該加強層直接接合至電性元件與犧牲載板之外圍邊緣，並側向延伸至線路板之外圍邊緣。此外，可選擇於加強層中形成額外垂直連接件，以提供另一半導體元件或一散熱座從第一方向接置於加強層上之電性接點。 The reinforcing layer surrounds the peripheral edges of the first routing circuit, the sealing material and the second routing circuit, and can be made of any material with sufficient mechanical strength to provide mechanical support for the circuit board and avoid warping of the circuit board. In a preferred embodiment, the reinforcement layer is directly connected to the peripheral edges of the electrical components and the sacrificial carrier, and extends laterally to the peripheral edges of the circuit board. In addition, it is optional to form additional vertical connectors in the reinforcement layer to provide another semiconductor element or a heat sink connected to the electrical contact on the reinforcement layer from the first direction.

第一路由電路、第二路由電路及第三路由電路可為不具核心層之增層路由電路。第一路由電路及第二路由電路設於加強層內側壁表面所環繞的空間內，而第三路由電路則設於加強層內側壁表面所環繞的空間外，並側向延伸至加強層的表面上。更具體地說，第三路由電路側向延伸超過第一路由電路與第二路由電路之外圍邊緣，且第三路由電路之表面積大於第一路由電路之表面積及第二路由電路之表面積。較佳為，第三路由電路延伸至線路板之外圍邊緣，且實質上具有第二路由電路與加強層之相加表面積。 The first routing circuit, the second routing circuit, and the third routing circuit may be layer-added routing circuits without a core layer. The first routing circuit and the second routing circuit are provided in the space surrounded by the inner side wall surface of the reinforcement layer, and the third routing circuit is provided outside the space surrounded by the inner side wall surface of the reinforcement layer and extends laterally to the surface of the reinforcement layer on. More specifically, the third routing circuit laterally extends beyond the peripheral edges of the first routing circuit and the second routing circuit, and the surface area of the third routing circuit is larger than the surface area of the first routing circuit and the surface area of the second routing circuit. Preferably, the third routing circuit extends to the peripheral edge of the circuit board and substantially has the added surface area of the second routing circuit and the reinforcing layer.

第一路由電路可包括至少一介電層及至少一導線層，其中導線層包含有位於介電層中的金屬化盲孔，並側向延伸於介電層上。介電層與導線層係交替輪流形成，且需要的話更可重覆形成。舉例說明，第一路由電路可包括位於路由層、介電層及導線層，其中路由層位於犧牲載板上，介電層則位於路由層及犧牲載板上，而導線層由路由層之選定部分延伸，並填滿介電層中之盲孔，以形成金屬化盲孔，同時側向延伸於介電層上。若需要更多的信號路由，第一路由電路可進一步包括額外的介電層及額外的導線層。此外，第一路由電路可選擇性地包括一或多個被動元件嵌埋其中。於本發明中，可直接於犧牲載板上形成第一路由電路，或者分開形成第一路由電路後，再將第一路由電路可拆分地貼附於犧牲載板上，以完成於犧牲載板上形成第一路由電路的步驟。於第一路由電路中，路由層可包括與晶片I/O墊相配之接合墊。此外，路由線更可選擇性地更包括疊接墊，以對另一半導體元件(如塑膠封裝件或另一半導體組體)提供電性接點。因此，第一路由電路可為多層路由電路，且其外露表面可具有接合墊及選擇性疊接墊。據此，於一較佳實施態樣中，該第一路由電路可提供第一級扇出路由/互連，以供第二半導體元件得以接置於第一路由電路外露表面上。 接合墊、選擇性疊接墊、及鄰接犧牲載板之介電層可具有朝向第一方向且實質上呈相互共平面之表面。此外，加強層可朝第一方向延伸超過第一路由電路之外露表面，俾於移除犧牲載板後，形成一凹穴，以顯露第一路由電路。據此，可將第二半導體元件置於凹穴內，並將第二半導體元件電性耦接至凹穴所顯露之接合墊。 The first routing circuit may include at least one dielectric layer and at least one wire layer, wherein the wire layer includes a metalized blind hole in the dielectric layer and extends laterally on the dielectric layer. The dielectric layer and the wire layer are alternately formed, and can be formed repeatedly if necessary. For example, the first routing circuit may include a routing layer, a dielectric layer, and a wire layer. The routing layer is on the sacrificial carrier, the dielectric layer is on the routing layer and the sacrificial carrier, and the wire layer is selected by the routing layer Partially extends and fills the blind holes in the dielectric layer to form metalized blind holes, and at the same time extends laterally on the dielectric layer. If more signal routing is required, the first routing circuit may further include an additional dielectric layer and an additional wire layer. In addition, the first routing circuit can optionally include one or more passive components embedded therein. In the present invention, the first routing circuit can be directly formed on the sacrificial carrier, or after forming the first routing circuit separately, the first routing circuit can be detachably attached to the sacrificial carrier to complete the sacrificial carrier. The step of forming a first routing circuit on the board. In the first routing circuit, the routing layer may include bonding pads matching the chip I/O pads. In addition, the routing line can optionally further include a stacking pad to provide electrical contacts for another semiconductor element (such as a plastic package or another semiconductor assembly). Therefore, the first routing circuit can be a multilayer routing circuit, and its exposed surface can have bonding pads and selective overlapping pads. Accordingly, in a preferred embodiment, the first routing circuit can provide a first-level fan-out routing/interconnection for the second semiconductor element to be placed on the exposed surface of the first routing circuit. The bonding pad, the selective overlap pad, and the dielectric layer adjacent to the sacrificial carrier may have surfaces facing the first direction and substantially coplanar with each other. In addition, the reinforcement layer can extend in the first direction beyond the exposed surface of the first routing circuit, so that after the sacrificial carrier is removed, a cavity is formed to expose the first routing circuit. Accordingly, the second semiconductor element can be placed in the cavity, and the second semiconductor element can be electrically coupled to the bonding pad exposed by the cavity.

第二路由電路可包括一路由層，其側向延伸於密封材之第二表面，並電性耦接至垂直連接件，同時熱性導通至第一半導體元件非主動面上之選擇性散熱座。此外，第二路由電路更可包括至少一介電層及至少一導線層，其中導線層包含有位於介電層中的金屬化盲孔，並側向延伸於介電層上。介電層與導線層係交替輪流形成，且需要的話更可重覆形成。第二路由電路中鄰近於路由層之最內層導線層可透過與路由層接觸之金屬化盲孔，電性耦接至路由層，而第二路由電路中鄰近於第三路由電路之最外層導線層則可提供下級路由電路連接用之電性接點。據此，第二路由電路可提供垂直連接件與第三路由電路間之電性連接。 The second routing circuit may include a routing layer that extends laterally on the second surface of the sealing material and is electrically coupled to the vertical connector and thermally connected to the selective heat sink on the non-active surface of the first semiconductor element. In addition, the second routing circuit may further include at least one dielectric layer and at least one wire layer, wherein the wire layer includes a metalized blind hole located in the dielectric layer and extends laterally on the dielectric layer. The dielectric layer and the wire layer are alternately formed, and can be formed repeatedly if necessary. The innermost wire layer of the second routing circuit adjacent to the routing layer can be electrically coupled to the routing layer through the metalized blind via contacting the routing layer, and the second routing circuit is adjacent to the outermost layer of the third routing circuit The wire layer can provide electrical contacts for the connection of lower-level routing circuits. Accordingly, the second routing circuit can provide an electrical connection between the vertical connector and the third routing circuit.

第三路由電路可形成於第二路由電路上，並側向延伸至加強層之表面上，以提供進一步扇出路由/互連。由於第三路由電路可藉由第三路由電路之金屬化盲孔，電性耦接至電性元件之第二路由電路，故第二路由電路與第三路由電路間之電性連接無須使用焊接材料。此外，加強層與第三路由電路間及第二路由電路與第三路由電路間之介面亦無需使用焊材或黏著劑。更具體地說，第三路由電路可包括至少一介電層及至少一導線層，其中導線層包含有位於介電層中的金屬化盲孔，並側向延伸於介電層上。介電層與導線層係交替輪流形成，且需要的話更可重覆形成。舉例說明，第三路由電路可包括一介電層及一導線層，其中介電層由第二方向覆蓋電性元件及加強層，且導線層由第二路由電路延伸(且選擇性地自加強層 中之額外垂直連接件延伸)，並貫穿介電層以形成金屬化盲孔，同時側向延伸於介電層上。若需要更多的信號路由，第三路由電路可進一步包括額外之介電層及額外之導線層。據此，第三路由電路可接觸並電性耦接至電性元件之第二路由電路，以構成信號路由，且第三路由電路可選擇性地進一步電性耦接至加強層中額外的垂直連接件，以構成信號路由或進行接地連接。第三路由電路最外層導線層可容置導電接點，例如凸塊、焊球，以與下一級組體或另一電子元件電性傳輸及機械性連接。 The third routing circuit can be formed on the second routing circuit and extend laterally to the surface of the reinforcement layer to provide further fan-out routing/interconnection. Since the third routing circuit can be electrically coupled to the second routing circuit of the electrical component through the metalized blind vias of the third routing circuit, the electrical connection between the second routing circuit and the third routing circuit does not require welding material. In addition, the interface between the reinforcement layer and the third routing circuit and between the second routing circuit and the third routing circuit does not need to use solder or adhesive. More specifically, the third routing circuit may include at least one dielectric layer and at least one wire layer, wherein the wire layer includes a metalized blind hole in the dielectric layer and extends laterally on the dielectric layer. The dielectric layer and the wire layer are alternately formed, and can be formed repeatedly if necessary. For example, the third routing circuit may include a dielectric layer and a wire layer, wherein the dielectric layer covers the electrical components and the reinforcement layer from the second direction, and the wire layer extends from the second routing circuit (and is selectively self-reinforced) Floor The additional vertical connection element in the middle extends) and penetrates the dielectric layer to form a metalized blind hole, and at the same time extends laterally on the dielectric layer. If more signal routing is required, the third routing circuit can further include an additional dielectric layer and an additional wire layer. Accordingly, the third routing circuit can be contacted and electrically coupled to the second routing circuit of the electrical element to form a signal routing, and the third routing circuit can be selectively further electrically coupled to the additional vertical in the reinforcement layer Connectors to form signal routing or ground connections. The outermost wire layer of the third routing circuit can accommodate conductive contacts, such as bumps and solder balls, for electrical transmission and mechanical connection with the next level assembly or another electronic component.

本發明亦提供一種面朝面半導體組體，其係將一第二半導體元件電性耦接至上述線路板之接合墊。更具體地說，可將第二半導體元件置於線路板之凹穴中，並於線路板接合墊上設置各種連接媒介(如凸塊)，以將第二半導體元件電性連接至線路板。據此，第一半導體元件與第二半導體元件可藉由兩者間之第一路由電路相互電性連接，且第二半導體元件更可藉由第一路由電路、垂直連接件及第二路由電路，電性連接至第三路由電路。於該面朝面半導組體中，第一路由電路可提供第一半導體元件與第二半導體元件間之最短互連距離。該第二半導體元件可為已封裝或未封裝之晶片。舉例來說，該第二半導體元件可為裸晶片，或是晶圓級封裝晶粒等。或者，該第二半導體元件可為堆疊晶片。 The present invention also provides a face-to-face semiconductor assembly, which electrically couples a second semiconductor element to the bonding pad of the circuit board. More specifically, the second semiconductor element can be placed in the cavity of the circuit board, and various connection media (such as bumps) can be arranged on the circuit board bonding pad to electrically connect the second semiconductor element to the circuit board. Accordingly, the first semiconductor element and the second semiconductor element can be electrically connected to each other through the first routing circuit therebetween, and the second semiconductor element can further be connected to each other through the first routing circuit, the vertical connector, and the second routing circuit , Electrically connected to the third routing circuit. In the face-to-face semiconductor assembly, the first routing circuit can provide the shortest interconnection distance between the first semiconductor element and the second semiconductor element. The second semiconductor element can be a packaged or unpackaged chip. For example, the second semiconductor device can be a bare chip, or a wafer-level package die. Alternatively, the second semiconductor element may be a stacked wafer.

此外，可進一步提供額外半導體元件，並藉由導電接點，如焊球，以將該額外之半導體元件電性耦接至線路板之疊接墊。舉例來說，該額外之半導體元件可設置於第二半導體元件上方，並且電性耦接至線路板之疊接墊。或者，可將一散熱座貼附至第二半導體元件之非主動面上。 In addition, additional semiconductor components can be further provided, and conductive contacts, such as solder balls, can be used to electrically couple the additional semiconductor components to the overlap pads of the circuit board. For example, the additional semiconductor device can be disposed above the second semiconductor device and electrically coupled to the bonding pad of the circuit board. Alternatively, a heat sink can be attached to the inactive surface of the second semiconductor element.

「覆蓋」一詞意指於垂直及/或側面方向上不完全以及完全覆蓋。例如，在凹穴向上之狀態下，第二路由電路係於下方覆蓋第一路由 電路，不論另一元件例如第一半導體元件、垂直連接件及密封材是否位於第一路由電路與第二路由電路之間。 The term "covering" means incomplete and complete coverage in the vertical and/or lateral directions. For example, when the cavity is upward, the second routing circuit covers the first routing below The circuit, regardless of whether another element such as the first semiconductor element, the vertical connector and the sealing material is located between the first routing circuit and the second routing circuit.

「接置於…上」及「貼附於…上」一詞包括與單一或多個元件間之接觸與非接觸。例如，選擇性散熱座可貼附於第二半導體元件上，不論此散熱座係接觸該第二半導體元件，或與該第二半導體元件以一導熱黏著劑或焊球相隔。 The terms "attached to" and "attached to" include contact and non-contact with single or multiple components. For example, the selective heat sink can be attached to the second semiconductor element regardless of whether the heat sink is in contact with the second semiconductor element or is separated from the second semiconductor element by a thermally conductive adhesive or solder ball.

「電性連接」及「電性耦接」之詞意指直接或間接電性連接。例如，於一較佳實施態樣中，第二路由電路直接接觸並電性連接至垂直連接件，而第三路由電路與垂直連接件保持距離，並藉由第二路由電路而電性連接至垂直連接件。 The terms "electrical connection" and "electrical coupling" mean direct or indirect electrical connection. For example, in a preferred embodiment, the second routing circuit directly contacts and is electrically connected to the vertical connector, and the third routing circuit keeps a distance from the vertical connector and is electrically connected to the vertical connector by the second routing circuit. Vertical connector.

「第一方向」及「第二方向」並非取決於線路板之定向，凡熟悉此項技藝之人士即可輕易瞭解其實際所指之方向。例如，密封材之第一表面係面朝第一方向，而密封材之第二表面係面朝第二方向，此與線路板是否倒置無關。因此，該第一及第二方向係彼此相反且垂直於側面方向。再者，在凹穴向上之狀態，第一方向係為向上方向，第二方向係為向下方向；在凹穴向下之狀態，第一方向係為向下方向，第二方向係為向上方向。 The "first direction" and "second direction" do not depend on the orientation of the circuit board. Those who are familiar with the art can easily understand the actual direction they are pointing. For example, the first surface of the sealing material faces the first direction, and the second surface of the sealing material faces the second direction, which has nothing to do with whether the circuit board is upside down. Therefore, the first and second directions are opposite to each other and perpendicular to the lateral direction. Furthermore, when the cavity is upward, the first direction is upward and the second direction is downward; when the cavity is downward, the first direction is downward and the second direction is upward. direction.

本發明之線路板具有許多優點。舉例來說，藉由習知之覆晶接合製程例如熱壓或迴焊，將第一半導體元件電性耦接至第一路由電路，其可避免可堆疊式組體製程中使用黏著載體作為暫時接合時，會遭遇位置準確度問題。第一路由電路可提供第一級扇出/互連，使第二半導體元件可接置其上，而密封材上之第二路由電路則可提供第二級扇出/互連。第二路由電路與加強層上之第三路由電路可提供第三級扇出/互連，並提供用於下一級板組裝之電性接點。藉此，具有精細接墊之第二半導體元件可電性耦接至第一路由電路之一側，其中該側的墊間距係與第二半導體元件相符， 而第三路由電路則可藉由第二路由電路及垂直連接元件，電性耦接至第一路由電路之另一側，以將第二半導體元件之墊尺寸及墊間距進一步放大。加強層可提供一抗彎平台，供第三路由電路形成其上，以避免線路板發生彎翹狀況。藉由此方法製備成的線路板係為可靠度高、價格低廉、且非常適合大量製造生產。 The circuit board of the present invention has many advantages. For example, the first semiconductor element is electrically coupled to the first routing circuit by a conventional flip chip bonding process such as hot pressing or reflow, which can avoid the use of an adhesive carrier as a temporary bonding in the stackable assembly process When, you will encounter location accuracy problems. The first routing circuit can provide the first level of fan-out/interconnection, so that the second semiconductor element can be connected to it, and the second routing circuit on the sealing material can provide the second level of fan-out/interconnection. The second routing circuit and the third routing circuit on the reinforcement layer can provide a third level of fan-out/interconnection and provide electrical contacts for the next level of board assembly. Thereby, the second semiconductor device with fine pads can be electrically coupled to one side of the first routing circuit, wherein the pad pitch on the side is consistent with the second semiconductor device, The third routing circuit can be electrically coupled to the other side of the first routing circuit through the second routing circuit and the vertical connection element, so as to further enlarge the pad size and the pad spacing of the second semiconductor device. The reinforcement layer can provide a bending resistant platform for the third routing circuit to be formed thereon, so as to avoid warping of the circuit board. The circuit board prepared by this method has high reliability, low price, and is very suitable for mass production.

本發明之製作方法具有高度適用性，且係以獨特、進步之方式結合運用各種成熟之電性及機械性連接技術。此外，本發明之製作方法不需昂貴工具即可實施。因此，相較於傳統技術，此製作方法可大幅提升產量、良率、效能與成本效益。 The manufacturing method of the present invention has high applicability, and combines various mature electrical and mechanical connection technologies in a unique and progressive way. In addition, the manufacturing method of the present invention can be implemented without expensive tools. Therefore, compared with traditional technology, this manufacturing method can greatly improve the yield, yield, performance and cost-effectiveness.

在此所述之實施例係為例示之用，其中該些實施例可能會簡化或省略本技術領域已熟知之元件或步驟，以免模糊本發明之特點。同樣地，為使圖式清晰，圖式亦可能省略重覆或非必要之元件及元件符號。 The embodiments described here are for illustrative purposes, and these embodiments may simplify or omit elements or steps that are well known in the art so as not to obscure the characteristics of the present invention. Similarly, in order to make the drawings clear, the drawings may omit repeated or unnecessary components and component symbols.

100:線路板 100: circuit board

20:電性元件 20: Electrical components

203:外露表面 203: exposed surface

21:第一路由電路 21: The first routing circuit

211:路由層 211: routing layer

212:接合墊 212: Bonding pad

213:疊接墊 213: Stacking Pad

23:垂直連接件 23: Vertical connector

25:第一半導體元件 25: The first semiconductor component

27:密封材 27: Sealing material

271:第一表面 271: First Surface

272:第二表面 272: second surface

29:第二路由電路 29: Second routing circuit

296:導線層 296: Wire Layer

40:加強層 40: Strengthening layer

405、516:凹穴 405, 516: cavities

409:內側壁表面 409: inner wall surface

51:第三路由電路 51: Third routing circuit

514:介電層 514: Dielectric layer

518:金屬化盲孔 518: metalized blind hole

Claims (11)

一種線路板，其包括：一電性元件，其包含一第一半導體元件、一密封材、一系列垂直連接件、一第一路由電路及一第二路由電路，該第一半導體元件具有一主動面，且每一該些垂直連接件各自具有一第一端及一第二端，其中(i)該密封材側向覆蓋該第一半導體元件及該些垂直連接件，並具有面向該第一路由電路之一第一表面及相反於該第一表面之一第二表面，(ii)該第一路由電路延伸至該密封材之該第一表面上、該第一半導體元件之該主動面上、及該些垂直連接件之該些第一端上，以使該第一半導體元件及該些垂直連接件電性耦接至該第一路由電路，且(iii)該第二路由電路設於該密封材之該第二表面上及該些垂直連接件之該些第二端上，以使該第二路由電路藉由該些垂直連接件，電性連接至該第一路由電路；一加強層，其側向環繞該電性元件之該第一半導體元件、該密封材、該些垂直連接件、該第一路由電路及該第二路由電路，且該加強層之內側壁表面鄰近於該電性元件之外圍邊緣；以及一第三路由電路，其設於該第二路由電路上，並側向延伸於該加強層上，其中該第三路由電路電性耦接至該第二路由電路。 A circuit board includes: an electrical component, which includes a first semiconductor component, a sealing material, a series of vertical connectors, a first routing circuit, and a second routing circuit. The first semiconductor component has an active Each of the vertical connecting elements has a first end and a second end, wherein (i) the sealing material laterally covers the first semiconductor element and the vertical connecting elements, and has a surface facing the first A first surface of the routing circuit and a second surface opposite to the first surface, (ii) the first routing circuit extends to the first surface of the sealing material and the active surface of the first semiconductor element , And on the first ends of the vertical connectors, so that the first semiconductor element and the vertical connectors are electrically coupled to the first routing circuit, and (iii) the second routing circuit is provided on On the second surface of the sealing material and on the second ends of the vertical connectors, so that the second routing circuit is electrically connected to the first routing circuit through the vertical connectors; a reinforcement Layer, which laterally surrounds the first semiconductor element of the electrical element, the sealing material, the vertical connectors, the first routing circuit and the second routing circuit, and the inner sidewall surface of the reinforcing layer is adjacent to the The peripheral edge of the electrical component; and a third routing circuit, which is arranged on the second routing circuit and extends laterally on the reinforcement layer, wherein the third routing circuit is electrically coupled to the second routing circuit . 如申請專利範圍第1項所述之線路板，其中，該第三路由電路包括側向延伸超過該第二路由電路之外圍邊緣的至少一導線層。 The circuit board according to claim 1, wherein the third routing circuit includes at least one wire layer extending laterally beyond the peripheral edge of the second routing circuit. 如申請專利範圍第1項所述之線路板，更包括額外垂直連接件，其位於該加強層內，其中該些額外垂直連接件電性耦接至該第三路由電路。 The circuit board described in item 1 of the scope of the patent application further includes additional vertical connectors located in the reinforcing layer, wherein the additional vertical connectors are electrically coupled to the third routing circuit. 如申請專利範圍第1項所述之線路板，其中，該第一路由電路具有一外露表面，其背向該密封材之該第一表面。 The circuit board according to the first item of the scope of patent application, wherein the first routing circuit has an exposed surface facing away from the first surface of the sealing material. 如申請專利範圍第4項所述之線路板，其中，該加強層之該內側壁表面的一部分與該第一路由電路之該外露表面形成一凹穴。 The circuit board according to claim 4, wherein a part of the inner sidewall surface of the reinforcing layer and the exposed surface of the first routing circuit form a cavity. 一種面朝面半導體組體，其包括：如申請專利範圍第1項至第4項中任一項所述之該線路板；以及一第二半導體元件，其藉由該第一半導體元件與該第二半導體元件間之該第一路由電路，與該第一半導體元件面朝面地相互電性耦接。 A face-to-face semiconductor assembly, comprising: the circuit board as described in any one of items 1 to 4 in the scope of the patent application; and a second semiconductor element, which includes the first semiconductor element and the The first routing circuit between the second semiconductor elements and the first semiconductor element are electrically coupled to each other face to face. 如申請專利範圍第6項所述之面朝面半導體組體，其中，該加強層之該內側壁表面的一部分與該第一路由電路之一表面形成一凹穴，且該第二半導體元件設置於該凹穴內。 The face-to-face semiconductor assembly described in item 6 of the scope of patent application, wherein a portion of the inner sidewall surface of the reinforcing layer and a surface of the first routing circuit form a cavity, and the second semiconductor element is disposed In the cavity. 如申請專利範圍第6項所述之面朝面半導體組體，更包括：一散熱座，其貼附於該第二半導體元件之一非主動面，並側向延伸至該加強層上。 The face-to-face semiconductor assembly described in item 6 of the scope of patent application further includes: a heat sink attached to an inactive surface of the second semiconductor element and extending laterally to the reinforcing layer. 一種線路板之製作方法，其包括：提供一電性元件於一犧牲載板上，該電性元件包含一半導體元件、一密封材、一系列垂直連接件、一第一路由電路及一第二路由電路， 其中(i)該第一路由電路可拆分式地接置於該犧牲載板上，並鄰接該密封材之一第一表面，(ii)該半導體元件及該些垂直連接件嵌埋於該密封材中，且電性耦接至該第一路由電路，且(iii)該第二路由電路設於該密封材之一相反第二表面上，並藉由該些垂直連接件電性連接至該第一路由電路；提供一加強層，其側向環繞該電性元件及該犧牲載板；形成一第三路由電路，其設於該第二路由電路上，並側向延伸於該加強層上，其中該第三路由電路電性耦接至該第二路由電路；以及從該第一路由電路移除該犧牲載板。 A method for manufacturing a circuit board includes: providing an electrical component on a sacrificial carrier board, the electrical component including a semiconductor component, a sealing material, a series of vertical connectors, a first routing circuit and a second Routing circuit, Wherein (i) the first routing circuit is detachably connected to the sacrificial carrier board and adjacent to a first surface of the sealing material, (ii) the semiconductor element and the vertical connectors are embedded in the In the sealing material, and electrically coupled to the first routing circuit, and (iii) the second routing circuit is provided on an opposite second surface of the sealing material, and is electrically connected to the sealing material through the vertical connectors The first routing circuit; providing a reinforcement layer, which laterally surrounds the electrical component and the sacrificial carrier; forming a third routing circuit, which is arranged on the second routing circuit and extends laterally on the reinforcement layer Above, wherein the third routing circuit is electrically coupled to the second routing circuit; and the sacrificial carrier board is removed from the first routing circuit. 如申請專利範圍第9項所述之製作方法，提供該電性元件於該犧牲載板上之該步驟包括：於該犧牲載板上提供該第一路由電路，其中該第一路由電路係可拆分式地接置於該犧牲載板上；將該半導體元件電性耦接至該第一路由電路；形成該些垂直連接件；提供該密封材於該第一路由電路上；以及形成該第二路由電路於該密封材上。 According to the manufacturing method described in claim 9, the step of providing the electrical component on the sacrificial carrier includes: providing the first routing circuit on the sacrificial carrier, wherein the first routing circuit can be Detachably connect to the sacrificial carrier; electrically couple the semiconductor element to the first routing circuit; form the vertical connectors; provide the sealing material on the first routing circuit; and form the The second routing circuit is on the sealing material. 如申請專利範圍第9項所述之製作方法，其中，形成該第三路由電路之該步驟包括：將該第三路由電路電性耦接至該加強層中之額外垂直連接件。 According to the manufacturing method of claim 9, wherein the step of forming the third routing circuit includes: electrically coupling the third routing circuit to the additional vertical connector in the reinforcement layer.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201731041A (en) * 2013-09-27 2017-09-01 英特爾公司 Die package with superposer substrate for passive components
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US10418298B2 (en) * 2013-09-24 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual fan-out semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201731041A (en) * 2013-09-27 2017-09-01 英特爾公司 Die package with superposer substrate for passive components
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