TW201933568A - Method of making wiring board with interposer and electronic component incorporated with base board - Google Patents

Abstract

A wiring board includes an interposer and an electronic component laterally surrounded by a base board and a dielectric layer and connected to a routing circuitry. The interposer and the electronic component are inserted into a first through opening and a second through opening of the base board, respectively. The dielectric layer covers the top side of the base board and the top surface of the electronic component, and fills in gaps between the interposer and the base board and between the electronic component and the base board. The routing circuitry is deposited on the dielectric layer and electrically connected to the electronic component and a top wiring layer of the base board.

Description

Circuit board manufacturing method for interposer and electric component in base board

The invention relates to a method for manufacturing a circuit board, in particular to a method for manufacturing a circuit board provided with an interposer, electrical components and a substrate.

High-speed semiconductor assemblies (such as multi-chip modules) usually require high-performance circuit boards to interconnect signals. However, when the power is increased, the large amount of heat generated by the semiconductor wafer will degrade the performance of the device and cause thermal stress on the wafer. Accordingly, ceramic materials (such as alumina or aluminum nitride) are often considered suitable materials for such applications because they are thermally and electrically insulating and have a low coefficient of thermal expansion (CTE). U.S. Patent Nos. 8,895,998 and 7,670,872 have disclosed various circuit boards, which use ceramics as a wafer pad material to achieve better reliability. However, because these circuit boards are not provided with electrical components such as capacitors, decoupling capacitors, or resistors, electrical performance is limited.

The main object of the present invention is to provide a circuit board manufacturing method for an electrical component and an interposer in a substrate. The manufacturing method includes the steps of forming a dielectric layer on a substrate and making the surface of the dielectric layer flush with the surface of the interposer, so that the thickness difference between the interposer and the substrate can be compensated. In addition, the dielectric material can also cover the electrical components and fill the gaps between the substrate and the interposer and between the substrate and the electrical components. Therefore, the dielectric layer can mechanically interpose the interposers, the electrical components, and the substrate. Join together.

Another object of the present invention is to provide a circuit board manufacturing method for electrically connecting an electrical component to a substrate. The manufacturing method includes a step of depositing a routing circuit. The routing circuit extends laterally on the dielectric layer and extends through the dielectric layer to form a metallized blind hole in contact with the substrate. The routing circuit is also electrically connected. To electrical components. The routing circuit can also extend laterally to the top surface of the interposer and provide an electrical connection between the electrical component and the built-in circuit of the interposer.

According to the above and other objects, the present invention provides a method for manufacturing a circuit board, which includes the following steps: providing a base board having a top side, a bottom side, a first through opening, a second through opening, and A top circuit layer located on the top side, wherein each of the first through opening and the second through opening has an inner sidewall extending from the top side to the bottom side; an interposer is inserted into the first of the base board An electrical component is inserted into the through-opening in the second through-opening of the base plate, wherein the interposer comprises a ceramic block; a dielectric layer is formed on a top surface of the electric component, and the base plate On the top side, the gap between the peripheral edge of the interposer and the inner side walls of the first through opening, and the gap between the outer edge of the electrical component and the inner side walls of the second through opening And forming a routing circuit on a top surface of the dielectric layer, and the routing circuit is electrically connected to the electrical component, and is electrically connected to the base plate through a metallized blind hole.

Unless specifically described or steps must occur sequentially, the order of the above steps is not limited to the above, and can be changed or rearranged according to the desired design.

Accordingly, the present invention provides a circuit board including a base board including a top side, a bottom side, a first through opening, a second through opening, and a top circuit layer on the top side. Each of the first through-openings and the second through-openings has an inner sidewall extending from the top side to the bottom side; an interposer is disposed in the first through-opening of the base plate, wherein the interposer Including a ceramic block; an electrical component disposed in the second through opening of the base plate; a dielectric layer covering a top surface of the electrical component and the top side of the base plate, and Extending into the gap between the peripheral edge of the interposer and the inner side walls of the first through opening, and the gap between the outer edge of the electrical component and the inner side walls of the second through opening; and a routing circuit It is disposed on a top surface of the dielectric layer, and is electrically connected to the electrical component, and is electrically connected to the base plate through a metallized blind hole. In addition, the present invention also provides a semiconductor assembly, which includes a semiconductor element connected to the top surface of the interposer of the circuit board, and the semiconductor element is electrically connected to the routing circuit.

The circuit board, semiconductor assembly and manufacturing method of the invention have many advantages. For example, the method of combining the interposer and the electrical components with the substrate is particularly advantageous because the interposer can provide a CTE compensation platform for chip placement, and the electrical components can improve the assembly Electrical characteristics, while the base board can improve the wiring flexibility of the circuit board. The method of forming a dielectric layer can provide a mechanical bonding force between the substrate and the interposer, and between the substrate and the electrical component, and provide a platform for high-resolution circuits to be deposited on the platform, thereby enabling fine-pitch spacing. Components, such as chip-on-chip and surface mount components, can be assembled on the circuit board and interconnected to electrical components through routing circuits.

The above and other features and advantages of the present invention can be made clearer by the following detailed description of the preferred embodiments.

In the following, examples will be provided to explain the aspects of the present invention in detail. The advantages and effects of the present invention will be more significant by the content disclosed by the present invention. The attached drawings are simplified and used for illustration. The number, shape and size of the components shown in the drawings can be modified according to the actual situation, and the configuration of the components may be more complicated. The present invention can also be practiced or applied in other aspects, and various changes and adjustments can be made without departing from the spirit and scope defined by the present invention.

[Example 1]

FIG. 1-12 is a diagram of a method for manufacturing a circuit board in a first embodiment of the present invention, which includes a base substrate, an interposer, an electrical component, a base dielectric layer, a routing circuit, and a base coating layer.

1 and 2 are a schematic cross-sectional view and a top perspective view of the base plate 10, respectively. In this embodiment, the base plate 10 includes a top circuit layer 13 on the top side, a bottom metal film 15 on the bottom side, a core layer 17 between the top circuit layer 13 and the bottom metal film 15, and a first through opening 18 And the second through opening 19. The core layer 17 may be made of ceramic, glass, epoxy resin, molding material, glass epoxy resin, polyimide, or the like. The top circuit layer 13 is usually a patterned copper layer, and may be an inductor, an antenna, or any conductive circuit, and the bottom metal film 15 is an unpatterned copper layer, which completely covers the core layer 17 from below. The first through-opening 18 and the second through-opening 19 each have an inner side wall extending from the top side to the bottom side of the base plate 10. Here, the first through-opening 18 and the second through-opening 19 can be formed by various techniques, such as punching, drilling, or laser cutting.

3 and 4 are a schematic cross-sectional view and a top perspective view of the interposer 20 and the electrical component 30 inserted into the first through opening 18 and the second through opening 19 of the base plate 10, respectively. The bottom surface of the electrical component 30 may optionally include a thermally conductive material 31. In the present embodiment, the interposer 20 includes a ceramic block 21 having a thickness greater than the thickness of the base plate 10, and has a high elastic modulus and low thermal expansion coefficient (for example, 2 x 10 ^-6 K ^-1 to 10 x 10 ^{- 6} K ^-1 ), and the thickness of the electrical component 30 is smaller than the thickness of the interposer 20. Here, the electrical component 30 may be a resistor, a capacitor, an inductor, or any other passive or active component. The interposer 20 is placed in the first through opening 18 of the base plate 10, and the bottom side of the base plate 10 and the bottom surface of the interposer 20 are substantially coplanar. The electrical component 30 is placed in the second through opening 19 of the base plate 10, and the bottom side of the base plate 10 and the bottom surface of the electrical component 30 are substantially coplanar. The size of the first through opening 18 is larger than the size of the interposer 20, and the size of the second through opening 19 is larger than the size of the electrical component 30. In some examples, the inner side wall of the first through-opening 18 and the inner side wall of the second through-opening 19 can be used as positioning members to ensure the accuracy of the interposer 20 and the electrical component 30. According to this, the interposer 20 and the electrical component 30 can be accurately restricted to predetermined positions, and the peripheral edge of the interposer 20 will be close to the inner sidewall of the first through opening 18, and the peripheral edge of the electrical component 30 will be close to the Two inner walls of the through-opening 19.

5 and 6 are a schematic cross-sectional view and a top perspective view of the dielectric layer 40, respectively. The dielectric layer 40 can be formed by a molding process or other methods (such as laminating epoxy resin or polyimide resin). Here, the dielectric layer 40 covers the top side of the substrate 10, the top surface of the interposer 20, and the top surface of the electrical component 30, and extends into the periphery of the interposer 10 and the inner side wall of the first through opening 18 and the electrical component 30. A gap between the peripheral edge and the inner wall of the second through opening 19. According to this, the dielectric layer 40 will laterally cover, surround, and uniformly cover the sidewalls of the interposer 20 and the sidewalls of the electrical component 30, and provide a mechanism between the substrate 10 and the interposer 20 and between the substrate 10 and the electrical component 30 Bonding force.

7 and 8 are a schematic cross-sectional view and a top perspective view after the upper half of the dielectric layer 40 is removed, respectively. Here, the upper half of the dielectric layer 40 may be removed by a planarization process to expose the top surface of the interposer 20 from above. The planarization process may be a lapping / grinding process or It is a chemical mechanical polishing (CMP) process. After planarization, the top surface of the dielectric layer 40 will be substantially coplanar with the top surface of the interposer 20, and the bottom surface of the dielectric layer 40 will be on the bottom side of the substrate 10, the bottom surface of the interposer 20, and the bottom surface of the electrical component 30. It is substantially coplanar.

9 and 10 are a schematic cross-sectional view and a top perspective view of the first blind hole 403 and the second blind hole 404, respectively. The first blind hole 403 and the second blind hole 404 respectively expose the top circuit layer 13 of the base plate 10 from above. A selected portion of the electrical component 30. The first blind hole 403 and the second blind hole 404 can be formed by various technologies, including laser drilling, plasma etching, and lithography. The first blind hole 403 and the second blind hole 404 usually have a thickness of 50 μm. Of its diameter. Pulse lasers can be used to improve laser drilling performance. Alternatively, a scanning laser beam can be used with a metal mask. The first blind hole 403 and the second blind hole 404 extend through the dielectric layer 40 and are respectively aligned with a selected portion of the top circuit layer 13 and a selected portion of the electrical component 30.

11 and 12 are a schematic cross-sectional view and a top perspective view of the routing circuit 51 formed by the metal pattern deposition method described below, respectively. First, the top surface of the structure can be metallized by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof, to form a single or multiple conductive layer (usually a copper layer). The conductive layer may be made of Cu, Ni, Ti, Au, Ag, Al, a combination thereof, or other suitable conductive materials. Generally, a seed layer is formed on the topmost surface of the structure before the conductive layer is plated to a desired thickness. The seed layer can be formed by a diffusion resistance layer and a plating bus layer. The diffusion resistance layer is used to offset oxidation or erosion of the conductive layer (such as copper). In most examples, the diffusion barrier layer can also be used as an adhesion enhancement layer for the underlying material, and can be formed by physical vapor deposition (PVD). For example, Ti can be formed by sputtering to a thickness of about 0.01 μm to 0.1 μm Or TiW layer. However, the diffusion barrier layer can also be made of other materials, such as TaN or other suitable materials, and its thickness is not limited to the above range. The plating carrier layer is usually made of the same material as the conductive layer and has a thickness ranging from about 0.1 μm to 1 μm. For example, when the conductive layer is copper, the plating carrier layer is preferably a copper thin film made by physical vapor deposition or electroless plating. However, the electroplated support layer can also be made of other suitable materials, such as silver, gold, chromium, nickel, tungsten, or a combination thereof, and its thickness is not limited to the above range.

After the seed layer is deposited, a photoresist layer (not shown) is formed on the seed layer. The photoresist layer can be formed by a wet process (such as a spin coating process) or a dry process (such as a lamination dry film). After the photoresist layer is formed, the photoresist layer is patterned to form openings, and then the openings are filled with a covering metal (such as copper) to form routing circuits 51. After the metal is plated, the exposed seed layer is removed through an etching process to form conductive wires that are electrically isolated from each other. In this figure, the routing circuit 51 is a patterned metal layer that extends upward from the top circuit layer 13 and the electrical component 30 and fills the first blind hole 403 and the second blind hole 404 to form direct contact with the top circuit, respectively. The layer 13 and the first metallized blind hole 513 and the second metallized blind hole 514 of the component 30 are laterally extended on the dielectric layer 40. According to this, the routing circuit 51 can form electrical contacts on the interposer 20 and the dielectric layer 40, and is electrically coupled to the substrate 10 through the first metallized blind hole 513 and the second metallized blind hole 514. Top circuit layer 13 and electrical component 30.

In addition, it is also possible to metalize the bottom surface of the structure to form a coating layer 50 having a single-layer or multi-layer structure. The coating layer 50 is an unpatterned metal layer (usually a copper layer), which contacts and completely covers the bottom metal film 15 of the base plate 10, the interposer 20, the heat conductive material 31 of the electrical component 30, and the first The dielectric layer 40 in the through-opening 18 and the second through-opening 19. Therefore, the covering layer 50 can connect the interposer 20 to the bottom metal film 15 to construct a heat dissipation surface having an area larger than that of the interposer 20.

Accordingly, as shown in FIGS. 11 and 12, the completed circuit board 100 includes a base substrate 10, a base interlayer 20, an electrical component 30, a dielectric layer 40, a coating layer 50, and a routing circuit 51. The interposer 20 is disposed on the first through opening 18 of the base plate 10, and the electrical component 30 is disposed on the second through opening 19 of the base plate 10. The dielectric layer 40 provides a mechanical bonding force between the inner sidewall of the substrate 10 and the peripheral edge of the interposer 20 and between the inner sidewall of the substrate 10 and the peripheral edge of the electrical component 30. The routing circuit 51 extends laterally on the top surface of the dielectric layer 40 and the top surface of the interposer 20 to provide horizontal routing, and includes a first metalized blind hole 513 and a second metalized blind hole 514 to provide vertical routing. Furthermore, it is electrically connected to the top circuit layer 13 and the electrical element 30 of the base plate 10. The covering layer 50 is a continuous and unpatterned metal layer, which is disposed below the base plate 10, the interposer 20, and the electrical component 30, and is in thermal conduction with the interposer 20 and the electrical component 30.

13 and 14 are a schematic cross-sectional view and a top perspective view of a semiconductor assembly 110 electrically connected to a semiconductor element 71 and a passive element 73 to the circuit board 100 shown in FIGS. 11 and 12, respectively. The semiconductor element 71 (shown as a wafer) is connected on the top surface of the interposer 20 in a flip-chip manner, and is electrically coupled to the routing circuit 51 through a conductive bump 81. The passive component 73 is connected to the top surface of the dielectric layer 40 and is electrically coupled to the routing circuit 51.

15 is a schematic cross-sectional view of a circuit board according to another aspect of the first embodiment of the present invention. The circuit board 120 is similar to the structure shown in FIG. 11. The difference is that it further includes a top layer increasing circuit 61 on the routing circuit 51. In this figure, the top build-up circuit 61 includes a resin layer 611 and a wire layer 615. The resin layer 611 covers the routing circuit 51 from above, and may be made of epoxy resin, glass epoxy resin, polyimide, or the like. The wire layer 615 extends laterally on the resin layer 611 and includes a third metallized blind hole 617 in the resin layer 611. The third metallized blind holes 617 contact the routing circuit 51 and extend through the resin layer 611.

FIG. 16 is a schematic cross-sectional view of a circuit board according to another aspect of the first embodiment of the present invention. The circuit board 130 is similar to the structure shown in FIG. 11. The difference is that the interposer 20 further includes a built-in circuit 25 which is electrically coupled to the routing circuit 51.

17 is a schematic cross-sectional view of a circuit board according to another aspect of the first embodiment of the present invention. The circuit board 140 is similar to the structure shown in FIG. 16. The difference is that it further includes a top layer increasing circuit 61 on the routing circuit 51. According to this, the top layer-increasing circuit 61 can be electrically connected to the top circuit layer 13 of the substrate 10, the built-in circuit 25 of the interposer 20, and the electrical component 30 through the routing circuit 51.

[Example 2]

18-22 are diagrams of a method for manufacturing a circuit board with a bottom circuit layer in a second embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated herein, and it is not necessary to repeat the same description.

FIG. 18 is a schematic cross-sectional view of the interposer 20 and the electrical component 30 placed in the first through opening 18 and the second through opening 19 of the base plate 10, respectively. The base plate 10 is similar to the structure shown in FIG. 1 except that it further includes a metalized through hole 14 in the core layer 17. The metalized through hole 14 extends through the core layer 17 to provide an electrical connection between the top circuit layer 13 and the bottom metal film 15.

FIG. 19 is a schematic cross-sectional view of forming the dielectric layer 40. The dielectric layer 40 is formed on the top side of the base plate 10 and the top surface of the electrical element 30, and extends into the gap between the base plate 10 and the interposer 20 and between the base plate 10 and the qualitative element 30.

FIG. 20 is a schematic cross-sectional view of forming a blind hole 405 and a through hole 406. The blind holes 405 extend through the dielectric layer 40 to expose selected portions of the top circuit layer from above. The through holes 406 extend through the base plate 10 and the dielectric layer 40 in a vertical direction. The through hole 406 may be formed by mechanical drilling, or by other techniques, such as laser drilling, plasma etching, or a combination of plasma etching and wet etching.

FIG. 21 is a schematic cross-sectional view of forming the coating layer 50 on the top and bottom surfaces of the structure and in the blind holes 405 and the through holes 406. The covering layer 50 fills the blind holes 405 and the through holes 406 to form the metallized blind holes 515 and the covered through holes 56, and completely covers the top and bottom surfaces of the structure.

22 is a schematic cross-sectional view of a routing circuit 51 and a bottom circuit layer 53 formed by a metal patterning process. According to this, the circuit board 200 can be completed at this stage, which includes the base board 10, the interposer 20, the electrical component 30, the dielectric layer 40, the routing circuit 51, the bottom circuit layer 53 and the covered through hole 56. The routing circuit 51 is formed by patterning the coating layer 50 on the top surface of the structure, and the bottom circuit layer 53 is formed by patterning the coating layer 50 on the bottom surface of the structure. At the same time, the bottom metal film 15 is also formed. Be patterned. The routing circuit 51 extends laterally on the top surface of the interposer 20 and the top surface of the dielectric layer 40 and includes a metallized blind hole 515 that contacts the top circuit layer 13 of the base plate 10. The bottom circuit layer 53 extends laterally from the bottom surface of the base plate 10, the bottom surface of the interposer 20, and the bottom surface of the electrical component 30, and is electrically coupled to the metalized through hole 14, the electrical component 30, and the covered through hole 56. Therefore, the bottom circuit layer 53 is electrically connected to the routing circuit 51 through the top circuit layer 13, the metallized through-holes 14 and the covered vias 56, and provides an electrical connection between the electrical component 30 and the routing circuit 51.

23 is a schematic cross-sectional view of a circuit board according to another aspect of the second embodiment of the present invention. The circuit board 210 is similar to the structure shown in FIG. 22, except that it further includes a top layer-increasing circuit 61 on the routing circuit 51. In this figure, the top build-up circuit 61 includes a resin layer 611 and a wire layer 615. The resin layer 611 covers the routing circuit 51 from above, and the wire layer 615 extends laterally on the resin layer 611 and includes a metallized blind hole 618 that contacts the routing circuit 51.

24 is a schematic cross-sectional view of a circuit board according to another aspect of the second embodiment of the present invention. The circuit board 220 is similar to the structure shown in FIG. 23, except that it further includes a bottom build-up circuit 63 on the bottom circuit layer 53. In this figure, the bottom build-up circuit 63 includes a resin layer 631 and a wire layer 635. The resin layer 631 covers the bottom circuit layer 53 from below, and the wiring layer 635 extends laterally on the resin layer 631 and includes metallized blind holes 637 contacting the bottom circuit layer 53.

25 is a schematic cross-sectional view of a circuit board according to another aspect of the second embodiment of the present invention. The circuit board 230 is similar to the structure shown in FIG. 22. The difference is that it further includes a bottom build-up circuit 63 electrically coupled to one of the bottom circuit layers 53, and the interposer 20 further includes an electrical coupling to the routing circuit 51. Built-in circuit 25. In this figure, the bottom build-up circuit 63 includes a resin layer 631 and a wire layer 635. According to this, the built-in circuit 25 of the interposer 20 can be electrically connected to the bottom build-up circuit 63 through the routing circuit 51, the substrate 10, the covered vias 56, and the bottom circuit layer 53.

FIG. 26 is a schematic cross-sectional view of a semiconductor element 240 electrically connected to the semiconductor element 71 and the passive element 73 to the circuit board 200 shown in FIG. 22. Here, the semiconductor element 71 is aligned with the interposer 20, and is connected to the routing circuit 51 in a flip-chip manner through the conductive bump 81, and is electrically coupled to the routing circuit 51. The passive component 73 is connected to the top surface of the dielectric layer 40 and is electrically coupled to the routing circuit 51.

27 is a schematic cross-sectional view of a semiconductor assembly according to another aspect of the second embodiment of the present invention. The semiconductor assembly 250 is similar to the structure shown in FIG. 16 except that it further includes an additional semiconductor element 72 and a sealing material 89. The additional semiconductor element 72 is connected to the semiconductor element 71 and is electrically coupled to the routing circuit 51 through a bonding wire 83. The sealing material 89 covers the semiconductor elements 71 and 72, the passive element 73, and the bonding wire 83 from above.

FIG. 28 is a schematic cross-sectional view of a semiconductor assembly according to another aspect of the second embodiment of the present invention. The semiconductor assembly 260 is similar to the structure shown in FIG. 26, except that (i) the routing circuit 51 does not extend laterally onto the interposer 20, and (ii) the semiconductor element 71 is placed on the interposer 20 and bonded by bonding The line 83 is electrically coupled to the routing circuit 51. (iii) A sealing material 89 is further provided to cover the semiconductor element 71, the passive element 73, and the bonding wire 83 from above.

FIG. 29 is a schematic cross-sectional view of a semiconductor assembly according to another aspect of the second embodiment of the present invention. The semiconductor assembly 270 is similar to the structure shown in FIG. 28. The difference is that the routing circuit 51 extends laterally on the interposer 20 to provide a thermal pad 52 between the interposer 20 and the semiconductor element 71. In this figure, the thermal pad 52 is electrically connected to the base plate 10 through the metallized blind hole 515 to form a ground connection.

[Example 3]

FIG. 30 is a schematic cross-sectional view of a circuit board according to a third embodiment of the present invention. The dielectric layer further covers the top surface of the interposer.

For the purpose of brief description, any description that can be used for the same application in the above embodiments is incorporated herein, and it is not necessary to repeat the same description.

The circuit board 300 is similar to the structure shown in FIG. 11 except that (i) the top surface of the interposer 20 further includes a built-in circuit 25, (ii) the dielectric layer 40 covers the interposer 20 from above, and (iii) the routing circuit 51 further includes a third metallization blind hole 516 connected to the top surface of the interposer 20. In this figure, the substrate 10, the interposer 20, and the electrical component 30 have the same thickness, and the first metallized blind hole 513, the second metallized blind hole 514, and the third metallized blind hole 516 of the routing circuit 51 have Same depth. Through the routing circuit 51, the built-in circuit 25 of the interposer 20 can be electrically connected to the top circuit layer 13 and the electrical component 30 of the substrate 10.

FIG. 31 is a schematic cross-sectional view of the semiconductor element 71 and the passive element 73 electrically connected to the semiconductor group 310 of the circuit board 300 shown in FIG. 30. The semiconductor element 71 is aligned with the interposer 20, and is connected to the top surface of the dielectric layer 60 in a flip-chip manner through the conductive bump 81, and is electrically coupled to the routing circuit 51, and the passive element 73 is also connected. The top surface of the dielectric layer 40 is electrically coupled to the routing circuit 51.

32 is a schematic cross-sectional view of a circuit board according to another aspect of the third embodiment of the present invention. The circuit board 320 is similar to the structure shown in FIG. 30, except that (i) the circuit board 320 further includes a bottom circuit layer 53 and a bottom build-up circuit 63, wherein the bottom circuit layer 53 is located on the bottom surface of the substrate 10 and the interposer 20 on the bottom surface, and the bottom build-up circuit 63 is electrically coupled to the bottom circuit layer 53. (ii) the base plate 10 further includes a metalized through hole 14 and a bottom metal film 15, wherein the metalized through hole 14 is located in the core layer 17. The bottom metal film 15 is located at the bottom side of the base plate 10. The bottom metal film 15 is a patterned metal film, which is combined with the bottom circuit layer 53 and is electrically connected to the top circuit layer 13 through the metalized through holes 14. In this figure, the bottom build-up circuit 63 includes a resin layer 631 and a wire layer 635. The wire layer 635 includes a fourth metallized blind hole 638 that contacts the bottom circuit layer 53. According to this, the combination of the top circuit layer 13, the metalized through hole 14, the bottom circuit layer 53, and the bottom metal film 15 can provide the electrical connection between the routing circuit 51 and the bottom build-up circuit 63, so that the circuit board 320 can be stacked. Sex. In addition, the third metallized blind hole 516 of the routing circuit 51 and the fourth metallized blind hole 638 of the bottom build-up circuit 63 can be used as heat dissipation pipes for heat dissipation.

As shown in the above embodiment, the present invention constructs a unique circuit board, which has an interposer, electrical components, and a substrate, and has high reliability. Preferably, the circuit board mainly includes an interposer, an electrical component, a substrate, a dielectric layer, a routing circuit, and a selective bottom circuit layer, wherein (i) the interposer is inserted on the substrate In the first through opening, and the bottom surface of the interposer is substantially coplanar with the bottom side of the substrate; (ii) the electrical component is inserted into the second through opening in the substrate, and the bottom surface of the electrical component and the substrate The bottom side of the board is substantially coplanar; (iii) the dielectric layer provides mechanical bonding between the interposer and the base board, and between the electrical component and the base board, and the bottom surface of the dielectric layer and the bottom face of the interposer and the base board The bottom side and the bottom surface of the electrical component are substantially coplanar; (iv) the routing circuit is deposited on the top surface of the dielectric layer and is electrically connected to the electrical component and includes an electrical connection to the top circuit layer of the base board Metallized blind vias, where the routing circuit can further extend laterally on the top surface of the interposer; (v) the bottom circuit layer is formed at the bottom side of the substrate, and passes through the metallized through holes and the top circuit layer of the substrate, Or / and electrically coupled to the routing circuit through the covered via .

The thickness of the interposer is greater than or equal to the thickness of the substrate, and the interposer is merged with the substrate by a dielectric layer. Preferably, the interposer has a high coefficient of elasticity and a low coefficient of thermal expansion (for example, 2 x 10 ^-6 K ^-1 to 10 x 10 ^-6 K ^-1 ). For example, the interposer may include a ceramic block (such as Al ₂ O ₃ , AIN, silicon, or the like). Therefore, the thermal expansion coefficient of the interposer can be matched with the semiconductor element placed on it to provide a CTE compensation platform for the semiconductor element, and the internal stress caused by the CTE mismatch can be greatly compensated or reduced. In addition, the interposer also provides a preliminary heat conduction path for the semiconductor device, so that the heat generated by the semiconductor device can be conducted out. Furthermore, the interposer may further include a built-in circuit at the ceramic block, and the built-in circuit is electrically coupled to the routing circuit. Preferably, the built-in circuit can provide electrical contacts on the top surface of the interposer for the next level of circuit connection.

The electrical component may be a resistor, a capacitor, an inductor, or any other passive or active component, and the electrical component may be combined with the substrate through a dielectric layer. In a preferred embodiment, the electrical component is disposed face-up in the second through opening of the base plate, and is electrically connected to the routing circuit through a metallized blind hole of the routing circuit. The bottom surface of the electrical component facing upward may further include a heat conducting material. According to this, the heat generated by the electrical component can be conducted out through the thermally conductive material.

The base board can improve the wiring flexibility of the circuit board. More specifically, the top circuit layer of the substrate board may provide additional routing, which is electrically connected to the routing circuit on the dielectric layer through a metallized blind hole embedded in the dielectric layer. The base plate may further include one or more metallized through holes extending through the base plate in a vertical direction and providing an electrical connection between the top wiring layer and the bottom wiring layer. In addition, the substrate can be used to control the placement accuracy of the interposer and electrical components. More specifically, the inner side walls of the first through opening and the second through opening of the base plate can be used as positioning members when the interposer and the electrical component are placed. The inner side wall of the first through opening of the base plate may be laterally aligned with the four lateral surfaces of the interposer to define an area having the same or similar shape as the interposer to avoid lateral displacement of the interposer. Similarly, the inner side wall of the second through-opening of the base plate can be aligned laterally to the four sides of the electrical component to define a region with the same or similar shape as the electrical component to avoid lateral displacement of the electrical component. Therefore, the inner side wall of the base plate is close to the peripheral edge of the interposer and the peripheral edge of the electrical component to control the placement accuracy of the interposer and the electrical component.

The dielectric layer may further cover the top surface of the interposer, or the top surface of the dielectric layer and the top surface of the interposer may be substantially coplanar. Since the dielectric layer extends into the gap between the peripheral edge of the interposer and the inner side wall of the first through-opening and the peripheral edge of the electrical element and the inner side wall of the second through-opening, the interlayer and the electric component can be formed by the dielectric layer. It is firmly joined with the base plate.

The routing circuit on the top surface of the dielectric layer can further extend to the top surface of the interlayer. Therefore, the routing circuit can provide electrical contacts on the top surface of the interposer, so that the semiconductor device can be flip-chiped on the interposer, or the routing circuit can provide a thermal pad on the top surface of the interposer, so that the semiconductor component faces The ground is placed on top. When the dielectric layer covers the top surface of the interposer, the routing circuit preferably includes an additional metallized blind hole, and the additional metallized blind hole is connected to the top surface of the interposer. For example, an additional metallized blind hole in the dielectric layer can be contacted and electrically coupled to a built-in circuit of the interposer to be electrically connected to the interposer. Alternatively, the additional metallized blind holes can be used as a heat pipe contacting the top surface of the interposer for heat dissipation. The routing circuit can be formed by lithographic metal deposition. Preferably, the routing circuit is formed by a sputtering process followed by a plating process.

The bottom circuit layer may further extend laterally on the bottom surface of the electrical component or / and the bottom surface of the interposer. In a preferred embodiment, the base board includes a bottom metal film, which is a patterned metal film at the bottom side of the base board and is electrically connected to the top circuit layer of the base board, and the bottom circuit layer is Combined with the bottom metal film. Therefore, the bottom circuit layer can be electrically connected to the routing circuit through the metalized vias connected to the top circuit layer and the bottom metal film. The metalized through holes can extend through the base plate in a vertical direction and are located between the top circuit layer and the bottom circuit layer. Alternatively, and / or, the bottom circuit layer may be electrically connected to the routing circuit through a covered via connected to the top circuit layer and the bottom circuit layer. The covered through holes can extend through the substrate and the dielectric layer in a vertical direction, and are located between the routing circuit and the bottom circuit layer. According to this, the routing circuit and the bottom circuit layer can provide electrical contacts at the top and bottom sides of the circuit board to make the circuit board stackable. In addition, when the electrical component is disposed face down in the second through opening of the base plate, the bottom circuit layer can be electrically coupled to the electrical component. According to this, the electrical component can be electrically connected to the routing circuit through the bottom circuit layer.

For further wiring, the circuit board may further include a top build-up circuit or / and a bottom build-up circuit. The top layer-increasing circuit can cover the top surface of the interposer, the top surface of the dielectric layer, and the routing circuit, and is electrically coupled to the routing circuit, and is preferably in thermal conduction with the interposer. The bottom build-up circuit can cover the bottom surface of the interposer, the bottom side of the substrate, the bottom surface of the electrical component, and the bottom circuit layer, and is electrically coupled to the bottom circuit layer, and is preferably in thermal conduction with the interposer. In a preferred embodiment, the top build-up circuit and the bottom build-up circuit are multilayer build-up circuits without a core layer, which include at least one resin layer and at least one wire layer, and the wire layer fills the blind in the resin layer. Holes and extend laterally on the resin layer. The resin layer and the wire layer can be formed alternately and alternately, and can be repeatedly formed if necessary. In addition, the outermost wire layers of the top build-up circuit and the bottom build-up circuit can be respectively connected with conductive contacts, such as solder balls or bonding wires, for electrical transmission and mechanical connection with the assembly, electronic components or other components.

The present invention also provides a semiconductor assembly. A semiconductor element (such as a wafer) is connected to the top surface of the interposer of the circuit board, and is electrically coupled to the routing circuit. More specifically, the semiconductor element can be electrically connected to the circuit board through various connection media, where the connection medium can include a conductive bump (such as a gold bump or a solder bump) provided on the routing circuit of the circuit board, or Connect to the bonding wire of the circuit board routing circuit.

The group can be a first- or second-stage single crystal or polycrystalline device. For example, the group may be a first-level package including a single chip or multiple chips. Alternatively, the group may be a second-level module including a single package or multiple packages, where each package may include a single or multiple chips. The semiconductor device may be a packaged wafer or an unpackaged wafer. In addition, the semiconductor device may be a bare chip, or a wafer-level package die.

The term "coverage" means incomplete and complete coverage in vertical and / or lateral directions. For example, in a preferred embodiment, the bottom build-up circuit may cover the interposer, the substrate, and the electrical components below, regardless of whether another component (such as the bottom circuit layer) is located between the bottom build-up circuit and the interposer. , Between the bottom buildup circuit and the substrate, and between the bottom buildup circuit and the electrical component.

The terms "connected to" and "connected to" include contact and non-contact with one or more components. For example, a semiconductor element can be placed on the interposer, regardless of whether the semiconductor element is separated from the interposer by a routing circuit and a conductive bump.

The term "aligned" means the relative position between elements, whether or not the elements are kept at a distance or abutted from each other, or one element is inserted and extended into another element. For example, in a preferred embodiment, when the imaginary horizontal line intersects the inner wall of the substrate and the peripheral edge of the interposer / electrical component, the inner wall of the substrate is laterally aligned with the outer edge of the interposer / electrical component. , Whether or not there is another component that intersects the imaginary horizontal line between the inner wall of the substrate and the peripheral edge of the interposer / electrical component, and whether it has another intersection with the peripheral edge of the interposer / electrical component but not inside the substrate An imaginary horizontal line that intersects the side wall, or intersects the inner side wall of the substrate but does not intersect the peripheral edge of the interposer / electrical component. Similarly, in a preferred embodiment, part of the metallized blind vias of the routing circuit are aligned with the interposer.

The term "close" means that the width of the gap between the components does not exceed the maximum acceptable range. As is known in the art, when the gap between the peripheral edge of the interposer / electrical component and the inner wall of the substrate is not narrow enough, the interposer / electrical component cannot be accurately restricted to a predetermined position. The maximum acceptable limit of the gap between the peripheral edge of the interposer / electrical component and the inner wall of the substrate can be determined according to the degree of accuracy desired when the interposer / electrical component is set at a predetermined position. Therefore, the descriptions of "the peripheral edge of the interposer near the inner wall of the first through opening" and "the peripheral edge of the electrical component near the inner wall of the second through opening" refer to the gap between the peripheral edge of the interposer / electrical component and the inner wall of the through opening. It is narrow enough to prevent the positional error of the interposer / electrical component from exceeding the acceptable maximum error limit. For example, the gap between the peripheral edge of the interposer and the inner side wall of the first through opening, and the gap between the peripheral edge of the electrical component and the inner side wall of the second through opening may be in the range of about 25 microns to 100 microns.

The terms "electrically connected" and "electrically coupled" mean directly or indirectly electrically connected. For example, in a preferred embodiment, the electrical component can be electrically connected to the built-in circuit of the interposer via a routing circuit, but the electrical component does not contact the built-in circuit of the interposer.

The circuit board of the present invention has many advantages. For example, the interposer can provide a platform for compensating CTE for connecting semiconductor components, and at the same time provide a heat dissipation path to dissipate the heat generated by the semiconductor components. This electrical element can improve the electrical characteristics of the semiconductor assembly. The base board can provide mechanical support and improve the wiring flexibility of the circuit board. The dielectric layer can provide a mechanical bonding force between the interposer and the base plate and between the electrical component and the base plate. The routing circuit can provide horizontal electrical routing and vertical electrical routing to electrically connect another horizontal electrical routing and electrical component in the base board. The circuit board prepared by this method has high reliability, low price, and is very suitable for mass production.

The manufacturing method of the present invention has high applicability, and uses various mature electrical and mechanical connection technologies in a unique and progressive way. In addition, the manufacturing method of the present invention can be implemented without expensive tools. Therefore, compared with the traditional technology, this production method can greatly improve the yield, yield, efficiency and cost effectiveness.

The embodiments described herein are for illustrative purposes, and the embodiments may simplify or omit elements or steps that are well known in the technical field, so as not to obscure the features of the present invention. Similarly, to make the drawings clear, the drawings may omit repeated or unnecessary components and component symbols.

100, 200, 300‧‧‧ circuit boards

110, 120, 130, 140, 210, 220, 230, 240, 250, 260, 270, 310, 320

10‧‧‧ base plate

13‧‧‧Top circuit layer

14‧‧‧ metallized through holes

15‧‧‧ bottom metal film

17‧‧‧ core layer

18‧‧‧ the first through opening

19‧‧‧ Second through opening

20‧‧‧ intermediary

21‧‧‧Ceramic block

25‧‧‧Built-in circuit

30‧‧‧electrical components

31‧‧‧Conductive material

40‧‧‧ Dielectric layer

403‧‧‧first blind hole

404‧‧‧Second Blind Hole

405‧‧‧ blind hole

406‧‧‧through hole

50‧‧‧ Coating

51‧‧‧ routing circuit

513‧‧‧First metallized blind hole

514‧‧‧Second metallized blind hole

515, 618, 637‧‧‧ metallized blind holes

516, 617‧‧‧ Third metallized blind hole

52‧‧‧ Thermal Pad

53‧‧‧ bottom circuit layer

56‧‧‧ Covered Through Hole

61‧‧‧Top layer increase circuit

611, 631‧‧‧ resin layer

615, 635‧‧‧conductor layer

638‧‧‧The fourth metallized blind hole

63‧‧‧Bottom layer increase circuit

71, 72‧‧‧ semiconductor components

73‧‧‧Passive components

81‧‧‧Conductive bump

83‧‧‧ bonding wire

89‧‧‧sealing material

With reference to the accompanying drawings, the present invention can be more clearly understood through the detailed description of the following preferred embodiments, wherein: FIGS. 1 and 2 are a schematic cross-sectional view and a top perspective view of a base plate in the first embodiment of the present invention, respectively; 3 and 4 are respectively a cross-sectional schematic diagram and a top perspective schematic diagram of an interposer and an electrical component provided in the structure of FIGS. 1 and 2 in the first embodiment of the present invention; FIGS. 5 and 6 are respectively the first embodiment of the present invention. Sectional and top perspective views of the dielectric layer are provided in the structures of Figs. 3 and 4; Figs. 7 and 8 respectively show the upper half of the dielectric layer in the structure of Figs. 5 and 6 in the first embodiment of the present invention. Sectional schematic diagram and top perspective diagram; Figures 9 and 10 are the first and second blind hole cross-sectional diagrams and top perspective diagrams of the first embodiment of the present invention, respectively, in the structure of Figures 7 and 8; Figures 11 and 12 In the first embodiment of the present invention, cross-sectional schematic diagrams and top perspective schematic diagrams of providing routing circuits and coatings to complete the production of circuit boards are provided in the structures of FIGS. 9 and 10 respectively. FIGS. 13 and 14 are the first embodiment of the present invention, respectively. Figures 11 and 12 A schematic cross-sectional view and a top perspective view of a semiconductor element and a passive element are provided in the structure; FIG. 15 is a schematic cross-sectional view of a circuit board in another aspect of the first embodiment of the present invention; FIG. 16 is a further schematic view of the first embodiment of the present invention. A schematic cross-sectional view of a circuit board in one aspect; FIG. 17 is a schematic cross-sectional view of a circuit board in another aspect in the first embodiment of the present invention; FIG. 18 is a schematic view of a substrate, an interposer, and an electrical component in the second embodiment of the present invention; 19 is a schematic cross-sectional view of a dielectric layer provided in the structure of FIG. 18 in a second embodiment of the present invention; FIG. 20 is a schematic view of a blind hole and a through-hole provided in the structure of FIG. 19 in a second embodiment of the present invention 21 is a schematic cross-sectional view of a coating layer provided in the structure of FIG. 20 in a second embodiment of the present invention; FIG. 22 is a routing circuit and a bottom circuit layer formed in the structure of FIG. 21 in a second embodiment of the present invention; A schematic cross-sectional view of the finished circuit board; FIG. 23 is a schematic cross-sectional view of another circuit board in the second embodiment of the present invention; FIG. 24 is a cross-sectional schematic view of another circuit board in the second embodiment of the present invention 25; FIG. 25 is a schematic cross-sectional view of a circuit board according to another aspect of the second embodiment of the present invention; FIG. 26 is a schematic cross-sectional view of a semiconductor element and a passive element provided in the structure of FIG. 22 in the second embodiment of the present invention; 27 is a schematic cross-sectional view of a semiconductor element, a passive element, and a sealing material provided in the structure of FIG. 22 in the second embodiment of the present invention; FIG. 28 is a diagram of providing a semiconductor in a circuit board of another aspect in the second embodiment of the present invention A schematic cross-sectional view of a component, a passive component and a sealing material; FIG. 29 is a schematic cross-sectional view of a semiconductor device, a passive component and a sealing material provided in another aspect of a circuit board in a second embodiment of the present invention; In the third embodiment, a schematic cross-sectional view of a circuit board; FIG. 31 is a schematic cross-sectional view of a semiconductor device and a passive component provided in the structure of FIG. 30 in a third embodiment of the present invention; FIG. 32 is another view of a third embodiment of the present invention. Schematic diagram of the circuit board section.

Claims (8)

A method for manufacturing a circuit board provided with an interposer and electrical components includes the following steps: providing a base board having a top side, a bottom side, a first through opening, a second through opening, and One of the top circuit layers on the top side, wherein the first through opening and the second through opening each have an inner side wall extending from the top side to the bottom side; an interposer is inserted into the first through opening of the base board And inserting an electrical component into the second through opening of the base plate, wherein the interposer comprises a ceramic block; forming a dielectric layer on a top surface of the electrical component, the A gap between the peripheral edge of the interposer and the inner side walls of the first through opening on the top side, and a gap between the outer edge of the electrical component and the inner side walls of the second through opening; and A routing circuit is on a top surface of the dielectric layer, and the routing circuit is electrically connected to the electrical component, and is electrically connected to the base plate through a metallized blind hole. The manufacturing method according to item 1 of the scope of patent application, wherein the thickness of the interposer is greater than the thickness of the substrate, and a top surface of the interposer is substantially coplanar with the top surface of the dielectric layer. The routing circuit extends laterally to the top surface of the interposer. The manufacturing method described in item 1 of the patent application scope further includes a step of forming a bottom circuit layer at the bottom side of the base board, and the bottom circuit layer is electrically coupled to the routing circuit. The manufacturing method as described in item 3 of the scope of patent application, wherein the bottom circuit layer extends laterally to the bottom surface of the electrical component, and the electrical component is electrically connected to the electrical component through the bottom circuit layer. Routing circuit. The manufacturing method according to item 3 of the scope of patent application, wherein the bottom circuit layer extends laterally to the bottom surface of the interposer. The manufacturing method according to item 1 of the scope of patent application, wherein the interposer further includes a built-in circuit, and the routing circuit is more electrically connected to the built-in circuit of the interposer. The manufacturing method described in item 6 of the patent application scope further includes a step of forming a top build-up circuit covering the routing circuit and the interposer. The top build-up circuit includes at least one resin layer formed alternately and At least one wire layer, and the wire layer is electrically coupled to the built-in circuit and the routing circuit of the interposer. The manufacturing method described in item 3 of the patent application scope further includes a step of forming a bottom build-up circuit that covers the bottom circuit layer, the interposer, and the electrical component. The bottom build-up circuit includes alternate turns formation. At least one resin layer and at least one wire layer, and the wire layer is electrically coupled to the bottom circuit layer.