TW201937673A - 3D stacking semiconductor assembly having heat dissipation characteristics - Google Patents

Abstract

A semiconductor assembly having heat dissipation characteristics includes stacked semiconductor chips thermally conductible to a thermal pad of an interconnect substrate and electrically connected to the interconnect substrate through bonding wire. The bonding wires extending from a primary routing circuitry in between the stacked chips can accommodate the height difference between the stacked chips and the interconnect substrate. These wires can also effectively compensate for the thermal expansion mismatch between the stacked chips and the interconnect substrate, thereby allowing a higher manufacturing yield and better reliability.

Description

Three-dimensional stackable semiconductor assembly with heat dissipation characteristics

The present invention relates to a semiconductor assembly, in particular to a semiconductor assembly that thermally conducts a stacked semiconductor sub-assembly to a thermal conductive pad of an interconnect substrate, wherein the stacked semiconductor sub-assembly system is electrically connected to the interconnect through a bonding wire Substrate.

The market trend of multimedia devices tends to be faster and thinner. One method is to stack two devices to interconnect the two devices so that the two devices have the shortest routing distance. Because the stacked devices can directly transmit to each other to reduce the delay, the signal integrity of the group can be greatly improved, and additional energy consumption can be saved. However, since semiconductor devices are prone to performance degradation at high operating temperatures, if the stacked chips are not properly radiated, the device performance will deteriorate, and the reliability and service life of the assembly will decrease.

US Patent Nos. 5,790,384, 6,984,544, 7,026,719, 8,971,053, and 9,263,332 disclose various face-to-face three-dimensional stacked assemblies for this purpose. However, these stacked wafers have no way to dissipate heat, so the heat generated by the tightly stacked wafers can quickly accumulate, leading to an immediate failure condition during operation. In addition, because these sub-groups need to use soldering materials to connect to the external environment, solder cracks or misalignments may occur between the group and the interconnect substrate due to warping or thermal expansion mismatch, which will cause serious problems. Reliability issues.

For the above reasons and other reasons described below, it is urgent to develop a semiconductor assembly to meet the requirements of high package density, better signal integrity and high heat dissipation.

An object of the present invention is to provide a semiconductor assembly, so as to place a stacked semiconductor sub-assembly on a thermal pad of an interconnection substrate. Since the heat generated by the stacked wafers can be efficiently dissipated, the thermal performance of the assembly can be greatly improved.

The semiconductor assembly may further include a plurality of bonding wires, which extend from the primary routing circuit between the stacked wafers to the interconnection substrate, whereby the stacked sub-assembly can be electrically connected to the external environment. The bonding wire can correspond to the height difference between the primary routing circuit and the interconnection substrate, and can effectively compensate for the thermal expansion mismatch between the sub-group and the interconnection substrate, thereby improving yield and reliability.

According to the above and other objectives, the present invention provides a three-dimensional semiconductor assembly having heat dissipation properties, which includes: a stacked semiconductor sub-assembly including a primary routing circuit, a first device, and a second device, where (i The primary routing circuit has a first surface facing the first direction, a second surface facing the opposite second direction, a first conductive pad located on the first surface, and a first surface located on the second surface and electrically connected to the first conductive pad. Two conductive pads, (ii) the first device is disposed on the first surface of the primary routing circuit, and is electrically coupled to the primary routing circuit through the first conductive pad, and (iii) the second device is disposed on the primary routing circuit The second surface is electrically coupled to the primary routing circuit through a second conductive pad; an interconnect substrate having a thermal pad and a plurality of metal leads, and the metal leads are disposed around the thermal pad, wherein heat is conducted The pad and the metal lead each have a front side facing the first direction, and the front side of the thermal pad is attached to the second device by a thermal conductive material; and a plurality of bonding wires that electrically electrically connect the first surface of the primary routing circuit Connected to the front side of a lead wire.

In another aspect, the present invention further provides another heat-dissipative three-dimensional semiconductor assembly including a stacked semiconductor sub-assembly including a primary routing circuit, a first device, and a second device. (I) the primary routing circuit has a first surface facing the first direction, a second surface facing the opposite second direction, a first conductive pad on the first surface, and a second surface electrically connected to the first conductive surface A second conductive pad of the pad, (ii) the first device is disposed on the first surface of the primary routing circuit, and is electrically coupled to the primary routing circuit through the first conductive pad, and (iii) the second device is disposed on The second surface of the primary routing circuit is electrically coupled to the primary routing circuit through a second conductive pad; an interconnect substrate having a thermal pad and a surrounding layer, wherein (i) the thermal pad has a facing The front side of the first direction, and the front side of the thermal pad is attached to the second device by a thermal conductive material, (ii) the surrounding layer of the interconnect substrate has a dielectric layer and a contact pad, and (iii) the dielectric layer is bonded to the thermal A sidewall of the pad, and the dielectric layer has a first side To the front side, (iv) a contact pad is disposed on the front surface of the dielectric layer; a plurality of terminals are electrically coupled to the contact pad and disposed around a peripheral edge of the stacked semiconductor sub-group; and a plurality of bonding wires, which The contact pads are connected to the primary routing circuit and the surrounding layer to electrically connect the stacked semiconductor sub-groups to the terminals.

The semiconductor assembly of the present invention has many advantages. For example, stacking and electrically coupling the first device and the second device to opposite sides of the primary routing circuit can provide the shortest interconnection distance between the first device and the second device. It is particularly advantageous to place the stacked semiconductor sub-groups on the thermally conductive pad of the interconnect substrate, because the thermally conductive pad can provide a second device heat dissipation path. In addition, the method of connecting the bonding wires to the primary routing circuit and the interconnection substrate can provide a reliable connection channel to interconnect the devices assembled in the sub-assembly to the external environment.

The above and other features and advantages of the present invention can be made clearer by the following detailed description of the preferred embodiments.

In the following, an embodiment will be provided to explain the implementation of the present invention in detail. The advantages and effects of the present invention will be more significant by the content disclosed by the present invention. The attached drawings are simplified and used for illustration. The number, shape and size of the components shown in the drawings can be modified according to the actual situation, and the configuration of the components may be more complicated. The present invention can also be practiced or applied in other aspects, and various changes and adjustments can be made without departing from the spirit and scope defined by the present invention.

[Example 1]

1-16 is a diagram of a method for fabricating a semiconductor assembly in the first embodiment of the present invention, which includes a primary routing circuit, a reinforcement layer, a first device, a second device, an interconnect substrate, and a bonding wire. And a molding material.

FIGS. 1, 2 and 3 are a schematic cross-sectional view, a top perspective view and a bottom perspective view of the bonding of the primary routing circuit 11 and the reinforcing layer 13, respectively. In this embodiment, the primary routing circuit 11 is a multilayer build-up circuit, and includes a dielectric layer 111 and a circuit layer 113. The dielectric layer 111 generally has a thickness of 50 micrometers, and may be made of epoxy resin, glass epoxy resin, polyimide, or the like. The circuit layer 113 is usually made of copper and extends laterally on the dielectric layer 111 and includes a conductive blind hole 114 extending through the dielectric layer 111. As shown in FIGS. 2 and 3, the circuit layer 113 provides a first conductive pad 115 and a terminal pad 117 on the first surface 101, and a second conductive pad 119 on the second surface 103. The pad size and pad spacing of the terminal pad 117 are larger than the pad size and pad spacing of the first conductive pad 115, and the second conductive pad 119 is exposed from the reinforcing layer 13 opening 135 on the second surface 103 of the primary routing circuit 11. The reinforcing layer 13 may be made of resin, ceramic, metal, metal composite, or a single-layer or multi-layer structure having sufficient mechanical strength to provide mechanical support for the substrate.

4, 5 and 6 are a schematic cross-sectional view, a top perspective view and a bottom perspective view, respectively, of the first device 21 and the second device 23 electrically coupled to the primary routing circuit 11. At this stage, the fabrication of the stacked semiconductor sub-group 10 is completed, which includes a primary routing circuit 11, a reinforcing layer 13, a first device 21 and a second device 23. The first device 21 is disposed on the first surface 101 of the primary routing circuit 11, and the second device 23 is disposed in the cavity 107, where the cavity 107 is opened by the second surface 103 of the primary routing circuit 11 and the reinforcing layer 13 135 The inner side wall 105 is formed. In this embodiment, the first device 21 and the second device 23 (illustrated as bare chips) are electrically coupled to the primary routing circuit 11 through the first conductive bump 213 and the second conductive bump 233, respectively. The first conductive bump 213 contacts the first device 21 and the first conductive pad 115 so that the first device 21 is electrically coupled to the circuit layer 113 of the primary routing circuit 11. The second conductive bump 223 contacts the second device 23 and the second conductive pad 119, so that the second device 23 is electrically coupled to the circuit layer 113 of the primary routing circuit 11. Accordingly, the first device 21 and the second device 23 can be electrically connected to each other through the primary routing circuit 11.

7 and 8 are a schematic cross-sectional view and a top perspective view of the interconnect substrate 30, respectively. In this figure, the interconnect substrate 30 is a lead frame 31, which is generally made of copper alloy, steel, or alloy 42 and can be wet-etched by rolling a metal strip. Or formed by stamping / punching process. Here, an etching process may be performed on one or both sides to etch through the metal strip, and then the metal strip is made into a lead frame 31 having a predetermined overall pattern. In this embodiment, the lead frame 31 has a uniform thickness in a range of about 0.15 mm to 1.0 mm, and includes a metal frame 32, a plurality of metal leads 33, a thermal pad 35, and a plurality of connecting rods 36. The metal leads 33 extend laterally from the metal frame 32 toward a central region in the metal frame 32. Therefore, each metal lead 33 has an outer end 331 and an inner end 333. The outer end 331 of the metal lead 33 is integrally connected to the inner side wall of the metal frame 32, and the inner end 333 of the metal lead 33 faces away from the inside. Metal frame 32. The thermal pad 35 is a metal pad, which is located in a central region of the metal frame 32 and is connected to the metal frame 32 by a connecting rod 36.

9 and 10 are a schematic cross-sectional view and a top perspective view of the stacked semiconductor sub-group 10 shown in FIG. 4 attached to the interconnection substrate 30, respectively. The stacked semiconductor sub-group 10 shown in FIG. 4 is connected to the heat-conducting pad 35 of the interconnection substrate 30, and the second device 23 is attached to the front side 311 of the heat-conducting pad 35 by the heat-conducting material 51.

11 and 12 are a schematic cross-sectional view and a top perspective view of the bonding wire 61 connected to the stacked semiconductor sub-group 10 and the interconnect substrate 30, respectively. It can usually be achieved by gold or copper ball bonding or gold or aluminum wedges. In a wedge bonding method, a bonding wire 61 is connected. The bonding wire 61 contacts and is electrically coupled to the terminal pad 117 of the primary routing circuit 11 and the front side 311 of the metal lead 33 of the interconnection substrate 30. Therefore, the first device 21 and the second device 23 can be electrically connected to the interconnection substrate 30 through the primary routing circuit 11 and the bonding wire 61.

FIG. 13 is a schematic cross-sectional view provided with a molding material 71. The molding compound 71 covers and covers the primary routing circuit 11, the reinforcing layer 13, the first device 21 and the bonding wire 61 from above, and further extends into the space between the metal leads 33 and the gap between the thermal pad 35 and the metal leads 33. .

14, 15, and 16 are a schematic cross-sectional view, a top perspective view, and a bottom perspective view of the semiconductor assembly 100 separated from the metal frame 32, respectively. The metal frame 32 may be removed by various methods including chemical etching, mechanical cutting / cutting or sawing. Accordingly, the metal frame 32 can be separated from the outer end 331 of the metal lead 33. At this stage, the interconnect substrate 30 includes metal leads 33, a thermal pad 35, and a connecting rod 36, wherein the outer end 331 of the metal lead 33 is located at the peripheral edge of the interconnect substrate 30, and the outer end 331 of the metal lead 33 is on the side It is flush with the peripheral edge of the molding material 71.

17 is a schematic cross-sectional view of a semiconductor assembly according to another aspect of the first embodiment of the present invention. The semiconductor assembly 110 is similar to the structure shown in FIG. 14 except that the primary routing circuit 11 includes a plurality of dielectric layers 111 and a plurality of circuit layers 113 which are alternately formed in turn, and the first device 21 is electrically connected by a bonding wire 215. Sexually connected to the primary routing circuit 11. In this aspect, the primary routing circuit 11 has a first conductive pad 115 and a metal pad 116 on the first surface 101 and a second conductive pad 119 on the second surface 103. The first device 21 is attached to the metal pad 116 and is electrically connected to the first conductive pad 115 through a bonding wire 215. In addition, the first conductive pad 115 is further electrically connected to the metal lead 33 through a bonding wire 61.

18 and 19 are respectively a schematic cross-sectional view and a bottom perspective view of a semiconductor assembly according to another aspect of the first embodiment of the present invention. The structure of the semiconductor assembly 120 is similar to that shown in FIG. 14. The difference is that the thermal pad 35 is an electrically insulating pad having thermal conductivity, and the interconnect substrate 30 does not include a connecting rod integrally formed with the thermal pad 35. Electrically conductive pads with thermal conductivity are usually made of materials with high elastic modulus and low coefficient of thermal expansion (for example, 2 x 10 ^-6 K ^-1 to 10 x 10 ^-6 K ^-1 ), such as ceramics, silicon, Glass or other materials. In this embodiment, the thermal pad 35 is a ceramic pad having a thickness substantially equal to the thickness of the metal lead 33. Therefore, the thermally conductive pad 35 can not only provide main heat dissipation, but also provide a CTE compensation platform for the second device 23.

[Example 2]

20-24 are diagrams of a method for fabricating another semiconductor assembly according to a second embodiment of the present invention, in which the thermal pad has a stepped peripheral edge.

For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated herein, and it is not necessary to repeat the same description.

FIG. 20 is a schematic cross-sectional view of a stacked semiconductor sub-group 10 having a primary routing circuit 11, a reinforcing layer 13, a first device 21, a second device 23, a passive element 24, and a metal pillar 25. In this figure, the primary routing circuit 11 is a multi-layer build-up circuit, which includes a dielectric layer 111 and a plurality of circuit layers 113 which are alternately formed. The first device 21 is electrically connected to the first routing circuit 11 from the first surface 101 of the primary routing circuit 11, and the second device 23, the passive element 24 and the metal pillar 25 are connected from the second surface 103 of the primary routing circuit 11. Is electrically coupled to the primary routing circuit 11. In this embodiment, the first device 21 is electrically coupled to the first conductive pad 115 of the primary routing circuit 11 through the first conductive bump 213, and the second device 23 is connected to the first conductive pad 115 through the second conductive bump 233. Is electrically coupled to the second conductive pad 119 of the primary routing circuit 11. The reinforcing layer 13 covers the second surface 103 of the primary routing circuit 11, and surrounds and uniformly covers and surrounds the second device 23, the passive element 24 and the metal pillar 25. Alternatively, the reinforcing layer 13 may be omitted.

FIG. 21 is a schematic cross-sectional view of the stacked semiconductor sub-group 10 shown in FIG. 20 attached to the interconnect substrate 30. The interconnection substrate 30 is similar to the structure shown in FIGS. 7 and 8 except that the peripheral edge of the thermal pad 35 is stepped. In this figure, the second device 23 is in thermal conduction with the thermal pad 35 for heat dissipation, and the metal pillar 25 is electrically connected to the thermal pad 35 to form a ground connection.

FIG. 22 is a schematic cross-sectional view of the stacked semiconductor sub-group 10 electrically connected to the interconnection substrate 30 through a bonding wire 61. The bonding wire 61 is connected to the terminal pad 117 of the primary routing circuit 11 and the metal lead 33 of the interconnection substrate 30 to electrically connect the stacked semiconductor sub-group 10 to the interconnection substrate 30.

FIG. 23 is a schematic cross-sectional view of the molding material 71. The molding material 71 covers and surrounds the primary routing circuit 11, the reinforcing layer 13, the first device 21, and the bonding wire 61 from above, and further extends into the space between the metal leads 33 and the gap between the thermal pad 35 and the metal leads 33. Since the molding material 71 surrounds the side surface and covers the thermal pad 35 in the same shape, the molding material 71 also has a stepped cross-sectional profile at the stepped peripheral edge of the contacting thermal pad 35. According to this, the molding material 71 can be firmly bonded to the interconnection substrate 30 to prevent the interconnection substrate 30 from detaching from the molding material 71 in a vertical direction, and avoid forming a crack at the interface in a vertical direction.

FIG. 24 is a schematic cross-sectional view of the semiconductor assembly 200 separated from the metal frame 32. The metal frame 32 and the metal lead 33 can be separated by chemical etching, mechanical cutting / cutting or sawing to cut off the connection between the metal leads 33, and the side of the outer end 331 of the metal lead 33 is connected to the molding material 71 The peripheral edges are flush.

25 is a schematic cross-sectional view of a semiconductor assembly according to another aspect of the second embodiment of the present invention. The semiconductor assembly 210 is similar to the structure shown in FIG. 24 except that (i) the first device 21 is electrically connected to the primary routing circuit 11 through a bonding wire 215, and (ii) the third device 27 is further provided. The third conductive bump 273 is electrically coupled to the primary routing circuit 11, (iii) the thermal pad 35 is an electrically insulating pad having thermal conductivity, and the interconnect substrate 30 does not include a connecting rod integrally formed with the thermal pad 35 .

[Example 3]

26-33 are diagrams of a method for fabricating a semiconductor assembly according to a third embodiment of the present invention, in which the metal leads have a stepped peripheral edge.

For the purpose of brief description, any description that can be used for the same application in the above embodiments is incorporated herein, and it is not necessary to repeat the same description.

26 and 27 are a schematic cross-sectional view and a top perspective view of the lead frame 31, respectively, which have a metal frame 32, a plurality of metal leads 33, and a thermal pad 35. In the present embodiment, the metal leads 33 are parallel to each other, and are integrally connected to the metal frame 32 with a stepped peripheral edge. The thermally conductive pad 35 is an electrically insulating pad having thermal conductivity, and is located in a central region within the metal frame 32.

28 and 29 are a schematic sectional view and a top perspective view of the compound layer 37, respectively. The compound layer 37 can be formed by applying a molding compound to the remaining space in the metal frame 32. According to this, the compound layer 37 can fill the space between the metal leads 33 and the gap between the metal leads 33 and the thermal pad 35 to provide a stable bonding force between the metal leads 33 and the thermal pad 35. In addition, through the planarization step, the front surface 371 of the compound layer 37 is substantially coplanar with the front side 311 of the metal lead 33 and the thermal pad 35, and the back surface 373 of the compound layer 37 is back to the back of the metal lead 33 and the thermal pad 35. The sides 313 are substantially coplanar. Preferably, the compound layer 37 has an elastic modulus greater than 1.0 GPa and a linear thermal expansion coefficient ranging from about 5 x 10 ^-6 K ^-1 to 15 x 10 ^-6 K ^-1 . In addition, since the compound layer 37 surrounds in the lateral direction and covers the metal lead 33 in the same shape, the compound layer 37 also has a stepped cross-sectional profile at the stepped peripheral edge of the contacting metal lead 33. According to this, the compound layer 37 can be firmly bonded to the lead frame 31 to prevent the lead frame 31 from detaching from the compound layer 37 in the vertical direction, and to prevent the formation of cracks at the interface in the vertical direction.

The uncut interconnect substrate 30 has been completed at this stage, which includes a lead frame 31 and a compound layer 37.

30 and 31 are a schematic cross-sectional view and a top perspective view, respectively, of the stacked semiconductor sub-group 10 shown in FIG. 4 electrically connected to the interconnect substrate 30 shown in FIGS. 28 and 29. The stacked semiconductor sub-group 10 shown in FIG. 4 is connected to the thermal pad 35 of the interconnection substrate 30 through a thermally conductive material 51. The thermally conductive material 51 will contact the second device 23 and the thermally conductive pad 35, and the stack The semiconductor sub-group 10 is electrically connected to the metal lead 33 through a bonding wire 61. Here, the bonding wire 61 is connected to the terminal pad 117 of the primary routing circuit 11 and the metal lead 33 of the interconnection substrate 30.

32 and 33 are a schematic cross-sectional view and a top perspective view of the semiconductor assembly 300 separated from the metal frame 32, respectively, and a molding material 71 may optionally be further provided. The metal frame 32 and the metal lead 33 can be separated by chemical etching, mechanical cutting / cutting or sawing to cut the connection between the metal leads 33. In addition, a molding material 71 may be optionally further formed to cover and surround the primary routing circuit 11, the reinforcing layer 13, the first device 21, and the bonding wire 61 from above. In this embodiment, each metal lead 33 has a horizontal extending portion 335 extending laterally beyond the peripheral edge of the molding material 71 as a pin terminal for external connection.

34 and 35 are a schematic cross-sectional view and a top perspective view of a semiconductor assembly according to another aspect of the third embodiment of the present invention, respectively. The semiconductor group body 310 is similar to the structure shown in FIGS. 32 and 33 except that the metal leads 33 are bent upward, and each metal lead 33 has a horizontal flat portion 336 and a vertical extension portion 337. Here, the vertical extension portion 337 extends upward from the front side 311 of the horizontal flat portion 336 beyond the outer surface of the molding material 71.

36 and 37 are a schematic sectional view and a top perspective view of a semiconductor assembly according to another aspect of the third embodiment of the present invention, respectively. The structure of the semiconductor assembly 320 is similar to that shown in FIGS. 34 and 35. The difference is that (i) this embodiment uses the stacked semiconductor sub-assembly 10 shown in FIG. 20, and (ii) the molding material 71 is in the side direction. The vertical extensions 337 surrounding the metal leads 33, (iii) the thermal pad 35 is a metal pad with a stepped peripheral edge. Therefore, the compound layer 37 can be firmly bonded to the metal lead 33 and the thermally conductive pad 35 to prevent the metal lead 33 and the thermally conductive pad 35 from detaching from the compound layer 37 in a vertical direction, and avoid forming a crack at the interface in a vertical direction.

[Example 4]

38-42 are diagrams of a method for fabricating a semiconductor assembly according to a fourth embodiment of the present invention, wherein the interconnect substrate further includes an external routing circuit.

For the purpose of brief description, any description that can be used for the same application in the above embodiments is incorporated herein, and it is not necessary to repeat the same description.

FIG. 38 is a schematic cross-sectional view of the lead frame 31. The lead frame 31 is similar to the structure shown in FIG. 7 except that the thermally conductive pad 35 is an electrically insulating pad having thermal conductivity, and the lead frame 31 does not include a connecting rod integrally formed with the thermally conductive pad 35.

FIG. 39 is a schematic cross-sectional view of the compound layer 37. FIG. The compound layer 37 fills the space between the metal leads 33 and the gap between the metal leads 33 and the thermal pad 35 to provide a stable bonding force between the metal leads 33 and the thermal pad 35. In addition, through the planarization step, the front surface 371 of the compound layer 37 is substantially coplanar with the front side 311 of the metal lead 33 and the thermal pad 35, and the back surface 373 of the compound layer 37 is back to the back of the metal lead 33 and the thermal pad 35. The sides 313 are substantially coplanar.

FIG. 40 is a schematic cross-sectional view of forming an external routing circuit 38. The external routing circuit 38 is formed on the back surface 373 of the compound layer 37, the thermal pad 35, and the back side 313 of the metal lead 33, and is electrically coupled to the metal lead 33. In this figure, the external routing circuit 38 is a redistribution layer 381, which is formed by a metal pattern deposition process as described below. First, the bottom surface of the structure can be metallized by various techniques (such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof) to form a single-layer or multi-layer conductive layer (usually a copper layer). The conductive layer may be made of Cu, Ni, Ti, Au, Ag, Al, a combination thereof, or other suitable conductive materials. Generally, a seed layer is formed on the bottom of the structure before the electroconductive layer is plated to a desired thickness. The seed layer can be composed of a diffusion resistance layer and a plating bus layer. The diffusion resistance layer is used to offset oxidation or erosion of the conductive layer (such as copper). In most examples, the diffusion barrier layer can be used as an adhesion-reinforcing layer for the underlying material, and can be formed by physical vapor deposition (PVD). For example, sputtering can form Ti or TiW layer. However, the diffusion barrier layer can also be made of other materials, such as TaN or other suitable materials, and its thickness is not limited to the above range. The plating carrier layer is usually made of the same material as the conductive layer and has a thickness ranging from about 0.1 μm to 1 μm. For example, when the conductive layer is copper, the plating carrier layer is preferably a copper thin film made by physical vapor deposition or electroless plating. However, the electroplated support layer can also be made of other suitable materials, such as silver, gold, chromium, nickel, tungsten, or a combination thereof, and its thickness is not limited to the above range.

After the seed layer is deposited, a photoresist layer (not shown) is formed on the seed layer. The photoresist layer can be formed by a wet process (such as a spin coating process) or a dry process (such as a lamination dry film). After the photoresist layer is formed, the photoresist layer is patterned to form openings, and then the openings are filled with a covering metal (such as copper) to form a redistribution having a uniform thickness and a thickness smaller than that of the metal lead 33. Layer 381. The thickness of the cladding metal layer usually ranges from about 10 μm to 100 μm. After the metal is plated, the exposed seed layer is removed through an etching process to form conductive wires that are electrically isolated from each other.

The uncut interconnect substrate 30 has been completed at this stage, which includes a metal frame 32, a metal lead 33, a metal pad 35, a compound layer 37, and an external routing circuit 38.

FIG. 41 is a schematic cross-sectional view of the stacked semiconductor sub-group 10 shown in FIG. 4 electrically connected to the interconnect substrate 30 shown in FIG. 40. The stacked semiconductor sub-group 10 shown in FIG. 4 is connected to the thermal pad 35 of the interconnection substrate 30 through a thermally conductive material 51, wherein the thermally conductive material 51 is in contact with the second device 23 and the thermally conductive pad 35 and stacked The semiconductor sub-group 10 is electrically connected to the metal lead 33 through a bonding wire 61. The bonding wire 61 is connected to the metal lead 33 of the primary routing circuit 11 and the interconnection substrate 30.

FIG. 42 is a schematic cross-sectional view of the semiconductor assembly 400 separated from the metal frame 32, which may be optionally further provided with a molding material 71. The metal frame 32 and the metal lead 33 can be separated by chemical etching, mechanical cutting / cutting or sawing to cut the connection between the metal leads 33. In addition, a molding material 71 may be optionally further formed to cover and surround the primary routing circuit 11, the reinforcing layer 13, the first device 21, and the bonding wire 61 from above.

43 is a schematic cross-sectional view of a semiconductor assembly according to another aspect of the fourth embodiment of the present invention. The semiconductor assembly 410 is similar to the structure shown in FIG. 42 except that (i) the thermal pad 35 is a metal pad, and the external routing circuit 38 is a build-up circuit, and (ii) the interconnect substrate 30 further includes another external routing circuit. 39, which is located on the front side of the compound layer 37 and the front side of the metal leads 33 and the thermal pad 35, and (iii) the bonding wire 61 electrically connects the stacked semiconductor sub-group 10 to the additional external routing circuit 39. In this figure, the external routing circuit 38 at the bottom of the interconnect substrate 30 is a multi-layer build-up circuit, which includes a dielectric layer 382 and a circuit layer 383 alternately formed in turn, and the other outer portion on the top of the interconnect substrate 30 The routing circuit 39 is a redistribution layer 391 having a thickness smaller than that of the metal lead 33. The dielectric layer 382 covers the metal lead 33, the thermal pad 35, and the compound layer 37 from below. The circuit layer 383 extends laterally on the dielectric layer 382, and has a conductive blind hole 387 contacting the metal lead 33 to constitute an electrical route. At the same time, it also has an additional conductive blind hole 388 contacting the thermal pad 35 for thermal conduction and grounding. connection. The redistribution layer 391 extends laterally on the front surface of the compound layer 37 and on the front side of the thermal pad 35 and the metal lead 33, and is electrically coupled to the metal lead 33. Therefore, the redistribution layer 391 can be electrically connected to the circuit layer 383 through the metal lead 33.

[Example 5]

FIG. 44 is a schematic cross-sectional view of a semiconductor assembly according to a fifth embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above embodiments is incorporated herein, and it is not necessary to repeat the same description.

The semiconductor assembly 500 includes the stacked semiconductor sub-assembly 10 shown in FIG. 4, another interconnection substrate 40, a plurality of bonding wires 61, a plurality of terminals 63, and a selective molding material 71. The interconnection substrate 40 includes There is a thermal pad 41 and a surrounding layer 43. The thermal pad 41 is shown as a metal block, and the front side of the thermal pad 41 is attached to the second device 23 of the stacked semiconductor sub-group 10 shown in FIG. Circum thermal pad 41. In this embodiment, the surrounding layer 43 is a multilayer build-up circuit, which includes a dielectric layer 431 and a contact pad 437 on the dielectric layer 431. The dielectric layer 431 is bonded to the sidewall of the thermal pad 41, and the contact pad 437 is deposited on the front surface of the dielectric layer 431. The bonding wire 61 is connected to the terminal pad 117 of the primary routing circuit 11 and the contact pad 437 of the surrounding layer 43 to provide an electrical connection between the primary routing circuit 11 and the surrounding layer 43. The terminal 63 is electrically coupled to the contact pad 437 and is disposed around the peripheral edge of the stacked semiconductor sub-group 10 to provide an electrical contact for the next level of connection. The molding compound 71 covers the stacked semiconductor sub-group 10 and the bonding wire 61, and covers a part of the side wall of the terminal 63. As shown in FIG. 44, the terminal 63 extends upward beyond the outer surface of the molding material 71 to form a pin-type terminal for external connection.

45 is a schematic cross-sectional view of a semiconductor assembly according to another aspect of the fifth embodiment of the present invention. The semiconductor assembly 510 is similar to the structure shown in FIG. 44 except that in this aspect, the stacked semiconductor sub-assembly 10 shown in FIG. 25 is used, and the thermal pad 41 is an electrically insulating block having thermal conductivity. Electrically conductive blocks with thermal conductivity are usually made of materials with high elastic modulus and low thermal expansion coefficient (for example, 2 x 10 ^-6 K ^-1 to 10 x 10 ^-6 K ^-1 ), such as ceramics, silicon, Glass or other materials. In this embodiment, the thermal pad 41 is a ceramic block.

[Example 6]

FIG. 46 is a schematic cross-sectional view of a semiconductor assembly according to a sixth embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above embodiments is incorporated herein, and it is not necessary to repeat the same description.

The semiconductor assembly 600 is similar to the structure shown in FIG. 42 except that the thermal pad 41 includes a pillar portion 411 and a base portion 413. The pillar portion 411 contacts the base portion 413 and protrudes from the base portion 413, wherein the sidewall of the pillar portion 411 is bonded to the dielectric layer 431 surrounding the layer 43, and the pillar portion 411 is attached to the second device 23. The base portion 413 is located below the pillar portion 411 and extends laterally from the pillar portion 411 in a lateral direction, so that the dielectric layer 431 of the surrounding layer 43 covers the base portion 413 from above. In this embodiment, the thickness of the pillar portion 411 ranges from 0.05 to 0.1 mm, and the thickness of the base portion 413 ranges from 0.3 to 3 mm. Preferably, the pillar portion 411 and the base portion 413 are integrally formed. For example, the thermally conductive pad 41 may be a selectively etched single metal piece or a stamped single metal piece. By a wet etching or stamping process, the thermal conductive pad 41 can be made into a form including the pillar portion 411 and the base portion 413. Alternatively, the pillar portion 411 may be deposited on the base portion 413 by various metal deposition technologies, such as electroplating, chemical vapor deposition, physical vapor deposition, or other methods. Thereby, the pillar portion 411 and the base portion 413 have a metallurgical interface, and the pillar portion 411 and the base portion 41 are in contact with each other but are not integrally formed.

47 is a schematic cross-sectional view of a semiconductor assembly according to another aspect of the sixth embodiment of the present invention. The semiconductor assembly 610 is similar to the structure shown in FIG. 46 except that the stacked semiconductor sub-assembly 10 shown in FIG. 20 is used in this state, and the outer surfaces of the terminals 63 and the molding material 71 are aligned with each other in the upward direction. level.

As shown in the above embodiment, the present invention constructs a unique semiconductor assembly including a stacked semiconductor sub-assembly and an interconnection substrate electrically coupled to each other by a bonding wire. To improve heat dissipation, the interconnect substrate preferably includes a thermal pad surrounded by metal leads or a surrounding layer, and the stacked semiconductor sub-group is attached to the thermal pad of the interconnect substrate. In addition, a molding compound can be optionally provided to cover the stacked semiconductor sub-assembly and the bonding wire. For the convenience of description below, the direction facing the first surface of the primary routing circuit is defined as the first direction, and the direction facing the second surface of the primary routing circuit is defined as the second direction.

The stacked semiconductor sub-group includes a first device and a second device electrically connected to each other. More specifically, the stacked semiconductor sub-group may further include a primary routing circuit, which is located between the first device and the second device, and may optionally include a reinforcing layer bonded to the primary routing circuit, and Surround the second device laterally. The primary routing circuit may be a layered circuit without a core layer to provide preliminary fan-out routing / interconnection and the shortest interconnection distance between the first and second devices. Preferably, the primary routing circuit is a multilayer build-up circuit, which may include at least one dielectric layer and at least one circuit layer. The circuit layer extends laterally on the dielectric layer and has a conductive blind layer located on the dielectric layer. hole. The dielectric layer and the circuit layer are continuously formed alternately, and can be formed repeatedly if necessary. Accordingly, the primary routing circuit is formed with a first conductive pad or a selective terminal pad on the first surface, and a second conductive pad is formed on the second surface. Here, the first conductive pad and the terminal pad may be electrically connected to the second conductive pad through a conductive blind hole. In a preferred embodiment, the terminal pad can be used to connect bonding wires, and the pad size and pad pitch of the terminal pad are larger than the pad size and pad pitch of the first conductive pad, the pad size and pad pitch of the second conductive pad, and the The pad size and pad spacing of the I / O pads of one device and the second device. The selective reinforcement layer extends laterally to the peripheral edge of the primary routing circuit to provide mechanical support for the primary routing circuit from the second direction. The reinforcing layer may cover and cover the second device in the same shape, or the reinforcing layer may have an opening aligned with the second conductive pad to expose the second conductive pad of the primary routing circuit from the second direction. According to this, the second surface of the primary routing circuit and the inner wall of the reinforcement layer opening will form a cavity in the opening of the reinforcement layer, and the second device may be disposed in the cavity and from the second surface of the primary routing circuit. Electrically coupled to the second conductive pad. In a preferred embodiment, the thickness of the reinforcing layer is substantially equal to the thickness of the second device and the conductive bump.

The first device and the second device may be packaged wafers, unpackaged wafers, or passive components. Here, the first device can use the conventional flip-chip bonding process to electrically connect the primary routing circuit to the primary routing circuit with the active surface facing the primary routing circuit, and no metalized blind hole contacts the first device. . Alternatively, the first device may use a wire-bonding process to electrically couple the primary routing circuit to the primary routing circuit with the active side facing away from the primary routing circuit. Similarly, the second device with the active surface facing the primary routing circuit may also The conventional flip-chip bonding process is electrically coupled to the primary routing circuit through conductive bumps, and no metallized blind hole contacts the second device. In a preferred embodiment, the second device is disposed in the opening of the reinforcing layer, and the peripheral edge of the second device is kept away from the inner sidewall of the opening of the reinforcing layer.

The interconnect substrate may include a lead frame and a selective compound layer, wherein the compound layer is bonded to the lead frame. The lead frame mainly includes a thermal pad and a plurality of metal leads, wherein the thermal pad is attached to the second device, and the metal leads are electrically connected from the first surface of the primary routing circuit to the stacked semiconductor sub-group through a bonding wire. . These metal leads surround the side walls of the thermal pad and can be used as horizontal and vertical signal transmission paths, or provide ground / power planes for energy transfer and return. Preferably, the metal leads have a flat front side and a flat back side, and the front side of the metal lead is substantially coplanar with the flat front side of the thermal pad in the first direction, and the back side of the metal lead is in the second direction. The upper side is substantially coplanar with the flat back side of the thermal pad. The selective compound layer fills the space between the metal leads and the gap between the thermal conductive pad and the metal lead, and the thermal conductive pad and the metal lead are not covered by the compound layer in the first direction and the second direction. More specifically, the front surface of the compound layer is substantially coplanar with the front side of the thermal pad and the metal lead in the first direction, and the back of the compound layer is substantially coplanar with the back side of the thermal pad and the metal lead in the second direction. Co-planar. Alternatively, the space between the metal leads and the gap between the thermally conductive pad and the metal leads can be filled with a selective molding material used to cover the stacked semiconductor sub-assembly and the bonding wires.

The metal leads extend laterally outside the peripheral edge of the primary routing circuit, and the inner end of each metal lead is oriented toward the side wall of the thermal pad, while the outer end is farther away from the thermal pad than the inner end. The thickness range between the front side and the back side of the metal lead is usually about 0.15 mm to 1.0 mm, and the thickness is larger than the thickness of the wiring layer of the primary routing circuit. In addition, the metal lead may extend laterally to the peripheral edge of the molding material and / or the compound layer, or the metal lead may have a horizontal extension portion that extends laterally beyond the peripheral edge of the molding material and / or the compound layer. Alternatively, the metal lead may be bent and has a horizontal flat portion and a vertical extending portion. In a preferred embodiment, the front and back sides of the horizontal flat portion may be substantially coplanar with the front and back sides of the thermal pad, and the vertical extension portion protrudes from the front side of the horizontal flat portion and faces the first The direction extends beyond the outer surface of the molding compound. Therefore, the vertical extensions surrounding the peripheral edges of the stacked semiconductor sub-group can provide external electrical contacts for electrical connection with the following level. Before cutting the metal frame, the metal leads are integrally connected to the metal frame. Preferably, after the compound layer or the molding compound is provided, the metal lead is separated from the metal frame. In order to firmly bond the metal lead to the compound layer or the metal lead to the molding compound, the metal lead may have a stepped peripheral edge bonded to the compound layer or the molding compound. Therefore, the compound layer or the molding compound also has a stepped cross-sectional profile at the point where it contacts the metal lead to prevent the metal lead from leaving the compound layer or the molding compound in the vertical direction, and it can avoid forming at the interface in the first and second directions. crack.

The thermal pad can be a metal pad or an electrically insulating pad with thermal conductivity as a main thermal conduction platform for the second device to be attached to, so that the heat generated by the second device can be dissipated. Before cutting, the metal pad can be connected to the metal frame by a connecting rod. In addition, thermally conductive electrical insulation pads can be made of ceramic, silicon, glass, or other materials and usually have a high modulus of elasticity and a low coefficient of thermal expansion (for example, 2 x 10 ^-6 K ^-1 to 10 x 10 ^-6 K ^-1 ). According to this, the thermal expansion coefficient of the electrically insulating pad with thermal conductivity can be matched with the second device placed on it to provide a CTE compensation platform for the second device, and it can greatly compensate or reduce the internal stress caused by the CTE mismatch. . Similarly, the peripheral edge of the thermal pad can be stepped, and the compound layer or molding compound has a stepped cross-sectional profile at the point where it contacts the thermal pad to prevent the thermal pad from detaching from the compound layer or molding compound in the vertical direction. Avoid forming cracks at the interface in the first and second directions.

The interconnection substrate may further include an external routing circuit, which is disposed on the back surface of the compound layer and is electrically coupled to the metal lead. Therefore, the electrical signal can be rerouted from the lead at the edge to a predetermined position. The external routing circuit can be a redistribution layer deposited by a lithographic process metal, which has a uniform thickness smaller than the thickness of the metal lead. In a preferred embodiment, the redistribution layer contacts and extends laterally on the back surface of the compound layer, and further extends laterally to the back side of the metal lead, and optionally further laterally extends to the back side of the thermal pad. . Alternatively, the external routing circuit may be a multilayer build-up circuit, which covers the back surface of the compound layer and the back side of the metal leads and the thermal pad. The build-up circuit may include at least one dielectric layer and at least one circuit layer. The circuit layer extends through the dielectric layer to form a conductive blind hole, and extends laterally on the dielectric layer. According to this, the circuit layer can be electrically coupled to the metal lead through the conductive blind hole in contact with the metal lead, and can be thermally conducted to the thermal pad and / or connected to the ground through the conductive blind hole in contact with the thermal pad. pad. The dielectric layer and the line system are continuously formed alternately, and can be formed repeatedly if necessary.

The interconnect substrate may further include an additional external routing circuit, which is disposed on the front surface of the compound layer and is electrically coupled to the metal lead. With the dual external routing circuits on both sides of the compound layer, the wiring flexibility of the interconnect substrate can be improved. The additional external routing circuit may be a redistribution layer deposited by a lithographic process metal, which has a uniform thickness that is less than the thickness of the metal leads. In a preferred embodiment, the additional redistribution layer contacts and extends laterally on the front surface of the compound layer, and further extends laterally to the front side of the metal lead, and optionally further laterally to the front side of the thermal pad. on. Therefore, the dual external routing circuits can be electrically connected to each other through metal leads.

The thermal pad can be combined with the surrounding layer as an interconnection substrate to provide a main thermal conduction platform for the second device and provide electrical contacts for connection to the preliminary routing circuit. The thermally conductive pad may be a metal block or an electrically insulating block having thermal conductivity, and the surrounding layer laterally surrounds the side wall of the thermally conductive pad. In a preferred embodiment, the thermal pad includes a pillar portion and a base portion, and the second device is attached to the pillar portion of the thermal pad. The pillar portion and the base portion can be integrally formed into a single member and made of the same material. The pillar portion contacts and protrudes from the base portion, and the sidewall of the pillar portion is joined to the surrounding layer, and the base portion extends laterally from the pillar portion to the peripheral edge of the surrounding layer, and is covered by the surrounding layer in the first direction. According to this, the pillar portion can provide a platform for the device to attach, and the base portion provides a heat dissipation surface with an area larger than that of the pillar portion, and provides mechanical support for the assembly to avoid warping.

The surrounding layer of the interconnect substrate can be a build-up circuit without a core layer to provide electrical contacts that can be connected to the primary routing circuit through bonding wires. Preferably, the surrounding layer may be a multi-layer build-up circuit and includes at least one dielectric layer and at least one circuit layer, and the circuit layer extends laterally on the dielectric layer. The dielectric layer and the circuit layer are continuously formed alternately, and can be formed repeatedly if necessary. According to this, the surrounding layer can be formed with electrical contacts, which can be electrically connected to the primary routing circuit through bonding wires. For the next level of connection, a plurality of terminals can be provided to electrically connect with the contact pads of the surrounding layer. In a preferred embodiment, the thickness of the terminal is greater than the thickness of the primary routing circuit plus the thickness of the first and second devices, and extends in a first direction beyond the outer surface of the molding material. Alternatively, the outer surface of the terminal may be flush with the outer surface of the molding compound. According to this, the terminal can provide electrical contacts, and can be externally connected in the first direction.

The bonding wire can provide electrical connection between the primary routing circuit and the interconnection substrate. More specifically, the bonding wire can electrically connect the primary routing circuit to the metal lead or the contact pad of the surrounding layer from the first surface of the primary routing circuit and the front side of the metal lead / surrounding layer. For example, when the stacked semiconductor sub-assembly is assembled on an interconnect substrate having metal leads, the bonding wires may be connected to the first surface of the primary routing circuit and the front side of the metal leads. Alternatively, the bonding wires can be connected to the first surface of the primary routing circuit and additional external routing circuits on the front side of the metal leads. Similarly, when the stacked semiconductor sub-assembly is assembled on an interconnect substrate having a surrounding layer bonded to the thermal pad, the bonding wire can be connected to the first surface of the primary routing circuit and the contact pad at the front side of the surrounding layer. Accordingly, the first device and the second device can be electrically connected to the metal lead or the surrounding layer of the interconnection substrate through the bonding wires, and connected with the following stage.

The term "coverage" means incomplete and complete coverage in vertical and / or lateral directions. For example, in a preferred embodiment, the base of the thermal pad covers the surrounding layer in the second direction, regardless of whether another component is located between the base and the surrounding layer.

The terms "attached to" and "connected to" include contact and non-contact with one or more components. For example, in a preferred embodiment, the second device may be attached to the thermal pad, regardless of whether the second device is separated from the thermal pad by a thermally conductive material.

The terms "electrically connected" and "electrically coupled" mean directly or indirectly electrically connected. For example, in a preferred embodiment, the first device and the second device may be electrically connected to the terminal through a primary routing circuit, a surrounding layer, and a bonding wire, but the first device and the second device are not in contact with the terminal.

The "first direction" and "second direction" do not depend on the orientation of the semiconductor assembly, and anyone who is familiar with this technique can easily understand the actual direction it refers to. For example, the first surface of the primary routing circuit faces the first direction, and the second surface of the primary routing circuit faces the second direction, which has nothing to do with whether the semiconductor group is inverted. Therefore, the first and second directions are opposite to each other and perpendicular to the side direction.

The semiconductor assembly of the present invention has many advantages. The primary routing circuit can provide primary fan-out routing / interconnection for the first device and the second device, and provide the shortest interconnection distance between the first device and the second device. The reinforcement layer provides mechanical support for the primary routing circuit. The thermal pad can provide a heat dissipation path to dissipate the heat generated by the second device. The combination of metal leads or surrounding layers and terminals can provide further routing to improve the routing flexibility of the assembly. Since the primary routing circuit is connected to the metal lead or the surrounding layer by a bonding wire, rather than directly connected by a build-up process, the simplified process steps can reduce the manufacturing cost. The semiconductor group system prepared by this method has high reliability, low price, and is very suitable for mass production.

The manufacturing method of the present invention has high applicability, and uses various mature electrical and mechanical connection technologies in a unique and progressive way. In addition, the manufacturing method of the present invention can be implemented without expensive tools. Therefore, compared with the traditional technology, this production method can greatly improve the yield, yield, efficiency and cost effectiveness.

The embodiments described herein are for illustrative purposes, and the embodiments may simplify or omit elements or steps that are well known in the technical field, so as not to obscure the features of the present invention. Similarly, to make the drawings clear, the drawings may omit repeated or unnecessary components and component symbols.

100, 110, 120, 200, 210, 300, 310, 320, 400, 410, 500, 510, 600, 610‧‧‧

10‧‧‧Stacked Semiconductor Subgroup

101‧‧‧first surface

103‧‧‧ second surface

105‧‧‧ inside wall

107‧‧‧Dent

11‧‧‧level routing circuit

111, 382, 431‧‧‧ dielectric layers

112‧‧‧The first conductive pad

113, 383‧‧‧ Line layer

114, 387, 388‧‧‧ conductive blind hole

115‧‧‧The first conductive pad

116‧‧‧metal pad

117‧‧‧Terminal Pad

119‧‧‧Second conductive pad

13‧‧‧ Enhancement

135‧‧‧ opening

21‧‧‧ the first device

213‧‧‧The first conductive bump

215, 61‧‧‧bonding line

23‧‧‧Second Device

233‧‧‧Second conductive bump

24‧‧‧ Passive components

25‧‧‧metal pillar

27‧‧‧ third device

273‧‧‧The third conductive bump

30, 40‧‧‧ interconnect substrate

31‧‧‧ lead frame

311‧‧‧front

313‧‧‧ dorsal side

32‧‧‧ metal frame

33‧‧‧metal lead

331‧‧‧outer end

333‧‧‧Inner end

335‧‧‧Horizontal extension

336‧‧‧Horizontal Flat

337‧‧‧Vertical Extension

35, 41‧‧‧ Thermal pad

36‧‧‧Connecting rod

37‧‧‧ Compound layer

371‧‧‧front

373‧‧‧Back

38, 39‧‧‧ external routing circuit

381, 391‧‧‧ heavy layer

411‧‧‧Column

413‧‧‧Base

43‧‧‧Surrounding layer

437‧‧‧Contact pad

51‧‧‧Conductive material

63‧‧‧terminal

71‧‧‧Moulding material

With reference to the accompanying drawings, the present invention can be more clearly understood through the detailed description of the following preferred embodiments, wherein: Figures 1, 2 and 3 are the first embodiment of the present invention, the bonding of the primary routing circuit and the reinforcement layer A schematic cross-sectional view, a top perspective view, and a bottom perspective view; Figures 4, 5 and 6 are the first embodiment and the second device of the first embodiment and the second device, respectively. Top perspective view and bottom perspective view; Figures 7 and 8 are cross-sectional views and top perspective views of the interconnect substrate in the first embodiment of the present invention; The 7 and 8 structures are further provided with cross-sectional schematic diagrams and top perspective schematic diagrams of the sub-assembly shown in Figs. 4, 5 and 6; Figs. 11 and 12 are the first embodiment of the present invention, and the structures of Figs. A schematic cross-sectional view and a top perspective view of the line; FIG. 13 is a schematic cross-sectional view of the first embodiment of the present invention, and the structure of FIGS. 11 and 12 further forms a molding material; FIGS. 14, 15 and 16 are the first embodiment of the present invention, respectively. From Figure 13 A cross-sectional view, a top perspective view, and a bottom perspective view of the semiconductor assembly are cut out; FIG. 17 is a schematic cross-sectional view of the semiconductor assembly in another aspect of the first embodiment of the present invention; FIGS. 18 and 19 are the present invention, respectively. In the first embodiment, a cross-sectional schematic diagram and a bottom perspective view of a semiconductor assembly in another aspect; FIG. 20 is a schematic cross-sectional diagram of a stacked semiconductor sub-assembly in a second embodiment of the present invention; In the embodiment, FIG. 20 is a schematic cross-sectional view of an interconnect substrate connected to the structure; FIG. 22 is a second embodiment of the present invention, FIG. 21 is a cross-sectional diagram of a connected connection line; FIG. 23 is a second embodiment of the present invention. In the aspect, the structure of FIG. 22 is further formed into a cross-sectional view of a molding compound; FIG. 24 is a schematic view of the cross-section of the semiconductor assembly cut from the structure of FIG. 23 in the second embodiment of the present invention; In one aspect, a schematic cross-sectional view of a semiconductor assembly in another aspect; FIGS. 26 and 27 are a schematic cross-sectional view and a top perspective view of a lead frame in a third embodiment of the present invention, respectively; FIGS. 28 and 29 are respectively In the third embodiment, the structure of FIGS. 26 and 27 further formed a compound layer to complete the cross-sectional schematic diagram and the top three-dimensional schematic diagram of the interconnection substrate. FIGS. 30 and 31 are the third embodiment of the invention, FIGS. 28 and 29. In the structure, the cross-sectional schematic diagram and the top three-dimensional schematic diagram of the secondary assembly and the bonding wire shown in Figs. 4, 5, and 6 are further connected; Figs. 32 and 33 are the third embodiment of the present invention. A cross-sectional schematic diagram and a top perspective diagram of a semiconductor assembly are cut out; FIGS. 34 and 35 are a schematic cross-sectional diagram and a top perspective diagram of a semiconductor assembly in another aspect of the third embodiment of the present invention; FIGS. 36 and 37 are respectively In the third embodiment of the present invention, another aspect of the semiconductor assembly is a schematic cross-sectional view and a top perspective view; FIG. 38 is a schematic cross-sectional view of a lead frame in the fourth embodiment of the present invention; FIG. 39 is a fourth embodiment of the present invention. In the example, the structure of FIG. 38 further forms a cross-sectional view of a compound layer; FIG. 40 is a schematic view of the fourth embodiment of the present invention, the structure of FIG. 39 further forms an external routing circuit to complete the production of an interconnect substrate; FIG. 41 In the fourth embodiment of the present invention, the cross-sectional view of the sub-assembly and the bonding wire shown in FIG. 4 are further connected in the structure of FIG. 40; FIG. 42 is a cut from the structure of FIG. 41 in the fourth embodiment of the present invention. A schematic cross-sectional view of a semiconductor assembly cut out to form a molding compound; FIG. 43 is a schematic cross-sectional view of a semiconductor assembly in another aspect of the fourth embodiment of the present invention; FIG. 44 is a cross-sectional view of semiconductors in a fifth embodiment of the present invention; 45 is a schematic cross-sectional view of a semiconductor assembly in another aspect of the fifth embodiment of the present invention; FIG. 46 is a schematic cross-sectional view of a semiconductor assembly in the sixth embodiment of the present invention; FIG. 47 It is a schematic cross-sectional view of a semiconductor assembly in another aspect of the sixth embodiment of the present invention.

Claims (22)

A three-dimensional semiconductor assembly includes: a stacked semiconductor sub-assembly including a primary routing circuit, a first device, and a second device, wherein (i) the primary routing circuit has one facing a first direction; A first surface, a second surface facing an opposite second direction, a first conductive pad located on the first surface, and a second conductive pad located on the second surface and electrically connected to the first conductive pads, (ii) the first device is disposed on the first surface of the primary routing circuit, and is electrically coupled to the primary routing circuit through the first conductive pads, and (iii) the second device is disposed on The second routing surface of the primary routing circuit is electrically coupled to the primary routing circuit through the second conductive pads; an interconnect substrate having a heat conducting pad and a plurality of metal leads, and the metals Leads are disposed around the thermal pad, wherein the thermal pad and the metal leads each have a front side facing the first direction, and the front side of the thermal pad is attached to the second side by a thermally conductive material. Set; and a plurality of bonding wires that connect the first surface of the primary electrical circuit is routed to the front side of the plurality of the plurality of metal lead. The semiconductor assembly according to item 1 of the patent application scope, wherein the stacked semiconductor sub-assembly further comprises a reinforcing layer, which is bonded to the primary routing circuit and surrounds the second device laterally. The semiconductor assembly according to item 2 of the scope of patent application, wherein (i) the reinforcing layer has an opening, (ii) a portion of the second surface of the primary routing circuit and the opening of the reinforcing layer The inner wall forms a cavity in the opening of the reinforcing layer, and (iii) the second device is disposed in the cavity. The semiconductor assembly according to item 1 of the scope of patent application, further includes a molding compound that covers the first device, the bonding wires, and the primary routing circuit. The semiconductor assembly according to item 4 of the scope of the patent application, wherein the molding compound further extends into the space between the metal leads and the gap between the thermal pad and the metal leads. The semiconductor assembly according to item 4 of the scope of the patent application, wherein each of the metal leads has a horizontal extension portion that extends beyond a peripheral edge of the molding material. The semiconductor assembly according to item 1 of the scope of patent application, wherein the interconnect substrate further has a compound layer that fills the space between the metal leads and the gap between the thermal pad and the metal leads, and The front surface of the compound layer is substantially coplanar with the front side of the thermal pad and the front sides of the metal leads. The semiconductor assembly according to item 1 of the scope of patent application, wherein each of the metal leads has a vertical extension portion that extends from the front side of the metal leads toward the first direction. The semiconductor assembly according to item 8 of the scope of patent application, further comprising a molding compound that covers the first device, the bonding wires, and the primary routing circuit, and the molding compound has a direction facing the first direction. An external surface, wherein the vertical extensions of the metal leads extend toward the first direction beyond the external surface of the molding material. The semiconductor assembly according to item 1 of the patent application scope, wherein the thermally conductive pad is an electrically insulating pad or a metal pad having thermal conductivity. The semiconductor assembly according to item 5 of the scope of patent application, wherein at least one of the thermal pad and the metal leads has a stepped peripheral edge that is bonded to the molding material. The semiconductor assembly according to item 7 of the scope of patent application, wherein at least one of the thermal pad and the metal leads has a stepped peripheral edge bonded to the compound layer. The semiconductor assembly according to item 1 of the patent application scope, wherein the first device is electrically connected to the first conductive pads through a first conductive bump or an additional bonding wire, and the second device is connected through The second conductive bumps are electrically connected to the second conductive pads. The semiconductor assembly according to item 7 of the scope of the patent application, wherein the interconnect substrate further has an external routing circuit, which is disposed on the back of the compound layer and is electrically coupled to the metal leads. The semiconductor assembly according to item 14 of the scope of patent application, wherein the interconnect substrate further has an additional external routing circuit disposed on the front surface of the compound layer and electrically coupled to the metal leads, And the bonding wires are electrically connected to the metal leads through the additional external routing circuit. A three-dimensional semiconductor assembly includes: a stacked semiconductor sub-assembly including a primary routing circuit, a first device, and a second device, wherein (i) the primary routing circuit has one facing a first direction; A first surface, a second surface facing an opposite second direction, a first conductive pad located on the first surface, and a second conductive pad located on the second surface and electrically connected to the first conductive pads, (ii) the first device is disposed on the first surface of the primary routing circuit, and is electrically coupled to the primary routing circuit through the first conductive pads, and (iii) the second device is disposed on The second routing surface of the primary routing circuit is electrically coupled to the primary routing circuit through the second conductive pads; an interconnect substrate having a thermally conductive pad and a surrounding layer, wherein (i) The thermal pad has a front side facing the first direction, and the front side of the thermal pad is attached to the second device through a thermally conductive material, (ii) the surrounding layer has a dielectric layer and a contact pad, ( iii) the dielectric layer is bonded to the A sidewall of the thermal pad, and the dielectric layer has a front surface facing the first direction, and (iv) the contact pads are disposed on the front surface of the dielectric layer; a plurality of terminals are electrically coupled to the contacts And a plurality of bonding wires connected to the primary routing circuit and the contact pads of the surrounding layer to electrically connect the stacked semiconductor sub-group To these terminals. The semiconductor assembly according to item 16 of the application, wherein the stacked semiconductor subassembly further includes a reinforcing layer bonded to the primary routing circuit and laterally surrounding the second device. The semiconductor assembly according to item 16 of the scope of patent application, further includes a molding compound that covers the first device, the bonding wires, and the primary routing circuit, and at least partially covers the sidewalls of the terminals. The semiconductor assembly according to item 18 of the scope of patent application, wherein the terminals extend toward the first direction beyond the outer surface of the molding material. The semiconductor assembly according to item 16 of the scope of application for a patent, wherein the thermal pad is a metal block or an electrically insulating block having thermal conductivity. The semiconductor assembly according to item 16 of the patent application scope, wherein the thermal pad has a pillar portion and a base portion, the pillar portion contacts the base portion and protrudes from the base portion, and a sidewall of the pillar portion is bonded to the The dielectric layer of the surrounding layer, and the base portion extends laterally from the pillar portion toward the side direction, and is covered by the dielectric layer of the surrounding layer in the first direction. The semiconductor assembly according to item 16 of the scope of patent application, wherein the first device is electrically connected to the first conductive pads through a first conductive bump or an additional bonding wire, and the second device is connected through The second conductive bumps are electrically connected to the second conductive pads.