TWI614855B - Semiconductor assembly with electromagnetic shielding and thermally enhanced characteristics and method of making the same - Google Patents

Abstract

The semiconductor package of the present invention comprises a buried device and a heat dissipation gain type device which are connected to each other through the first and second routing circuits, and is provided with a heat sink which can provide heat dissipation and electromagnetic shielding. The embedding device has a first semiconductor wafer embedded in the sealing material, and the heat dissipation gain type device has a second semiconductor wafer thermally coupled to the shielding cover of the heat sink, and the second semiconductor wafer is laterally protruded by the heat sink surround. The first and second semiconductor chip are connected to opposite sides of the first routing circuit, and the second routing circuit is disposed on the shielding cover and electrically coupled to the first routing circuit by the bump. The first routing circuit and the second routing circuit provide first and second semiconductor wafer stage fanout routes.

Description

Semiconductor assembly body with electromagnetic shielding and heat dissipation characteristics and manufacturing method thereof

The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package in which two semiconductor devices are surface-contacted by a dual routing circuit, and a heat sink is provided to provide heat dissipation and electromagnetic shielding.

The market trend for multimedia devices is tended to be more rapid and thinner design requirements. One such method is to face-to-face the two semiconductor devices to provide the shortest routing distance between the two semiconductor devices. Since the stacked devices can be directly transferred to each other to reduce the delay, the signal integrity of the group can be greatly improved, and additional energy consumption can be saved. Therefore, the face-to-face semiconductor package can exhibit almost all of the advantages of 3D IC stacking, and it is not necessary to form a cost-perfect via in the stacked wafer. However, since the semiconductor device is prone to performance degradation at high operating temperatures, if the face-to-face stacked wafer is not properly dissipated, the thermal environment of the device may be deteriorated, resulting in the problem of immediate failure during operation.

In addition, U.S. Patent Application No. 2014/0210107 discloses a stacked wafer assembly having a face-to-face arrangement. However, since the bottom wafer is unprotected and the thickness of the bottom wafer must be thinner than the solder balls for external connection, the assembly is not reliable and cannot be practically applied. U.S. Patent Nos. 8,008,121, 8,519,537 and 8,558,395 disclose various types of interposer assembly structures having interposers disposed between wafers disposed face to face. Although it is not necessary to form tantalum vias (TSVs) in stacked wafers, the vias used in the interposer to provide electrical routing between the wafers can result in complex processes, low production yields, and high costs.

For the above reasons and other reasons described below, there is an urgent need to develop a new type of semiconductor package to achieve high package density, better signal integrity and high heat dissipation.

It is an object of the present invention to provide a semiconductor package in which semiconductor devices are assembled face to face by a routing circuit and have a heat sink including a shield cover, a stud and another routing circuit The shielding cover can provide electromagnetic shielding and heat dissipation to the wafer directly attached to the shielding cover, and the protruding pillars can provide a heat dissipation path for the wafer not directly attached to the shielding cover, and the double routing circuit can provide the group The body stage fanout route, so the integrated characteristics of the heat sink can effectively improve the thermal and electrical performance of the group.

According to the above and other objects, the present invention provides a semiconductor package that electrically couples an embedding device to a heat dissipation gain type device, wherein the embedding device includes a first semiconductor wafer, a first routing circuit, and a sealing material. The heat dissipation type device includes a second semiconductor wafer and a heat sink. The heat sink has a shield cover, a stud and a second routing circuit. In a preferred embodiment, the first semiconductor wafer is electrically coupled to one side of the first routing circuit and buried in the sealing material; the second semiconductor wafer is electrically coupled to the first bump The other side of the routing circuit is disposed in one of the second routing circuits and is electrically connected to the shielding cover. The shielding cover is protruded from the surface of the shielding cover and electrically coupled to the first routing circuit. The pillars are grounded; the first routing circuit provides a primary fan-out route and a shortest interconnect distance for the first semiconductor wafer and the second semiconductor wafer; the second routing circuit is disposed on the surface of the shield cover and laterally surrounds the second semiconductor The chip and the bumps are electrically coupled to the first routing circuit to provide further fanout routing.

In another aspect, the present invention provides a semiconductor package having electromagnetic shielding and heat dissipation characteristics, including: a buried device including a first semiconductor wafer, a sealing material, and a first routing circuit, the first a routing circuit is disposed on a first surface of the sealing material, wherein the first semiconductor wafer is embedded in the sealing material and electrically coupled to the first routing circuit; and a heat dissipation gain type device includes a heat sink and a heat sink a second semiconductor wafer, the heat sink has a shielding cover, a stud, and a second routing circuit disposed on a surface of the shielding cover, wherein (i) the second routing circuit has a through opening, and the second semiconductor chip Provided in the through opening and attached to the shielding cover, and (ii) the protrusions protrude from the surface of the shielding cover and are laterally surrounded by the second routing circuit; wherein the heat dissipation type device Stacked on the embedding device, and the second semiconductor chip is electrically coupled to the first routing circuit by a series of first bumps, and the second routing circuit is electrically connected by a series of second bumps. Coupling to the first route Circuit.

In still another aspect, the present invention provides a semiconductor package manufacturing method having electromagnetic shielding and heat dissipation characteristics, comprising the steps of: providing a buried device including a first semiconductor wafer, a sealing material, and a first a routing circuit, the first routing circuit is disposed on a first surface of the sealing material, wherein the first semiconductor wafer is embedded in the sealing material and electrically coupled to the first routing circuit; by a series of first bumps a second semiconductor wafer is electrically coupled to the first routing circuit of the embedding device; a heat sink is provided, comprising a shielding cover, a protruding post and a second routing circuit, wherein the second routing circuit has a through opening And disposed on a surface of the shielding cover, the protrusions protrude from the surface of the shielding cover and are laterally surrounded by the second routing circuit; and the heat sink is stacked on the embedding device, and Electrically coupling the second routing circuit of the heat sink to the first routing circuit of the embedding device by a series of second bumps, and simultaneously disposing the second semiconductor wafer in the through opening of the second routing circuit, and second Semiconductor wafer is attached to the shield cover.

Unless specifically described or the words "subsequent" are used between steps, or steps that must occur sequentially, the order of the above steps is not limited to the above, and may be varied or rearranged depending on the desired design.

The semiconductor package of the present invention and its method of fabrication have many advantages. For example, electrically connecting the embedding device and the heat dissipation gain device to each other face to face can provide the shortest interconnection distance between the embedding device and the heat dissipation gain device. In addition, it is advantageous to insert the second semiconductor wafer into the through opening of the second routing circuit on the shielding cover, because the shielding cover of the heat sink can dissipate heat from the second semiconductor wafer and serve as a supporting platform for the assembly body, and the heat sink The studs provide electrical connection between the shield cover and the first routing circuit for grounding, thereby providing effective electromagnetic shielding of the second semiconductor wafer.

The above and other features and advantages of the present invention will become more apparent from the detailed description of the preferred embodiments.

In the following, an embodiment will be provided to explain in detail embodiments of the invention. The advantages and effects of the present invention will be more apparent by the disclosure of the present invention. The drawings attached hereto are simplified and are used for illustration. The number, shape and size of the components shown in the drawings can be modified as the case may be, and the configuration of the components may be more complicated. Other variations and modifications can be made without departing from the spirit and scope of the invention as defined in the invention.

[Example 1]

1-20 are diagrams showing a method of fabricating a semiconductor package according to a first embodiment of the present invention, including a first routing circuit 21, a first semiconductor wafer 22, a series of terminals 24, and a sealing material. 25 and a heat sink 31 and a second semiconductor wafer 36.

1 is a cross-sectional view of the routing line 212 formed on the sacrificial carrier 10, wherein the routing lines 212 are formed by metal deposition and metal patterning processes. In this figure, the sacrificial carrier 10 has a single layer structure. The sacrificial carrier 10 is typically made of copper, aluminum, iron, nickel, tin, stainless steel, tantalum or other metal or alloy, but may be made of any other electrically conductive or non-conductive material. In this embodiment, the sacrificial carrier 10 is made of a ferrous material. The routing lines 212 are typically made of copper and may be patterned by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or combinations thereof, or formed by thin film deposition followed by a metal patterning step. In the case of a sacrificial carrier 10 having electrical conductivity, it is typically deposited by metal plating to form routing lines 212. Metal patterning techniques include wet etching, electrochemical etching, laser assisted etching, and combinations thereof, and an etch mask (not shown) is used to define routing lines 212.

2 is a cross-sectional view of dielectric layer 215 and blind vias 216 with dielectric layer 215 on sacrificial carrier 10 and routing line 212 and blind vias 216 in dielectric layer 215. The dielectric layer 215 can be deposited by lamination or coating, and contacts the sacrificial carrier 10 and the routing line 212, and the dielectric layer 215 is covered by the underside and laterally extends to the sacrificial carrier 10 and the routing line. 212 on. Dielectric layer 215 typically has a thickness of 50 microns and can be made of epoxy, glass epoxy, polyimine, or the like. After deposition of dielectric layer 215, blind vias 216 can be formed by various techniques, such as laser drilling, plasma etching, and lithography, and typically have a diameter of 50 microns. Pulsed lasers can be used to improve laser drilling performance. Alternatively, a scanning laser beam can be used with a metal reticle. The blind vias 216 extend through the dielectric layer 215 and are aligned with selected portions of the routing line 212.

Referring to FIG. 3, a first conductive line 217 is formed on the dielectric layer 215 by a metal deposition and metal patterning process. The first wire 217 extends downwardly from the routing line 212 and fills the blind hole 216 to form a metallized blind hole 218 that directly contacts the routing line 212 while extending laterally over the dielectric layer 215. Thus, the first wire 217 can provide horizontal signal routing in the X and Y directions as well as vertical routing through the blind hole 216 to serve as an electrical connection for the routing line 212.

The first wire 217 can be deposited as a single layer or multiple layers by various techniques such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof. For example, first, by immersing the structure in an activator solution, the dielectric layer 215 is reacted with electroless copper to generate a catalyst, and then a thin copper layer is coated as a seed layer by electroless plating, and then electroplated. A second copper layer of the desired thickness is formed on the seed layer. Alternatively, the seed layer may be formed by a sputtering method such as a titanium/copper seed layer film before the electroplated copper layer is deposited on the seed layer. Once the desired thickness is achieved, the coating can be patterned using various techniques to form a first wire 217, such as wet etching, electrochemical etching, laser assisted etching, and combinations thereof, and using an etch mask (not shown). To define the first wire 217.

This stage has been completed by the process of forming the first routing circuit 21 on the sacrificial carrier 10. In the figure, the first routing circuit 21 is a multi-layer build-up circuit comprising a routing line 212, a dielectric layer 215 and a first conductor 217.

4 is a cross-sectional view of the first semiconductor wafer 22 electrically coupled to the first routing circuit 21. The first semiconductor wafer 22 (shown as a bare wafer) can be electrically coupled to the first lead 217 of the first routing circuit 21 via the conductive bumps 223 by hot pressing, reflow soldering, or thermal ultrasonic bonding techniques, wherein The conductive bumps 223 contact the first semiconductor wafer 22 and the first routing circuit 21.

FIG. 5 is a cross-sectional view showing the solder ball 241 being placed on the first routing circuit 21. The solder ball 241 is electrically connected to the first wire 217 of the first routing circuit 21 and is in contact with the first wire 217 as a terminal 24 surrounding the first semiconductor wafer 22.

6 is a cross-sectional view showing the formation of the sealing material 25 on the first routing circuit 21, the first semiconductor wafer 22, and the solder balls 241, wherein the sealing material 25 can be coated, for example, by resin-glass lamination, resin-glass coating, or molding. (molding) formation. The sealing material 25 covers the first routing circuit 21, the first semiconductor wafer 22 and the solder balls 241 from below, and surrounds and covers the sidewalls of the first semiconductor wafer 22 and the solder balls 241.

FIG. 7 is a cross-sectional view showing the opening 254 in the sealing member 25. The openings 254 are aligned with the solder balls 241 to reveal selected portions of the solder balls 241 from below.

8 and 9 are a cross-sectional view and a top perspective view, respectively, of the removal of the sacrificial carrier 10. The sacrificial carrier 10 can be removed by various means to expose the first routing circuit 21 from above, including wet chemical etching using an acidic solution (such as ferric chloride, copper sulfate solution) or an alkaline solution (such as ammonia solution). Chemical etching, or electrochemical etching after mechanical etching (such as drilling or end milling). In this embodiment, the sacrificial carrier 10 made of a ferrous material can be removed by a chemical etching solution, wherein the chemical etching solution is selective between copper and iron to avoid removal of the sacrificial carrier 10. The copper routing line 212 is etched. Accordingly, the first routing circuit 21 adjacent to the first surface 251 of the sealing material 25 can provide an electrical contact from above, and the solder ball 241 exposed from the second surface 253 of the self-sealing material 25 can be electrically connected to the next level by the bottom. point. As shown in FIG. 9 , the routing line 212 includes a first contact pad 213 and a second contact pad 214 . The pad size and the pad pitch of the second contact pads 214 are greater than the pad size and pad of the first contact pads 213 . spacing. Thus, the first contact pad 213 can provide an electrical contact to another semiconductor wafer, while the second contact pad 214 can provide an electrical contact to the next level of interconnect structure.

At this stage, the fabrication of the embedding device 20 has been completed, which includes a first routing circuit 21, a first semiconductor wafer 22, a series of terminals 24, and a sealing material 25.

10 and 11 are respectively a cross-sectional view and a bottom perspective view of a shield cover 321, a series of protrusions 323 and a protrusion 325. The shield cover 321 , the stud 323 and the projection 325 are generally integrally formed and may be made of any material for heat dissipation and electromagnetic shielding, such as copper, aluminum, stainless steel, or other metal or alloy materials. In this embodiment, the material of the shielding cover 321, the protrusion 323 and the protrusion 325 is copper. The stud 323 and the protrusion 325 are protruded from the surface of one of the shielding covers 321 and are usually formed by a lithography and wet etching process.

12 to 13 are cross-sectional views showing a process of laminating the routing substrate 351 to the shield cover 321 by the bonding film 341. Here, the stud 323 and the protrusion 325 are inserted into the through hole 352 of the routing substrate 351 and the opening 342 of the bonding film 341 to perform a lamination process. The openings 342 and the through holes 352 are generally formed by laser cutting through the bonding film 341 and the routing substrate 351, respectively, and may also be formed by other means such as stamping or mechanical drilling. The bonding film 341 can be composed of various dielectric films or prepregs formed of various organic or inorganic electrically insulating materials. In the figure, the routing substrate 351 is a board comprising an insulating layer 353, a second wire 354, a third wire 355 and a metallized perforation 356. The insulating layer 353 usually has a thickness of 50 μm and may be made of epoxy resin, glass epoxy resin, polyimide, or the like. The second wire 354 and the third wire 355 are disposed on opposite sides of the insulating layer 353. The metallized vias 356 extend through the insulating layer 353 and are electrically coupled to the second wires 354 and the third wires 355.

Under heat and pressure, the bonding film 341 between the shield cover 321 and the routing substrate 351 is in a molten state, and flows into the gap between the stud 323 and the routing substrate 351 and between the protruding seat 325 and the routing substrate 351. Accordingly, the bonding film 341 separates the shielding cover 321 , the stud 323 and the protruding seat 325 from the routing substrate 341 , and the cured bonding film 341 can provide the shielding cover 321 and the routing substrate 351 , the stud 323 and the routing A stable mechanical connection between the substrates 351 and between the protrusions 325 and the routing substrate 351 is achieved.

At this stage, the process of forming the second routing circuit 33 on the shield cover 321 is completed. The second routing circuit 33 includes the bonding film 341 and the routing substrate 351. In this figure, the studs 323 and the protrusions 325 extend through the second routing circuit 33 and both have an exposed surface that is substantially coplanar with the outer surface of the third conductor 355 of the routing substrate 351.

14 and 15 are respectively a cross-sectional view and a bottom perspective view of the removal protrusion 325 to expose a selected portion of the shield cover 321 from below. The protrusion 325 can be removed by various means to expose selected portions of the shield cover 321 from the through opening 331 of the second routing circuit 33, including using an acidic solution (such as ferric chloride, copper sulfate solution) or an alkaline solution ( For example, wet chemical etching, electrochemical etching, or mechanical etching (such as drilling or end milling) after chemical etching.

At this stage, the fabrication of the heat sink 31 has been completed, which includes a shield cover 321, a series of posts 323 and a second routing circuit 33. In the figure, the shielding cover 321 is partially exposed by the through opening 331 of the second routing circuit 33, and the protrusions 323 are formed around the through opening 331 of the second routing circuit 33.

16 is a cross-sectional view of the second semiconductor wafer 36 attached to the heat sink 31. The first bump 41 is disposed on the active surface of the second semiconductor wafer 36 (shown as a bare wafer), and the heat conductive contact 37 contacts the inactive surface to make the second semiconductor wafer 36 and the shield cover 321 of the heat sink 31 thermally. Conduction, wherein the thermally conductive contact 37 can be made of an organic resin or solder mixed with metal particles. Accordingly, the second semiconductor wafer 36 is disposed in the through-opening 331 of the second routing circuit 33 in a face-down manner, and the heat sink 31 can provide heat dissipation from the second semiconductor wafer 36.

At this stage, the fabrication of the heat dissipation type device 30 is completed, which includes a heat sink 31 and a second semiconductor wafer 36.

17 is a cross-sectional view showing the second bump 43 and the third bump 45 being placed on the heat sink 31. The second bumps 43 and the third bumps 45 are respectively in contact with and electrically coupled to the second routing circuit 33 and the protrusions 323 of the heat sinks 31 .

18 is a cross-sectional view of the heat dissipation gain type device 30 of FIG. 17 stacked on the embedding device 20 of FIG. In this figure, the first semiconductor wafer 22 is disposed face up, and the second semiconductor wafer 36 is disposed to face downward.

19 is a cross-sectional view of the second semiconductor wafer 36 and the heat sink 31 electrically coupled to the first routing circuit 21. The first bump 41 is in contact with and electrically coupled to the first contact pad 213 of the first routing circuit 21 to provide an electrical connection between the first routing circuit 21 and the second semiconductor wafer 36. The second bump 43 and the third bump 45 are in contact with and electrically coupled to the second contact pad 214 of the first routing circuit 21 to provide a first routing circuit 21 and a second routing circuit 33 and a first routing circuit. 21 is electrically connected to the stud 323.

20 is a cross-sectional view showing the resin 48 filled between the embedding device 20 and the heat dissipation gain type device 30. Optionally, a gap 48 between the first routing circuit 21 and the second routing circuit 33 and between the first routing circuit 21 and the second semiconductor wafer 36 is filled, and the resin 48 also fills the second semiconductor wafer 36 and penetrates A gap between the sidewalls of the opening 331 is defined in the through opening 331.

Accordingly, as shown in FIG. 20, the completed semiconductor package 110 includes a buried device 20 and a heat dissipation gain type device 30. The heat dissipation type device 30 is electrically coupled and stacked on the embedding device 20 by a series of first bumps 41, a series of second bumps 43 and a series of third bumps 45. . In the figure, the embedding device 20 includes a first routing circuit 21, a first semiconductor wafer 22, a series of terminals 24, and a sealing material 25. The heat dissipation gain type device 30 includes a heat sink 31 and a first Two semiconductor wafers 36.

The first semiconductor wafer 22 is embedded in the sealing material 25 and electrically coupled to the first routing circuit 21 by one side of the first routing circuit 21 in a flip chip manner. The terminals 24 surround the first semiconductor wafer 22 and are electrically coupled to the first routing circuit 21 and are laterally covered by the sealing material 25. The second semiconductor wafer 36 is separated from the first routing circuit 21 by the first bump 41, and the second semiconductor wafer 36 is flipped by the first bump 41 from the other side of the first routing circuit 21 Electrically coupled to the first routing circuit 21. Accordingly, the first routing circuit 21 can provide a primary fanout route and a shortest interconnect distance between the first semiconductor wafer 22 and the second semiconductor wafer 36. The heat sink 31 has a shield cover 321 , a protrusion 323 and a second routing circuit 33 . The protrusions 323 are protruded from a surface of the shielding cover 321 , and the second routing circuit 33 is located at the shielding cover 321 . On the surface. The shield cover 321 of the heat sink 31 is thermally conducted to the second semiconductor wafer 36 and covers the second semiconductor wafer 36 from above. The second routing circuit 33 is electrically separated from the first routing circuit 21 by the second bumps 43 and electrically coupled to each other. The stud 323 laterally surrounds the second semiconductor wafer 36 and extends through the second routing circuit 33. In addition, the shielding cover 321 and the protruding post 323 are electrically connected to the terminal 24 in the sealing material 25 through the first routing circuit 21 and the third bump 45 as a ground connection, wherein the third bump 45 contacts the stud 323 and the first A routing circuit 21. Accordingly, the shielding cover 321 can provide heat dissipation and electromagnetic shielding of the second semiconductor wafer 36, and the stud 323 can serve as a heat dissipation tube to provide a heat dissipation path for the first semiconductor wafer 22.

Figure 21 is a cross-sectional view showing another semiconductor package in the first embodiment of the present invention. The semiconductor package 120 includes another heat sink 23 attached to the first semiconductor wafer 22. The semiconductor package 120 is similar in construction to that shown in FIG. 20, except that the embedding device 20 further includes a heat sink 23, and the terminal 24 has a substantially coplanar exposed surface with the second surface 253 of the seal member 23. The heat sink 23 is typically made of a thermally conductive material such as a metal, alloy, tantalum, ceramic or graphite. In this aspect, the heat sink 23 is attached to the inactive surface of the first semiconductor wafer 22 before the sealing material 25 is formed, and is exposed by the second surface 253 of the sealing material 25, and the solder ball 241 is routed by the first Circuit 21 extends to second surface 253 of sealing material 25 as terminal 24.

Figure 22 is a cross-sectional view showing still another semiconductor package body in the first embodiment of the present invention. The semiconductor package body 130 is provided with a metal post 243 as a terminal 24. The semiconductor package 130 is similar in construction to that shown in FIG. 20 except that the embedding device 20 includes a metal post 243 as the terminal 24. The metal posts 243 are disposed prior to forming the sealing material 25 and extend from the first routing circuit 21 to the second surface 253 of the sealing material 25.

[Embodiment 2]

23-31 are diagrams showing a method of fabricating a semiconductor package having an external routing circuit on a sealing material in a second embodiment of the present invention.

For the purpose of brief description, any description of the same application in the above-described embodiment 1 is hereby made, and the same description is not repeated.

23 is a cross-sectional view showing the sealing material 25 formed on the first routing circuit 21 and the first semiconductor wafer 22 of FIG. The sealing material 25 covers the first routing circuit 21 and the first semiconductor wafer 22 from below, and is wrapped around the same shape and covers the sidewalls of the first semiconductor wafer 22.

FIG. 24 is a cross-sectional view showing the formation of the blind hole 256 in the sealing material 25. The blind holes 256 are aligned with the selected portions of the first wires 217 of the first routing circuit 21 and extend through the sealing material 25 between the first surface 251 and the second surface 253 of the sealing material 25.

25 is a cross-sectional view showing the formation of conductive vias 244 in blind vias 256 and forming external leads 262 on sealing material 25. The conductive vias 244 may be formed by a metal deposition process in the blind vias 256 that is in contact with the first leads 217 of the first routing circuit 21 to serve as the terminals 24 surrounding the first semiconductor wafer 22. The external wires 262 are formed on the second surface 253 of the sealing material 25 by a metal deposition and metal patterning process, and are electrically coupled to the conductive vias 244.

This stage has been completed to form the outer routing circuit 26 on the second surface 253 of the sealing material 25. In the figure, the external routing circuit 26 includes an outer lead 262 that extends laterally over the second surface 253 of the sealing material 25 and that is in contact with and electrically coupled to the terminal 24 in the sealing material 25.

26 and 27 are a cross-sectional view and a top perspective view, respectively, showing the sacrificial carrier 10 removed to reveal the first routing circuit 21 from above. As shown in FIG. 27, the routing line 212 includes a first contact pad 213 and a second contact pad 214. The pad size and the pad pitch of the second contact pads 214 are larger than the pad size and pad of the first contact pads 213. spacing. Accordingly, the fabrication of the embedding device 20 has been completed at this stage, including a first routing circuit 21, a first semiconductor wafer 22, a series of terminals 24, a sealing material 25, and an external routing circuit 26.

28 and 29 are a cross-sectional view and a top perspective view, respectively, of the second semiconductor wafer 36 electrically coupled to the first routing circuit 21. The second semiconductor wafer 36 is connected to the first routing circuit 21 in a flip chip manner by a series of first bumps 41 , wherein the first bumps 41 are in contact with the first contact pads 213 of the first routing circuit 21 . The underfill 42 may be optionally filled in the gap between the first routing circuit 21 and the second semiconductor wafer 36.

Figure 30 is a cross-sectional view showing the heat sink 31 of Figure 14 stacked on the structure of Figure 28. Before the stacking step, the heat conducting contact 37 is applied to the shielding cover 321 exposed from the recess 305 of the heat sink 31, and is respectively connected to the second routing circuit 33 and the protruding post 323 of the heat sink 31. The second bump 43 and the third bump 45 are series.

31 is a cross-sectional view of the heat sink 31 attached to the second semiconductor wafer 36 and electrically coupled to the first routing circuit 21. The second semiconductor wafer 36 is inserted into the recess 305 of the heat sink 31, and the second semiconductor wafer 36 is thermally connected to the shield cover 321 of the heat sink 31 by the heat conductive contact 37. At the same time, the second routing block 33 and the protruding post 323 of the heat sink 31 are electrically coupled to the first routing circuit 21, respectively, by the second bumps 43 and the third bumps 45 contacting the second contact pads 214.

Accordingly, as shown in FIG. 31, the completed semiconductor package 210 includes a buried device 20 and a heat dissipation gain type device 30. In the figure, the embedding device 20 includes a first routing circuit 21, a first semiconductor wafer 22, a series of terminals 24, a sealing material 25 and an external routing circuit 26, and the heat dissipation gain type device 30 includes a The heat sink 31 and a second semiconductor wafer 36.

The first semiconductor wafer 22 and the second semiconductor wafer 36 are disposed on opposite sides of the first routing circuit 21, and are electrically coupled to each other in a face-to-face manner by the first routing circuit 21 therebetween. The first semiconductor wafer 22 is embedded in the sealing material 25 and surrounded by the terminal 24 , and is electrically coupled to the first routing circuit 21 by the conductive bumps 223 . The second semiconductor wafers 36 are received in the recesses 305 of the heat sinks 31, and are separated from the first routing circuit 21 by the first bumps 41 and electrically coupled to each other. The heat sink 31 has a shielding cover 321, a series of protrusions 323 and a second routing circuit 33. The shielding cover 321 is thermally connected to the second semiconductor wafer 36. The protrusion 323 is protruded from the shielding cover 321 and the second routing circuit 33 is disposed. On the shielding cover 321 . In addition, the shield 321 is electrically coupled to the first routing circuit 21 and the terminal 24 as a ground connection by electrically connecting the stud 323 to the first routing circuit 21. Accordingly, the shield cover 321 can provide heat dissipation, electromagnetic shielding, and moisture barrier of the second semiconductor wafer 36. The second routing circuit 33 is electrically coupled to the first routing circuit 21 by the second bumps 43 , and the external routing circuit 26 is electrically coupled to the first routing circuit 21 by the terminals 24 in the sealing material 25 . Accordingly, the first routing circuit 21, the second routing circuit 33, and the external routing circuit 26 are electrically connected to each other, and provide a staged fanout route of the first semiconductor wafer 22 and the second semiconductor wafer 36.

Figure 32 is a cross-sectional view showing another semiconductor package in a second embodiment of the present invention. The terminal 24 of the semiconductor package 220 is a combination of a metal post 243 and a conductive blind via 244. The semiconductor package 220 is similar in structure to that shown in FIG. 31 except that the embedding device 20 further includes a metal post 243 between the first routing circuit 21 and the conductive via 244. The metal posts 243 contact the first wire 217 and the conductive blind holes 244 extend from the metal post 243 to the outer wire 262.

Figure 33 is a cross-sectional view showing another semiconductor package in accordance with a second embodiment of the present invention. The terminal 24 of the semiconductor package 230 is a solder ball 241. The semiconductor package 230 is similar in construction to that shown in FIG. 31 except that the external routing circuit 26 is not provided on the sealing material 25 of the embedding device 20, and the terminals 24 are formed in other different aspects. In this aspect, the embedding device 20 is fabricated by attaching the solder balls 241 to the blind holes 256 of the sealing material 25 of FIG. 24, and then removing the sacrificial carrier 10. Accordingly, the solder ball 241 contacts the first routing circuit 21 and fills the blind via 256 of the sealing material 25 as the terminal 24.

[Example 3]

34-55 are diagrams showing a method of fabricating a semiconductor package in which a heat sink extends laterally beyond the peripheral edge of the embedding device in a third embodiment of the present invention.

For the purpose of brevity, the description of any of the above embodiments that can be used for the same application is the same, and the same description is not repeated.

34 and 35 are respectively a cross-sectional view and a top perspective view of a plurality of sets of positioning members 28 on the heat sink 23. The thickness of the heat sink 23 is preferably in the range of 0.1 to 1.0 mm. The positioning member 28 is convex from the surface of the heat sink 23 and may have a thickness of 5 to 200 μm. In this embodiment, the heat sink 23 has a thickness of 0.5 mm and the positioning member 28 has a thickness of 50 microns. The locating member 28 can be formed by patterning deposition by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof, and simultaneously using lithography techniques, or formed by thin film deposition followed by a metal patterning step. Metal patterning techniques include wet etching, electrochemical etching, laser assisted etching, and combinations thereof, and an etch mask (not shown) is used to define the positioning member 28. In the case of a conductive heat sink 23, it is typically deposited by metal (e.g., copper) electroplating to form the locating member 28. Alternatively, if a non-conductive heat sink 23 is used, a solder mask or photoresist material can be used to form the locator 28. As shown in Fig. 35, each set of positioning members 28 is composed of a plurality of studs and conforms to the four corners of the subsequently disposed semiconductor wafer. However, the pattern of the positioning member is not limited thereto, and it may have other various patterns that prevent unnecessary displacement of the subsequently disposed semiconductor wafer. For example, the locating member 28 can be comprised of a continuous or discontinuous ridge and conforms to the four sides, two diagonals, or four corners of the subsequently disposed semiconductor wafer. Alternatively, the keeper 28 can extend laterally to the peripheral edge of the heat sink 23 and have an inner peripheral edge that conforms to the peripheral edge of the subsequently disposed semiconductor wafer.

36 and 37 are respectively a cross-sectional view and a top perspective view of the first semiconductor wafer 22 attached to the heat sink 23, which is typically attached to the first semiconductor wafer 22 by a thermally conductive adhesive. In the figure, the active bread of each first semiconductor wafer 22 includes bumps 222, and the first semiconductor wafer 22 is attached to the heat sink 23 with the inactive surface facing the heat sink 23. Each set of locating members 28 is laterally aligned and adjacent to a peripheral edge of each of the first semiconductor wafers 22. The positioning member 28 can control the accuracy of wafer placement. The positioning member 28 extends in the upward direction beyond the inactive surface of the first semiconductor wafer 22 and is located outside the four corners of the first semiconductor wafer 22 while laterally aligning the four corners of the first semiconductor wafer 22 in the lateral direction. Since the positioning members 28 are laterally adjacent and conform to the four corners of the first semiconductor wafer 22, they can avoid any unnecessary displacement of the first semiconductor wafer 22 when the adhesive is cured. The gap between the locating member 28 and the first semiconductor wafer 22 is preferably in the range of about 5 to 50 microns. In addition, the attaching step of the first semiconductor wafer 22 may not use the positioning member 28.

38 is a cross-sectional view showing the sealing material 25 formed on the first semiconductor wafer 22 and the heat sink 23. The sealing material 25 covers the first semiconductor wafer 22 and the heat sink 23 from above, and is wrapped around the same shape and covers the sidewalls of the first semiconductor wafer 22 while extending laterally from the first semiconductor wafer 22 to the peripheral edge of the structure.

39 is a cross-sectional view showing the bump 222 of the first semiconductor wafer 22 exposed from above. The top region of the sealing material 25 can be removed by grinding, polishing or laser. After partial removal of the sealing material 25, the top surface of the sealing material 25 is substantially coplanar with the outer surface of the bump 222.

40 and 41 are respectively a cross-sectional view and a top perspective view of the primary conductive line 211 formed by a metal deposition and metal patterning process. The primary lead 211 extends laterally on the sealing material 25 and is electrically coupled to the bump 222 of the first semiconductor wafer 22 .

42 is a cross-sectional view of dielectric layer 215 and blind vias 216 with dielectric layer 215 on seal 25 and primary lead 211 and blind via 216 in dielectric layer 215. The dielectric layer 215 contacts the sealing material 25 and the primary conductive wire 211 and is covered by the upper surface and extends laterally on the sealing material 25 and the primary conductive wire 211. After deposition of dielectric layer 215, a blind via 216 is formed that extends through dielectric layer 215 that is aligned with selected portions of primary conductor 211.

43 and 44 are respectively a cross-sectional view and a top perspective view of a first conductive line 217 formed on the dielectric layer 215, wherein the first conductive line 217 is formed by a metal deposition and metal patterning process. The first wire 217 extends upward from the primary wire 211 and fills the blind hole 216 to form a metallized blind hole 218 that directly contacts the primary wire 211 while extending laterally over the dielectric layer 215. As shown in FIG. 44, the first wire 217 includes a first contact pad 213 and a second contact pad 214. The pad size and pad pitch of the second contact pad 214 are greater than the pad size and pad pitch of the first contact pad 213. Thus, the first contact pad 213 can provide an electrical contact for another semiconductor wafer connection, and the second contact pad 214 can provide an electrical contact to the next level of interconnect structure.

At this stage, the fabrication of the embedding device 20 has been completed, which includes a heat sink 23, a positioning member 28, a first semiconductor wafer 22, a sealing material 25, and a first routing circuit 21. In the figure, the first routing circuit 21 includes a primary conductive line 211, a dielectric layer 215, and a first conductive line 217.

45 and 46 are respectively a cross-sectional view and a top perspective view of the second semiconductor wafer 36 electrically coupled to the first routing circuit 21. The active surface of the second semiconductor chip 36 faces the first routing circuit 21 and can be electrically coupled to the first contact pad 213 of the first wire 217 by the first bump 41.

47-51 are cross-sectional views showing another manufacturing method in which the second semiconductor wafer 36 is electrically coupled to the single piece after the cutting device 20 is cut.

47 is a cross-sectional view showing the dielectric layer 215 and forming the blind vias 216, wherein the dielectric layer 215 is laminated/coated on the first semiconductor wafer 22 and the sealing material 25, and the blind vias 216 are formed in the dielectric layer 215. . The dielectric layer 215 contacts the bump 222 of the first semiconductor wafer 22 and the sealing material 25 and is covered by the upper surface and extends laterally on the bump 222 of the first semiconductor wafer 22 and the sealing material 25. The blind vias 216 extend through the dielectric layer 215 and are aligned with the bumps 222 of the first semiconductor wafer 22.

48 is a cross-sectional view of the first conductive line 217 formed on the dielectric layer 215 by a metal deposition and metal patterning process. The first wire 217 extends upward from the bump 222 of the first semiconductor wafer 22 and fills the blind via 216 to form a metallized blind via 218 that directly contacts the bump 222 while extending laterally over the dielectric layer 215. .

49 is a cross-sectional view showing the second semiconductor wafer 36 attached to the first conductive line 217. The second semiconductor wafer 36 is electrically coupled to the first contact pad 213 of the first wire 217 by the first bump 41 .

Figure 50 is a cross-sectional view showing the panel size structure of Figure 49 cut into individual pieces. As shown, along the cutting line "L", the panel size structure is separated into individual pieces.

51 is a cross-sectional view of a single semiconductor device 36 electrically coupled to the embedding device 20, wherein the embedding device 20 includes a heat sink 23, a positioning member 28, a first semiconductor wafer 22, and a sealing material. 25 and a first routing circuit 21. In the figure, the first routing circuit 21 includes a dielectric layer 215 and a first conductive line 217 extending laterally beyond the peripheral edges of the first semiconductor wafer 22 and the second semiconductor wafer 36. The first semiconductor wafer 22 is electrically coupled to the first routing circuit 21 from below and is covered by the heat sink 23 and the sealing material 25 . The second semiconductor wafer 36 is electrically coupled to the first routing circuit 21 from above and is electrically connected to the first semiconductor wafer 22 face to face through the first routing circuit 21 .

52 and 53 are respectively a cross-sectional view and a bottom perspective view of the heat sink 31. The heat sink 31 is similar to the structure shown in FIG. 14, except that the heat sink 31 further has an additional protrusion 324, and the second routing circuit 33 further includes a build-up insulating layer 361 and a fourth lead 364. The layer insulating layer 361 is laminated/coated on the routing substrate 351 and the studs 323, 324, and the fourth wire 364 is deposited on the build-up insulating layer 361. The build-up insulating layer 361 contacts the routing substrate 351 and the studs 323 and 324, and is covered by the lower side and extends laterally on the routing substrate 351 and the studs 323 and 324. The build-up insulating layer 361 typically has a thickness of 50 microns and may be made of epoxy resin, glass epoxy, polyimide, or the like. The fourth wire 364 is deposited on the build-up insulating layer 361 by a metal deposition and metal patterning process, and includes a metallized blind via 365 contacting the routing substrate 351, the third wire 355 and the protrusions 323, 324. Metallized blind vias 365 extend through buildup insulating layer 361. As shown in FIG. 53, the fourth wire 364 includes a first terminal pad 367 and a second terminal pad 368. The pad size and pad pitch of the first terminal pad 367 are greater than the pad size and pad pitch of the first semiconductor wafer 22 and the second semiconductor wafer 36, and are consistent with the pad size and pad pitch of the second contact pad 214 of the first routing circuit 21. The pad size and the pad pitch of the second terminal pad 368 are larger than the pad size and the pad pitch of the first terminal pad 367, and conform to the next-level interconnection structure.

Figure 54 is a cross-sectional view showing the heat sink 31 of Figure 52 stacked on the structure of Figure 51. Before the stacking step, the heat conducting contact 37 is applied to the shield cover 321 exposed from the second routing circuit 33 through the opening 331, and the second bump is attached to the fourth wire 364 of the second routing circuit 33. Block 43.

55 is a cross-sectional view of the heat sink 31 attached to the second semiconductor wafer 36 and electrically coupled to the first routing circuit 21. The second semiconductor wafer 36 is inserted into the through opening 331 of the second routing circuit 33, and the second semiconductor wafer 36 is thermally connected to the shield cover 321 of the heat sink 31 by the heat conducting contact 37. At the same time, the first terminal pad 367 of the second routing circuit 33 is electrically coupled to the second contact pad 214 of the first routing circuit 21 by the second bump 43.

Accordingly, as shown in FIG. 55, the completed semiconductor package 310 includes a buried device 20 and a heat dissipation gain type device 30. In the figure, the embedding device 20 includes a first routing circuit 21, a first semiconductor wafer 22, a heat sink 23, a sealing material 25 and a positioning member 28, and the heat dissipation gain type device 30 includes a heat dissipation device. a holder 31 and a second semiconductor wafer 36.

The first semiconductor wafer 22 is attached to the heat sink 23, and the positioning member 28 is located around its inactive surface and conforms to the four corners of the first semiconductor wafer 22. The first routing circuit 21 is electrically coupled to the first semiconductor wafer 22 and extends laterally beyond the peripheral edge of the first semiconductor wafer 22 while laterally extending over the sealing material 25, and the sealing material 25 laterally surrounds the first semiconductor. Wafer 22. The second semiconductor wafer 36 is electrically connected to the first semiconductor wafer 22 in a face-to-face manner by the first routing circuit 21 and the first bump 41 in contact with the first routing circuit 21. In this way, the first routing circuit 21 can provide the shortest interconnection distance between the first semiconductor wafer 22 and the second semiconductor wafer 36, and provide the first semiconductor fan 22 and the second semiconductor wafer 36 with a first-stage fan-out route. . The heat sink 31 has a shield cover 321, a series of posts 323, 324 and a second routing circuit 33. The shielding cover 321 of the heat sink 31 is electrically connected to the second semiconductor wafer 36 and covers the second semiconductor wafer 36 from above. The protrusions 323 and 324 of the heat sink 31 laterally surround the second semiconductor wafer 36 and are electrically connected. The second routing circuit 33 is connected to form a ground connection. The second routing circuit 33 of the heat sink 31 includes a second wire 354, a third wire 355 and a fourth wire 364 extending laterally beyond the peripheral edge of the first routing circuit 21, and is electrically coupled by the second bump 43. To the first routing circuit 21. Accordingly, the second routing circuit 33 can provide a second-stage fan-out route to the first routing circuit 21 and provide an electrical contact for the external connection, and the shield cover 321 of the heat sink 31 is electrically connected to the first The routing circuit 21 is configured to provide heat dissipation and electromagnetic shielding of the second semiconductor wafer 36.

[Example 4]

56-71 are diagrams showing a method of fabricating a semiconductor package having terminals disposed around a buried device in a fourth embodiment of the present invention.

For the purpose of brevity, the description of any of the above embodiments that can be used for the same application is the same, and the same description is not repeated.

Figure 56 is a cross-sectional view showing the first routing circuit 21 detachably attached to the sacrificial carrier 10. In the figure, the sacrificial carrier 10 is a two-layer structure comprising a support plate 111 and a barrier layer 113 deposited on the support plate 111. The first routing circuit 21 is formed on the barrier layer 113 by the steps shown in FIGS. 1-3. The barrier layer 113 may have a thickness of 0.001 to 0.1 mm, and may be a metal layer, wherein the metal layer may resist chemical etching when chemically removing the support plate 111, and may remove the metal without affecting the routing line 212. Floor. For example, when the support plate 111 and the routing line 212 are both made of copper, the barrier layer 113 may be made of tin or nickel. Further, in addition to the metal material, the barrier layer 113 may be a dielectric layer such as a peelable laminate film. In this embodiment, the support plate 111 is a copper plate, and the barrier layer 113 is a nickel layer having a thickness of 5 micrometers.

57 is a cross-sectional view of the first semiconductor wafer 22 electrically coupled from the lower side to the first routing circuit 21. The first semiconductor wafer 22 is electrically coupled to the first routing circuit 21 via the conductive bumps 223 .

Figure 58 is a cross-sectional view showing the formation of the sealing material 25 on the first routing circuit 21 and the first semiconductor wafer 22. The sealing material 25 covers the first routing circuit 21 and the first semiconductor wafer 22 from below, and is wrapped around the same shape and covers the sidewalls of the first semiconductor wafer 22.

Figure 59 is a cross-sectional view showing the lower region of the sealing material 25. Accordingly, the inactive surface of the first semiconductor wafer 22 is exposed from below and substantially coplanar with the bottom surface of the sealing material 25.

60 is a cross-sectional view of the heat sink 23 attached to the first semiconductor wafer 22. The heat sink 23 is attached to the inactive surface of the first semiconductor wafer 22 and the bottom surface of the sealing material 25.

61 and 62 are a cross-sectional view and a top perspective view, respectively, of the removal of the sacrificial carrier 10. Here, the support plate 111 made of copper can be removed by an alkaline etching solution, and then the barrier layer 113 made of nickel can be removed by an acidic etching solution to expose the first routing circuit from above. twenty one. In another aspect in which the barrier layer 113 is a peelable laminate film, the barrier layer 113 can be removed by mechanical peeling or plasma ashing. As shown in FIG. 62, the routing line 212 includes a first contact pad 213 and a second contact pad 214. The pad size and pad pitch of the second contact pad 214 are greater than the pad size and pad pitch of the first contact pad 213. Accordingly, the first contact pad 213 can provide an electrical contact to another semiconductor wafer, and the second contact pad 214 can provide an electrical contact to the next level of interconnect structure.

At this stage, the fabrication of the embedding device 20 is completed, which includes a first routing circuit 21, a first semiconductor wafer 22, and a sealing material 25.

63 and 64 are a cross-sectional view and a top perspective view, respectively, of the second semiconductor wafer 36 electrically coupled to the first routing circuit 21. The second semiconductor wafer 36 is connected to the first routing circuit 21 in a flip chip manner by a series of first bumps 41 , wherein the first bumps 41 are in contact with the first contact pads 213 of the first routing circuit 21 .

65 is a cross-sectional view showing the structure of a shield cover 321, a series of studs 323, 324, and a second routing circuit 33. In this figure, the structure of FIG. 65 is similar to the structure shown in FIG. 52, except that the protrusions 323 and 324 extend through the second routing circuit 33, and the routing substrate 351 and the protrusions 323 and 324 are not provided. A layer of insulating layer and a fourth wire are added.

FIG. 66 is a cross-sectional view showing the second bump 43, the third bump 45, the fourth bump 47, and the metal pin 381. The second bumps 43 are connected to the third wires 355 of the second routing circuit 33, and the third bumps 45 and the fourth bumps 47 are respectively placed on the studs 323, 324. The partial metal pins 381 are electrically coupled to the second bumps 43 located at the edge regions of the outer surface of the second routing circuit 33, and the other metal pins 381 are attached to the fourth bumps 47 on the protrusions 324. .

At this stage, the fabrication of the heat sink 31 has been completed, which includes a shield cover 321, a series of posts 323, 324, a second routing circuit 33, and a series of terminals 38. In this aspect, the terminals 38 are shown as metal pins 381 and are electrically coupled to the second routing circuit 33 to form a signal route, and are electrically coupled to the shield cover 321 to form a ground. connection.

Figure 67 is a cross-sectional view showing another heat dissipating seat pattern in the fourth embodiment of the present invention. The heat sink 31 is provided with a reinforcing layer 39 on the outer surface of the second routing circuit 33. The reinforcing layer 39 is usually formed by a printing or molding process of the resin sealing material to cover the edge regions of the outer surface of the terminal 38 and the second routing circuit 33 from below, and is surrounded and conformed in the lateral direction. Cover terminal 38. After the reinforcement layer 39 is formed, the lower region of the reinforcement layer 39 is removed to expose the terminal 38 from below.

Figure 68 is a cross-sectional view showing still another heat sink seat in the fourth embodiment of the present invention. The heat sink 31 is provided with solder balls 383 in the reinforcing layer 39. In this aspect, the heat sink 31 is similar in structure to that shown in FIG. 67, except that it is provided with a solder ball 383 as a terminal 38 that contacts the third wire 355 and the post 324 of the second routing circuit 33. And the reinforcement layer 39 has an opening 391 to expose selected portions of the solder balls 383 from below.

Figure 69 is a cross-sectional view showing still another heat sink seat in the fourth embodiment of the present invention. The heat sink 31 is provided with a conductive blind hole 385 in the reinforcing layer 39, and is provided with a solder ball 383 contacting the conductive blind hole 385. In this aspect, the heat sink 31 is similar in construction to that shown in FIG. 67, except that the terminal 38 includes a combination of solder balls 383 and conductive blind holes 385. The conductive vias 385 can be formed by performing a metal deposition process in the blind vias 393 of the reinforcement layer 39, which contacts the third conductors 355 and the pillars 324 of the second routing circuit 33. After depositing the conductive vias 385, solder balls 383 are disposed to contact the conductive vias 385, and the solder balls 383 fill the remaining space of the blind vias 393 of the reinforcement layer 39 and extend downward beyond the outer surface of the reinforcement layer 39.

Figure 70 is a cross-sectional view showing the heat sink 31 of Figure 66 stacked on the structure of Figure 63. Before the stacking step, the heat conducting contact 37 is applied to the shield cover 321 exposed from the second routing circuit 33 through the opening 331.

71 is a cross-sectional view of the heat sink 31 attached to the second semiconductor wafer 36 and electrically coupled to the first routing circuit 21. The second semiconductor wafer 36 is disposed in the through opening 331 of the second routing circuit 33, and the second semiconductor wafer 36 is thermally connected to the shielding cover 321 of the heat sink 31 by the heat conducting contact 37. At the same time, the second routing circuit 33 and the protrusions 323 of the heat sinks 31 are electrically coupled to the second contact pads 214 of the first routing circuit 21, respectively, by the second bumps 43 and the third bumps 45. [001] [002] [003] [004] [005] [006] [007] [008] [009] [010] [011] [012] [013] [014] [015] [016] [017 】 【018】 【019】 【020】 【021】 【022】 【023】 【024】 【025】 【026】 【027】 【028】 [029] [030] [031] [032] [033] [034] [035] [036] [037] [038] [039] [040] [041] [042] [043] [044] [045 】 【046】 【047】 【048】 【049】 【050】 【051】 【052】 【053】 【054】 【055】 【056】 [057] [058] [059] [060] [061] [062] [063] [064] [065] [066] [067] [068] [069] [070] [071] [072] [073 】 【074】 【075】 【076】 【077】 【078】 【079】 【080】 【081】 【082】 【083】 【084】 【085】 【086】 【087】 【088】 【089】 【090】 【091】 【092】 【093】 【094】 【095】 【096】 【097】 【098】 【099】

Accordingly, as shown in FIG. 71, the completed semiconductor package 410 includes a buried device 20 and a heat dissipation type device 30. In the figure, the embedding device 20 includes a first routing circuit 21, a first semiconductor wafer 22, a heat sink 23 and a sealing material 25. The heat dissipation gain device 30 includes a shielding cover 321 and a series of convexities. Columns 323, 324, a second routing circuit 33, a second semiconductor wafer 36 and a series of terminals 38.

The first semiconductor wafer 22 and the second semiconductor wafer 36 are disposed on opposite sides of the first routing circuit 21, and are electrically coupled to each other in a face-to-face manner by the first routing circuit 21 therebetween. The first semiconductor wafer 22 is embedded in the sealing material 25, and the second semiconductor wafer 36 is received in the through opening 331 of the second routing circuit 33 and thermally conductive to the shielding cover 321 of the heat sink 31. The first routing circuit 21 and the second routing circuit 33 are electrically coupled to each other to provide a phased fanout route of the first semiconductor wafer 22 and the second semiconductor wafer 36. The second routing circuit 33 extends laterally beyond the peripheral edge of the first routing circuit 21 to provide an electrical contact for the next level of interconnection. The terminals 38 are disposed around the embedding device 20 and are electrically coupled to the shielding cover 321 by the studs 324 to form a ground connection and electrically coupled to the second routing circuit 33 to form a signal route.

Figure 72 is a cross-sectional view showing another semiconductor package in accordance with a fourth embodiment of the present invention. The semiconductor package 420 is such that the embedding device 20 is received in the through opening 395 of the reinforcing layer 39, and the embedding device 20 is laterally surrounded by the terminals 38 in the reinforcing layer 39. The embedding device 20 is made by removing the sacrificial carrier 10 of FIG. After the sacrificial carrier 10 is removed, the second semiconductor wafer 36 is electrically coupled to the first routing circuit 21 by the first bumps 41, and then by the second bumps 43 and the third bumps 45. The heat sink 31 of FIG. 67 is electrically coupled to the first routing circuit 21.

Figure 73 is a cross-sectional view showing another semiconductor package in accordance with a fourth embodiment of the present invention. The semiconductor body 430 is provided with a bonding wire 29 to provide an electrical connection between the first routing circuit 21 and the first semiconductor wafer 22. The semiconductor package 430 is similar in structure to that shown in FIG. 72 except that the first semiconductor wafer 22 is electrically coupled to the first routing circuit 21 by wire bonding.

[Example 5]

74-77 are diagrams showing a method of fabricating a semiconductor package having an external routing circuit on a reinforcing layer in a fifth embodiment of the present invention.

For the purpose of brevity, the description of any of the above embodiments that can be used for the same application is the same, and the same description is not repeated.

74 is a cross-sectional view of the heat dissipation gain type device 30 electrically coupled and stacked on the embedding device 20. In the figure, the embedding device 20 includes a first routing circuit 21, a first semiconductor wafer 22 and a sealing material 25, and the heat dissipation gain type device 30 includes a shielding cover 321, a series of protrusions 323, 324, A second routing circuit 33, a second semiconductor wafer 36 and a series of terminals 38. The embedding device 20 is made by removing the sacrificial carrier 10 of FIG. After the sacrificial carrier 10 is removed, the second semiconductor wafer 36 is electrically coupled to the first routing circuit 21 by the first bumps 41, and then by the second bumps 43 and the third bumps 45. The heat sink 31 of FIG. 66 is electrically coupled to the first routing circuit 21.

75 is a cross-sectional view showing the reinforcing layer 39 formed on the embedding device 20 and the heat dissipation gain type device 30. The reinforcing layer 39 covers the embedding device 20, the second routing circuit 33 and the terminal 38 from below, and is wrapped around the same shape and covers the side walls of the embedding device 20 and the terminal 38.

Figure 76 is a cross-sectional view of the lower region of the reinforcing layer 39 removed to reveal the terminal 38 from below. In this figure, the exposed surfaces of the terminals 38 are substantially coplanar with the outer surface of the reinforcing layer 39.

77 is a cross-sectional view showing the outer lead 515 formed on the reinforcing layer 39. The outer leads 515 extend laterally on the outer surface of the reinforcing layer 39 and contact the terminals 38. At this stage, the process in which the external routing circuit 51 is formed on the outer surface of the reinforcing layer 39 has been completed.

Accordingly, as shown in FIG. 77, the completed semiconductor package 510 includes a first routing circuit 21, a first semiconductor wafer 22, a sealing material 25, a shielding cover 321, a series of studs 323, 324, and a first Two routing circuits 33, a second semiconductor wafer 36, a series of terminals 38, a reinforcing layer 39 and an external routing circuit 51.

The first routing circuit 21 and the second routing circuit 33 provide a phased fanout route of the first semiconductor wafer 22 and the second semiconductor wafer 36. The terminal 38 sealed in the reinforcing layer 39 provides electrical connection between the external routing circuit 51 and the second routing circuit 33, and between the external routing circuit 51 and the stud 324. The shielding cover 321 provides heat dissipation of the second semiconductor wafer 36, and is respectively connected to the first routing circuit 21 and the terminal 38 by the studs 323, 324 to form a ground connection, thereby providing effective electromagnetic shielding of the second semiconductor wafer 36.

The above semiconductor package is merely illustrative, and the present invention can be implemented by other various embodiments. In addition, the above embodiments may be used in combination with each other or in combination with other embodiments based on design and reliability considerations. The embedding device may include a plurality of first semiconductor wafers and may be electrically coupled to the plurality of second semiconductor wafers, and the second semiconductor wafer may independently use one of the heat sinks or share a recess with the other second semiconductor wafers . For example, a recess can accommodate a single second semiconductor wafer, and the heat sink can include a plurality of pockets arranged in an array to accommodate a plurality of second semiconductor wafers. Alternatively, a plurality of second semiconductor wafers can be placed in a single recess of the heat sink. In addition, the embedding device can use a heat sink alone or share a heat sink with other embedding devices. For example, a single buried device can be attached to the heat sink. Alternatively, connect several embedding devices to a heat sink. For example, four buried devices arranged in a 2x2 array can be connected to a heat sink, and the second routing circuit of the heat sink can include additional wires to connect additional plugging devices.

As shown in the above embodiment, the present invention constructs a unique semiconductor package comprising a face-to-face stacked buried device and a heat dissipation gain type device. The embedding device comprises a first semiconductor wafer, a first routing circuit and a sealing material, and the heat dissipation gain type device comprises a second semiconductor wafer and a heat sink. The first semiconductor wafer is embedded in the sealing material, and the second semiconductor wafer is disposed in the cavity of the heat sink instead of being embedded in the sealing material. In the semiconductor package, a series of terminals for external connection may be disposed in the sealing material of the embedding device or on the second routing circuit of the heat sink to surround the embedding device. A resin may be selectively filled in the space between the first routing circuit and the second semiconductor wafer and between the first routing circuit and the second routing circuit, and the resin may fill the second semiconductor wafer and the sidewall of the cavity in the heat sink pocket The gap between the two.

For convenience of the following description, the direction in which the first surface of the sealing material faces is defined as the first direction, and the direction in which the second surface of the sealing material faces is defined as the second direction.

The first and second semiconductor wafers can be wafers that are packaged or unpackaged. For example, the first and second semiconductor wafers can be bare wafers, or wafer level packaged dies, and the like. Alternatively, the first and second semiconductor wafers can be stacked wafers. In a preferred embodiment, the embedding device for electrically coupling the first semiconductor wafer to the first routing circuit can be formed by electrically coupling the first semiconductor wafer to the first routing circuit. The first routing circuit is detachably coupled to a sacrificial carrier; a sealing material and a selective terminal are provided on the first routing circuit; and the sacrificial carrier is removed from the first routing circuit. Here, the conventional flip chip bonding process can be used to electrically couple the active surface toward the first semiconductor wafer of the first routing circuit by the bumps, and the metallized blind via contacts the first Semiconductor wafer. Alternatively, the first semiconductor wafer facing away from the active circuit to the first routing circuit can be electrically coupled to the first routing circuit by wire bonding. Similarly, after removing the sacrificial carrier, the second semiconductor wafer with the active surface facing the first routing circuit can also be electrically coupled to the first routing circuit by using a conventional flip chip bonding process, and there is no The metallized blind via contacts the second semiconductor wafer. In a state in which the first semiconductor wafer is flip-chip mounted on the first routing circuit, a heat sink can be selectively attached to the inactive surface of the first semiconductor wafer before or after the sealing material is provided. Accordingly, the heat generated by the first semiconductor wafer can be dissipated by the heat sink. In addition, the embedding device can also be prepared by another process, which comprises the steps of: attaching the first semiconductor wafer to a heat sink by a heat conductive adhesive; providing a sealing material on the reinforcing layer; and forming The first routing circuit is on the active surface of the first semiconductor wafer and the sealing material, and electrically couples the first semiconductor wafer to the first routing circuit. In this process, the first routing circuit can be electrically coupled to the first semiconductor wafer directly by the build-up process. Additionally, a keeper can be provided to ensure the accuracy with which the first semiconductor wafer is placed on the heat sink. More specifically, the locating member is raised from one of the surfaces of the heat sink, and the first semiconductor wafer is attached to the heat sink by laterally aligning the peripheral edge of the first semiconductor wafer with the keeper. Since the positioning member extends beyond the inactive surface of the first semiconductor wafer in the first direction and is adjacent to the peripheral edge of the first semiconductor wafer, unnecessary displacement of the first semiconductor wafer can be avoided. Thereby, it is ensured that the first routing circuit has a high production yield when interconnected to the first semiconductor wafer.

The keeper may have various patterns that prevent unnecessary displacement of the first semiconductor wafer. For example, the positioning member can include a continuous or discontinuous rib or an array of studs. Alternatively, the locating member can extend laterally to the peripheral edge of the heat sink and the inner peripheral edge thereof conforms to the peripheral edge of the first semiconductor wafer. In particular, the locating members can be laterally aligned with the four sides of the first semiconductor wafer to define regions of the same or similar shape as the first semiconductor wafer and to avoid lateral displacement of the first semiconductor wafer. For example, the locating members can be aligned and conform to the four sides, two diagonals, or four corners of the first semiconductor wafer to limit lateral displacement of the first semiconductor wafer. Further, the positioning member (located around the inactive surface of the first semiconductor wafer) preferably has a height of 5 to 200 microns.

The first routing circuit can be a layered circuit without a core layer. Preferably, the first routing circuit is a multi-layer build-up circuit comprising at least one dielectric layer and wires, the wires filling the blind holes in the dielectric layer and extending laterally on the dielectric layer. The dielectric layer and the wire are continuously formed in turns and can be formed repeatedly if desired. The first routing circuit is provided with a first contact pad and a second contact pad on one side of the first direction for connecting the second semiconductor chip and the second routing circuit, respectively, and the other side facing the second direction is disposed There is an electrical contact connecting the first semiconductor wafer. Here, the pad size and pad pitch of the first contact pad are consistent with the I/O pads of the second semiconductor wafer, and can be electrically coupled to the second semiconductor wafer by the first bumps. The pad size and the pad pitch of the second contact pad are larger than the pad size and the pad pitch of the first contact pad, and are larger than the I/O pads of the first and second semiconductor chips, and are matched with the pad size and the pad pitch of the second routing circuit. Thereby, the second contact pad can be interconnected to the second routing circuit by the second bump. Thus, the first routing circuit can provide a preliminary fanout routing/interconnect and a shortest interconnect distance between the first and second semiconductor wafers.

The heat sink includes a shield cover, a stud and a second routing circuit. Preferably, the shielding cover is integrally formed with the plurality of protrusions and is made of a material that is thermally and electrically conductive. Accordingly, the shield cover can provide heat dissipation to the second semiconductor wafer attached to the shield cover, wherein the second semiconductor wafer is attached to the shield cover by a thermally conductive contact such as an organic resin or solder mixed with metal particles. The second routing circuit laterally surrounds the second semiconductor wafer and the bump of the heat sink, which may be a multilayer routing circuit including at least one insulating layer and a wire. The insulating layer and the wire are continuously formed in turns, and can be formed repeatedly if necessary. In a preferred embodiment, the second routing circuit includes a bonding film and a routing substrate. The routing substrate preferably includes an insulating layer, wires and metallized vias, wherein the wires are on opposite sides of the insulating layer, and the metallized vias extend through the insulating layer to provide electrical connection between the wires on both sides. The bonding film can bond the routing substrate to the shielding cover and the stud of the heat sink. More specifically, the protruding post of the heat sink is disposed in the through hole of the routing substrate, and the bonding film between the shielding cover and the routing substrate is partially squeezed into and filled in the gap between the protruding post and the routing substrate in the through hole. Therefore, the bonding film can provide a stable mechanical connection between the shielding cover and the routing substrate and between the stud and the routing substrate. The second routing circuit can optionally further include at least one build-up insulating layer and additional wires that fill the blind vias in the build-up insulating layer and extend laterally over the build-up insulating layer. For grounding, the second routing circuit can be further electrically coupled to the shielding cover and the stud by contacting the stud with a metallized blind hole. For example, the second routing circuit can include a metallized blind via that is located in the build-up insulating layer and that contacts the stud of the heat sink. Alternatively, the stud can extend through the second routing circuit and be aligned with the first routing circuit, and a series of third bumps can be disposed to contact the stud and the first routing circuit to provide a shielding cover and the embedding device. Electrical and thermal connections. Accordingly, the shield cover and the stud can be electrically coupled to the first routing circuit.

For the next level of connection, a series of terminals may be provided in the sealing material of the embedding device, or a series of terminals may be provided outside the embedding device to surround the peripheral edge of the embedding device. The terminals may include metal posts, solder balls, conductive blind holes, metal pins, or combinations thereof to provide electrical contacts for the next level of connection. In the aspect in which the terminal is not provided in the embedding device, the second routing circuit includes at least one wire extending laterally beyond the peripheral edge of the first routing circuit to provide an electrical contact for external connection. More specifically, the second routing circuit can include first and second terminal pads for connecting the first routing circuit and for externally connecting from the second direction. Preferably, the pad size and the pad pitch of the first terminal pad are larger than the I/O pads of the first and second semiconductor chips, and match the second contact pads of the first routing circuit, and the pad size of the second terminal pad and The pad spacing is greater than the pad size and pad spacing of the first terminal pad and conforms to the next level of connection. Accordingly, in the aspect in which the second routing circuit extends laterally beyond the peripheral edge of the embedding device, the heat sink further includes a series of terminals electrically coupled to the second routing circuit and surrounding the embedding device. In addition, some of the terminals may be electrically coupled to the shielding cover by a second routing circuit electrically connected to the studs to form a ground connection; or, an additional stud may be provided, which is protruded from the surface of the shielding cover. And aligning the area outside the peripheral edge of the embedding device, and the plurality of additional protrusions can be provided with a series of fourth bumps, so that some of the terminals can be electrically connected to the shielding cover by the fourth bump to form a ground. connection. In addition, the heat sink may further include a reinforcing layer covering the sidewalls of the terminals. The reinforcing layer is typically a resin molded reinforcing layer and may have a through opening to accommodate the embedding device. Alternatively, after the heat sink is electrically coupled to the embedding device, a reinforcing layer is provided to embed the terminals and the embedding device. In a preferred embodiment, the reinforcing layer extends laterally to the peripheral edge of the heat sink. In another aspect in which the terminal is disposed in the embedding device, a terminal electrically connected to the first routing circuit can be formed before or after the sealing material is provided. In a preferred embodiment, the terminals are located in an edge region of the first routing circuit and extend in a second direction toward the second surface of the sealing material by the first routing circuit. Accordingly, the terminal can have a first end in contact with the first routing circuit and an opposite second end adjacent to the second surface of the sealing material.

In an aspect in which the terminal is formed in the embedding device, an external routing circuit is selectively formed on the second surface of the sealing material; or, in another aspect in which the terminal is disposed outside the embedding device, An external routing circuit is formed on the outer surface of the reinforcement layer. The external routing circuit can be a build-up circuit and is electrically coupled to the terminal. More specifically, the embedding device may further include an additional wire contacting and electrically connected to the terminal in the sealing material and extending laterally on the second surface of the sealing material; or the semiconductor package may further comprise An additional wire that contacts and is electrically connected to the terminals in the reinforcement layer and extends laterally on the outer surface of the reinforcement layer. If more signal routing is required, the external routing circuit can be a multi-layer routing circuit that can further include one or more dielectric layers, blind vias in the dielectric layer, and additional wires. The outermost wire of the external routing circuit can accommodate conductive contacts, such as solder balls, for electrical transmission and mechanical connection with the next group or another electronic component.

The term "overlay" means incomplete and complete coverage in the vertical and / or lateral directions. For example, in a state in which the pockets face upward, the shield cover of the heat sink covers the second semiconductor wafer underneath, regardless of whether another component such as a thermally conductive contact is located between the second semiconductor wafer and the shield cover.

The words "attached to" and "attached to" include contact and non-contact with a single or multiple components. For example, the shield cover of the heat sink is attached to the inactive surface of the second semiconductor wafer, whether or not the shield cover is separated from the second semiconductor wafer by a thermally conductive contact.

The term "aligned" means the relative position between elements, whether or not the elements are spaced apart from each other or abut, or one element is inserted and extends into the other element. For example, when the imaginary horizontal line intersects the positioning member and the first semiconductor wafer, the positioning member is laterally aligned with the first semiconductor wafer, regardless of whether there are other components intersecting the imaginary horizontal line between the positioning member and the first semiconductor wafer. And whether or not there is another imaginary horizontal line that intersects the first semiconductor wafer but does not intersect the aligning member or intersects the locating member but does not intersect the first semiconductor wafer. Likewise, the second semiconductor wafer is aligned with the recess of the heat sink.

The term "close" means that the width of the gap between the elements does not exceed the maximum acceptable range. As is known in the art, when the gap between the first semiconductor wafer and the locating member is not sufficiently narrow, the positional error due to lateral displacement of the first semiconductor wafer in the gap may exceed the acceptable maximum error limit. In some cases, once the position error of the first semiconductor wafer exceeds the maximum limit, it is impossible to align the predetermined position of the first semiconductor wafer with the laser beam, thereby causing electrical connection between the first semiconductor wafer and the routing circuit. failure. According to the size of the contact pads of the first semiconductor wafer, those skilled in the art can confirm the maximum acceptable range of the gap between the first semiconductor wafer and the positioning member through trial and error to ensure the metallization blind holes of the routing circuit and The I/O pads of the first semiconductor wafer are aligned. Thus, the term "the positioning member is adjacent to the peripheral edge of the first semiconductor wafer" means that the gap between the peripheral edge of the first semiconductor wafer and the positioning member is narrow enough to prevent the positional error of the first semiconductor wafer from exceeding the acceptable maximum error. limit. For example, the gap between the first semiconductor wafer and the locating member can be in the range of about 5 microns to 50 microns.

The terms "electrical connection" and "electrical coupling" mean direct or indirect electrical connection. For example, in the case where the terminal is provided in the sealing material, the terminal is in direct contact and electrically connected to the first routing circuit, and the second semiconductor wafer is kept at a distance from the first routing circuit and electrically connected by the first bump. Connect to the first routing circuit.

The "first direction" and "second direction" do not depend on the orientation of the semiconductor body. Anyone familiar with the art can easily understand the direction in which they actually refer. For example, the first surface of the sealing material faces in a first direction and the second surface of the sealing material faces in a second direction, regardless of whether the semiconductor body is inverted. Therefore, the first and second directions are opposite to each other and perpendicular to the side direction. Furthermore, in the state where the pocket is facing downward, the first direction is the upward direction, and the second direction is the downward direction; in the state where the pocket is upward, the first direction is the downward direction, and the second direction is the downward direction. Up direction.

The semiconductor package of the present invention has a number of advantages. For example, placing the first and second semiconductor wafers on opposite sides of the first routing circuit provides the shortest interconnection distance between the first semiconductor wafer and the second semiconductor wafer. The first routing circuit can provide a first stage of fanout routing/interconnection to the first and second semiconductor wafers, and the terminals can provide electrical contacts for external connections or routing of the next level of routing circuitry. Since the second semiconductor wafer and the heat sink are electrically coupled to the first routing circuit by bumps, instead of being electrically coupled to the first routing circuit directly by the build-up process, the simplified process steps can be reduced. cost. The external routing circuit can provide pads that are densely distributed outside the entire area to add external electrical contacts for the next level of assembly. The heat sink can provide heat dissipation, electromagnetic shielding, and moisture barrier of the second semiconductor wafer, and provide mechanical support for the assembly. The semiconductor group system prepared by this method is high in reliability, low in cost, and is very suitable for mass production and production.

The manufacturing method of the present invention has high applicability, and combines various mature electrical and mechanical connection technologies in a unique and progressive manner. Furthermore, the manufacturing method of the present invention can be carried out without expensive tools. Therefore, compared to the traditional technology, this production method can greatly increase the yield, yield, efficiency and cost-effectiveness.

The embodiments described herein are illustrative, and the elements or steps that are well known in the art may be simplified or omitted in order to avoid obscuring the features of the present invention. Similarly, in order to make the drawings clear, the drawings may also omit redundant or non-essential components and component symbols.

110, 120, 130, 210, 220, 230, 310, 410, 420, 430, 510 ‧ ‧ semiconductor group
10‧‧‧ sacrificial carrier
111‧‧‧Support plate
113‧‧‧Barrier layer
20‧‧‧buried device
21‧‧‧First routing circuit
211‧‧‧Primary wire
212‧‧‧Route line
213‧‧‧First contact pad
214‧‧‧Second contact pad
215‧‧‧ dielectric layer
216, 256, 393‧‧ ‧ blind holes
217‧‧‧First wire
218, 365‧‧‧metallized blind holes
22‧‧‧First semiconductor wafer
222‧‧‧Bumps
223‧‧‧Electrical bumps
23, 31‧‧‧ Heat sink 24, 38‧‧‧ terminals
241‧‧‧ solder balls
243‧‧‧Metal column
244, 385‧‧‧ conductive blind holes
246, 383‧‧‧ solder balls
25‧‧‧ Sealing material
251‧‧‧ first surface
253‧‧‧ second surface
254, 342, 391‧‧ holes
26, 51‧‧‧ External routing circuit
262, 515‧‧‧ external conductor
28‧‧‧ Positioning parts
29‧‧‧welding line
30‧‧‧heating gain type device
305‧‧‧ recess
321‧‧‧Shield cover
323, 324‧‧ ‧ stud
325‧‧‧ protruding seat
33‧‧‧Second routing circuit
331, 395‧‧‧through openings
341‧‧‧ Bonding film
351‧‧‧ routing substrate
352‧‧‧Perforation
353‧‧‧Insulation
354‧‧‧second wire
355‧‧‧ Third wire
356‧‧‧Metalized perforation
36‧‧‧Second semiconductor wafer
364‧‧‧fourth wire
367‧‧‧First terminal pad
368‧‧‧Second terminal pad
37‧‧‧ Thermal contact parts
381‧‧‧Metal pins
39‧‧‧ Strengthening layer
41‧‧‧First bump
42‧‧‧ underfill
43‧‧‧second bump
45‧‧‧ third bump
47‧‧‧fourth bump
48‧‧‧Resin
L‧‧‧ cutting line

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a routing line formed on a sacrificial carrier in a first embodiment of the present invention, with reference to the accompanying drawings; FIG. 2 is a cross-sectional view showing a dielectric layer and a blind via hole in the structure of FIG. 1 according to the first embodiment of the present invention; FIG. 3 is a cross-sectional view showing the first conductor formed on the structure of FIG. 2 in the first embodiment of the present invention; In the first embodiment of the present invention, FIG. 3 is a cross-sectional view of the structure of the first semiconductor wafer; FIG. 5 is a cross-sectional view of the solder ball in the structure of FIG. 4 according to the first embodiment of the present invention; In the first embodiment of the present invention, a cross-sectional view of the sealing material is formed on the structure of FIG. 5; FIG. 7 is a cross-sectional view showing the opening of the structure of FIG. 6 in the first embodiment of the present invention; FIGS. 8 and 9 are respectively the first embodiment of the present invention. In the embodiment, the cross-sectional view and the top perspective view of the sacrificial carrier are removed from the structure of FIG. 7; FIGS. 10 and 11 are respectively a cross-sectional view of the protrusion and the protrusion from the shielding cover in the first embodiment of the present invention; Bottom perspective view; Figure 12 is a first embodiment of the present invention FIG. 10 is a cross-sectional view showing the structure of the bonding film and the routing substrate in FIG. 10; FIG. 13 is a cross-sectional view showing the structure of FIG. 12 after the layering process in the first embodiment of the present invention; FIGS. 14 and 15 are respectively the first embodiment of the present invention. In the sample, the structure of FIG. 13 forms a recess to complete the cross-sectional view of the heat sink and the bottom perspective view. FIG. 16 is a cross-sectional view showing the second semiconductor wafer having the first bump on the structure of FIG. 14 according to the first embodiment of the present invention. Figure 17 is a cross-sectional view showing the second bump and the third bump in the structure of Figure 16 in the first embodiment of the present invention; Figure 18 is a cross-sectional view of the structure of Figure 17 in the first embodiment of the present invention; FIG. 19 is a cross-sectional view showing the structure of FIG. 17 electrically coupled to the structure of FIG. 8 in the first embodiment of the present invention; FIG. 20 is a first embodiment of the present invention, and FIG. FIG. 21 is a cross-sectional view showing another semiconductor package in a first embodiment of the present invention; FIG. 22 is a view showing another semiconductor package in the first embodiment of the present invention; Sectional view; Figure 23 is the hair In the second embodiment, a cross-sectional view of the sealing material is formed on the structure of Fig. 4; Fig. 24 is a cross-sectional view showing the blind hole formed in the structure of Fig. 23 in the second embodiment of the present invention; and Fig. 25 is a second embodiment of the present invention. Figure 24 is a cross-sectional view showing the conductive blind hole and the external wire in the structure of Figure 24; Figures 26 and 27 are respectively a cross-sectional view and a top perspective view of the sacrificial carrier plate removed from the structure of Figure 25 in the second embodiment of the present invention; Figures 28 and 29 2 is a cross-sectional view and a top perspective view of the second semiconductor wafer in the second embodiment of the present invention; FIG. 30 is a second embodiment of the present invention, and the heat sink is stacked on the second embodiment of the present invention. 28 is a cross-sectional view of the semiconductor assembly; FIG. 31 is a cross-sectional view of the heat dissipation mount of FIG. 14 electrically coupled to the structure of FIG. 28 to fabricate a semiconductor package; FIG. 32 is a second embodiment of the present invention; FIG. 33 is a cross-sectional view showing another semiconductor package according to a second embodiment of the present invention; and FIGS. 34 and 35 are respectively a heat sink in the third embodiment of the present invention. Section forming the positioning member FIG. 36 and FIG. 37 are respectively a cross-sectional view and a top perspective view of the first semiconductor wafer in the structure of FIGS. 34 and 35 in the third embodiment of the present invention; FIG. 38 is a third embodiment of the present invention; Figure 36 is a cross-sectional view showing the structure of the sealing material in the structure of Figure 36; Figure 39 is a cross-sectional view showing the top region of the sealing material removed from the structure of Figure 38 in the third embodiment of the present invention; Figures 40 and 41 are respectively a third embodiment of the present invention. FIG. 39 is a cross-sectional view showing a primary conductor and a top bottom perspective view. FIG. 42 is a cross-sectional view showing a dielectric layer and a blind via formed on the structure of FIG. 40 in the third embodiment of the present invention; FIGS. 43 and 44 are respectively In the third embodiment of the present invention, a cross-sectional view and a top perspective view of the first wire are formed on the structure of FIG. 42. FIGS. 45 and 46 are respectively a second embodiment of the present invention, and the second semiconductor wafer is connected to the structure of FIGS. 43 and 44, respectively. FIG. 47 is a cross-sectional view showing a dielectric layer and a blind via formed on the structure of FIG. 39 in the third embodiment of the present invention; FIG. 48 is a view showing the structure of FIG. 47 in the third embodiment of the present invention; First Figure 49 is a cross-sectional view of the second semiconductor wafer of Figure 48 in a third embodiment of the present invention; Figure 50 is a third embodiment of the present invention, the panel size structure of Figure 49 is cut Figure 51 is a cross-sectional view showing a structure of a heat-dissipating block in a third embodiment of the present invention; Figure 52 and Figure 53 are respectively a perspective view of the heat-dissipating block and a bottom perspective view of the third embodiment of the present invention; 54 is a cross-sectional view of the heat sink of FIG. 52 stacked on the structure of FIG. 51 in the third embodiment of the present invention; FIG. 55 is a third embodiment of the present invention, the heat sink of FIG. 52 is electrically coupled to the structure of FIG. FIG. 56 is a cross-sectional view showing a first routing circuit formed on a sacrificial carrier board in a fourth embodiment of the present invention; FIG. 57 is a fourth embodiment of the present invention, and FIG. FIG. 58 is a cross-sectional view showing the sealing material formed on the structure of FIG. 57 in the fourth embodiment of the present invention; FIG. 59 is a view showing the structure of FIG. Section of the bottom of the material Figure 60 is a cross-sectional view showing the structure of the heat sink of Figure 59 in the fourth embodiment of the present invention; Figures 61 and 62 respectively illustrate the removal of the sacrificial carrier from the structure of Figure 60 in the fourth embodiment of the present invention. FIG. 63 and FIG. 64 are respectively a cross-sectional view and a top perspective view of the second semiconductor wafer in the structure of FIGS. 61 and 62 in the fourth embodiment of the present invention; FIG. 65 is a fourth embodiment of the present invention; A cross-sectional view of a structure having a shield cover, a stud, a bonding film, and a routing substrate. FIG. 66 is a fourth embodiment of the present invention, wherein the second bump, the third bump, and the fourth bump are attached to the structure of FIG. And a metal pin to make a cross-sectional view of the heat sink; FIG. 67 is a cross-sectional view of another heat sink in the fourth embodiment of the present invention; FIG. 68 is a heat sink in the fourth embodiment of the present invention. Figure 69 is a cross-sectional view showing another heat dissipation seat in the fourth embodiment of the present invention; Figure 70 is a fourth embodiment of the present invention, the heat sink of Figure 66 is stacked on the structure of Figure 63. Figure 71 is a fourth embodiment of the present invention, 66 is a cross-sectional view of the semiconductor package in a fourth embodiment of the present invention; FIG. 73 is a fourth embodiment of the present invention; FIG. 74 is a cross-sectional view of the heat dissipation gain type device electrically coupled to the embedding device in the fifth embodiment of the present invention; FIG. 75 is a fifth embodiment of the present invention. Figure 76 is a cross-sectional view showing the structure of the reinforcing layer in the structure of Figure 74; Figure 76 is a cross-sectional view showing the bottom portion of the sealing material removed from the structure of Figure 75 in the fifth embodiment of the present invention; Figure 76 is structurally formed with external leads to make a cross-sectional view of the completed semiconductor package.

110‧‧‧Semiconductor group

21‧‧‧First routing circuit

22‧‧‧First semiconductor wafer

241‧‧‧ solder balls

254‧‧‧ openings

31‧‧‧ Heat sink

323‧‧‧Bump

341‧‧‧ Bonding film

36‧‧‧Second semiconductor wafer

43‧‧‧second bump

48‧‧‧Resin

20‧‧‧buried device

212‧‧‧Route line

24‧‧‧terminal

25‧‧‧ Sealing material

30‧‧‧heating gain type device

321‧‧‧Shield cover

33‧‧‧Second routing circuit

351‧‧‧ routing substrate

41‧‧‧First bump

45‧‧‧ third bump

Claims (18)

A semiconductor package having electromagnetic shielding and heat dissipation characteristics, comprising: a buried device comprising a first semiconductor wafer, a sealing material and a first routing circuit, the first routing circuit being disposed on one of the sealing materials a first surface, wherein the first semiconductor wafer is embedded in the sealing material and electrically coupled to the first routing circuit; a heat dissipation gain type device comprising a heat sink and a second semiconductor wafer, the heat dissipation The base has a shielding cover, a protruding post and a second routing circuit, and the second routing circuit is disposed on a surface of the shielding cover, wherein (i) the second routing circuit has a through opening, and the second semiconductor a wafer is disposed in the through opening and attached to the shielding cover, and (ii) the protrusions protrude from the surface of the shielding cover and are laterally surrounded by the second routing circuit; and the heat dissipation type The device is stacked on the embedding device, and the second semiconductor chip is electrically coupled to the first routing circuit by a series of first bumps The second routing circuit is electrically coupled to the first routing circuit by a series of second bumps. The semiconductor package of claim 1, wherein the bumps of the heat sink are electrically connected to the second routing circuit. The semiconductor package of claim 1, further comprising: a series of third bumps disposed on the studs to provide electrical and thermal connection between the shield cover and the embedding device . The semiconductor package of claim 1, wherein the second routing circuit comprises at least one wire extending laterally beyond a peripheral edge of the embedding device. The semiconductor package of claim 4, further comprising: a series of terminals electrically coupled to the second routing circuit and the shielding cover and surrounding the embedding device. The semiconductor package of claim 5, further comprising: a reinforcing layer covering the sidewalls of the terminals. The semiconductor package of claim 5, further comprising: a series of fourth bumps disposed on the studs to provide electrical connection between the shield cover and the terminals. The semiconductor package of claim 6, further comprising: an external routing circuit disposed on an outer surface of the reinforcing layer, wherein the external routing circuit is electrically coupled to the terminals. The semiconductor package of claim 1, wherein the embedding device further comprises a series of terminals located in the sealing material, surrounding the first semiconductor wafer, and electrically coupled to the first And a shielding circuit and the shielding cover extending toward an opposite second surface of the sealing material. The semiconductor package of claim 9, wherein the terminals of the sealing material are electrically connected to the protruding posts and the shielding cover by the first routing circuit of the embedding device. The semiconductor package of claim 9, wherein the embedding device further comprises an external routing circuit disposed on the second surface of the sealing material and electrically coupled to the sealing material The terminals. A semiconductor assembly manufacturing method having electromagnetic shielding and heat dissipation characteristics, comprising: providing a buried device comprising a first semiconductor wafer, a sealing material and a first routing circuit, wherein the first routing circuit is disposed on the sealing a first surface of the material, wherein the first semiconductor wafer is embedded in the sealing material and electrically coupled to the first routing circuit; and a second semiconductor wafer is electrically connected by a series of first bumps The first routing circuit is coupled to the embedding device; a heat sink is provided, and includes a shielding cover, a protruding post and a second routing circuit, wherein the second routing circuit has a through opening and is disposed on the shielding a surface of one of the covers protruding from the surface of the shielding cover and laterally surrounded by the second routing circuit; and the heat sink is stacked on the embedding device, and by a a second bump of the series, electrically coupling the second routing circuit of the heat sink to the embedded device A routing circuit, while the second semiconductor wafer is disposed in the through opening in the second routing circuits, and the second semiconductor wafer is attached to the shield cover. The manufacturing method of claim 12, further comprising: providing a series of third bumps on the protrusions to electrically couple the shielding cover and the embedding device. The manufacturing method of claim 12, further comprising: forming a series of terminals electrically coupled to the second routing circuit and the shielding cover and surrounding the embedding device. The manufacturing method of claim 14, further comprising: forming a reinforcing layer covering the sidewalls of the terminals. The manufacturing method of claim 15, further comprising: forming an external routing circuit on an outer surface of the reinforcing layer, wherein the external routing circuit is electrically coupled to the terminals in the reinforcing layer. The manufacturing method of claim 12, wherein the embedding device further comprises a series of terminals located in the sealing material and surrounding the first semiconductor wafer and electrically coupled to the first route Circuit and the shielding cover. The manufacturing method of claim 17, wherein the embedding device further comprises an external routing circuit disposed on the opposite second surface of the sealing material and electrically coupled to the sealing material The terminals.