TWI626865B - Wiring board with dual stiffeners and dual routing circuitries integrated together and method of making the same - Google Patents

Abstract

The circuit board having the double reinforcing layer and the integrated dual routing circuit is characterized in that first and second routing circuits are respectively disposed in the through opening of the first reinforcing layer and outside the through opening, and the second routing circuit is provided with the second The reinforcing layer laterally surrounds one of the series of vertical connecting channels. The mechanical strength of the first and second reinforcing layers can be used to avoid bending of the wiring board. The vertical connection channel provides an electrical contact for the next level of connection. The first routing circuit located in the first reinforcement layer through the opening can provide a primary fanout route, and the second routing circuit located outside the first reinforcement layer through the opening can provide not only a further fanout route to the first routing circuit, but also The first routing circuit can be mechanically coupled to the first reinforcement layer.

Description

Circuit board with double reinforcement layer and integrated dual routing circuit and its preparation method

The present invention relates to a circuit board, and more particularly to a circuit board having a double reinforcing layer and integrating a dual routing circuit into one body and a manufacturing method thereof.

Market trends in electronic devices, such as multimedia devices, tend to be more rapid and thinner in design requirements. One such method is to interconnect the semiconductor wafer through a coreless substrate to make the assembly thinner and improve signal integrity. U.S. Patent Nos. 7,851,269, 7,902,660, 7,981,728 and 8,227,703 disclose various non-core layer substrates for this purpose. However, although these boards can reduce inductance, they cannot solve other characteristics because they do not have sufficient fan-out routing capability to meet the high requirements of ultra-dense pitch flip-chips. Problems (such as design flexibility).

For the above reasons and other reasons described below, there is an urgent need to develop a new type of circuit board to address routing requirements while ensuring that bending is less likely to occur during assembly and operation.

SUMMARY OF THE INVENTION A primary object of the present invention is to provide a circuit board that integrates the first and second routing circuits to provide a high degree of routing flexibility while achieving excellent signal integrity. For example, the first routing circuit can be constructed as a primary fanout circuit with a very high routing density, while the second routing circuit is constructed to form a further fanout route with a coarse width/pitch. The integrated routing circuit allows the board to have the shortest possible interconnect length, which reduces inductance and improves the electrical performance of the package.

Another object of the present invention is to provide a circuit board which can use the first and second reinforcing layers to provide mechanical support force on opposite sides of the integrated routing circuit, and the second reinforcing layer is embedded therein The channels are connected vertically, thereby avoiding the bending of the board, thereby improving the mechanical reliability of the board, while the vertical connecting channels provide electrical contacts for connecting the next level of routing circuits or board assembling.

A further object of the present invention is to provide a circuit board having a first routing circuit located in the first reinforcement layer through opening and a second routing circuit located outside the first reinforcement layer through the opening, thereby improving the production of the circuit board. rate.

According to the above and other objects, the present invention provides a circuit board including a first reinforcement layer, a first routing circuit, a second routing circuit, a second reinforcement layer, and a series of vertical connection channels. In a preferred embodiment, the first reinforcement layer and the second reinforcement layer are located on opposite sides of the integrated dual routing circuit, and can provide a high modulus bending platform to the circuit board; the first routing circuit is located a first reinforcement layer is provided in the through opening, and provides a primary fan-out route to the semiconductor component subsequently assembled thereon, whereby the pad size and pitch of the semiconductor component can be enlarged before the subsequent formation of the second routing circuit; The second routing circuit extends laterally on the first reinforcement layer and is electrically connected to the first routing circuit, and the second routing circuit can mechanically bond the first routing circuit to the first reinforcement layer while providing the semiconductor component Two-stage fan-out routing, and the pad spacing and pad size of the second routing circuit are greater than the pad spacing and pad size of the first routing circuit; the vertical connection channel is buried in the second reinforcement layer and located at the edge of the second routing circuit The area and the vertical connection channel are electrically connected to the second routing circuit to provide electrical contacts for the next group of groups.

In another aspect, the present invention provides a circuit board comprising: a first reinforcement layer having a through opening, wherein the through opening has an inner sidewall surface extending through one of the first reinforcement layers; a routing circuit having a first surface and a second surface opposite thereto, wherein the first routing circuit is located in the through opening and adjacent to the inner sidewall surface of the first reinforcement layer; a second routing circuit, The first routing circuit is disposed on the second surface of the first routing circuit and extends laterally on a surface of the first reinforcement layer. The second routing circuit is electrically coupled to the first via a metallized blind hole. a routing circuit, the second routing circuit having a third surface facing away from the second surface; a second reinforcement layer disposed on the third surface of the second routing circuit; and a series of vertical connection channels And being laterally surrounded by the second reinforcing layer, wherein the vertical connecting channels are electrically connected to the second routing circuit and are exposed by an outer surface of one of the second reinforcing layers.

In still another aspect, the present invention provides a method of fabricating a circuit board, comprising the steps of: forming a first routing circuit on a removable sacrificial carrier, wherein the first routing circuit has a proximity to the sacrificial load a first surface of the plate and a second surface opposite; a first reinforcement layer having a through opening, wherein the through opening has an inner sidewall surface extending through the first reinforcement layer; a routing circuit and the sacrificial carrier are inserted into the through opening of the first reinforcement layer, and the first routing circuit and the sacrificial carrier are adjacent to the inner sidewall surface of the first reinforcement layer; forming a second routing circuit The second routing circuit is electrically coupled to the first routing circuit and has a back side a third surface of the second surface; forming a series of vertical connecting channels on the third surface of the second routing circuit, wherein the vertical connecting channels are electrically coupled to the second routing circuit; forming a second strengthen And on the third surface of the second routing circuit; and removing the sacrificial carrier to expose the first surface of the first routing circuit; wherein the vertical routing channels are laterally surrounded by the second reinforcement layer And exposed by the outer surface of one of the second reinforcement layers.

The order of the above steps is not limited to the above, and may be varied or rearranged depending on the desired design, unless specifically stated or steps that must occur in sequence.

The circuit board manufacturing method of the present invention has many advantages. For example, it is particularly advantageous to insert the sacrificial carrier board and the first routing circuit into the first reinforcement layer through opening before forming the second routing circuit, because the sacrificial carrier and the first reinforcement layer are A stable platform is provided together for the formation of the second routing circuit, and the problem that the micro-blind hole is not connected to the contact pad occurs when the second routing circuit is subsequently formed. In addition, forming a second reinforcement layer on the second routing circuit ensures optimum strength of the circuit board, whereby the dual reinforcement layer on the opposite sides of the integrated dual routing circuit provides mechanical strength and prevents the board from moving. The bending problem occurs after the sacrificial carrier is sacrificed. In addition, when a multilayer routing circuit is to be formed, a severe bending problem can be avoided by a two-stage process to form an interconnect substrate.

The above and other features and advantages of the present invention will become more apparent from the detailed description of the preferred embodiments.

In the following, an embodiment will be provided to explain in detail embodiments of the invention. The advantages and effects of the present invention will be more apparent by the disclosure of the present invention. The drawings attached hereto are simplified and are used for illustration. The number, shape and size of the components shown in the drawings can be modified as the case may be, and the configuration of the components may be more complicated. Other variations and modifications can be made without departing from the spirit and scope of the invention as defined in the invention.

[Example 1]

1-18 are diagrams showing a method of fabricating a circuit board according to a first embodiment of the present invention, including a first reinforcement layer, a first routing circuit, a second routing circuit, a series of vertical connection paths, and a first Two reinforcement layers.

1 and 2 are a cross-sectional view and a top perspective view, respectively, of a routing line 135 formed on a sacrificial carrier 110, wherein the routing line 135 is formed by a metal deposition and metal patterning process. In this figure, the sacrificial carrier 110 is a single layer structure, and the routing line 135 includes a bonding pad 138 and a bonding pad 139. The sacrificial carrier 110 is typically made of copper, aluminum, iron, nickel, tin, stainless steel, tantalum or other metal or alloy, but may be made of any other electrically conductive or non-conductive material. The thickness of the sacrificial carrier 110 is preferably in the range of 0.1 to 2.0 mm. In this embodiment, the sacrificial carrier 110 is made of a ferrous material and has a thickness of 1.0 mm. The routing line 135 is typically made of copper and can be patterned by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof, or formed by thin film deposition followed by a metal patterning step. In the case of a sacrificial carrier 110 having conductivity, it is typically deposited by metal plating to form routing lines 135. Metal patterning techniques include wet etching, electrochemical etching, laser assisted etching, and combinations thereof, and an etch mask (not shown) is used to define routing lines 135.

3 is a cross-sectional view of the first dielectric layer 141 and the first blind via 143, wherein the first dielectric layer 141 is on the sacrificial carrier 110 and the routing line 135, and the first blind via 143 is on the first dielectric layer 141. in. The first dielectric layer 141 can be deposited by lamination or coating, and contacts the sacrificial carrier 110 and the routing line 135, and the first dielectric layer 141 is covered by the upper side and extends laterally to the sacrificial carrier. 110 and routing line 135. The first dielectric layer 141 typically has a thickness of 50 microns and may be made of epoxy, glass epoxy, polyimine, or the like. After deposition of the first dielectric layer 141, a first blind via 143 can be formed by various techniques including laser drilling, plasma etching, and lithography, and typically has a diameter of 50 microns. Pulsed lasers can be used to improve laser drilling performance. Alternatively, a scanning laser beam can be used with a metal reticle. The first blind via 143 extends through the first dielectric layer 141 and is aligned with selected portions of the routing line 135.

Referring to FIG. 4, a first conductive line 145 is formed on the first dielectric layer 141 by a metal deposition and metal patterning process. The first wire 145 extends upward from the routing line 135 and fills the first blind via 143 to form a first metallization blind via 147 that directly contacts the routing line 135 while extending laterally over the first dielectric layer 141. Thus, the first wire 145 can provide horizontal signal routing in the X and Y directions and a vertical route through the first blind hole 143 to serve as an electrical connection to the routing line 135.

The first wire 145 can be deposited as a single layer or multiple layers by various techniques such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof. For example, first, by immersing the structure in an activator solution, the first dielectric layer 141 is reacted with electroless copper to generate a catalyst, and then a thin copper layer is coated as a seed layer by electroless plating, and then electroplated. A second copper layer of a desired thickness is formed on the seed layer. Alternatively, the seed layer may be formed by a sputtering method such as a titanium/copper seed layer film before the electroplated copper layer is deposited on the seed layer. Once the desired thickness is achieved, the coating can be patterned using various techniques to form a first wire 145 that includes wet etching, electrochemical etching, laser assisted etching, and combinations thereof, and using an etch mask (not shown) ) to define the first wire 145.

5 is a cross-sectional view of the second dielectric layer 151 and the second via 153, wherein the second dielectric layer 151 is located on the first dielectric layer 141 and the first conductive line 145, and the second blind via 153 is in the second In the electrical layer 151. The second dielectric layer 151 can be deposited by lamination or coating, and contacts the first dielectric layer 141 and the first conductive line 145, and is covered by the upper surface and laterally extended to the first dielectric layer 141. On the first wire 145. The second dielectric layer 151 typically has a thickness of 50 microns and may be made of epoxy, glass epoxy, polyimine, or the like. After depositing the second dielectric layer 151, a second blind via 153 extending through the second dielectric layer 151 is formed to expose selected portions of the first conductive trace 145. As described for the first blind via 143, the second blind via 153 can also be formed by a variety of techniques including laser drilling, plasma etching, and lithography, and typically has a diameter of 50 microns.

6 and 7 are respectively a cross-sectional view and a top perspective view showing the formation of the second wire 155, wherein the second wire 155 is formed on the second dielectric layer 151 by a metal deposition and metal patterning process. The second wire 155 extends upward from the first wire 145 and fills the second blind hole 153 to form a second metallization blind hole 157 directly contacting the first wire 145 while extending laterally on the second dielectric layer 151. . As shown in FIG. 7, the second wire 155 includes a patterned array of contact pads 158 with a distance between the contact pads 158 that is greater than the spacing between the bond pads 138.

This stage has been completed by the process of forming the first routing circuit 120 on the sacrificial carrier 110. In the figure, the first routing circuit 120 includes a routing line 135, a first dielectric layer 141, a first conductive line 145, a second dielectric layer 151, and a second conductive line 155.

8 and 9 are respectively a cross-sectional view and a top perspective view of the panel-scale structure of Figs. 6 and 7 cut into individual pieces. This panel size structure (with the first routing circuit 120 on the sacrificial carrier 110) is separated into individual sub-groups 10 along the cutting line "L".

10 is a cross-sectional view of an individual sub-assembly 10 in which the sub-assembly 10 includes a sacrificial carrier 110 and a first routing circuit 120. In the figure, the first routing circuit 120 is a layered routing circuit and has a first surface 101 adjacent to the sacrificial carrier 110, a second surface 103 opposite to the first surface 101, and a first surface 101. Bond pads 138 and bond pads 139, and contact pads 158 on second surface 103. The bond pads 138 are aligned with the wafer I/O pads, while the outermost wires facing away from the sacrificial carrier 110 have contact pads 158 that are spaced apart from the pads 138. Accordingly, the first routing circuit 120 has a fan-out conductor pattern that is fanned out by the fine pitch of the bond pads 138 to a relatively coarse pitch of the contact pads 158, which provides a first stage fan-out routing/interconnect pre-connection. A semiconductor component placed thereon. The stacking pad 139 selectively included in the first routing circuit 120 can provide an electrical contact to another semiconductor component.

FIG. 11 is a cross-sectional view showing the 10th sub-body 10 and the first reinforcement layer 20 disposed on the third dielectric layer 441/metal layer 44. The thickness of the first reinforcement layer 20 is preferably substantially the same as the thickness of the sub-assembly 10. The first reinforcement layer 20 may be made of a ceramic, metal, resin, metal composite, or single layer or multilayer circuit structure having sufficient mechanical strength and has a through opening 205. The through opening 205 has an inner side wall surface 209 extending through the first reinforcing layer 20, and the through opening 205 preferably has a size substantially the same as or slightly larger than the sub-assembly 10. In this figure, the through opening 205 is slightly larger in size than the sub-assembly 10 and may be formed by laser cutting, punching, or mechanical drilling. The sub-assembly 10 is located in the through opening 205 of the first reinforcement layer 20. The third dielectric layer 441 is sandwiched between the sub-assembly 10 and the metal layer 44 and between the first reinforcement layer 20 and the metal layer 44, and the third dielectric layer 441 contacts the second conductor 155 of the sub-group 10. And the first reinforcement layer 20. The third dielectric layer 441 may be made of epoxy resin, glass epoxy resin, polyimide, or the like, and usually has a thickness of 50 μm. Metal layer 44 is typically a copper layer having a thickness of 25 microns. The surface of the second wire 155 is substantially coplanar with the surface of the first reinforcement layer 20 in the downward direction, and the gap 207 between the secondary assembly 10 and the first reinforcement layer 20 is located in the through opening 205. The first reinforcement layer 20 laterally surrounds the gap 207, and the gap 207 laterally surrounds the sacrificial carrier 110 and the first routing circuit 120.

FIG. 12 is a cross-sectional view of the third dielectric layer 441 entering the gap 207. The third dielectric layer 441 flows into the gap 207 under application of heat and pressure. The heated third dielectric layer 441 can be arbitrarily shaped under pressure. Therefore, after the third dielectric layer 441 sandwiched between the sub-assembly 10 and the metal layer 44 and between the first reinforcement layer 20 and the metal layer 44 is pressed, the original shape is changed and flows upward into the gap 207, thereby being isomorphous. The inner sidewall surface 209 of the through opening 205 and the peripheral edge of the sacrificial carrier 110 and the first routing circuit 120 are covered. The cured third dielectric layer 441 can provide a strong mechanical bond between the sub-assembly 10 and the first reinforcement layer 20, between the sub-assembly 10 and the metal layer 44, and between the first reinforcement layer 20 and the metal layer 44. The sub-assembly 10 is fixed in the through opening 205 of the first reinforcement layer 20.

FIG. 13 is a cross-sectional view showing the formation of the third blind via 443 which exposes the contact pads 158 of the second lead 155. Here, the third blind via 443 extends through the metal layer 44 and the third dielectric layer 441 and is aligned with the contact pads 158 of the second conductor 155. As described for the first and second blind vias 143, 153, the third blind via 443 can also be formed by a variety of techniques including laser drilling, plasma etching, and lithography, and typically has a diameter of 50 microns.

Referring to FIG. 14, a third wire 445 is formed on the third dielectric layer 441, wherein a coating layer 44' is deposited on the metal layer 44 and in the third blind via 443, and then on the metal layer 44 and thereon. The cover layer 44' is patterned to form a third wire 445. The third wire 445 extends downward from the contact pad 158 and fills the third blind hole 443 to form a third metallization blind hole 447 that directly contacts the contact pad 158 while extending laterally on the third dielectric layer 441. .

For convenience of illustration, the metal layer 44 and the coating layer 44' are represented by a single layer. Since copper is a homogeneous coating, the boundaries between the metal layers (indicated by dashed lines) may be less noticeable or even undetectable.

At this stage, the process of forming the second routing circuit 420 on the sub-assembly 10 and the first reinforcement layer 20 is completed. The second routing circuit 420 extends laterally beyond the peripheral edge of the first routing circuit 120 and extends over one surface of the first reinforcement layer 20 and has a third surface 403 that faces away from the second surface 103 of the first routing circuit 120. In the figure, the second routing circuit 420 includes a third dielectric layer 441 and a third conductive line 445, and substantially has a combined surface area of the first routing circuit 120 and the first reinforcement layer 20.

15 is a cross-sectional view showing the formation of the array vertical connection channel 51 on the third surface 403 of the second routing circuit 420. In the figure, the vertical connecting channels 51 are shown as solder balls 511 and are in contact with the third wires 445 of the second routing circuit 420.

16 is a cross-sectional view showing the formation of the second reinforcement layer 53 on the third surface 403 of the second routing circuit 420. The second reinforcing layer 53 is usually formed by a printing or molding process of the resin sealing material to cover a selected portion of the vertical connecting passage 51 and the second routing circuit 420 from below, and is surrounded and conformed in the lateral direction. The cover is covered and covers the vertical connection channel 51.

17 is a cross-sectional view showing the opening 533 formed in the second reinforcing layer 53. The openings 533 are aligned with the vertical connecting passages 51 to expose the vertical connecting passages 51 from below.

18 is a cross-sectional view of the sacrificial carrier 110 after removal. The sacrificial carrier 110 can be removed by various means, including wet etching using an acidic solution (such as ferric chloride, copper sulfate solution) or an alkaline solution (such as ammonia solution), electrochemical etching, or mechanical means (such as drilling). Hole or end milling) followed by chemical etching. In this embodiment, the sacrificial carrier 110 made of a ferrous material can be removed by a chemical etching solution, wherein the chemical etching solution is selective between copper and iron to avoid removal of the sacrificial carrier 110. The copper routing line 135 is etched.

Accordingly, as shown in FIG. 18, the completed circuit board 100 includes a first reinforcement layer 20, a first routing circuit 120, a second routing circuit 420, a vertical connection channel 51, and a second reinforcement layer 53, wherein Both the first routing circuit 120 and the second routing circuit 420 are layered routing circuits that do not have a core layer.

The first routing circuit 120 is located in the through opening 205 of the first reinforcement layer 20 and adjacent to the inner sidewall surface 209 of the first reinforcement layer 20 while the first surface 101 of the first routing circuit 120 is from the first reinforcement layer 20 The through opening 205 is revealed. The second routing circuit 420 is located outside the through opening 205 of the first reinforcement layer 20 and on the second surface 103 of the first routing circuit 120 while extending laterally to the peripheral edge of the circuit board 100. Therefore, the surface area of the first surface 101 of the first routing circuit 120 is smaller than the surface area of the second routing circuit 420 (ie, the area of the lower surface of the third dielectric layer 441). The first routing circuit 120 is a multi-layer routing circuit and includes a fan-out wire pattern that is fanned out by a finer pitch at the first surface 101 to a coarser pitch at the second surface 103.

The second routing circuit 420 is electrically coupled to the contact pad 158 of the first routing circuit 120 by the third metallization via 447 of the second routing circuit 420, wherein the second routing circuit 420 includes a third wire 445, and The third wire 445 extends into a region outside the first reinforcement layer 20 through the opening 205 and extends laterally above the surface of the first reinforcement layer 20. Thereby, the second routing circuit 420 can not only provide the first routing circuit 120 with a further fan-out line structure, but also mechanically engage the first routing circuit 120 with the first reinforcement layer 20.

The first reinforcement layer 20 surrounds the peripheral edge of the first routing circuit 120 and extends laterally to the peripheral edge of the circuit board 100 to provide mechanical support and to avoid bending of the circuit board 100. The first reinforcement layer 20 also extends upward beyond the first surface 101 of the first routing circuit 120 to form a recess 206 in the through opening 205 of the first reinforcement layer 20.

The vertical connecting channel 51 is disposed in an edge region of the third surface 403 of the second routing circuit 420 and is buried in the second reinforcing layer 53 and exposed by the opening 533 of the second reinforcing layer 53. Therefore, the vertical connection channels 51 can provide electrical contacts for the next stage of connection.

The second reinforcing layer 53 is disposed on the third surface 403 of the second routing circuit 420 and has a through opening 505 , wherein the through opening 505 is centrally aligned with the through opening 205 of the first reinforcing layer 20 . Therefore, the first reinforcing layer 20 and the second reinforcing layer 53 at opposite sides of the circuit board 100 can provide a double supporting force to effectively prevent the circuit board 100 from being bent.

19 is a cross-sectional view of another embodiment of the circuit board 200 with an electrical component 61 disposed within the opening 505 of the second reinforcement layer 53. The circuit board 200 is similar to the circuit board 100 shown in FIG. 18 except that the circuit board 200 further includes an electrical component 61 disposed on the third surface 403 of the second routing circuit 420. The electrical component 61 (shown as a wafer) is electrically coupled to the second routing circuit 420 by a bump 71 on the third wire 445 of the second routing circuit 420. In addition, a gap between the electrical component 61 and the second routing circuit 420 of the circuit board 200 can be selectively filled with the filling material 91.

FIG. 20 is a cross-sectional view of the semiconductor package in which the first semiconductor component 63 is placed on the circuit board 200 of FIG. 19, wherein the first semiconductor component 63 is illustrated as a wafer. The first semiconductor component 63 is located in the recess 206 and is connected to the bonding pad 138 exposed in the first routing circuit 120 through the bump 73 in a flip chip manner. Accordingly, the first semiconductor element 63 and the electrical element 61 can be electrically connected to each other face-to-face by the first routing circuit 120 and the second routing circuit 420.

21 is a cross-sectional view of a package-on-package assembly by electrically bonding the second semiconductor component 65 to the lap pad 139 of the first routing circuit 120 by solder balls 75. Accordingly, the second semiconductor component 65 can be electrically connected to the first semiconductor component 63 by the first routing circuit 120 of the circuit board 200, and the electrical component is connected by the first routing circuit 120 and the second routing circuit 420. 61 electrical connection.

[Embodiment 2]

22-31 are diagrams showing a method of fabricating a circuit board in which an electrical component is embedded in a second reinforcement layer in a second embodiment of the present invention.

For the purpose of brief description, any description of the same application in the above-described embodiment 1 is hereby made, and the same description is not repeated.

22 is a cross-sectional view showing the sub-assembly 10 and the first reinforcement layer 20 placed on the carrier film 30. The sub-assembly 10 is similar to the structure shown in FIG. 10 except that the sacrificial carrier 110 of the present embodiment has a two-layer structure. The sub-assembly 10 is located in the through opening 205 of the first reinforcement layer 20, and the sacrificial carrier 110 is attached to the carrier film 30. The carrier film 30 is typically a tape that provides a temporary securing force to secure the sub-assembly 10 within the through opening 205. In the figure, the sub-assembly 10 and the first reinforcement layer 20 are attached to the carrier film 30 by the adhesiveness of the carrier film 30. Alternatively, an additional adhesive may be applied to attach the sub-assembly 10 and the first reinforcement layer 20 to the carrier film 30. After the sub-assembly 10 is inserted into the through opening 205, the second surface 103 of the first routing circuit 120 is substantially coplanar with the surface of one of the first reinforcement layers 20 in the upward direction. In a state in which the area of the through opening 205 is slightly larger than the sub-group 10, an adhesive (not shown) may be selectively applied to the gap between the sub-group 10 and the first reinforcing layer 20 in the through-opening 205 ( Not shown), providing a strong mechanical bond between the first routing circuit 120 and the first reinforcement layer 20. The sacrificial carrier 110 includes a support plate 111 and a barrier layer 113 deposited on the support plate 111, and the first routing circuit 120 is formed on the barrier layer 113. The barrier layer 113 may have a thickness of 0.001 to 0.1 mm, and may be a metal layer, wherein the metal layer may resist chemical etching when chemically removing the support plate 111, and may remove the metal without affecting the routing line 135. Floor. For example, when the support plate 111 and the routing line 135 are made of copper, the barrier layer 113 may be made of tin or nickel. Further, in addition to the metal material, the barrier layer 113 may be a dielectric layer such as a peelable laminate film. In this embodiment, the support plate 111 is a copper plate, and the barrier layer 113 is a nickel layer having a thickness of 3 micrometers.

23 is a cross-sectional view of the third dielectric layer 441 and the metal layer 44 laminated/coated on the sub-assembly 10 and the first reinforcement layer 20 from above. The third dielectric layer 441 contacts the second dielectric layer 151 / the second wire 155 , the metal layer 44 , and the first reinforcement layer 20 , and is sandwiched between the second dielectric layer 151 / the second wire 155 and the metal layer 44 And between the first reinforcement layer 20 and the metal layer 44.

24 is a cross-sectional view of the third blind via 443 showing the contact pads 158 of the second lead 155. Here, the third blind via 443 extends through the metal layer 44 and the third dielectric layer 441 and is aligned with the contact pads 158 of the second conductor 155.

FIG. 25 is a cross-sectional view showing the formation of the third wire 445 on the third dielectric layer 441. Here, the third wire 445 is formed by depositing the coating layer 44' on the metal layer 44 and the third blind hole 443, and then patterning the metal layer 44 and the coating layer 44' thereon. The third wire 445 extends upward from the contact pad 158 and fills the third blind hole 443 to form a third metallization blind hole 447 that directly contacts the contact pad 158 while extending laterally over the third dielectric layer 441.

At this stage, the process of forming the second routing circuit 420 on the first routing circuit 120 and the first enhancement layer 20 is completed. In the figure, the second routing circuit 420 includes a third dielectric layer 441 and a third wire 445.

26 is a cross-sectional view of the carrier film 30 removed and a vertical connection channel 51 deposited on the second routing circuit 420. After the carrier film 30 is removed from the sacrificial carrier 110 and the first reinforcement layer 20, a vertical connection channel 51 is then formed on the third conductor 445 of the second routing circuit 420. In the figure, the vertical connecting channels 51 are shown as metal posts 513 and are electrically connected to the second routing circuit 420.

27 is a cross-sectional view of the electrical component 61 attached to the second routing circuit 420. The electrical component 61 (shown as a wafer) is electrically coupled to the second routing circuit 420 by a bump 71 on the third wire 445 of the second routing circuit 420.

28 is a cross-sectional view showing the second reinforcement layer 53 formed on the second routing circuit 420. The second reinforcing layer 53 covers the second routing circuit 420, the vertical connecting channel 51 and the electrical component 61 from above, and is circumferentially covered and covered in the lateral direction and covers the vertical connecting channel 51 and the electrical component 61.

Figure 29 is a cross-sectional view showing the top region of the second reinforcing layer 53 removed to reveal the vertical connecting passage 51 from above. In this figure, the outer surface of the second reinforcing layer 53 is substantially coplanar with the exposed surface of the vertical connecting channel 51.

Figure 30 is a cross-sectional view showing the support plate 111 removed. Here, the support plate 111 made of copper can be removed by an alkaline etching solution.

FIG. 31 is a cross-sectional view showing the barrier layer 113 removed. Here, the barrier layer 113 made of nickel can be removed by an acidic etching solution to expose the first surface 101 of the first routing circuit 120 from above. In another aspect in which the barrier layer 113 is a peelable laminate film, the barrier layer 113 can be removed by mechanical peeling or plasma ashing. Accordingly, the first surface 101 of the first routing circuit 120 and a portion of the inner sidewall surface 209 of the first reinforcement layer 20 together form a recess 206 in the first reinforcement layer 20 through opening 205.

Accordingly, as shown in FIG. 31, the completed circuit board 300 includes a first reinforcement layer 20, a first routing circuit 120, a second routing circuit 420, a vertical connection channel 51, a second reinforcement layer 53 and a The electrical component 61, wherein the first routing circuit 120 and the second routing circuit 420 are all layered routing circuits without a core layer.

The first routing circuit 120 is located in the through opening 205 of the first reinforcement layer 20, and the second routing circuit 420 is located outside the through opening 205 of the first reinforcement layer 20 and extends to the peripheral edge of the circuit board 300. In the figure, the first routing circuit 120 has a bond pad 138 and a bond pad 139 at the first surface 101 and a contact pad 158 at the second surface 103. Since the size and pad pitch of the contact pads 158 are designed to be larger than the size and pad pitch of the bond pads 138 (where the size and pad pitch of the bond pads 138 are consistent with the subsequent wafer I/O pads), the first The routing circuit 120 can provide a primary fanout route to ensure that the next level of the layered circuit interconnect process exhibits a higher production yield. The second routing circuit 420 is in contact with the first routing circuit 120 and the first reinforcement layer 20 and extends laterally on the first routing circuit 120 and the first reinforcement layer 20, and is electrically coupled to the first routing circuit 120. Pad 158. In addition, the first reinforcement layer 20 and the second reinforcement layer 53 are located at opposite sides of the circuit board 300 to prevent the circuit board 300 from being bent. The vertical connection via 51 is buried in the second reinforcement layer 53 and electrically connected to the second routing circuit 420 and exposed by the second reinforcement layer 53. The electrical component 61 is surrounded by the second reinforcement layer 53 while being laterally surrounded by the vertical connection channel 51 and electrically coupled to the second routing circuit 420.

32 is a cross-sectional view of the semiconductor package in which the first semiconductor component 63 is placed on the wiring board 300 of FIG. 31, wherein the first semiconductor component 63 is illustrated as a wafer. The first semiconductor component 63 is located in the recess 206 of the circuit board 300 and is connected to the bonding pad 138 exposed in the first routing circuit 120 through the bump 73 in a flip chip manner.

33 is a cross-sectional view of a package-on-package assembly by electrically bonding the second semiconductor component 65 to the lap pad 139 of the first routing circuit 120 by solder balls 75. Accordingly, the second semiconductor component 65 can be electrically connected to the first semiconductor component 63 by the first routing circuit 120 of the circuit board 300, and the electrical component is connected by the first routing circuit 120 and the second routing circuit 420. 61 electrical connection.

[Example 3]

34-37 are diagrams showing a method of fabricating a circuit board having a third routing circuit in a third embodiment of the present invention.

For the purpose of brevity, the description of any of the above embodiments that can be used for the same application is the same, and the same description is not repeated.

Figure 34 is a cross-sectional view showing the formation of a third wire 835 on the second reinforcing layer 53 of Figure 29. The third wire 835 is formed by a metal deposition and metal patterning process, and extends laterally on the outer surface of the second reinforcement layer 53 and contacts the vertical connection channel 51.

35 is a cross-sectional view of the fourth dielectric layer 841 and the fourth blind via 843, wherein the fourth dielectric layer 841 is on the second reinforcement layer 53 and the fourth conductor 835, and the fourth blind via 843 is on the fourth dielectric layer. In layer 841. The fourth dielectric layer 841 can be deposited by lamination or coating, and contacts the second reinforcement layer 53 and the fourth conductor 835, and is covered by the upper side and extends laterally to the second reinforcement layer 53 and the fourth layer. On wire 835. The fourth dielectric layer 841 typically has a thickness of 50 microns and may be made of epoxy, glass epoxy, polyimine, or the like. After depositing the fourth dielectric layer 841, a fourth blind via 843 extending through the fourth dielectric layer 841 is formed to expose selected portions of the fourth conductive trace 835. The fourth blind via 843 can also be formed by a variety of techniques including laser drilling, plasma etching, and lithography, and typically has a diameter of 50 microns.

36 is a cross-sectional view showing the fifth conductive line 855 on the fourth dielectric layer 841 by a metal deposition and metal patterning process. The fifth wire 855 extends upward from the fourth wire 835 and fills the fourth blind hole 843 while extending laterally on the fourth dielectric layer 841.

This stage has been completed on the second enhancement layer 53 to form a third routing circuit 820. In the figure, the third routing circuit 820 includes a fourth wire 835, a fourth dielectric layer 841, and a fifth wire 855.

37 is a cross-sectional view of the sacrificial carrier 110 after removal. Thereby, the first surface 101 of the first routing circuit 120 is exposed from the through opening 205 of the first reinforcement layer 20.

Accordingly, as shown in FIG. 37, the completed circuit board 400 includes a first reinforcement layer 20, a first routing circuit 120, a second routing circuit 420, a vertical connection channel 51, a second reinforcement layer 53, and a The electrical component 61 and a third routing circuit 820.

The first routing circuit 120 is located in the through opening 205 of the first reinforcement layer 20, and the second routing circuit 420 is disposed on the first routing circuit 120 and the first reinforcement layer 20. The electrical component 61 is electrically coupled to the second routing circuit 420 and surrounded by the second reinforcement layer 53 while being laterally surrounded by the vertical connection channel 51 in the second reinforcement layer 53. The third routing circuit 820 is disposed on the second reinforcement layer 53 and electrically connected to the vertical connection channel 51.

38 is a cross-sectional view of the semiconductor package in which the first semiconductor element 63 and the heat sink 58 are placed on the wiring board 400 of FIG. 37. The first semiconductor component 63 is connected to the first surface 101 of the first routing circuit 120 in a flip chip manner, and is electrically connected to the electrical component 61 by the first routing circuit 120 and the second routing circuit 420. Sexual connection. The heat sink 58 is attached to the inactive surface of the first semiconductor component 63 and extends laterally on the first reinforcement layer 20.

[Example 4]

39 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention, having a conductive via 515 in the second reinforcement layer 53 and a solder ball 517 in contact with the conductive via 515.

In the present embodiment, the circuit board 500 is prepared in a process similar to that described in Embodiment 2, except that the vertical connection channel 51 includes a combination of conductive vias 515 and solder balls 517.

[Example 5]

Figure 40 is a cross-sectional view of a wiring board according to a fifth embodiment of the present invention, in which an additional vertical connecting passage is provided in the first reinforcing layer.

In the present embodiment, the circuit board 600 is prepared in a process similar to that described in Embodiment 3, except that the circuit board 600 forms an additional vertical connection channel 21 in the first reinforcement layer 20, which An additional third metallization via 448 in the third dielectric layer 441 is electrically coupled to the second routing circuit 420. In this figure, the additional vertical connecting channels 21 in the first reinforcing layer 20 are depicted as metal posts. However, as described in the vertical connection channel 51 of the second reinforcement layer 53, the vertical connection channels 21 in the first reinforcement layer 20 may also be solder balls, conductive blind holes or a combination thereof.

41 is a cross-sectional view of the semiconductor package in which the first semiconductor element 63 and the heat sink 58 are placed on the wiring board 600 of FIG. The first semiconductor component 63 is connected to the first surface 101 of the first routing circuit 120 in a flip chip manner. The heat sink 58 is thermally conductive to the first semiconductor component 63 and electrically coupled to the vertical connection channel 21 in the first reinforcement layer 20 for grounding.

42 is a cross-sectional view showing the first semiconductor element 63, the second semiconductor element 65, and the third semiconductor element 67 placed on the wiring board 600 of FIG. The first semiconductor component 63 is located in the recess 206 of the circuit board 600 and is electrically coupled to the bonding pad 138 of the first routing circuit 120. The second semiconductor component 65 is disposed above the first semiconductor component 63 and electrically coupled to the stack pad 139 of the first routing circuit 120 . The third semiconductor component 67 is disposed above the second semiconductor component 65 and the second reinforcement layer 53 and electrically coupled to the vertical connection channel 51.

The above-mentioned circuit boards and assemblies are merely illustrative examples, and the present invention can be implemented by other various embodiments. In addition, the above embodiments may be used in combination with each other or in combination with other embodiments based on design and reliability considerations. For example, the first reinforcement layer may include a plurality of through openings arranged in an array shape, and a first routing circuit may be disposed in each of the through openings. In addition, the second routing circuit can also include additional wires to receive and connect additional contact pads of the additional first routing circuit. Similarly, the second reinforcing layer may include a plurality of openings arranged in an array shape, and each of the openings may accommodate an electrical component.

As shown in the above embodiment, the present invention constructs a unique circuit board that exhibits better reliability, including a first reinforcement layer, a first routing circuit, a second routing circuit, a series of vertical connection channels, and a second reinforcement. Layer, selective electrical components, and selective third routing circuitry. For convenience of the following description, the direction in which the first surface of the first routing circuit faces is defined as the first direction, and the direction in which the second surface of the first routing circuit faces is defined as the second direction. The second routing circuit is disposed on the second surface of the first routing circuit and has a third surface facing the second direction.

The first reinforcement layer has a through opening and may be a single layer or a multi-layer structure, and may optionally be embedded with a single-level wire or a multi-layer wire. In a preferred embodiment, the first reinforcement layer surrounds a peripheral edge of the first routing circuit and extends laterally to a peripheral edge of the circuit board. The first reinforcement layer can be made of any material having sufficient mechanical strength, such as a metal, a metal composite, a ceramic, a resin, or other non-metallic material. Accordingly, the first reinforcement layer located around the first routing circuit can provide mechanical support to the circuit board to prevent the circuit board from being bent. Additionally, additional vertical connection channels can be formed in the first reinforcement layer to provide electrical contacts for the semiconductor component to be placed on the first reinforcement layer from the first direction. Additional vertical connection channels in the first reinforcement layer can include, but are not limited to, metal posts, solder balls, conductive blind holes, or combinations thereof.

The first and second routing circuits may be layered routing circuits having no core layer, respectively located in the through openings of the first reinforcement layer and outside the through openings. Additionally, the second routing circuit extends laterally beyond the peripheral edge of the first routing circuit and has a surface area greater than the surface area of the first routing circuit. Preferably, the second routing circuit extends to a peripheral edge of the circuit board and substantially has a combined surface area of the first routing circuit and the first reinforcement layer. The first and second routing circuits each include at least one dielectric layer and wires, wherein the wires fill the blind vias in the dielectric layer and extend laterally over the dielectric layer. The dielectric layer and the wire are continuously formed in turns and can be formed repeatedly if desired.

The first routing circuit can be formed on the removable sacrificial carrier to form a sub-group, and then insert the sub-assembly into the through-opening of the first reinforcement layer, and preferably the first routing circuit and the sacrificial carrier The peripheral edge is adjacent to the inner wall surface of the through opening of the first reinforcement layer. More specifically, the first routing circuit can include a routing circuit, a dielectric layer, and a wire, wherein the routing circuit is on the sacrificial carrier board, the dielectric layer is on the routing line and the sacrificial carrier board, and the wire is routed. The selected portion extends and fills the blind vias in the dielectric layer to form metallized blind vias that extend laterally over the dielectric layer. If more signal routing is required, the first routing circuit can further include additional dielectric layers, additional blind vias, and additional traces. Additionally, the first routing circuit can optionally include one or more passive components embedded therein. In the present invention, the first routing circuit can be formed directly on the sacrificial carrier board, or the first routing circuit can be separately formed, and then the first routing circuit can be detachably attached to the sacrificial carrier board to complete the sacrificial load. The step of forming a first routing circuit on the board. In the first routing circuit, the routing circuitry can include bond pads that mate with the wafer I/O pads, while the outermost conductors that face away from the sacrificial carrier can include contact pads that are spaced apart from the bond pad pitch. The routing circuitry can optionally further include a bond pad to provide an electrical contact to another semiconductor component, such as a plastic package or another semiconductor package. Therefore, the first routing circuit can be a multi-layer routing circuit, and the first surface thereof can have a bonding pad and a selective bonding pad, and the second surface can have a contact pad, wherein the contact pad can be electrically connected by a metallized blind hole The utility model is coupled to the bonding pad and selectively electrically coupled to the bonding pad. Accordingly, in a preferred embodiment, the first routing circuit has a fan-out conductor pattern that is fanned out from the fine pitch of the bond pad to a relatively coarse pitch of the contact pads, and provides a first-stage fan-out. Routing/interconnecting to the semiconductor components that are subsequently placed thereon. The bond pads, the selective landing pads, and the innermost dielectric layer adjacent the sacrificial carrier may have substantially coplanar surfaces (facing the first direction) while facing away from the outermost conductor surface of the sacrificial carrier (facing The second direction) is preferably substantially coplanar with the surface of the first reinforcement layer. In addition, the first reinforcement layer may extend beyond the first surface of the first routing circuit in a first direction, and after removing the sacrificial carrier, a recess is formed in the through opening of the first reinforcement layer to reveal the first route. The first surface of the circuit. Accordingly, the semiconductor component can be placed in the recess and the semiconductor component can be electrically coupled to the bond pad exposed by the recess. After inserting the sub-assembly into the through-opening of the first reinforcement layer, the adhesive may be selectively applied to the gap between the sub-group and the first reinforcement layer, and provided between the first routing circuit and the first reinforcement layer. Robust mechanical joints. Alternatively, the gap between the sub-assembly and the first reinforcement layer may be filled by a dielectric material extruded from a dielectric layer of the second routing circuit. Accordingly, the adhesive or dielectric material can be applied over the inner sidewall surface of the opening and the peripheral edge of the first routing circuit and the sacrificial carrier.

After the first routing circuit is inserted into the through opening of the first reinforcement layer, the second routing circuit may be formed on the second surface of the first routing circuit and laterally extend on the surface of the first reinforcement layer to provide further Fanout routing/interconnecting to the first routing circuit. Since the second routing circuit is electrically coupled to the first routing circuit through the metallized blind via of the second routing circuit, the electrical connection between the first routing circuit and the second routing circuit does not require the use of solder material. In addition, the interface between the first reinforcement layer and the second routing circuit does not require the use of solder or adhesive. More specifically, the second routing circuit can include a dielectric layer and a wire, wherein the dielectric layer is on the first routing circuit and the first reinforcement layer, and the wire extends from the contact pad of the first routing circuit (and selects And extending from the first reinforcement layer or the additional vertical connection channel in the first reinforcement layer) and filling the blind holes in the dielectric layer of the second routing circuit while extending laterally on the dielectric layer of the second routing circuit . Therefore, the second routing circuit can be contacted and electrically coupled to the contact pads of the first routing circuit to form a signal route, and the second routing circuit can be selectively further electrically coupled to the first reinforcement layer to serve as a ground. Connected, or selectively further electrically coupled to additional vertical connection channels in the first reinforcement layer to form a signal route or as a ground connection. If more signal routing is required, the second routing circuit can further include additional dielectric layers, additional blind vias, and additional traces.

A carrier film (usually an adhesive tape) can be used to provide a temporary holding force before forming the second routing circuit. For example, the carrier film may be temporarily attached to the sacrificial carrier and the first reinforcement layer to fix the secondary assembly in the through opening of the first reinforcement layer, and then, as described above, the adhesive may be selectively coated. Between the first reinforcement layer and the first routing circuit and the gap between the first reinforcement layer and the sacrificial carrier. After forming the second routing circuit on the first routing circuit and the first reinforcement layer, the carrier film can be removed. Alternatively, the sub-group and the first reinforcement layer may be directly disposed on a dielectric layer, and the outermost wires of the first routing circuit and the first reinforcement layer are in contact with the dielectric layer, and then the dielectric layer is further Bonding to the first routing circuit and the first reinforcement layer, and preferably causing the dielectric layer to flow into the gap between the first routing circuit and the first reinforcement layer and between the sacrificial carrier and the first reinforcement layer. Thereby, the dielectric material extruded from the dielectric layer can provide a strong mechanical bond between the sub-assembly and the first reinforcement layer, and fix the sub-assembly within the through-opening of the first reinforcement layer. Then, the second routing circuit (including the dielectric layer bonded to the first routing circuit and the first reinforcement layer) can be electrically coupled to the first routing circuit.

After the second routing circuit is formed, the sacrificial carrier that provides the strong support force to the first routing circuit can be removed from the first routing circuit by chemical etching or mechanical peeling. The sacrificial carrier can have a thickness of 0.1 mm to 2.0 mm and can be made of any conductive or non-conductive material such as copper, nickel, chromium, tin, iron, stainless steel, tantalum, glass, graphite, plastic film, or other metal. Or non-metallic materials. In the aspect of removing the sacrificial carrier by chemical etching, the sacrificial carrier is typically made of a chemically removable material. In order to avoid etching to the bonding pad in contact with the sacrificial carrier when removing the sacrificial carrier, the sacrificial carrier may be made of nickel, chromium, tin, iron, stainless steel, or other selective etching solution (not made of copper) The mat and the optional lap pad react to remove the material. Alternatively, the bond pads and selective splicing pads can be made of any stabilizing material to avoid etching when the sacrificial carrier is removed. For example, when the sacrificial carrier is made of copper, the bond pads and the selective lap pads can be gold pads. In addition, the sacrificial carrier may also be a multi-layer structure having a barrier layer and a support plate, and the first routing circuit is formed on the barrier layer of the sacrificial carrier. Since the first routing circuit and the support plate are separated from each other by the barrier layer therebetween, even if the routing circuit and the support plate of the first routing circuit are made of the same material, when the support plate is removed It will not harm the routing circuit of the first routing circuit. Here, the barrier layer may be a metal layer, and the metal layer does not act on the chemical etching when the support plate is chemically removed, and may be removed using an etching solution that does not react to the routing line. For example, a nickel layer, a chromium layer or a titanium layer may be formed on the surface of the support plate made of copper or aluminum as a barrier layer, and a routing line made of copper or aluminum may be deposited on the nickel layer, chromium. On the layer or on the titanium layer. Accordingly, the nickel, chrome or titanium layer protects the routing circuitry from etching when the support plate is removed. Alternatively, the barrier layer can be a dielectric layer that can be removed by, for example, mechanical stripping or plasma ashing. For example, the release layer can be used as a barrier layer between the support plate and the first routing circuit, and the support plate can be removed together with the release layer by mechanical peeling.

The second reinforcement layer is typically a resin molded reinforcement layer and may have a mouthpiece for receiving a selective electrical component. Alternatively, after the electrical component is electrically coupled to the second routing circuit, a second reinforcement layer is provided to embed the electrical component. In a preferred embodiment, the second reinforcement layer extends laterally to the peripheral edge of the circuit board. Accordingly, the second reinforcement layer can provide mechanical support to the circuit board from the second direction. The first reinforcing layer and the second reinforcing layer on opposite sides of the dual routing circuit combined to provide double support, effectively avoiding bending of the circuit board. In addition, the interface between the second reinforcement layer and the second routing circuit may eliminate the need for solder or adhesive.

The vertical connection channel in the second reinforcement layer can provide an electrical connection connecting the next level group or the next level routing circuit. In a preferred embodiment, the vertical connecting channels are disposed in an edge region of the third surface of the second routing circuit before the second reinforcing layer is provided. The vertical connection channels in the second reinforcement layer may include metal posts, solder balls, conductive blind holes, or a combination thereof, and may have the same or different thickness as the second reinforcement layer. For example, the surface of the vertical connecting channel facing the second direction may be substantially coplanar with the outer surface of the second reinforcing layer in the second direction. Alternatively, the thickness of the second reinforcement layer may be greater or less than the height of the vertical connection channel. In the aspect that the second reinforcement layer has a large thickness, the second reinforcement layer is formed with an opening extending from the outer surface of the second reinforcement layer to the vertical connection channel to expose the selection of the vertical connection channel in the second direction. Part. In a manner that the second reinforcement layer has a small thickness, the vertical connection channels extend beyond the outer surface of the second reinforcement layer in the second direction and have a convex shape from the outer surface of the second reinforcement layer and are not subjected to the second The selected area of the reinforcement layer is covered. In any event, the vertical connection channel is exposed by the outer surface of the second reinforcement layer to provide an electrical contact for the next level of connection.

The selective electrical component can be connected to the second routing circuit by bumping on the third surface of the second routing circuit and electrically coupled to the second routing circuit. The electrical component can be a semiconductor component such as a packaged or unpackaged wafer. For example, the electrical component can be a bare die, or a wafer level package die. Alternatively, the electrical component can be a stacked wafer.

The selective third routing circuit is formed on the outer surface of the second reinforcement layer and electrically coupled to the vertical connection channel. More specifically, the third routing circuit can include a wire electrically connected to the vertical connection channel in the second reinforcement layer and extending laterally on the second reinforcement layer. If more signal routing is desired, the third routing circuit can include one or more dielectric layers, blind vias in the dielectric layer, and additional traces. The outermost wire of the third routing circuit can accommodate conductive contacts, such as solder balls, for electrical transmission and mechanical connection with the next group or another electronic component.

The present invention also provides a semiconductor package that electrically couples a first semiconductor component to a bond pad of the circuit board. More specifically, the first semiconductor component can be placed in the recess of the circuit board, and various connection media (such as bumps) can be disposed on the circuit board bond pad to electrically connect the first semiconductor component to the circuit board. Accordingly, in the aspect of the electrical component having the second reinforcement layer embedded in the circuit board, the first semiconductor component and the electrical component can be electrically connected to each other by the first and second routing circuits therebetween Connected to form a face-to-face assembly. In the face-to-face assembly, the first and second routing circuits provide a shortest interconnection distance between the first semiconductor component and the electrical component. The first semiconductor component can be a packaged or unpackaged wafer. For example, the first semiconductor component can be a bare wafer, or a wafer level package die or the like. Alternatively, the first semiconductor component can be a stacked wafer.

In addition, a second semiconductor component can be further provided, and the second semiconductor component is electrically coupled to the stack pad of the circuit board by a conductive contact, such as a solder ball. Accordingly, the present invention can provide a package-on-package assembly including a first semiconductor component and a second semiconductor component, wherein the first semiconductor component is located in a recess of the circuit board, and The second semiconductor component is electrically connected to the bonding pad of the circuit board. The second semiconductor component is electrically connected to the bonding pad of the circuit board. In a preferred embodiment, the first semiconductor component is flip-chip mounted on the bond pad, and the second semiconductor component is over the first reinforcement layer and the first semiconductor component and is attached to the bond pad. Here, a filling material may be selectively filled in the gap between the first semiconductor element and the first routing circuit of the circuit board.

The term "overlay" means incomplete and complete coverage in the vertical and / or lateral directions. For example, in the state where the pocket is up, the selective third routing circuit covers the second routing circuit below, regardless of whether another component such as the second enhancement layer is located between the third routing circuit and the second routing circuit.

The words "attached to" and "attached to" include contact and non-contact with a single or multiple components. For example, the selective heat sink can be attached to the first reinforcement layer, whether the heat sink contacts the first reinforcement layer or is separated from the first reinforcement layer by an adhesive or solder ball.

The term "aligned" means the relative position between elements, whether or not the elements are spaced apart from each other or abut, or one element is inserted and extends into the other element. For example, when the imaginary horizontal line intersects the inner wall surface of the first reinforcement layer and the peripheral edge of the first routing circuit, the inner sidewall surface of the first reinforcement layer is laterally aligned with the peripheral edge of the first routing circuit, regardless of the first reinforcement layer. Whether there is another element between the sidewall surface and the peripheral edge of the first routing circuit that intersects the imaginary horizontal line, and whether or not there is another intersection with the peripheral edge of the first routing circuit but does not intersect the inner sidewall surface of the first reinforcement layer, or An imaginary horizontal line where the inner sidewall surfaces of the first reinforcement layer intersect but do not intersect the peripheral edge of the first routing circuit.

The term "close" means that the width of the gap between the elements does not exceed the maximum acceptable range. As is known in the art, when the gap between the inner wall surface of the first reinforcing layer and the sub-group is not sufficiently narrow, the position error due to the lateral displacement of the sub-group in the gap may exceed the maximum acceptable. Error limit. In some cases, once the position error of the sub-group exceeds the maximum limit, it is impossible to use the laser beam to align with the predetermined position of the first routing circuit, which may result in a relationship between the first routing circuit and the second routing circuit. The electrical connection failed. According to the contact pad size of the first routing circuit, a person skilled in the art can confirm the maximum acceptable limit of the gap between the first routing circuit and the first reinforcement layer through trial and error to ensure metallization of the second routing circuit. The blind via is aligned with the contact pads of the first routing circuit. Thus, the phrase "the first routing circuit and the peripheral edge of the sacrificial carrier are adjacent to the inner sidewall surface of the first reinforcement layer through opening" means the gap between the peripheral edge of the sacrificial carrier and the inner sidewall surface of the through opening, and the first The gap between the peripheral edge of the routing circuit and the inner sidewall surface of the through opening is narrow enough to prevent the position error of the subgroup from exceeding an acceptable maximum error limit. For example, the gap between the peripheral edge of the sub-assembly and the inner sidewall surface of the through opening is preferably in the range of about 10 microns to 50 microns. [00100] The terms "electrical connection" and "electrical coupling" mean direct or indirect electrical connection. For example, the first wire is in direct contact and electrically connected to the routing line, while the second wire is spaced from the routing wire and electrically connected to the routing wire by the first wire. [00101] The "first direction" and "second direction" do not depend on the orientation of the board. Anyone familiar with the art can easily understand the direction in which they actually refer. For example, the first surface of the first routing circuit faces in a first direction, and the second surface of the first routing circuit faces in a second direction, regardless of whether the board is inverted. Therefore, the first and second directions are opposite to each other and perpendicular to the side direction. Furthermore, in the state where the pocket is upward, the first direction is the upward direction, and the second direction is the downward direction; in the downward state of the pocket, the first direction is the downward direction, and the second direction is the upward direction. direction. [00102] The circuit board of the present invention has many advantages. For example, the first and second reinforcement layers provide a bend resistant platform for the integrated dual routing circuit to avoid bending of the board. The vertical connection channel in the second reinforcement layer provides an electrical contact for the next stage of connection. In addition, the first routing circuit in the first reinforcement layer through the opening can provide the first stage fanout/interconnect to the semiconductor component mounted thereon, and the first routing circuit and the second routing circuit on the first enhancement layer A second stage fanout/interconnect is available. Thereby, the semiconductor component having the fine pad can be electrically coupled to one side of the first routing circuit, wherein the pad pitch of the side is consistent with the semiconductor component, and the second routing circuit is electrically coupled to the first The routing circuit has the other side of the larger pad pitch to further amplify the pad size and spacing of the semiconductor components. The circuit board prepared by this method is highly reliable, inexpensive, and is very suitable for mass production. [00103] The manufacturing method of the present invention has high applicability, and combines various mature electrical and mechanical connection technologies in a unique and progressive manner. Furthermore, the manufacturing method of the present invention can be carried out without expensive tools. Therefore, compared to the traditional technology, this production method can greatly increase the yield, yield, efficiency and cost-effectiveness. The embodiments described herein are illustrative, and the elements or steps that are well known in the art may be simplified or omitted in order to avoid obscuring the features of the present invention. Similarly, in order to make the drawings clear, the drawings may also omit redundant or non-essential components and component symbols.

[00105] circuit board 100, 200, 300, 400, 500, 600 sub-assembly 10 first surface 101 second surface 103 sacrificial carrier 110 support plate 111 barrier layer 113 first routing circuit 120 routing line 135 bonding pad 138 Lamination pad 139 first dielectric layer 141 first blind hole 143 first wire 145 first metallization blind hole 147 second dielectric layer 151 second blind hole 153 second wire 155 second metallization blind hole 157 contact pad 158 first reinforcement layer 20 through opening 205 pocket 206 gap 207 inner wall surface 209 vertical connection channel 21, 51 carrier film 30 third surface 403 second routing circuit 420 metal layer 44 coating layer 44' third dielectric layer 441 Three blind holes 443 third wire 445 third metallization blind hole 447, 448 hole 505 solder ball 511, 517 metal column 513 conductive blind hole 515 second reinforcement layer 53 opening 533 heat sink 58 electrical component 61 first semiconductor Element 63 Second semiconductor element 65 Third semiconductor element 67 Bump 71, 73 Solder ball 75 Third routing circuit 820 Third wire 835 Fourth dielectric layer 841 Fourth blind hole 843 Fifth wire 855 Filling material 9 1 cutting line L

The invention will be more apparent from the following detailed description of the preferred embodiments, wherein: FIG. 1 and FIG. 2 are respectively forming a routing line on a sacrificial carrier board in the first embodiment of the present invention. 3 is a cross-sectional view showing a first dielectric layer and a first blind hole in the structure of FIG. 1 according to the first embodiment of the present invention; FIG. 4 is a first embodiment of the present invention, FIG. FIG. 5 is a cross-sectional view showing the second dielectric layer and the second blind hole in the structure of FIG. 4 according to the first embodiment of the present invention; FIGS. 6 and 7 are respectively the first embodiment of the present invention; In the aspect, FIG. 5 is a cross-sectional view showing a second wire and a top perspective view. FIGS. 8 and 9 are respectively a cross-sectional view and a top perspective view of the panel size structure of FIGS. 6 and 7 in the first embodiment of the present invention. Figure 10 is a cross-sectional view of a sub-group corresponding to the excision unit of Figures 8 and 9 in the first embodiment of the present invention; Figure 11 is a first embodiment of the present invention, FIG. 12 is a cross-sectional view showing the structure of FIG. 11 after a layer press process in the first embodiment of the present invention; FIG. 13 is a cross-sectional view of the structure of the first dielectric layer/metal layer; FIG. In the first embodiment of the present invention, a cross-sectional view of the third blind hole is formed on the structure of FIG. 12; FIG. 14 is a cross-sectional view showing the third wire formed on the structure of FIG. 13 in the first embodiment of the present invention; In the embodiment, a cross-sectional view of the solder ball is formed on the structure of FIG. 14; FIG. 16 is a cross-sectional view showing the second reinforcing layer formed on the structure of FIG. 15 in the first embodiment of the present invention; FIG. 17 is a first embodiment of the present invention. Figure 16 is a cross-sectional view showing the opening of the structure in Figure 16; Figure 18 is a cross-sectional view of the first embodiment of the present invention in which the sacrificial carrier is removed from the structure of Figure 17 to complete the circuit board; In the first embodiment of the present invention, the first semiconductor component is placed on the semiconductor package of the circuit board of FIG. FIG. 21 is a cross-sectional view showing a second embodiment of the present invention, wherein the second semiconductor device is electrically coupled to the package stack of the semiconductor package of FIG. 20; FIG. 22 is a second embodiment of the second embodiment of the present invention. Figure 23 is a cross-sectional view showing a third dielectric layer and a metal layer in the structure of Figure 22 in the second embodiment of the present invention; Figure 24 is a second embodiment of the present invention; 23 is a cross-sectional view showing a third blind hole in the structure of FIG. 23; FIG. 25 is a cross-sectional view showing the third wire in the structure of FIG. 24 in the second embodiment of the present invention; FIG. 26 is a view showing a second embodiment of the present invention. 25 is a cross-sectional view of a metal pillar formed on the structure; FIG. 27 is a cross-sectional view showing the electrical component of FIG. 26 in a second embodiment of the present invention; FIG. 28 is a second embodiment of the present invention, and FIG. Figure 29 is a cross-sectional view of the second reinforcement layer removed from the structure of Figure 28 in a second embodiment of the present invention; Figure 30 is a cross-sectional view of the second embodiment of the present invention, after removing the support plate in the sacrificial carrier from the structure of Figure 29; Figure 31 is a second embodiment of the present invention, the sacrificial carrier is removed from the structure of Figure 30 After the barrier layer is formed, a cross-sectional view of the circuit board is completed. FIG. 32 is a cross-sectional view showing the semiconductor device of the first semiconductor component placed on the circuit board of FIG. 31 in the second embodiment of the present invention; In a second embodiment, a second semiconductor device is electrically coupled to a cross-sectional view of the package stack of the semiconductor package of FIG. 32. FIG. 34 is a cross-sectional view of the fourth wire formed on the structure of FIG. 29 in a third embodiment of the present invention. Figure 35 is a cross-sectional view showing the fourth dielectric layer and the fourth blind via in the structure of Figure 34 in the third embodiment of the present invention; Figure 36 is a fifth embodiment of the present invention in the third embodiment of the present invention; Figure 37 is a cross-sectional view of the circuit board after removing the sacrificial carrier from the structure of Figure 36 in the third embodiment of the present invention; 3 is a cross-sectional view of a semiconductor package in which the first semiconductor device and the heat sink are placed on the circuit board of FIG. 37; FIG. 39 is a cross-sectional view of another circuit board in the fourth embodiment of the present invention; 40 is a cross-sectional view of another circuit board in a fifth embodiment of the present invention; FIG. 41 is a cross-sectional view showing a semiconductor package in which a semiconductor element and a heat sink are placed on the circuit board of FIG. 40 according to a fifth embodiment of the present invention; FIG. 42 is a cross-sectional view showing a plurality of semiconductor elements electrically coupled to the package stacking assembly on the circuit board of FIG. 40 in the fifth embodiment of the present invention.

Claims (15)

A circuit board having a double reinforcing layer and an integrated dual routing circuit, comprising: a first reinforcing layer having a through opening, wherein the through opening has an inner side wall surface extending through one of the first reinforcing layers; a routing circuit having a first surface and a second surface opposite thereto, wherein the first routing circuit is located in the through opening and adjacent to the inner sidewall surface of the first reinforcement layer; a second routing circuit, The first routing circuit is disposed on the second surface of the first routing circuit and extends laterally on a surface of the first reinforcement layer. The second routing circuit is electrically coupled to the first via a metallized blind hole. a routing circuit, the second routing circuit having a third surface facing away from the second surface; a second reinforcement layer disposed on the third surface of the second routing circuit; and a series of vertical connection channels Surrounded by the second reinforcing layer, wherein the vertical connecting channels are electrically connected to the second routing By one of the exposed outer surface of the second reinforcement layer. The circuit board of claim 1, further comprising: an electrical component disposed on the third surface of the second routing circuit, wherein the electrical component is electrically coupled to the second routing Circuit. The circuit board of claim 2, further comprising: a third routing circuit disposed on the outer surface of the second reinforcement layer, wherein the third routing circuit is electrically coupled to the vertical lines The channel is connected, and the electrical component is embedded in the second reinforcement layer and surrounded by the vertical connection channels. The circuit board of claim 2, wherein the electrical component is disposed in one of the openings of the second reinforcement layer. The circuit board of claim 1, wherein the first surface of the first routing circuit is exposed by the through opening of the first reinforcement layer, and the area of the first surface of the first routing circuit Less than the area of the third surface of the second routing circuit. The circuit board of claim 1, wherein a portion of the inner sidewall surface of the first reinforcement layer forms a recess with the first surface of the first routing circuit, and the recess is located The through-opening of the first reinforcement layer. The circuit board of claim 1, wherein the vertical connection channels comprise metal posts, solder balls, conductive blind holes, or a combination thereof. The circuit board of claim 1, further comprising: an additional vertical connecting channel in the first reinforcing layer, wherein the additional vertical connecting channels are electrically coupled to the first through the additional metallized blind holes Two routing circuits. The circuit board of claim 8, wherein the additional vertical connection channels comprise metal posts, solder balls, conductive blind holes, or a combination thereof. A circuit board manufacturing method having a dual reinforcement layer and an integrated dual routing circuit, comprising: forming a first routing circuit on a removable sacrificial carrier board, wherein the first routing circuit has one adjacent to the sacrificial carrier board a first surface and a second surface opposite; a first reinforcement layer having a through opening, wherein the through opening has an inner sidewall surface extending through the first reinforcement layer; the first routing circuit and The sacrificial carrier is inserted into the through opening of the first reinforcement layer, and the first routing circuit and the sacrificial carrier are adjacent to the inner sidewall surface of the first reinforcement layer; forming a second routing circuit at the first On the second surface of the routing circuit and on a surface of the first reinforcement layer, wherein the second routing circuit is electrically coupled to the first routing circuit by a metallized blind hole and has a second a third surface of the surface; forming a series of vertical connecting channels on the third surface of the second routing circuit, The vertical connection channel is electrically coupled to the second routing circuit; forming a second reinforcement layer on the third surface of the second routing circuit; and removing the sacrificial carrier to expose the first route The first surface of the circuit; wherein the vertical routing channels are laterally surrounded by the second reinforcement layer and are exposed by an outer surface of the second reinforcement layer. The manufacturing method of claim 10, further comprising: electrically coupling an electrical component to the second routing circuit, wherein the electrical component is disposed on the third surface of the second routing circuit And being laterally surrounded by the vertical connecting channel. The manufacturing method of claim 11, wherein the step of electrically coupling the electrical component to the second routing circuit comprises: inserting the electrical component into one of the second reinforcement layers . The manufacturing method of claim 11, wherein the electrical component is electrically coupled to the second routing circuit and forms the second reinforcement layer before the step of forming the second reinforcement layer This step includes embedding the electrical component with the second reinforcement layer. The manufacturing method of claim 13, further comprising: forming a third routing circuit on the outer surface of the second reinforcing layer, wherein the third routing circuit is electrically coupled to the vertical connecting channels . The manufacturing method of claim 10, wherein the step of forming the second routing circuit comprises: electrically coupling the second routing circuit to the first reinforcement layer by additionally metalizing a blind via Extra vertical connection channel in the middle.