KR101150464B1 - Semiconductor device and method for forming the same - Google Patents

Abstract

The semiconductor device of the present invention includes a through silicon via buried in a semiconductor substrate, and a conductive bump disposed over the through silicon via, a part of which is embedded in the semiconductor substrate, and a part of which is provided on the semiconductor substrate. It provides an effect of improving the yield of the semiconductor device by improving the adhesion between the via and the conductive bump.

Description

Semiconductor device and method for forming the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device including a through silicon via and a method of forming the same.

Three-dimensional lamination technology among packaging technologies of semiconductor integrated circuits has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance, and the three-dimensional lamination package has a plurality of chips having the same storage capacity. This is a stacked package, which is commonly referred to as a stacked chip package.

The technology of the multilayer chip package can reduce the manufacturing cost of the package by a simplified process, and also has advantages such as mass production, while insufficient wiring space for the electrical connection inside the package according to the increase in the number and size of the stacked chips. The disadvantage is that.

That is, the existing laminated chip package is manufactured in a structure in which a plurality of chips are attached to the chip attaching region of the substrate so as to be electrically connected between the bonding pads of the chips and the conductive circuit patterns of the substrate so as to be electrically energized. Space is needed for the circuit pattern area of the substrate to which the wire is connected, and thus the size of the semiconductor package is increased.

In view of this, a structure using a through silicon via (TSV) has been proposed as an example of a stack package. The through silicon via is formed in a chip, and the physical and electrical inter-chips are vertically formed by the through silicon via. The structure is such that the connection is made, and the conventional through-silicon via and the chip stacking method using the same are briefly described as follows.

First, holes are formed in adjacent portions of the bonding pads of each chip of the wafer, and conductive silicon is embedded in the holes to form through silicon vias. The backside of the wafer is then back ground to expose the through silicon vias. Subsequently, the wafer is sawed and separated into individual chips, and then at least two or more chips are stacked and stacked vertically on the substrate for signal exchange through the through silicon vias.

More specifically, in the electrical connection structure between the upper chip and the lower chip stacked on each other, the metal exposed to the bottom through the through silicon via of the upper chip and the metal exposed to the top through the through silicon via of the lower chip are conductive. The bumps are electrically connected to each other.

Subsequently, the stacked upper and lower chips are mounted on a substrate, wire bonding is performed between the substrate and the upper chip, molded with a molding compound resin, and solder balls are mounted on the lower surface of the substrate to complete a stack package.

1A to 1D are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.

As shown in FIG. 1A, after forming a mask pattern (not shown) for defining a trench on the semiconductor substrate 10, the trench is formed by etching the semiconductor substrate 10 using the mask pattern (not shown) as a mask. To form. Subsequently, a conductive layer is embedded in the trench to form a through silicon via 12.

As shown in FIG. 1B, the semiconductor substrate 10 is turned over and the back surface 14 of the bottom surface of the semiconductor substrate 10 having the through silicon vias 12 formed thereon is exposed until the through silicon vias 12 are exposed. Etch).

As illustrated in FIG. 1C, an interlayer insulating layer 16 is formed on the bottom surface of the semiconductor substrate 10 where the through silicon via 12 is exposed.

As shown in FIG. 1D, the interlayer insulating layer 16 is etched to expose the through silicon via 12, and then a conductive bump 18 is formed.

However, the through silicon via 12 and the conductive bumps 18 are formed of the same material, and thus the adhesion force between the through silicon vias 12 and the conductive bumps 18 may be changed depending on the surface state of the through silicon vias 12 after wafer back grinding. This deterioration problem occurs.

The present invention is intended to solve the problem that the adhesive force with the conductive bumps are different depending on the surface state of the through silicon vias during back grinding after the through silicon vias are formed.

A method of forming a semiconductor device according to the present invention includes forming a buried layer in a trench bottom formed by etching a semiconductor substrate, forming a through silicon via on the buried layer, and forming a back on the bottom surface of the semiconductor substrate to expose the buried layer. Performing grinding, removing the buried layer to form a recess, forming an insulating film on the semiconductor substrate to fill the recess, and etching the insulating film to expose the through silicon vias. And embedding a conductive material to form a conductive bump.

The forming of the buried layer in the bottom of the trench may include forming a spin on glass (SOG) to fill the trench, and performing an etch back on the SOG.

In the forming of the through silicon via, the copper may be formed on the buried layer.

The removing of the buried layer to form a recess may include performing a dip out process on the buried layer.

The forming of the conductive bumps may include etching the insulating layer to a width greater than that of the through silicon vias.

The forming of the conductive bumps may include burying copper after etching the insulating film.

The present invention provides an effect of improving the yield of the semiconductor device by improving the adhesion between the through silicon via and the conductive bumps.

1A to 1D are cross-sectional views showing a method of forming a semiconductor device according to the prior art.
2 is a cross-sectional view showing a semiconductor device according to the present invention.
3A to 3E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Hereinafter, with reference to the accompanying embodiments according to the present invention will be described in detail.

As illustrated in FIG. 2, the semiconductor device of the present invention is provided with a through silicon via 104 embedded in the semiconductor substrate 100 and an upper portion of the through silicon via 104. It is embedded in the 100, a part includes a conductive bump (112) provided above the semiconductor substrate 100.

Here, the conductive bumps 112 embedded in the semiconductor substrate 100 preferably have a first width that is the same as the width of the through silicon vias 104, and the conductive bumps 112 provided on the semiconductor substrate 100 may include It is preferred to have a second width that is greater than the first width. In addition, the through silicon vias 104 and the conductive bumps 112 preferably include copper.

As described above, the conductive bumps 112 have a first width and are embedded in the semiconductor substrate 100, thereby increasing adhesion to the through silicon vias 104 and having a larger width than the first width on the semiconductor substrate 100. The second width may be formed to secure an area where the chip is connected.

The formation method of the semiconductor element which has the above-mentioned structure is as follows.

As shown in FIG. 3A, after forming a mask pattern (not shown) for defining a trench on the semiconductor substrate 100, the trench is formed by etching the semiconductor substrate 100 using the mask pattern (not shown) as a mask. do. Subsequently, after the buried layer 102 is formed to fill the trench, the buried layer 102 may be etched back so that the buried layer 102 remains only at the bottom of the trench. In this case, the buried layer 102 is preferably a material having good embedding characteristics, and is preferably SOG (Spin On Glass). Herein, the material embedded in the trench bottom is not limited to SOG, and any material may be changed as long as the buried property is good. Subsequently, a conductive material is formed on the buried layer 102 to completely fill the trench to form through silicon vias 104. Here, the conductive material embedded to form the through silicon vias 104 preferably includes copper.

As shown in FIG. 3B, the semiconductor substrate 100 is etched by performing back grinding 106 on the bottom surface of the semiconductor substrate 100 so that the buried layer 102 is exposed.

As shown in FIG. 3C, the semiconductor substrate 100 is turned upside down so that the buried layer 102 (see FIG. 3B) is placed on the top surface, and the buried layer 102 is removed to form the recess 108. In this case, the recess 108 may be formed by removing the buried layer 102 by a dip out. The formation of the recess 108 may be performed to improve adhesion by expanding the area where the conductive bumps are connected to the semiconductor substrate 100 in a subsequent process.

As shown in FIG. 3D, an insulating layer 110 is formed on the through silicon via 104 and the semiconductor substrate 100 to fill the recess 108.

As shown in FIG. 3E, after forming a mask pattern (not shown) on the insulating layer 110, the insulating layer 119 is etched to expose the through silicon vias 104 using the mask pattern (not shown) as a mask. Thereafter, the conductive material is embedded to form the conductive bumps 112. Here, the conductive material forming the conductive bumps 112 preferably includes copper.

In this case, the width of the insulating layer 110 is preferably larger than the width of the recess 108. This may improve the adhesion between the conductive bumps 112 and the through silicon vias 104 while securing an area connected between the chips, thereby easily preventing defects in the semiconductor device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. Of the present invention.

Claims (6)

Forming a buried layer in a trench bottom formed by etching the semiconductor substrate;
Forming through silicon vias on the buried layer;
Performing back grinding on a bottom surface of the semiconductor substrate to expose the buried layer;
Removing the buried layer to form a recess;
Forming an insulating film on the semiconductor substrate to fill the recess; And
And etching the insulating layer to expose the through silicon via, and then filling a conductive material to form a conductive bump. Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1,
Forming a buried layer in the bottom of the trench
Forming a spin on glass (SOG) to fill the trench; And
And etching back the SOG. Claim 3 has been abandoned due to the setting registration fee. The method according to claim 1,
Forming the through silicon vias is
Forming copper on the buried layer; Claim 4 was abandoned when the registration fee was paid. The method according to claim 1,
Removing the buried layer to form a recess
A method of forming a semiconductor device, characterized in that to perform a dip out process to the buried layer. Claim 5 was abandoned upon payment of a set-up fee. The method according to claim 1,
Forming the conductive bumps
And etching the insulating film to a width greater than the width of the through silicon via. Claim 6 was abandoned when the registration fee was paid. The method according to claim 1,
Forming the conductive bumps
And embedding copper after the insulating film is etched.

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