KR101001205B1

KR101001205B1 - Semiconductor device and method for manufacturing the same

Info

Publication number: KR101001205B1
Application number: KR20080043783A
Authority: KR
Inventors: 장상재
Original assignee: 앰코 테크놀로지 코리아 주식회사
Priority date: 2008-05-13
Filing date: 2008-05-13
Publication date: 2010-12-17
Also published as: KR20090118160A

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, in stacking a semiconductor chip on which a through silicon via (TSV) is formed at a wafer level, the portion of the semiconductor chip on which the through silicon via is formed is more than that. The present invention relates to a semiconductor device and a method of manufacturing the same, which can eliminate an underfill process of filling a filler between semiconductor chips stacked on each other and to reduce the thickness of the stack between semiconductor chips.

To this end, the present invention is a through-silicon via formed in a vertical direction from a position adjacent to the bonding pad on the upper surface of the semiconductor chip, the depth is smaller than the thickness of the semiconductor chip; A conductive metal embedded in the through silicon via; A stepped portion formed on a bottom surface of the edge of the semiconductor chip such that the lower end of the conductive metal is exposed to the outside; A semiconductor device and a method of manufacturing the same, wherein the conductive bumps are fused to a conductive metal exposed to the outside while the conductive bumps are positioned in the stepped portion so as to vertically stack the semiconductor chips.

Semiconductor Device, Through Silicon Via, Semiconductor Chip, Stacked, Stepped, Conductive Metal

Description

Semiconductor device and method for manufacturing the same

Three-dimensional lamination technology among packaging technologies of semiconductor integrated circuits has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance, and the three-dimensional lamination package has a plurality of chips having the same storage capacity. This is a stacked package, which is commonly referred to as a stacked chip package.

The technology of the multilayer chip package can reduce the manufacturing cost of the package by a simplified process, and also has advantages such as mass production, while lacking wiring space for the electrical connection inside the package due to the increase in the number and size of the stacked chips. The disadvantage is that.

That is, the conventional laminated chip package is manufactured in a structure in which a plurality of chips are attached to the chip attaching region of the substrate, so that the bonding pads of the chips and the conductive circuit patterns of the substrate are electrically connected to each other by wire, so that the wire bonding is possible. Space is needed for the circuit pattern area of the substrate to which the wire is connected, and thus the size of the semiconductor package is increased.

In view of this, a structure using through silicon vias has been proposed as an example of a stack package. As a through silicon via is formed in a chip, physical and electrical connections between chips are vertically formed by the through silicon vias. The structure is made to be made, and the conventional through-silicon via and chip stacking method using the same are as follows.

FIG. 3 is a cross-sectional view illustrating a conventional through silicon via forming method and a chip stacking method.

First, a vertical hole 12 is formed in a portion adjacent to the bonding pad 24 of each chip 10 at the wafer level, and an insulating film (not shown) is formed on the surface of the vertical hole 12.

In the state in which the seed metal film is formed on the insulating layer, the through silicon via 16 is formed by filling an electrolytic material, that is, the conductive metal 14, through the electroplating process in the vertical hole 12.

Next, the back surface of the wafer is back ground to expose the conductive metal 14 embedded in the through silicon via 16.

Subsequently, the wafer is sawed and separated into individual chips, and then at least two or more chips are stacked and stacked vertically on the substrate in a signal exchangeable manner via conductive metal of through silicon vias.

More specifically, in the electrical connection structure between the upper chip 10a and the lower chip 10b stacked on each other, the conductive metal 14 exposed to the bottom through the through silicon via 16 of the upper chip 10a and The conductive metals 14 exposed upward through the through silicon vias 16 of the lower chip 10b are electrically connected to each other by the conductive bumps 18.

Subsequently, the stacked upper and lower chips are mounted on a substrate, wire bonding between the substrate and the upper chip is performed, molded with a molding compound resin, and solder balls are mounted on the lower surface of the substrate to complete the stack package.

At this time, the thickness of the upper chip and the lower chip is about 20 ~ 25㎛, the conductive bump has a height of about 12㎛.

Therefore, a gap is formed between the upper chip and the lower chip by the height of the conductive bump.

When the gap between the upper chip and the lower chip is present, a problem may occur in that the injection pressure of the molding compound resin is concentrated in the gap during molding, causing cracks in the upper chip and the lower chip.

Accordingly, as shown in FIG. 3, an underfill process of filling a separate insulating filler 20 in the gap between the upper chip 10a and the lower chip 10b is performed to fill the gap.

However, since the gap between the upper chip and the lower chip is about 10 to 12 μm, it is difficult to fill the gap space with the insulating filler by the underfill process, and a portion of the gap space is properly filled with the insulating filler. It does not happen.

In addition, the stack height between the upper chip and the lower chip is increased as much as the conductive bumps and the underfilled insulating filler, and thus the stack height between the chips is increased, and thus, the semiconductor chip is manufactured in a smaller size and thinner. There is a disadvantage that the height of the manufactured semiconductor package is also increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and has a singulation step of forming through-silicon vias in a semiconductor chip at a wafer level, forming a thickness smaller than the thickness of the semiconductor chip, and separating the semiconductor chips in a wafer state into individual units. By removing the bottom edge of the semiconductor chip in the stepped shape at the same time to expose the lower end of the through-silicon via through the stepped portion, it is possible to reduce the thickness of the chip stacking, and to eliminate the conventional underfill process It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a through silicon via formed in a vertical direction from a position adjacent to a bonding pad on a top surface of a semiconductor chip, wherein the through silicon via is formed to a depth smaller than the thickness of the semiconductor chip; A conductive metal embedded in the through silicon via; A stepped portion formed on a bottom surface of the edge of the semiconductor chip such that the lower end of the conductive metal is exposed to the outside; It provides a semiconductor device characterized in that the configuration.

In a preferred embodiment, the conductive bumps are fused to the conductive metal exposed to the outside while the conductive bumps are positioned in the stepped portion so as to vertically stack the semiconductor chips.

The present invention for achieving the above object comprises: forming a vertical hole in a position adjacent to the bonding pad of each semiconductor chip at the wafer level, the vertical hole to a depth smaller than the thickness of the semiconductor chip; Forming an insulating film on a surface of the vertical hole; Embedding a conductive metal in a vertical hole in which the insulating layer is formed to form a through silicon via; Singulating each semiconductor chip in a wafer state individually, and forming a stepped portion at a bottom surface portion of each semiconductor chip such that a lower end portion of the conductive metal embedded in the through silicon via is exposed; It provides a semiconductor device manufacturing method comprising a.

In a preferred embodiment, the method further comprises fusing a conductive bump to an externally exposed conductive metal while placing the conductive bump in the stepped portion for stacking the semiconductor chips.

In another preferred embodiment, the stepped portion is characterized in that formed by the laser processing or the processing method by the blade for singulation used in the singulation process.

Through the above problem solving means, the present invention can provide the following effects.

1) The through silicon via is formed in the semiconductor chip, but the depth of the through silicon via may be shortened by forming a depth smaller than the thickness of the semiconductor chip.

2) In the singulation step of separating the semiconductor chips in the wafer state into individual units, a stepped portion is formed at the bottom edge of the semiconductor chip, and the lower end portion of the conductive metal filled in the through silicon via is exposed to the outside through the stepped portion. When the chip is stacked, conductive bumps are embedded in the stepped portion to reduce the chip stacking thickness.

3) When the chip is stacked, no gap is formed at the stacking boundary, so that the conventional underfill process can be eliminated, thereby reducing the number of steps and reducing the cost.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view sequentially illustrating a semiconductor device and a manufacturing method thereof according to the present invention.

First, through silicon vias 16 are formed in each semiconductor chip 10 in a wafer state.

That is, on the upper surface of each semiconductor chip 10 in the wafer state, a vertical hole 12 is formed at a position adjacent to the bonding pad 24, but the vertical hole 12 is formed to a depth smaller than the thickness of the semiconductor chip 10. To form.

In this case, the thickness of the semiconductor chip 10 is a thickness after wafer backgrinding, and has a thickness of about 20 to 25 μm, so that the vertical hole 12 is formed to a depth of 20 to 25 μm or less.

Next, an insulating film (not shown) is formed on the surface of the vertical hole 12, and then the conductive metal 14 is embedded in the vertical hole 12 where the insulating film is formed, thereby forming the through silicon via 16. Is complete.

Reference numeral 24 is a conductive pattern electrically connected between the bonding pad 24 of the semiconductor chip 10 and the conductive metal 14 of the through silicon via 16.

Subsequently, a wafer backgrinding process is performed until the wafer has a desired thickness, that is, the thickness of the semiconductor chip 10 is about 20 to 25 μm.

Of course, since the through silicon via 16 according to the present invention is formed to a depth smaller than the thickness of the semiconductor chip 10, the conductive metal 14 of the through silicon via 16 is formed through the bottom of the semiconductor chip 10. It is not exposed to the outside.

Next, a step of singulating each semiconductor chip 10 in a wafer state on an individual basis is performed.

That is, as the blade for singulation passes along each semiconductor chip boundary (singulation line) of the wafer, it is separated into individual semiconductor chips 10.

In this case, the conductive metal 14 embedded in the through silicon via 16 may be further removed in a stepped shape by removing the edge bottom portion of each semiconductor chip 10 by using a singulation blade. Make sure that the bottom of the is exposed.

In more detail, the stepped portion 22 is formed on the bottom of the edge of the semiconductor chip 10 by using a singulation blade, so that the conductive metal filled in the through silicon vias 16 of each semiconductor chip 10 is formed. 14) is in a state of being exposed to the outside.

In addition, the method of forming the stepped portion on the bottom of the edge of the semiconductor chip 10 may be formed using laser processing in addition to the method of using a singulation blade.

In the method of stacking the semiconductor chips provided as described above, the upper and lower chips 10a and 10b are stacked up and down, and the conductive bumps 18 are positioned in the stepped portion 22 of the upper chip 10a. The upper end of the bump 18 is fused to the conductive metal 14 of the through silicon via 16 of the upper chip 10a while the lower end of the conductive bump 18 is exposed through the upper surface of the lower chip 10b. It is made by fusing to the conductive metal 14 of (16).

In this case, as shown in FIG. 2, the insulating filler 20 may be easily filled through the underfill process to reinforce the conductive bumps 18 in the stepped part 22.

That is, since the space of the stepped portion 22 is exposed to the outside and thus forms a larger space than the gap space between the existing upper chip and the lower chip, the insulating filler 20 can be easily filled in the stepped portion 22. Can be.

As such, in the singulation step of separating the semiconductor chips in the wafer state into individual units, a stepped portion is formed at the bottom edge of the semiconductor chip, and the lower end portion of the conductive metal filled in the through silicon via is exposed to the outside through the stepped portion. As a result, conductive bumps are embedded in the stepped portions during chip stacking to reduce chip stacking thickness, and gaps are not formed in the stacking boundary portions during chip stacking, thereby eliminating the conventional underfill process.

1 is a cross-sectional view for sequentially explaining a semiconductor device and a manufacturing method thereof according to the present invention;

FIG. 2 is an enlarged cross-sectional view of a main portion illustrating that underfill may proceed as needed in a stepped portion of a semiconductor device according to the present disclosure; FIG.

3 is a cross-sectional view illustrating a conventional semiconductor device and a manufacturing method thereof in order.

10: semiconductor chip 10a: upper chip

10b: lower chip 12: vertical hole

14 conductive metal 16 through silicon via

18: conductive bump 20: insulating filler

22: stepped portion 24: bonding pad

Claims

A through silicon via 16 formed in a vertical direction from a position adjacent to the bonding pad 24 on the upper surface of the semiconductor chip 10 and having a depth smaller than the thickness of the semiconductor chip 10 and the through silicon via A semiconductor device comprising a conductive metal 14 embedded in 16

The stepped portion 22 is formed on the bottom surface of the edge of the semiconductor chip 10 so that the lower end of the conductive metal 14 is exposed to the outside, and the conductive bump 18 has a stepped portion 22 so as to vertically stack the semiconductor chips. And fused to the conductive metal (14) and filled with an insulating filler (20) for reinforcing the conductive bumps (18) in the stepped portion (22).

delete

Forming vertical holes at a wafer level adjacent to the bonding pads of the semiconductor chips, and forming vertical holes at a depth smaller than the thickness of the semiconductor chips;

Forming an insulating film on a surface of the vertical hole;

Embedding a conductive metal in a vertical hole in which the insulating layer is formed to form a through silicon via;

Singulating each semiconductor chip in a wafer state individually, and forming a stepped portion at a bottom surface portion of each semiconductor chip such that a lower end portion of the conductive metal embedded in the through silicon via is exposed;

A semiconductor device manufacturing method comprising a.

The method of manufacturing a semiconductor device according to claim 3, further comprising fusing a conductive bump to an externally exposed conductive metal while placing the conductive bump in the stepped portion for stacking the semiconductor chips.

The method of manufacturing a semiconductor device according to claim 3, wherein the stepped portion is formed by a machining method or a laser processing by a singulation blade used in a singulation process.