CN111128914A - Low-warpage multi-chip packaging structure and manufacturing method thereof - Google Patents
Low-warpage multi-chip packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN111128914A CN111128914A CN201911356873.5A CN201911356873A CN111128914A CN 111128914 A CN111128914 A CN 111128914A CN 201911356873 A CN201911356873 A CN 201911356873A CN 111128914 A CN111128914 A CN 111128914A
- Authority
- CN
- China
- Prior art keywords
- chip
- layer
- adapter plate
- conductive
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
The invention discloses a low-warpage multi-chip packaging structure, which comprises: an adapter plate; the adapter plate conductive through hole penetrates through the adapter plate; the first chip is flip-chip bonded to the front surface of the adapter plate and is electrically connected to the conductive through hole of the adapter plate; the underfill layer is arranged between the first chip and the adapter plate; the plastic packaging layer covers the upper part of the adapter plate and wraps the first chip and the bottom filling adhesive layer; the plastic packaging layer surface interconnection layer is arranged on the upper surface of the plastic packaging layer; the interlayer conductive interconnection structure is electrically connected with the conductive through hole of the adapter plate to the surface interconnection layer of the plastic package layer; a second chip disposed on the molding layer and electrically connected to the molding layer surface interconnection layer; and the external solder balls are arranged on the back surface of the adapter plate and are electrically connected to the conductive through holes of the adapter plate.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a low-warpage multi-chip packaging structure and a manufacturing method thereof.
Background
With the continuous development of microelectronic technology, users have higher and higher requirements on miniaturization, multiple functions, low power consumption and high reliability of systems, and especially in recent years, blowout required by portable handheld terminal markets, such as portable computers, smart phones, tablet computers and the like, has higher integration level and interconnection capacity. Three-dimensional stack packaging is a very effective technical approach to meet the above requirements.
In the existing three-dimensional stacked package structure, especially the three-dimensional fan-out package structure, one surface is usually made of silicon-based material, and the other surface is made of plastic package material. Due to the difference in material characteristics between the silicon material and the mold compound (e.g., resin material), warpage of the package structure is likely to occur after mold curing and during temperature change. The warpage directly results in the yield, reliability and lifetime of the package structure.
The invention provides a low-warpage multi-chip packaging structure and a manufacturing method thereof, aiming at the problem of warpage of the packaging structure caused by different materials on the upper and lower surfaces of the existing three-dimensional stacked packaging structure.
Disclosure of Invention
Aiming at the problem of package structure warpage caused by different materials on the upper and lower surfaces of the existing three-dimensional stacked package structure, according to one embodiment of the invention, a low-warpage multi-chip package structure is provided, which comprises:
an adapter plate;
the adapter plate conductive through hole penetrates through the adapter plate;
the first chip is flip-chip bonded to the front surface of the adapter plate and is electrically connected to the conductive through hole of the adapter plate;
the underfill layer is arranged between the first chip and the adapter plate;
the plastic packaging layer covers the upper part of the adapter plate and wraps the first chip and the bottom filling adhesive layer;
the plastic packaging layer surface interconnection layer is arranged on the upper surface of the plastic packaging layer;
the interlayer conductive interconnection structure is electrically connected with the conductive through hole of the adapter plate to the surface interconnection layer of the plastic package layer;
a second chip disposed on the molding layer and electrically connected to the molding layer surface interconnection layer; and
and the external solder balls are arranged on the back surface of the adapter plate and are electrically connected to the conductive through holes of the adapter plate.
In an embodiment of the present invention, the front surface of the interposer is further provided with a front surface layout wiring layer, and the front surface layout wiring layer is electrically connected to the interposer conductive through holes.
In one embodiment of the present invention, the first chip is flip-chip bonded to the chip pad of the front-side layout wiring layer.
In one embodiment of the invention, the number of the first chips is M, wherein M is more than or equal to 2.
In one embodiment of the present invention, the interlayer conductive interconnection structure is a plastic encapsulation layer conductive via.
In one embodiment of the present invention, the interlayer conductive interconnect structure is a bonding wire.
In an embodiment of the invention, a back layout wiring layer is further disposed on the back surface of the interposer, the back layout wiring layer is electrically connected to the interposer conductive through holes, and the external solder balls are electrically connected to the back layout wiring layer.
According to another embodiment of the invention, a manufacturing method for forming the low-warpage multi-chip package structure is provided, which comprises the following steps:
the method comprises the steps of flip-chip bonding a first chip to the front surface of an adapter plate with blind holes TSV;
forming an underfill layer below the first chip;
carrying out integral plastic package on the front surface of the butt joint plate to form a plastic package layer wrapping the first chip and the bottom filling adhesive layer;
forming a plastic packaging layer conductive through hole in the plastic packaging layer;
forming a wiring layer on the upper surface of the plastic packaging layer;
aligning the wafer containing the second chip with the wiring layer of the plastic packaging layer and then carrying out wafer-level bonding;
thinning the back of the adapter plate to realize the exposure of the back of the TSV; and
and forming external solder balls.
According to another embodiment of the invention, a manufacturing method for forming the low-warpage multi-chip package structure is provided, which includes:
the method comprises the steps of flip-chip bonding a first chip to the front surface of an adapter plate with blind holes TSV;
forming an underfill layer below the first chip;
carrying out integral plastic package on the front surface of the butt joint plate to form a plastic package layer wrapping the first chip and the bottom filling adhesive layer;
forming a wiring layer on the upper surface of the plastic packaging layer;
aligning the wafer containing the second chip with the wiring layer on the plastic packaging layer and then carrying out wafer-level bonding;
etching the wafer containing the second chip to expose the bonding pad of the plastic packaging layer;
the TSV bonding pads of the adapter plate are exposed by ablation of the plastic packaging layer;
forming an interconnection structure for electrically connecting the wiring layer bonding pad of the plastic packaging layer to the TSV bonding pad of the adapter plate;
thinning the back of the adapter plate to realize the exposure of the back of the TSV; and
and forming external solder balls.
In another embodiment of the invention, after the back face of the adapter plate is thinned to realize the exposure of the back face of the TSV, a wiring layer on the back face of the adapter plate is formed; and separating the packaging structures to form independent low-warpage multi-chip packaging structures.
The invention provides a low-warpage multi-chip packaging structure and a manufacturing method thereof. The low-warpage multi-chip packaging structure and the manufacturing method thereof provided by the invention have the following advantages: 1) the multi-chip integrated package has small volume; 2) the upper layer and the lower layer of silicon of the packaging structure can reduce the warpage; 3) the process difficulty of plastic packaging warping tape-out is improved.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 illustrates a cross-sectional view of a low warpage multi-chip package structure 100 in accordance with one embodiment of the present invention.
Fig. 2A-2D are cross-sectional views illustrating a process of forming the low warpage multi-chip package structure 100 according to an embodiment of the invention.
Fig. 3 illustrates a flow chart 300 for forming the low warpage multi-chip package structure 100 in accordance with one embodiment of the present invention.
Fig. 4 illustrates a cross-sectional view of a low warpage multi-chip package structure 400 in accordance with yet another embodiment of the present invention.
Fig. 5A-5G illustrate cross-sectional views of a process for forming the low warpage multi-chip package structure 400 according to one embodiment of the present invention.
Fig. 6 illustrates a flow chart 600 for forming the low warpage multi-chip package structure 400 according to one embodiment of the present invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
It should be noted that, in the embodiments of the present invention, the process steps are described in a specific order, however, this is only for convenience of distinguishing the steps, and the order of the steps is not limited, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
The invention provides a low-warpage multi-chip packaging structure and a manufacturing method thereof. The low-warpage multi-chip packaging structure and the manufacturing method thereof provided by the invention have the following advantages: 1) the multi-chip integrated package has small volume; 2) the upper layer and the lower layer of silicon of the packaging structure can reduce the warpage; 3) the process difficulty of plastic packaging warping tape-out is improved.
A low warpage multi-chip package structure according to an embodiment of the present invention is described in detail below with reference to fig. 1. Fig. 1 illustrates a cross-sectional view of a low warpage multi-chip package structure 100 in accordance with one embodiment of the present invention. As shown in fig. 1, the low warpage multi-chip package structure 100 further includes an interposer 110, interposer conductive vias 120, a first chip 130, an underfill 140, a molding compound layer 150, a molding compound layer conductive via 160, a molding compound layer surface interconnection layer 170, a second chip 180, and external solder balls 190.
Interposer 110 is typically a silicon interposer with a thickness between 50 microns and 300 microns. In one embodiment of the present invention, the interposer 110 may also be formed of other materials such as glass, silicon carbide, ceramic, and the like.
The interposer conductive via 120 is disposed through the interposer 110. In an embodiment of the present invention, the front surface and the back surface of the interposer 110 are further formed with interconnection layers, wherein a chip pad is further disposed on an outermost layer of the front interconnection layer, and an external pad is further disposed on an outermost layer of the back interconnection layer.
The first chip 130 is disposed above the interposer 110. In one embodiment of the present invention, the first chip 130 has a plurality of first chips 130-1 and 130-2, wherein the first chip 130-1 and the first chip 130-2 may be the same type or different types of chips. In still another embodiment of the present invention, the first chip 130 is disposed on the chip pad of the interconnection layer on the upper surface of the interposer 110 by flip-chip bonding.
An underfill 140 is disposed between the first chip 130 and the interposer 110 for insulation and mechanical protection of the flip-chip structure.
The molding compound layer 150 covers the entire upper surface of the interposer 110, encapsulating the first chip 130 and the underfill 140.
The molding layer conductive via 160 is separated from the first chip 130 in the vertical direction and penetrates through the molding layer 150, wherein the molding layer conductive via 160 is electrically connected to the interposer conductive via 120. In an embodiment of the present invention, the molding layer conductive via 160 may be a metal conductive via made of copper or a conductive via made of silver paste.
The molding layer surface interconnection layer 170 is disposed on the upper surface of the molding layer 150 and electrically connected to the molding layer conductive via 160. And further electrically connected to interposer vias 120 through molding layer conductive vias 160. In one embodiment of the present invention, the outermost layer of the molding layer surface interconnect layer 170 has chip pads.
The second chip 180 is disposed over the molding layer surface interconnection layer 170 and electrically connected to the molding layer surface interconnection layer 170 through a chip bonding structure 185. The second chip 180 is further electrically connected to the interposer via 120 through the molding layer surface interconnection layer 170 and the molding layer conductive via 160.
The external solder balls 190 are disposed under the interposer 110 and electrically connected to the interposer conductive vias 120, which serve as electrical and/or signal interconnections for the package structure to external circuits and systems.
A method of forming the low warpage multi-chip package structure 100 according to one embodiment of the present invention is described in detail below with reference to fig. 2A-2D and fig. 3. FIGS. 2A-2D are schematic cross-sectional views illustrating a process of forming the low warpage multi-chip package structure 100 according to one embodiment of the present invention; fig. 3 illustrates a flow chart 300 for forming the low warpage multi-chip package structure 100 in accordance with one embodiment of the present invention.
First, in step 310, as shown in fig. 2A, the first chips 230-1 and 230-2 are flip-chip bonded to the front surface of the interposer 210 with the blind vias TSV 220, underfill is performed below the first chip 230 to form an underfill layer 240, and then the front surface of the interposer 210 is integrally molded to form a molding layer 250 that is located on the front surface of the interposer 210 and covers the first chip 230 and the underfill 240. In one embodiment of the present invention, the front surface of the interposer 210 further has a layout wiring layer, a chip pad is disposed on the outermost layout wiring layer, and the first chip 230 is flip-chip bonded to the corresponding chip pad. In another embodiment of the present invention, the layout wiring layer on the upper surface of the interposer 210 has multiple layers.
Next, in step 320, as shown in fig. 2B, a molding layer conductive via 260 is formed in the molding layer 250, and a wiring layer 270 is formed on the upper surface of the molding layer 250. In one embodiment of the present invention, the wiring layer 270 has a single layer or a plurality of layers, wherein a chip pad or a conductive bonding material is disposed on the outermost wiring layer 270.
Then, in step 330, as shown in fig. 2C, the wafer containing the second chip 280 is aligned with the wiring layer 270 of the molding layer 250 and wafer level bonding is performed. After bonding, the chip pad 285 of the second chip 280 is electrically connected to the wiring layer 270, and further electrically connected to the molding layer conductive via 260 through the wiring layer 270.
Finally, in step 340, as shown in fig. 2D, the back surface of the interposer 210 is thinned, so as to expose the back surface of the TSV 220, and an external solder ball 290 is formed. The external solder balls 290 are electrically connected to the TSVs 220. In an embodiment of the present invention, a bottom interconnect layer/re-routing wiring layer may also be formed on the backside of interposer 210 where TSV 220 backside outcrops are implemented.
Optionally, the package structures are separated to form an independent low warpage multi-chip package structure.
A low warpage multi-chip package structure according to another embodiment of the present invention will be described in detail with reference to fig. 4. Fig. 4 illustrates a cross-sectional view of a low warpage multi-chip package structure 400 in accordance with yet another embodiment of the present invention. As shown in fig. 4, the low warpage multi-chip package structure 400 further includes an interposer 410, interposer conductive vias 420, a first chip 430, an underfill 440, a molding compound 450, bonding wires/pad connecting wires 460, a molding compound surface interconnect layer 470, a second chip 480, and external solder balls 490.
The low warpage multi-chip package structure 400 differs from the low warpage multi-chip package structure 100 described above in that the molding layer surface interconnect layer 470 is electrically connected to the interposer conductive vias 420 by bonding wire/pad connecting wires 460.
A method of forming the low warpage multi-chip package structure 400 according to one embodiment of the present invention is described in detail below with reference to fig. 5A-5G and fig. 6. FIGS. 5A-5G are cross-sectional views illustrating a process of forming the low warpage multi-chip package structure 400 according to one embodiment of the present invention; fig. 6 illustrates a flow chart 600 for forming the low warpage multi-chip package structure 400 according to one embodiment of the present invention.
First, in step 610, as shown in fig. 5A, a first chip 530-1, 530-2 is flip-chip bonded to the front surface of the interposer 510 with the blind via TSV 520, underfill is performed below the first chip 530 to form an underfill layer 540, and then the front surface of the interposer 510 is integrally molded to form a molding compound 550 that is located on the front surface of the interposer 510 and covers the first chip 530 and the underfill 540. In one embodiment of the present invention, the front surface of the interposer 510 further has a layout wiring layer, a chip pad is disposed on the outermost layout wiring layer, and the first chip 530 is flip-chip bonded to the corresponding chip pad. In yet another embodiment of the present invention, the layout wiring layer on the upper surface of the interposer 510 has a plurality of layers.
Next, in step 620, as shown in fig. 5B, a wiring layer 560 is formed on the upper surface of the molding layer 550. In one embodiment of the present invention, the wiring layer 560 has a single layer or multiple layers, wherein a chip pad or a conductive bonding material is disposed on the outermost wiring layer 560.
Then, in step 630, as shown in fig. 5C, the wafer containing the second chip 570 is aligned with the wiring layer 560 on the molding layer 550, and then wafer-level bonding is performed. The die pad 575 of the second die 570 is electrically connected to the wiring layer 560 after bonding.
Next, at step 640, as shown in fig. 5D, the wafer 570 is etched to expose the molding layer pad 560. In an embodiment of the present invention, the pad opening of the plastic encapsulation layer wiring layer 560 is realized by performing wet or dry etching on the wafer on which the second chip 570 is located.
Then, in step 650, as shown in fig. 5E, the molding layer is ablated to expose the TSV pads 520 of the interposer. In one embodiment of the present invention, the interposer TSV 520 pad opening is achieved by laser ablation or mechanical grooving of the molding layer 550.
Next, in step 660, as shown in fig. 5F, wire bonding is performed to form a bonding wire 580 electrically connecting the pad of the molding layer wiring layer 560 to the pad of the interposer TSV 520, and protective molding of the bonding wire 580 is performed to form a molding layer 555. Alternatively, as shown in fig. 5F', a wiring structure 580 for electrically connecting the pad of the plastic package layer wiring layer 560 to the pad of the interposer TSV 520 is formed by a wiring method, and a plastic package layer 555 is formed by plastic package.
Finally, in step 670, as shown in fig. 5G, the back surface of the interposer 510 is thinned, so as to expose the back surface of the TSV 520, and an external solder ball 590 is formed. The external solder balls 590 are electrically connected to the TSVs 520. In one embodiment of the present invention, a bottom interconnect layer/re-routing wiring layer may also be formed on the backside of the interposer 510 where the TSV 520 backside outcrop is implemented.
Optionally, the package structures are separated to form an independent low warpage multi-chip package structure.
Based on the low-warpage multi-chip packaging structure and the manufacturing method thereof, a plurality of chips are inversely welded on a TSV-containing wafer level adapter plate, underfill is filled to form a plastic packaging layer, a wiring layer and a conductive structure electrically connected to a TSV pad are formed on the top surface of the plastic packaging layer, then wafer level bonding is adopted on the plastic packaged wafer to realize that the wafer level packaging structure is silicon-plastic packaging layer-silicon, and finally back thinning is carried out on the wafer level adapter plate to realize that an external welding ball is formed after the TSV is exposed. The low-warpage multi-chip packaging structure and the manufacturing method thereof provided by the invention have the following advantages: 1) the multi-chip integrated package has small volume; 2) the upper layer and the lower layer of silicon of the packaging structure can reduce the warpage; 3) the process difficulty of plastic packaging warping tape-out is improved.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A low warpage multi-chip package structure, comprising:
an adapter plate;
the adapter plate conductive through hole penetrates through the adapter plate;
the first chip is flip-chip bonded to the front surface of the adapter plate and is electrically connected to the conductive through hole of the adapter plate;
the underfill layer is arranged between the first chip and the adapter plate;
the plastic packaging layer covers the upper part of the adapter plate and wraps the first chip and the bottom filling adhesive layer;
the plastic packaging layer surface interconnection layer is arranged on the upper surface of the plastic packaging layer;
the interlayer conductive interconnection structure is electrically connected with the conductive through hole of the adapter plate to the surface interconnection layer of the plastic package layer;
a second chip disposed on the molding layer and electrically connected to the molding layer surface interconnection layer; and
and the external solder balls are arranged on the back surface of the adapter plate and are electrically connected to the conductive through holes of the adapter plate.
2. The low warpage multi-chip package structure of claim 1, wherein the front side of the interposer is further provided with a front layout wiring layer electrically connected to the interposer conductive vias.
3. The low warpage multi-chip package structure of claim 2, wherein the first chip is flip-chip bonded to a chip pad of the front side layout wiring layer.
4. The low warpage multi-chip package structure of claim 1 or 3, wherein the number of the first chips is M, wherein M ≧ 2.
5. The low warpage multi-chip package structure of claim 1, wherein the interlayer conductive interconnect structure is a molding layer conductive via.
6. The low warpage multi-chip package structure of claim 1, wherein the interlayer conductive interconnect structure is a wire bond.
7. The low warpage multi-chip package structure of claim 1, wherein a backside layout wiring layer is further disposed on the backside of the interposer, the backside layout wiring layer is electrically connected to the interposer conductive vias, and the external solder balls are electrically connected to the backside layout wiring layer.
8. A manufacturing method for forming the low-warpage multi-chip packaging structure comprises the following steps:
the method comprises the steps of flip-chip bonding a first chip to the front surface of an adapter plate with blind holes TSV;
forming an underfill layer below the first chip;
carrying out integral plastic package on the front surface of the butt joint plate to form a plastic package layer wrapping the first chip and the bottom filling adhesive layer;
forming a plastic packaging layer conductive through hole in the plastic packaging layer;
forming a wiring layer on the upper surface of the plastic packaging layer;
aligning the wafer containing the second chip with the wiring layer of the plastic packaging layer and then carrying out wafer-level bonding;
thinning the back of the adapter plate to realize the exposure of the back of the TSV; and
and forming external solder balls.
9. A manufacturing method for forming the low-warpage multi-chip packaging structure comprises the following steps:
the method comprises the steps of flip-chip bonding a first chip to the front surface of an adapter plate with blind holes TSV;
forming an underfill layer below the first chip;
carrying out integral plastic package on the front surface of the butt joint plate to form a plastic package layer wrapping the first chip and the bottom filling adhesive layer;
forming a wiring layer on the upper surface of the plastic packaging layer;
aligning the wafer containing the second chip with the wiring layer on the plastic packaging layer and then carrying out wafer-level bonding;
etching the wafer containing the second chip to expose the bonding pad of the plastic packaging layer;
the TSV bonding pads of the adapter plate are exposed by ablation of the plastic packaging layer;
forming an interconnection structure for electrically connecting the wiring layer bonding pad of the plastic packaging layer to the TSV bonding pad of the adapter plate;
thinning the back of the adapter plate to realize the exposure of the back of the TSV; and
and forming external solder balls.
10. The manufacturing method of forming the low warpage multi-chip package structure as claimed in claim 8 or 9, forming a wiring layer on the back side of the interposer after the thinning of the back side of the interposer is completed to expose the back side of the TSV; and separating the packaging structures to form independent low-warpage multi-chip packaging structures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911356873.5A CN111128914A (en) | 2019-12-25 | 2019-12-25 | Low-warpage multi-chip packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911356873.5A CN111128914A (en) | 2019-12-25 | 2019-12-25 | Low-warpage multi-chip packaging structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111128914A true CN111128914A (en) | 2020-05-08 |
Family
ID=70503615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911356873.5A Pending CN111128914A (en) | 2019-12-25 | 2019-12-25 | Low-warpage multi-chip packaging structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111128914A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900095A (en) * | 2020-08-12 | 2020-11-06 | 上海先方半导体有限公司 | Multi-chip integrated packaging method and packaging structure |
| CN112234027A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 2.5D electronic packaging structure |
| WO2022151572A1 (en) * | 2021-01-18 | 2022-07-21 | 华进半导体封装先导技术研发中心有限公司 | Packaging structure for reducing warpage of molded wafer, and manufacturing method therefor |
| WO2023104095A1 (en) * | 2021-12-08 | 2023-06-15 | Tongfu Microelectronics Co., Ltd. | Fan-out packaging method and packaging structure of stacked chips thereof |
| WO2024001429A1 (en) * | 2022-06-30 | 2024-01-04 | 华进半导体封装先导技术研发中心有限公司 | System-on-wafer packaging structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110183464A1 (en) * | 2010-01-26 | 2011-07-28 | Texas Instruments Incorporated | Dual carrier for joining ic die or wafers to tsv wafers |
| CN103165479A (en) * | 2013-03-04 | 2013-06-19 | 江苏物联网研究发展中心 | Manufacture method of multi-chip and system-level packaging structure |
| CN103346097A (en) * | 2013-06-25 | 2013-10-09 | 华进半导体封装先导技术研发中心有限公司 | Method and structure for three-dimensional packaging based on TSV |
| CN104064551A (en) * | 2014-06-05 | 2014-09-24 | 华为技术有限公司 | Chip-stacking encapsulation structure and electronic equipment |
| CN105575938A (en) * | 2016-02-26 | 2016-05-11 | 中国科学院微电子研究所 | Silicon-based adapter plate and manufacturing method thereof |
-
2019
- 2019-12-25 CN CN201911356873.5A patent/CN111128914A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110183464A1 (en) * | 2010-01-26 | 2011-07-28 | Texas Instruments Incorporated | Dual carrier for joining ic die or wafers to tsv wafers |
| CN103165479A (en) * | 2013-03-04 | 2013-06-19 | 江苏物联网研究发展中心 | Manufacture method of multi-chip and system-level packaging structure |
| CN103346097A (en) * | 2013-06-25 | 2013-10-09 | 华进半导体封装先导技术研发中心有限公司 | Method and structure for three-dimensional packaging based on TSV |
| CN104064551A (en) * | 2014-06-05 | 2014-09-24 | 华为技术有限公司 | Chip-stacking encapsulation structure and electronic equipment |
| CN105575938A (en) * | 2016-02-26 | 2016-05-11 | 中国科学院微电子研究所 | Silicon-based adapter plate and manufacturing method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900095A (en) * | 2020-08-12 | 2020-11-06 | 上海先方半导体有限公司 | Multi-chip integrated packaging method and packaging structure |
| CN112234027A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 2.5D electronic packaging structure |
| WO2022151572A1 (en) * | 2021-01-18 | 2022-07-21 | 华进半导体封装先导技术研发中心有限公司 | Packaging structure for reducing warpage of molded wafer, and manufacturing method therefor |
| WO2023104095A1 (en) * | 2021-12-08 | 2023-06-15 | Tongfu Microelectronics Co., Ltd. | Fan-out packaging method and packaging structure of stacked chips thereof |
| WO2024001429A1 (en) * | 2022-06-30 | 2024-01-04 | 华进半导体封装先导技术研发中心有限公司 | System-on-wafer packaging structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11239157B2 (en) | Package structure and package-on-package structure | |
| US9881863B2 (en) | Semiconductor packages and methods of packaging semiconductor devices | |
| US10867897B2 (en) | PoP device | |
| US10276553B2 (en) | Chip package structure and manufacturing method thereof | |
| KR101640076B1 (en) | Stacked chip package and method for manufacturing the same | |
| KR101461630B1 (en) | Wafer level chip on chip package, package on package improving solder joint reliability but reducing mounting height and manufacturing method thereof | |
| KR100895813B1 (en) | Method for fabricating of semiconductor package | |
| KR100871382B1 (en) | Through silicon via stack package and method for manufacturing of the same | |
| JP4742079B2 (en) | Wafer level system-in-package and manufacturing method thereof | |
| TWI445152B (en) | Semiconductor structure and method for manufacturing the same | |
| TWI482261B (en) | Three-dimensional system-in-package package-on-package structure | |
| CN109300837B (en) | Thin 3D fan-out packaging structure and wafer level packaging method | |
| CN111128914A (en) | Low-warpage multi-chip packaging structure and manufacturing method thereof | |
| CN109003961B (en) | 3D system integrated structure and manufacturing method thereof | |
| CN111052371A (en) | Semiconductor device with laterally offset stacked semiconductor die | |
| KR102556517B1 (en) | Stack package include bridge die | |
| EP2779237A2 (en) | A chip arrangement and a method for manufacturing a chip arrangement | |
| US20120146216A1 (en) | Semiconductor package and fabrication method thereof | |
| KR20080038035A (en) | Semiconductor package and stacked layer type semiconductor package | |
| US20220310577A1 (en) | Semiconductor package | |
| CN110676240A (en) | 2.5D packaging structure and manufacturing method thereof | |
| CN213936169U (en) | Secondary plastic package packaging structure | |
| KR100983471B1 (en) | Semiconductor device and method for manufacturing the same | |
| US11227814B2 (en) | Three-dimensional semiconductor package with partially overlapping chips and manufacturing method thereof | |
| CN210692483U (en) | Packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200508 |