CN202633291U - Chip-on-chip packaging structure - Google Patents
Chip-on-chip packaging structure Download PDFInfo
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- CN202633291U CN202633291U CN2011205698581U CN201120569858U CN202633291U CN 202633291 U CN202633291 U CN 202633291U CN 2011205698581 U CN2011205698581 U CN 2011205698581U CN 201120569858 U CN201120569858 U CN 201120569858U CN 202633291 U CN202633291 U CN 202633291U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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Abstract
Disclosed is a chip-on-chip packaging structure, comprising a lead frame, a first metal material layer, a second metal material layer, a female IC chip, a sub-IC chip, a spacer, a paste material, insulation filling material, and plastic packaging material, wherein the lead frame comprises a chip carrier and multiple pins which surround the chip carrier and are arranged in multiple loops; the first metal material layer and the second metal material layer are respectively arranged upon the upper surface and lower surface of the lead frame; the insulation filling material is arranged under the steplike structure of the lead frame; the female IC chip is arranged at the position of the first metal material layer upon the upper surface of the lead frame; the sub-IC chip is arranged above the female IC chip; the female IC chip and the sub-IC chip are respectively connected to the inner pins of the multiple loops of pins via metal leads; and the plastic packaging material forms a packaging part by coating the female IC chip and the sub-IC chip. The chip-on-chip packaging structure, based on QFN packaging, is a three-dimensional packaging structure featuring high reliability, low cost, and high I/O density.
Description
Technical field
The utility model relates to semiconductor components and devices manufacturing technology field, refers more particularly to chip on the chip with many circle pin arrangements (Chip on Chip, CoC) encapsulation.
Background technology
Along with electronic product such as mobile phone, notebook computer etc. towards miniaturization; Portable; Ultra-thinization, multimedization and satisfy popular needed low-cost direction and develop, high density, high-performance, high reliability and packing forms and packaging technology thereof have obtained development fast cheaply.Compare with packing forms such as expensive BGA; Fast-developing in recent years novel encapsulated technology; I.e. four limit flat non-pin QFN (Quad Flat Non-lead Package) encapsulation; Because have good hot property and electrical property, size is little, cost is low and numerous advantages such as high production rate, has caused a new revolution in microelectronic packaging technology field.
Figure 1A and Figure 1B are respectively the schematic rear view of traditional Q FN encapsulating structure and along the generalized section of I-í section; This QFN encapsulating structure comprises lead frame 11, capsulation material 12, bonding die material 13; IC chip 14; Plain conductor 15, wherein lead frame 11 comprises chip carrier 111 and the pin of arranging around chip carrier 111 112 all around, IC chip 14 is fixed on the chip carrier 111 through bonding die material 13; IC chip 13 is realized being electrically connected through plain conductor 15 with the pin of arranging all around 112; 12 pairs of IC chips 14 of capsulation material, plain conductor 15 and lead frame 11 are sealed with the effect that reaches protection and support, and pin 112 exposes in the bottom surface of capsulation material 12, are welded on through scolder on the circuit board such as PCB to realize and extraneous being electrically connected.The exposed chip carrier in bottom surface 111 is welded on through scolder on the circuit board such as PCB, has direct heat dissipation channel, can effectively discharge the heat that IC chip 14 produces.Compare with traditional T SOP and SOIC encapsulation, the QFN encapsulation does not have gull wing lead-in wire, and conductive path is short, and coefficient of self-inductance and impedance are low, thereby good electrical properties can be provided, and can satisfy at a high speed or the application of microwave.Exposed chip carrier provides remarkable heat dispersion.
The continuous enhancing of the raising of As IC integrated level and function; The I/O number of IC increases thereupon, the also corresponding increase of I/O number of pins of corresponding Electronic Packaging, and gradually by traditional two-dimensional planar package form to the more 3 D stereo packing forms development of high integration; Four traditional limit flat non-pin packaging parts are typical two dimensional surface packing forms; The pin of individual pen is periphery around chip carrier to be arranged, and has limited the raising of I/O quantity, has satisfied not high density, has had the needs of the IC of more I/O numbers.Traditional lead frame does not have the staircase structural model design; Can't effectively pin plastic material; Cause lead frame and capsulation material bond strength low; Be easy to cause the layering of lead frame and capsulation material even coming off of pin or chip carrier, and can't effectively stop moisture to be diffused into Electronic Packaging inside, thereby had a strong impact on the reliability of packaging body along lead frame and capsulation material combination interface.Traditional Q FN product needs in advance at the lead frame back side Continuous pressing device for stereo-pattern to treat also need remove cleanings such as adhesive tape, plastic packaging material overlap behind the plastic packaging to prevent the flash phenomenon when plastic package process, has increased packaging cost and has increased.Use four traditional limit flat non-pin packaging parts of cutter cutting and separating; Cutter also can cut to the lead frame metal in the cutting capsulation material; Not only can cause the reduction and the shortening in cutting blade life-span of cutting efficiency; And can produce metallic bur power, influenced the reliability of packaging body.Therefore, for the bottleneck of the low I/O quantity that breaks through traditional Q FN, the reliability that improves packaging body with reduce packaging cost, be badly in need of the three-dimension packaging structure and the manufacturing approach thereof of a kind of high reliability of research and development, low cost, high I/O density based on the QFN encapsulation.
The utility model content
The utility model provides a kind of high density, enclose on the chip of pin arrangements chip (Chip on Chip, CoC) encapsulation and manufacturing approach thereof are with the purpose of bottleneck that reaches the low I/O quantity that breaks through traditional Q FN and the reliability that improves packaging body more.
To achieve these goals, the utility model adopts following technical proposals:
The utility model proposes chip package structure on a kind of chip, comprises lead frame, first metal material layer, second metal material layer, female IC chip, sub-IC chip, insulation filling material, adhesive material, partition, plain conductor and capsulation material.Lead frame has staircase structural model along thickness direction, has upper surface, lower surface and ledge surface.Lead frame comprises chip carrier and a plurality of pin that is many circle arrangements around chip carrier.Chip carrier is disposed at the lead frame central part, and edge, chip carrier four limit has staircase structural model along thickness direction.To be the shape of cross section that encloses the pin of arranging around chip carrier rounded or rectangular-shaped more, and wherein each pin comprises interior pin that is disposed at this upper surface and the outer pin that is disposed at this lower surface.First metal material layer and second metal material layer are disposed at the upper surface position and the lower surface position of lead frame respectively.Insulation filling material is disposed under the staircase structural model of lead frame, supports, protects lead frame.Female IC chip is disposed at the first metal material layer position of lead frame upper surface through adhesive material, and is fixed in the central part of chip carrier.Sub-IC chip is disposed on the face of having chance with of female IC chip through adhesive material, or on the face of having chance with of female IC chip, disposes partition, with sub-IC chip configuration on partition.A plurality of bonding welding pads on female IC chip and the sub-IC chip are connected to the interior pin of a plurality of pins that dispose first metal material layer respectively through plain conductor, to realize electrical interconnection.Capsulation material; Coat female IC chip, sub-IC chip, plain conductor, adhesive material, lead frame and first metal material layer; Form packaging part, perhaps coat female IC chip, sub-IC chip, plain conductor, partition, lead frame and first metal material layer, form packaging part.
Further, the chip package structure comprises one or more sub-IC chips on the said chip; Be connected through adhesive material or partition between sub-IC chip and the sub-IC chip.
Further, above-mentioned lead frame has a plurality of chip carriers that center on and is the pins that many circles are arranged, and the pin shape of cross section is circle or rectangle, and the arrangement number of turns is more than individual pen, two circle or three enclose.
Further, it is characterized in that many circles pin arrangements mode on the every limit of chip carrier is for being arranged in parallel or being staggered.
According to the embodiment of the utility model, nead frame has a plurality of pins that are three circle arrangements around chip carrier.
According to the embodiment of the utility model, comprise chip carrier and have staircase structural model around the lead frame that chip carrier is the pin that three circles arrange.
According to the embodiment of the utility model, be the rounded shape of shape of cross section of the pin of three circle arrangements around chip carrier.
According to the embodiment of the utility model, be the shape of cross section rectangular shaped of the pin of three circle arrangements around chip carrier.
According to the embodiment of the utility model, the pin arrangements mode on the every limit of chip carrier is for being arranged in parallel.
According to the embodiment of the utility model, the pin arrangements mode on the every limit of chip carrier is for being staggered.
According to the embodiment of the utility model, lead frame upper surface and lower surface dispose first metal material layer and second metal material layer respectively.
According to the embodiment of the utility model, first metal material layer that lead frame upper surface and lower surface dispose respectively and second metal material layer comprise nickel (Ni), palladium (Pd), gold (Au) metal material.
According to the embodiment of the utility model, the lead frame staircase structural model is the configuration insulation filling material down.
According to the embodiment of the utility model, lead frame staircase structural model configuration insulation filling material kind down is the thermosetting capsulation material, perhaps materials such as plug socket resin, printing ink and resistance weldering green oil.
According to the embodiment of the utility model, with adhesive materials such as the epoxy resin of argentiferous particle or adhesive tapes with female IC chip configuration in the chip carrier central part.
According to the embodiment of the utility model, sub-IC chip is disposed on the face of having chance with of female IC chip through adhesive material.
According to the embodiment of the utility model, on the face of having chance with of female IC chip, dispose partition, with sub-IC chip configuration on partition.
According to the embodiment of the utility model, the material of partition is silicon (Si) material, to mate female IC chip and sub-IC chip.
The utility model proposes the manufacturing approach of chip package on a kind of chip, may further comprise the steps:
Step 1: configuration mask material layer
The thin plate base material is cleaned and preliminary treatment, have the mask material layer pattern of window in the upper surface of thin plate base material and lower surface configuration.
Step 2: configuration metal material layer
In the window of the mask material layer that is disposed at thin plate base material upper surface and lower surface, dispose first metal material layer and second metal material layer respectively.
Step 3: the lower surface selectivity is partially-etched
Removing the mask material layer of thin plate base material lower surface, is resist layer with second metal material layer, and it is partially-etched that thin plate base material lower surface is carried out selectivity, forms groove.
Step 4: configuration insulation filling material
Etch partially fill insulant in the groove of formation in thin plate base material lower part through selectivity.
Step 5: the upper surface selectivity is partially-etched
Removing the mask material layer of thin plate base material upper surface, is corrosion preventing layer with first metal material layer, and it is partially-etched that thin plate base material upper surface is carried out selectivity, forms the lead frame with staircase structural model, comprises the chip carrier and many circle pins of separation.
Step 6: dispose female IC chip
Adhesive materials such as epoxy resin resin through the argentiferous particle or adhesive tape with female IC chip configuration in the chip carrier central part.
Step 7: dispose sub-IC chip
Adhesive materials such as epoxy resin resin through the argentiferous particle or adhesive tape on the face of having chance with of female IC chip, perhaps dispose partition with sub-IC chip configuration on the face of having chance with of female IC chip, with sub-IC chip configuration on partition.
Step 8: the plain conductor bonding connects
A plurality of bonding welding pads on female IC chip and the sub-IC chip are connected to respectively through plain conductor on the interior pin of a plurality of pins that dispose first metal material layer, to realize electrical interconnection.
Step 9: plastic packaging
Coat female IC chip, sub-IC chip, plain conductor, adhesive material, lead frame and first metal material layer through capsulation material; Form packaging part and produce array; Perhaps coat female IC chip, sub-IC chip, plain conductor, partition, lead frame and first metal material layer, form the packaging part product array.
Step 10: print
Product array behind the plastic packaging is carried out laser printing.
Step 11: cutting and separating product
The cutting and separating product forms independently single package.
According to the embodiment of the utility model, chemical plating method disposes first metal material layer and second metal material layer through electroplating perhaps.
According to the embodiment of the utility model, be resist layer with second metal material layer, select for use the etching solution of etched sheet base material only partially-etched to thin plate base material upper surface and lower surface selectivity.
According to the embodiment of the utility model, insulation filling material is configured in through methods such as silk screen printing or coatings and etches partially in the groove.
According to the embodiment of the utility model, select method cutting and separating products such as blade cuts, laser cutting or the cutting of water cutter for use, and only cut capsulation material and insulation filling material, not the cutting lead framework.
Based on above-mentioned,, be the 3 D stereo encapsulation based on chip package structure on the chip of traditional Q FN encapsulation according to the utility model; Highly can be controlled in 0.7 millimeter scope; Have higher I/O density and integrated level, the staircase structural model of lead frame has increased the bonded area with capsulation material and insulation filling material, has the effect that locks each other with capsulation material and insulation filling material; Can effectively prevent the lead frame and the layering of capsulation material and insulation filling material and coming off of pin or chip carrier; Effectively stop moisture from the package structure outside to diffusion inside, the generation of bridging phenomenon when the outer pin of small size size can effectively prevent surface mount, the lead frame upper surface can effectively improve metal lead wire bonding quality and surface mount quality with first metal material layer and second metal material layer that lower surface disposes; Owing to only link to each other with insulation filling material between the single packaging body by capsulation material; Therefore when using cutter cutting and separating product, can not cut to the lead frame metal material, thereby improve cutting efficiency; Prolonged the life-span of cutter; Prevent the generation of metallic bur power, saved simultaneously and removed technologies such as glued membrane and plastic packaging material overlap after glued membrane, plastic packaging are pasted in the lead frame back side before the plastic packaging in the traditional Q FN encapsulation flow process, reduced packaging cost.
Hereinafter is special lifts embodiment, and conjunction with figs. elaborates to the above-mentioned feature and advantage of the utility model.
Description of drawings
Figure 1A is the schematic rear view of traditional Q FN encapsulating structure;
Figure 1B is the generalized section along the I-í section among Figure 1A;
Fig. 2 A be the pin cross section drawn according to the embodiment of the utility model for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of chip package structure on the chip that is arranged in parallel;
Fig. 2 B is a rectangle for the pin cross section that the embodiment according to the utility model draws, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of chip package structure on the chip that is arranged in parallel;
Fig. 3 A be the pin cross section drawn according to the embodiment of the utility model for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of chip package structure on the staggered chip;
Fig. 3 B is a rectangle for the pin cross section that the embodiment according to the utility model draws, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of chip package structure on the staggered chip;
Fig. 4 draws according to the embodiment of the utility model, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B;
Fig. 5 draws according to the embodiment of the utility model, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B;
Fig. 6 A to Fig. 6 M is that all generalized sections all are along the generalized section shown in Fig. 4 section according to the manufacturing process generalized section of chip package structure on the chip of the embodiment drafting of the utility model.
Label among the figure: 100. traditional four limit flat non-leaded packages, 11. nead frames, 111. chip carriers, 112. pins, 12. capsulation materials, 13. bonding die materials; 14.IC chip, 15. plain conductors, 200, chip (CoC) package structure on the 200A, 200B, 200a, 200b, 200c, 200d. chip, 201. lead frames, 202. chip carriers; 203. pin, 20. thin plate base materials, 20a. thin plate base material upper surface, lead frame upper surface, 20b. thin plate base material lower surface, lead frame lower surface; 21a, 21b. mask material layer, 22. first metal material layers, 23. second metal material layers, the 22a. first metal material laminar surface; 23a. the second metal material laminar surface, 24. grooves, 24a. staircase structural model surface, 24b. staircase structural model; 25. insulation filling material, 25a. insulation filling material surface, 26. adhesive materials, 27. female IC chips; 28. sub-IC chip, 29. plain conductors, 30. capsulation materials, 31. partitions.
Embodiment
Below in conjunction with accompanying drawing the utility model is elaborated:
Fig. 2 A be the pin cross section drawn according to the embodiment of the utility model for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of chip package structure on the chip that is arranged in parallel.
Fig. 2 B is a rectangle for the pin cross section that the embodiment according to the utility model draws, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of chip package structure on the chip that is arranged in parallel.
Can find out with reference to above-mentioned Fig. 2 A-B; In the present embodiment; The lead frame 201 of chip package structure 200a and 200b comprises chip carrier 202 and is the pin 203 that many circles are arranged around chip carrier 202 on the chip; And the arrangement mode of the pin 203 on chip carrier 202 every limits disposes second metal material layer 23 for being arranged in parallel at lead frame 201 lower surfaces, in lead frame 201, disposes insulation filling material 25.Difference is that the pin cross section in the chip package structure is for circular on the chip of Fig. 2 A, and the pin cross section on the chip of Fig. 2 B in the chip package structure is a rectangle.
Fig. 3 A be the pin cross section drawn according to the embodiment of the utility model for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of chip package structure on the staggered chip.
Fig. 3 B is a rectangle for the pin cross section that the embodiment according to the utility model draws, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of chip package structure on the staggered chip.
Can find out with reference to above-mentioned Fig. 3 A-B; In the present embodiment; The lead frame 201 of chip package structure 200c and 200d comprises chip carrier 202 and is the pin 203 that many circles are arranged around chip carrier 202 on the chip; And the arrangement mode of the pin 203 on chip carrier 202 every limits disposes second metal material layer 23 for being staggered at lead frame 201 lower surfaces, in lead frame 201, disposes insulation filling material 25.Difference is that the pin cross section in the chip package structure is for circular on the chip of Fig. 3 A, and the pin cross section on the chip of Fig. 3 B in the chip package structure is a rectangle.
Fig. 4 is the generalized section along the I-I section among Fig. 2 A-B and Fig. 3 A-B.In conjunction with Fig. 2 A-B, Fig. 3 A-B; With reference to Fig. 4; In the present embodiment, chip package structure 200A comprises lead frame 201, first metal material layer 22, second metal material layer 23, insulation filling material 25, adhesive material 26, female IC chip 27, sub-IC chip 28, plain conductor 29 and capsulation material 30 on the chip.
In the present embodiment; Lead frame 201 is as the passage of conduction, heat radiation, connection external circuit; Have staircase structural model 24b along thickness direction, have upper surface 20a and with respect to the lower surface 20b of upper surface 20a, and the ledge surface 24a of staircase structural model 24b.Lead frame 201 comprises chip carrier 202 and is the pins 203 that many circles are arranged around chip carrier 202, chip carrier 202 and be the pins 203 that many circles arrange around chip carrier 202 and all have staircase structural model 24b.Chip carrier 202 is disposed at lead frame 201 central parts, and edge, chip carrier 202 4 limit has staircase structural model 24b along thickness direction.A plurality of pins 203 are disposed at around the chip carrier 202; Being many circles around chip carrier 202 arranges; And has ledge structure 24b along thickness direction; Its shape of cross section is rounded or rectangular-shaped, and wherein each pin 203 comprises interior pin that is disposed at this upper surface 20a and the outer pin that is disposed at this lower surface 20b.
First metal material layer 22 and second metal material layer 23 are disposed at the upper surface 20a position of lead frame 201 and the lower surface 20b position of lead frame 201 respectively; First metal material layer 22 has the same size size with the interior pin of pin 203, and second metal material layer 23 has the same size size with the outer pin of pin 203.First metal material layer 22 has the first metal material laminar surface 22a, and second metal material layer 23 has the second metal material laminar surface 23a.
Fig. 5 is the generalized section along the I-I section among Fig. 2 A-B and Fig. 3 A-B.In conjunction with Fig. 2 A-B, Fig. 3 A-B; With reference to Fig. 5; In the present embodiment, chip package structure 200B comprises lead frame 201, first metal material layer 22, second metal material layer 23, insulation filling material 25, adhesive material 26, female IC chip 27, sub-IC chip 28, plain conductor 29, capsulation material 30 and partition 31 on the chip.
In the present embodiment; Lead frame 201 is as the passage of conduction, heat radiation, connection external circuit; Have staircase structural model 24b along thickness direction, have upper surface 20a and with respect to the lower surface 20b of upper surface 20a, and the ledge surface 24a of staircase structural model 24b.Lead frame 201 comprises chip carrier 202 and is the pins 203 that many circles are arranged around chip carrier 202, chip carrier 202 and be the pins 203 that many circles arrange around chip carrier 202 and all have staircase structural model 24b.Chip carrier 202 is disposed at lead frame 201 central parts, the rectangular shape of its shape of cross section, and edge, chip carrier 202 4 limit has staircase structural model 24b along thickness direction.A plurality of pins 203 are disposed at around the chip carrier 202; Being many circles around chip carrier 202 arranges; And has ledge structure 24b along thickness direction; Its shape of cross section is rounded or rectangular-shaped, and wherein each pin 203 comprises interior pin that is disposed at this upper surface 20a and the outer pin that is disposed at this lower surface 20b.
First metal material layer 22 and second metal material layer 23 are disposed at the upper surface 20a position of lead frame 201 and the lower surface 20b position of lead frame 201 respectively; First metal material layer 22 has the same size size with the interior pin of pin 203, and second metal material layer 23 has the same size size with the outer pin of pin 203.First metal material layer 22 has the first metal material laminar surface 22a, and second metal material layer 23 has the second metal material laminar surface 23a.
To specify the manufacturing process of chip on a kind of chip (CoC) package structure below with Fig. 6 A to Fig. 6 M.
Fig. 6 A to Fig. 6 M is that all generalized sections all are along the generalized section shown in Fig. 4 section according to the manufacturing process generalized section of chip (CoC) package structure on the chip of the embodiment drafting of the utility model.
Please with reference to Fig. 6 A; Provide to have upper surface 20a and with respect to the thin plate base material 20 of the lower surface 20b of upper surface 20a, the material of thin plate base material 20 can be that copper, copper alloy, iron, ferroalloy, nickel, nickel alloy and other are applicable to the metal material of making lead frame.The thickness range of thin plate base material 20 is 0.1mm-0.25mm, for example is 0.127mm, 0.152mm, 0.203mm.Upper surface 20a and lower surface 20b to thin plate base material 20 clean and preliminary treatment, for example use plasma water degreasing, dust etc., with the upper surface 20a of realization thin plate base material 20 and the purpose of lower surface 20b cleaning.
Please with reference to Fig. 6 B; Configuration has the mask material layer 21a and the mask material layer 21b of window respectively on the upper surface 20a of thin plate base material 20 and lower surface 20b; Window described here is meant not by the thin plate base material 20 of mask material layer 21a and mask material layer 21b covering; Mask material layer 21a and mask material layer 21b protection will be to being carried out etching by the thin plate base material 20 of mask material layer 21a and mask material layer 21b covering in the processing step of back by the thin plate base material 20 of its covering.
Please with reference to Fig. 6 C; Configuration first metal material layer 22 in the window of mask material layer 21a on being disposed at the upper surface 20a of thin plate base material 20; First metal material layer 22 has the first metal material laminar surface 22a; Configuration second metal material layer 23, the second metal material layers 23 have the second metal material laminar surface 23a in the window of mask material layer 21b on being disposed at the lower surface 20b of thin plate base material 20.The collocation method of first metal material layer 22 and second metal material layer 23 is methods such as plating, chemical plating, evaporation, sputter; And allow to form by the different metallic material; In the present embodiment, preferential selection plating or chemical plating are as the collocation method of first metal material layer 22 and second metal material layer 23.The material of first metal material layer 22 and second metal material layer 23 is nickel (Ni), palladium (Pd), gold (Au), silver (Ag), tin metal material and alloys thereof such as (Sn); In the present embodiment; First metal material layer 22 and second metal material layer 23 for example are nickel-palladium-gold plates; For first metal material layer 22; The gold plate of outside is to guarantee bonding property and the bonding quality of plain conductor 29 on lead frame 201 with middle palladium coating; The nickel coating of the inside is as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents to be caused by Elements Diffusion-chemical reaction, and blocked up cocrystalization compound influence the regional reliability of bonding, for second metal material layer 23; But the gold plate of outside is to guarantee the wettability of scolder at lead frame 201 with middle palladium coating; Improve the quality that packaging body mounts at circuit board upper surfaces such as PCB, the nickel coating of the inside is that blocked up cocrystalization compound influences the reliability of surface mount welding region as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents to be caused by Elements Diffusion-chemical reaction.
Please with reference to Fig. 6 D; Mask material layer 21b on the lower surface 20b of thin plate base material 20 removed; The method that removes in the present embodiment can be chemical reaction method and mechanical means, and chemical reaction method is an alkaline solution of selecting solubility for use, for example potassium hydroxide (KOH), NaOH (NaOH); Adopt the mask material layer 21b on the lower surface 20b of mode such as spray and thin plate base material 20 to carry out chemical reaction; Thereby its dissolving is reached the effect that removes, remove mask material layer 21b after, only remaining second metal material layer 23 on the lower surface 20b of thin plate base material 20.
Please with reference to Fig. 6 E; With second metal material layer 23 on the lower surface 20b of thin plate base material 20 as etched resist layer; It is partially-etched to adopt the spray mode that thin plate base material 20 lower surface 20b are carried out selectivity; Form groove 24 and staircase structural model surface 24a, the etch depth scope can be the 40%-90% that accounts for the thickness of thin plate base material 20.In the present embodiment, the preferential employing of spray mode gone up the spray mode, and etching solution is preferentially selected alkaline etching liquid, like alkaline etching liquids such as alkaline copper chloride etching solution, ammonium chlorides, to reduce the destruction of etching solution to second metal material layer 23.
Please with reference to Fig. 6 F, in the groove 24 of the partially-etched formation of selectivity, fill insulation filling material 25 at the lower surface 20b of thin plate base material 20, insulation filling material 25 has surperficial 25a, and this surface and the second metal material laminar surface 23a are on the same horizontal plane.In the present embodiment; Insulation filling material 25 is insulating material such as thermosetting capsulation material, plug socket resin, printing ink and resistance weldering green oil; Insulation filling material 25 has enough acidproof, alkali resistance; To guarantee that follow-up technology can not damage forming insulation filling material 25, the fill method of insulation filling material 25 is to be filled in the groove 24 through methods such as injection moulding or silk screen printings, and too much insulation filling material 25 is removed with mechanical grinding method or chemical treatment method in the configuration back; To eliminate the flash of insulation filling material 25; The surperficial 25a and the second metal material laminar surface 23a of insulation filling material 25 are on the same horizontal plane,, remove flash through developing method for insulation filling materials 25 such as photosensitive type resistance weldering green oils.
Please with reference to Fig. 6 G; Mask material layer 21a on the upper surface 20a of thin plate base material 20 removed; The method that removes in the present embodiment can be chemical reaction method and mechanical means, and chemical reaction method is an alkaline solution of selecting solubility for use, for example potassium hydroxide (KOH), NaOH (NaOH); Adopt the mask material layer 21a chemical reaction on the upper surface 20a of mode such as spray and thin plate base material 20; Thereby its dissolving is reached the effect that removes, remove mask material layer 21a after, only remaining first metal material layer 22 on the upper surface 20a of thin plate base material 20.
Please with reference to Fig. 6 H; With first metal material layer 22 on the upper surface 20a of thin plate base material 20 as etched resist layer; Select the only etching solution of etched sheet base material 20 for use; It is partially-etched to adopt the spray mode that thin plate base material 20 upper surface 20a are carried out selectivity, is etched to staircase structural model surface 24a, exposes insulation filling material 25.Form lead frame 201; Lead frame 201 comprises chip carrier 202 and is the pin 203 that many circles are arranged around chip carrier 202; Dispose insulation filling material 25 in the lead frame 201, i.e. chip carrier 202 and be the pins 203 that many circles arrange around chip carrier 202 and be fixed together through insulation filling material 25.In the pin 203 of the separation that after selectivity is partially-etched, forms has pin with outside pin, interior pin is connected to the bonding welding pad of female IC chip 27 by plain conductor 28 in follow-up lead key closing process, outer pin is as the passage of connection external circuit.Form staircase structural model 24b, staircase structural model 24b has staircase structural model surface 24a.In the present embodiment, the preferential employing of the spray mode of etching solution gone up the spray mode, and etching solution is preferentially selected alkaline etching liquid, like alkaline etching liquids such as alkaline copper chloride etching solution, ammonium chlorides, to reduce the destruction of etching solution to first metal material layer 22.
Please with reference to Fig. 6 I; Female IC chip 27 is disposed at first metal material layer, 22 positions of lead frame upper surface 20a through adhesive material 26; And be fixed in the central part of chip carrier 202, in the present embodiment, adhesive material 26 can be the materials such as epoxy resin of bonding die adhesive tape, argentiferous particle.
Please with reference to Fig. 6 J, sub-IC chip 28 is disposed on the face of having chance with of female IC chip 27 through adhesive material 26, in the present embodiment, adhesive material 26 can be the materials such as epoxy resin of bonding die adhesive tape, argentiferous particle.
Please with reference to Fig. 6 K; A plurality of bonding welding pads on female IC chip 27 and the sub-IC chip 28 are connected to through plain conductor 29 on the interior pin of the many pins that dispose first metal material layer 22; Realize electrical interconnection; In the present embodiment, plain conductor 29 is gold thread, aluminum steel, copper cash and plating palladium copper cash etc.
Please with reference to Fig. 6 L, adopt injection moulding process, coat female IC chip 27, sub-IC chip 28, adhesive material 26, plain conductor 29, lead frame 201 and first metal material layer 22 through capsulation material 30, form product array.In the present embodiment; Capsulation material 30 can be materials such as thermosetting polymer; The insulation filling material 25 of being filled has the physical property similar with capsulation material 30, and thermal coefficient of expansion for example is to reduce the product failure that is caused by thermal mismatching; Improve reliability of products, insulation filling material 25 can be a commaterial with capsulation material 30.Toasting the back behind the plastic packaging solidifies; Capsulation material 30 has mutual lock function with insulation filling material 25 and the lead frame 201 with staircase structural model 24b; Can effectively prevent lead frame 201 and capsulation material 30 and the layering of insulation filling material 25 and coming off of pin 203 or chip carrier 202; And effectively stop moisture to be diffused into package interior along the combination interface of lead frame 201 and capsulation material 30 and insulation filling material 25, improved the reliability of packaging body.After forming product array, product array is carried out laser printing.
Please with reference to Fig. 6 M; Chip package infrastructure product array on the diced chip, thoroughly cutting and separating capsulation material 30 forms chip package structure 200 on the single chip with insulation filling material 25, in the present embodiment; Single product separation method is methods such as blade cuts, laser cutting or the cutting of water cutter; And only cut capsulation material 30 and insulation filling material 25, cutting lead framework metal material is not only drawn out chip package structure 200 on 2 chips after the cutting and separating among Fig. 6 M.
The description of the embodiment of the utility model is from effective explanation and describes the purpose of the utility model; Be not in order to limit the utility model; Those skilled in the art is to be understood that under any: under the condition of utility model design that does not break away from the utility model and scope, can change the foregoing description.So the utility model is not limited to the specific embodiment that disclosed, but cover the essence and the interior modification of scope of the defined the utility model of claim.
Claims (4)
1. chip-packaging structure on the chip is characterized in that comprising:
Lead frame has staircase structural model along thickness direction, has upper surface, lower surface and ledge surface, and wherein lead frame comprises chip carrier, a plurality of pin:
Chip carrier is disposed at the lead frame central part, and edge, chip carrier four limit has staircase structural model along thickness direction, has upper surface, lower surface and ledge surface, and
A plurality of pins; Be disposed at around the chip carrier, be many circles around chip carrier and arrange, have staircase structural model along thickness direction; Have upper surface, lower surface and ledge surface, wherein each pin comprises interior pin that is disposed at this upper surface and the outer pin that is disposed at this lower surface;
First metal material layer is disposed at the upper surface position of lead frame;
Second metal material layer is disposed at the lower surface position of lead frame;
Metal material layer is disposed at the upper surface and the lower surface position of lead frame;
Insulation filling material is disposed under the staircase structural model of lead frame;
Female IC chip is disposed on first metal material layer of lead frame upper surface position, and is disposed at the central part of chip carrier;
Sub-IC chip is disposed at the top of female IC chip through adhesive material, perhaps is disposed at the top of female IC chip through partition;
Plain conductor, a plurality of bonding welding pads on female IC chip and the sub-IC chip are connected to the interior pin of a plurality of pins that dispose first metal material layer respectively through plain conductor;
Capsulation material; Coat female IC chip, sub-IC chip, plain conductor, adhesive material, lead frame and first metal material layer; Form packaging part, perhaps coat female IC chip, sub-IC chip, plain conductor, partition, lead frame and first metal material layer, form packaging part.
2. chip-packaging structure on a kind of chip according to claim 1 is characterized in that, the chip package structure comprises one or more sub-IC chips on the said chip; Be connected through adhesive material or partition between sub-IC chip and the sub-IC chip.
3. chip-packaging structure on a kind of chip according to claim 1; It is characterized in that; Above-mentioned lead frame has a plurality of chip carriers that center on and is the pins that many circles are arranged, and the pin shape of cross section is circle or rectangle, and the arrangement number of turns is more than individual pen, two circle or three enclose.
4. chip-packaging structure on a kind of chip according to claim 1 is characterized in that, many circles pin arrangements mode on the every limit of chip carrier is for being arranged in parallel or being staggered.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205698581U CN202633291U (en) | 2011-12-30 | 2011-12-30 | Chip-on-chip packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011205698581U CN202633291U (en) | 2011-12-30 | 2011-12-30 | Chip-on-chip packaging structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522394A (en) * | 2011-12-30 | 2012-06-27 | 北京工业大学 | On-chip chip package and production method thereof |
| CN104681507A (en) * | 2013-12-03 | 2015-06-03 | 上海北京大学微电子研究院 | Round QFN (Quad Flat No Lead) package structure |
| CN104681508A (en) * | 2013-12-03 | 2015-06-03 | 上海北京大学微电子研究院 | Circular flat no-lead encapsulation structure |
-
2011
- 2011-12-30 CN CN2011205698581U patent/CN202633291U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522394A (en) * | 2011-12-30 | 2012-06-27 | 北京工业大学 | On-chip chip package and production method thereof |
| WO2013097580A1 (en) * | 2011-12-30 | 2013-07-04 | 北京工业大学 | Chip on chip package and manufacturing method |
| CN104681507A (en) * | 2013-12-03 | 2015-06-03 | 上海北京大学微电子研究院 | Round QFN (Quad Flat No Lead) package structure |
| CN104681508A (en) * | 2013-12-03 | 2015-06-03 | 上海北京大学微电子研究院 | Circular flat no-lead encapsulation structure |
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Granted publication date: 20121226 Termination date: 20131230 |