CN102420205B - Manufacturing method of advanced four-side flat pin-free package - Google Patents
Manufacturing method of advanced four-side flat pin-free package Download PDFInfo
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- CN102420205B CN102420205B CN2011103445253A CN201110344525A CN102420205B CN 102420205 B CN102420205 B CN 102420205B CN 2011103445253 A CN2011103445253 A CN 2011103445253A CN 201110344525 A CN201110344525 A CN 201110344525A CN 102420205 B CN102420205 B CN 102420205B
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
The invention discloses an advanced four-side flat pin-free package and a manufacturing method thereof. The advanced four-side flat pin-free package comprises a chip carrier, pins, a metal material layer, an IC (Integrated Circuit) chip, insulated filling materials, a bonding material, a metal wire and a plastic sealing material, wherein the chip carrier is provided with a groove structure and the pins for grounding; and the pins are arranged in a package structure in a plane array form. The metal material layer is configured at the upper surfaces and the lower surfaces of the chip carrier and the pins; the IC chip is configured on the metal material layer at the upper surface of the chip carrier, or configured on the metal material layers at the upper surfaces of the pins; and the insulated filling materials are configured below stepped structures of the plurality of chips and a groove of the chip carrier. A package part is formed by coating and sealing the plastic sealing material; and the chip carrier and the external pins which are exposed out of the bottom surface of a package part structure are provided with protruded parts. According to the advanced four-side flat pin-free package and the manufacturing method thereof disclosed by the invention, the bottleneck of less I/O (Input/Output) is broken through and the reliability of the package is improved.
Description
Technical field
The present invention relates to semiconductor components and devices manufacturing technology field, refer more particularly to advanced four limit flat non-pin encapsulation, the present invention also comprises the manufacture method of this packaging part.
Background technology
Along with electronic product such as mobile phone, notebook computer etc. towards miniaturization, portable, ultra-thinization, multimedization and satisfy popular needed low-cost direction and develop, high density, high-performance, high reliability and packing forms and packaging technology thereof have obtained development fast cheaply.Compare with packing forms such as expensive BGA, Kuai Sufazhan novel encapsulated technology in recent years, i.e. four limit flat non-pin QFN(Quad Flat Non-lead Package) encapsulation, because have good hot property and electrical property, size is little, cost is low and numerous advantages such as high production rate, has caused a new revolution in microelectronic packaging technology field.
Figure 1A and Figure 1B are respectively the schematic rear view of traditional Q FN encapsulating structure and along the generalized section of I-í section; this QFN encapsulating structure comprises lead frame 11; capsulation material 12; bonding die material 13; IC chip 14; plain conductor 15; wherein lead frame 11 comprises chip carrier 111 and the pin of arranging around chip carrier 111 112 all around; IC chip 14 is fixed on the chip carrier 111 by bonding die material 13; IC chip 13 is realized being electrically connected by plain conductor 15 with the pin of arranging all around 112; 12 pairs of IC chips 14 of capsulation material; plain conductor 15 and lead frame 11 are sealed the effect to reach protection and to support; pin 112 exposes in the bottom surface of capsulation material 12, is welded on by scolder on the circuit board such as PCB to realize and extraneous being electrically connected.The exposed chip carrier in bottom surface 111 is welded on by scolder on the circuit board such as PCB, has direct heat dissipation channel, can effectively discharge the heat that IC chip 14 produces.With traditional TSOP with SOIC encapsulation compare, the QFN encapsulation does not have gull wing lead-in wire, conductive path is short, coefficient of self-inductance and impedance are low, thereby good electrical properties can be provided, and can satisfy at a high speed or the application of microwave.Exposed chip carrier provides remarkable heat dispersion.
Along with the raising of IC integrated level and the continuous enhancing of function, the I/O number of IC increases thereupon, the also corresponding increase of I/O number of pins of corresponding Electronic Packaging, but four traditional limit flat non-pin packaging parts, the pin of individual pen is periphery around chip carrier and arranges, limited the raising of I/O quantity, do not satisfied high density, have the needs of the IC of more I/O numbers.Traditional lead frame does not have the staircase structural model design, can't effectively pin plastic material, cause lead frame and capsulation material bond strength low, be easy to cause the layering of lead frame and capsulation material even coming off of pin or chip carrier, and can't effectively stop moisture to be diffused into Electronic Packaging inside, thereby had a strong impact on the reliability of packaging body along lead frame and capsulation material combination interface.The chip carrier of traditional Q FN product and outer pin do not have certain bossing, the area coverage of scolder is limited when surface mount, and the thinner thickness of scolder, cause the fatigue life of plate level encapsulation shorter, and thin weld layer is because the thermal strain that thermal mismatching causes is bigger, cause fracture, the layering of weld layer to be lost efficacy easily, influenced the reliability of weld layer.Traditional Q FN product is because the size of chip carrier is far longer than the size of the pin that periphery arranges, and when being welded on circuit board such as PCB, the large tracts of land scolder chip carrier under easily causes the drift of packaging body, thus the inefficacy that the pin that causes periphery to be arranged welds.Traditional Q FN product needs in advance at lead frame back side Continuous pressing device for stereo-pattern to treat also need remove cleanings such as adhesive tape, plastic packaging material overlap behind the plastic packaging to prevent the flash phenomenon when plastic package process, has increased packaging cost and has increased.Use four traditional limit flat non-pin packaging parts of cutter cutting and separating, cutter also can cut to the lead frame metal in the cutting capsulation material, not only can cause the reduction and the shortening in cutting blade life-span of cutting efficiency, and can produce metallic bur power, influenced the reliability of packaging body.Therefore,, improve the reliability of packaging body and reduce packaging cost, be badly in need of the advanced QFN encapsulation and the manufacture method thereof of a kind of high reliability of research and development, low cost, high I/O density for the bottleneck of the low I/O quantity that breaks through traditional Q FN.
Summary of the invention
The invention provides a kind of battle array pin arrangements, advanced QFN encapsulation and manufacture method thereof, with bottleneck that reaches the low I/O quantity that breaks through traditional Q FN and the purpose that improves the reliability of packaging body.
To achieve these goals, the present invention adopts following technical proposals:
The present invention proposes a kind of advanced four limit flat non-pin package structures, comprises chip carrier, a plurality of pins, metal material layer, IC chip, insulation filling material, adhesive material, plain conductor and capsulation material.Chip carrier is disposed at the central part of package structure, has groove structure and the pin that is used for ground connection, and edge, four limits has staircase structural model along thickness direction, has upper surface, lower surface and ledge surface.A plurality of pins are face battle array arranged distribution in package structure, have upper surface, lower surface and ledge surface, have staircase structural model along thickness direction, and wherein each pin comprises interior pin that is disposed at this upper surface and the outer pin that is disposed at this lower surface.Metal material layer is disposed at the upper surface and the lower surface position of chip carrier and a plurality of pins.The IC chip configuration perhaps is disposed on the metal material layer of a plurality of pin upper surfaces position on the metal material layer of chip carrier upper surface position.The staircase structural model that insulation filling material is disposed at a plurality of pins supports, protects a plurality of pins and chip carrier down and in the groove of chip carrier.Adhesive material is disposed in the middle of the metal material layer of IC chip and chip carrier upper surface or in the middle of the metal material layer of IC chip and a plurality of pin upper surfaces, fixedly the IC chip is on a plurality of pins or chip carrier.A plurality of bonding welding pads on the IC chip are connected to a plurality of upper surfaces that dispose the interior pin of metal material layer and dispose the chip carrier of metal material layer by plain conductor, to realize electrical interconnection.Capsulation material coats the subregion and the part metals material layer of the above-mentioned IC chip of sealing, adhesive material, plain conductor, chip carrier and a plurality of pins, the chip carrier and the outer pin that dispose metal material layer expose the package structure bottom surface, and have bossing.
According to embodiments of the invention, advanced QFN packaging part has the pin of face battle array arranged distribution.
According to embodiments of the invention, the pin that is face battle array arranged distribution in package structure has staircase structural model.
According to embodiments of the invention, the chip carrier that is disposed at the central part of package structure has groove structure.
According to embodiments of the invention, the chip carrier that is disposed at the central part of package structure has staircase structural model.
According to embodiments of the invention, in package structure, be the rounded shape of shape of cross section of the pin of face battle array arranged distribution.
According to embodiments of the invention, in package structure, be the shape of cross section rectangular shaped of the pin of face battle array arranged distribution.
According to embodiments of the invention, the arrangement mode of the pin that the face battle array is arranged is for being arranged in parallel.
According to embodiments of the invention, the arrangement mode of the pin that the face battle array is arranged is for being staggered.
According to embodiments of the invention, chip carrier and a plurality of pin upper surface and lower surface dispose metal material layer.
According to embodiments of the invention, the metal material layer of chip carrier and a plurality of pin upper surface and lower surface configuration comprises nickel (Ni), palladium (Pd), gold (Au) metal material.
According to embodiments of the invention, the chip carrier and the outer pin that dispose metal material layer expose the package structure bottom surface, and have bossing.
According to embodiments of the invention, adhesive materials such as the epoxy resin of usefulness argentiferous particle or adhesive tape on the metal material layer of chip carrier upper surface position, perhaps are disposed at the IC chip configuration on the metal material layer of a plurality of pin upper surfaces position.
According to embodiments of the invention, a plurality of pin staircase structural models are the configuration insulation filling material down.
According to embodiments of the invention, dispose insulation filling material in the groove structure of chip carrier.
According to embodiments of the invention, a plurality of pin staircase structural models down and to dispose the insulation filling material kind in the groove structure of chip carrier be the thermosetting capsulation material, perhaps materials such as plug socket resin, printing ink and welding resistance green oil.
According to embodiments of the invention, the peripheral position of chip carrier is as the ground area, is connected to bonding welding pad on the chip by plain conductor.
The present invention proposes a kind of advanced four limit flat non-pin packaging part manufacture methods, may further comprise the steps:
Step 1: configuration mask material layer
The thin plate base material is cleaned and preliminary treatment, at the upper surface and the lower surface configuration mask material layer pattern of thin plate base material.
Step 2: form the etching window
The mask material layer that is disposed at thin plate base material lower surface is carried out exposure imaging, form the etching window.
Step 3: the lower surface selectivity is partially-etched
As resist layer, it is partially-etched that thin plate base material lower surface is carried out selectivity, forms groove structure with mask material layer with etching window.
Step 4: remove the mask material layer
Remove the mask material layer that is disposed at thin plate base material lower surface with chemical treatment method or mechanical means.
Step 5: configuration insulation filling material
At thin plate base material lower surface fill insulant in the groove structure of the partially-etched formation of selectivity.
Step 6: form the etching window
Mask material layer to thin plate base material upper surface carries out exposure imaging, forms the etching window.
Step 7: the upper surface selectivity is partially-etched
As resist layer, it is partially-etched that thin plate base material upper surface is carried out selectivity, forms a plurality of pins with staircase structural model, forms the chip carrier that has staircase structural model, groove structure and be used for the pin of ground connection with mask material layer with etching window.
Step 8: remove the mask material layer
Remove the mask material layer that is disposed at thin plate base material lower surface with chemical treatment method or mechanical means.
Step 9: configuration metal material layer
Upper surface, lower surface configuration metal material layer at the lead frame that forms.
Step 10: configuration IC chip
Adhesive materials such as epoxy resin resin by the argentiferous particle or adhesive tape on the metal material layer of chip carrier upper surface position, perhaps are disposed at the IC chip configuration on the metal material layer of a plurality of pin upper surfaces position
Step 11: the plain conductor bonding connects
A plurality of bonding welding pads on the IC chip are connected to a plurality of upper surfaces that dispose the interior pin of metal material layer and dispose the chip carrier of metal material layer respectively by plain conductor, to realize electrical interconnection and ground connection.
Step 12: plastic packaging
Coat subregion and the part metals material layer that seals above-mentioned IC chip, adhesive material, plain conductor, chip carrier and a plurality of pins with capsulation material, expose the metal material layer that is disposed at chip carrier and a plurality of pin lower surfaces.
Step 13: solidify the back
Carrying out the back according to the back solidifying requirements of selected capsulation material solidifies.
Step 14: print
Product array behind the plastic packaging is carried out laser printing.
Step 15: cutting and separating product
The cutting and separating product forms independently single package.
According to embodiments of the invention, by chemical plating method configuration metal material layer.
According to embodiments of the invention, as resist layer, select for use the etching solution of etched sheet base material only partially-etched to thin plate base material upper surface and lower surface selectivity with the mask material layer.
According to embodiments of the invention, insulation filling material is configured in by methods such as silk screen printing or coatings and etches partially in the groove structure.
According to embodiments of the invention, select method cutting and separating products such as blade cuts, laser cutting or the cutting of water cutter for use, and only cut capsulation material and insulation filling material, not the cutting lead framework.
Based on above-mentioned, according to the present invention, advanced person's four limit flat non-pin package structures of pin face battle array arranged distribution draw and have high I/O density, the staircase structural model of chip carrier and a plurality of pins has increased the bonded area with capsulation material and insulation filling material, has the effect that locks mutually with capsulation material and insulation filling material, can effectively prevent chip carrier and a plurality of pin and the layering of capsulation material and insulation filling material and coming off of pin or chip carrier, effectively stop moisture from the package structure outside to diffusion inside, the generation of bridging phenomenon when the outer pin of small size size can effectively prevent surface mount, the metal material layer of chip carrier and a plurality of pin upper surface and lower surface configuration can effectively improve metal lead wire bonding quality and surface mount quality, have the chip carrier of certain bossing and outer pin has increased scolder when surface mount wetted area, and the thickness of scolder, increased the fatigue life of plate level encapsulation, increased the bond strength of chip carrier and outer pin and scolder simultaneously, alleviated the thermal strain that causes by thermal mismatching, the inefficacy of the drift of chip and pin welding when the pin that the face battle array is arranged can effectively prevent surface mount, improved the surface mount quality, owing to only link to each other with insulation filling material between the single packaging body by capsulation material, therefore when using cutter cutting and separating product, can not cut to the lead frame metal material, thereby improved cutting efficiency, prolonged the life-span of cutter, prevented the generation of metallic bur power, glued membrane is pasted at the lead frame back side before having saved the plastic packaging in the traditional Q FN encapsulation flow process simultaneously, remove technologies such as glued membrane and plastic packaging material overlap behind the plastic packaging, reduced packaging cost.
Embodiment cited below particularly, and conjunction with figs. elaborates to above-mentioned feature and advantage of the present invention.
Description of drawings
Figure 1A is the schematic rear view of traditional Q FN encapsulating structure;
Figure 1B is the generalized section along the I-í section among Figure 1A;
Fig. 2 A be the pin cross section drawn according to embodiments of the invention for circular, and the arrangement mode of pin is the schematic rear view of the advanced QFN encapsulating structure that is arranged in parallel;
Fig. 2 B is a rectangle for the pin cross section of drawing according to embodiments of the invention, and the arrangement mode of pin is the schematic rear view of the advanced QFN encapsulating structure that is arranged in parallel;
Fig. 3 A is circle according to the pin cross section that embodiments of the invention are drawn, and the arrangement mode of pin is the schematic rear view of staggered advanced QFN encapsulating structure;
Fig. 3 B is a rectangle for the pin cross section of drawing according to embodiments of the invention, and the arrangement mode of pin is the schematic rear view of staggered advanced QFN encapsulating structure;
Fig. 4 draws according to embodiments of the invention, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B;
Fig. 5 draws according to embodiments of the invention, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B;
Fig. 6 A to Fig. 6 N is that all generalized sections all are along the generalized section shown in Fig. 4 section according to the manufacturing process generalized section of the advanced QFN encapsulating structure of embodiments of the invention drafting.
Number in the figure: 100. traditional four limit flat non-leaded packages, 11. nead frame, 111. chip carriers, 112. pins, 12. capsulation materials, 13. bonding die material 14.IC chip, 15. plain conductor, 200A, 200B, 200a, 200b, 200c, 200d. advanced four limit flat non-pin package structures, 201. pins, 202. chip carrier, 20. the thin plate base material, 20a. thin plate base material upper surface, the lead frame upper surface, 20b. thin plate base material lower surface, the lead frame lower surface, 21a, 21b. mask material layer, 22. groove, 22a. staircase structural model surface, 22b. staircase structural model, 23. insulation filling material, 23a. the insulation filling material surface, 24,25. metal material layer, 24a, 25a. metal material laminar surface, 26. adhesive material, 27.IC chip, 28. plain conductors, 29. capsulation materials.
Embodiment
The present invention is described in detail below in conjunction with accompanying drawing:
Fig. 2 A be the pin cross section drawn according to embodiments of the invention for circular, and the arrangement mode of pin is the schematic rear view of the advanced QFN encapsulating structure of the face battle array pin arrangements that is arranged in parallel.Fig. 2 B is a rectangle for the pin cross section of drawing according to embodiments of the invention, and the arrangement mode of pin is the schematic rear view of the advanced QFN encapsulating structure of the face battle array pin arrangements that is arranged in parallel.
With reference to above-mentioned Fig. 2 A-B as can be seen, in the present embodiment, the advanced QFN encapsulating structure 200a of face battle array pin arrangements and 200b have and are face battle array pin arranged evenly 201, and the arrangement mode of pin 201 is for being arranged in parallel, dispose metal material layer 25 at pin 201 lower surfaces, between pin 201, dispose insulation filling material 23.Difference is pin cross section in advanced person's four limit flat non-pin package structures of Fig. 2 A for circular, and the pin cross section in advanced person's four limit flat non-pin package structures of Fig. 2 B is a rectangle.
Fig. 3 A is circle according to the pin cross section that embodiments of the invention are drawn, and the arrangement mode of pin is the schematic rear view of the advanced QFN encapsulating structure of staggered battle array pin arrangements.Fig. 3 B is a rectangle for the pin cross section of drawing according to embodiments of the invention, and the arrangement mode of pin is the schematic rear view of the advanced QFN encapsulating structure of staggered battle array pin arrangements.
With reference to above-mentioned Fig. 3 A-B as can be seen, in the present embodiment, the advanced QFN encapsulating structure 200c of face battle array pin arrangements and 200d have and are face battle array pin arranged evenly 201, and the arrangement mode of pin 201 is for being staggered, dispose metal material layer 25 at pin 201 lower surfaces, between pin 201, dispose insulation filling material 23.Difference is pin cross section in advanced person's four limit flat non-pin package structures of Fig. 3 A for circular, and the pin cross section in advanced person's four limit flat non-pin package structures of Fig. 3 B is a rectangle.
Fig. 4 draws according to embodiments of the invention, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B.In conjunction with Fig. 2 A-B, Fig. 3 A-B, with reference to Fig. 4, in the present embodiment, advanced QFN encapsulating structure 200A comprises pin 201, insulation filling material 23, metal material layer 24, metal material layer 25, adhesive material 26, IC chip 27, plain conductor 28 and capsulation material 29.
In the present embodiment, pin 201 as conduction, heat radiation, connect the passage of external circuit, have staircase structural model 22b along thickness direction, have upper surface 20a and with respect to the lower surface 20b of upper surface 20a, and the ledge surface 22a of staircase structural model 22b.The shape of cross section of pin 201 is rounded or rectangular-shaped, and wherein a plurality of pins 201 comprise the interior pin that is disposed at this upper surface 20a and are disposed at the outer pin of this lower surface 20b.
Fig. 5 draws according to embodiments of the invention, along the generalized section of the I-I section among Fig. 2 A-B and Fig. 3 A-B.In conjunction with Fig. 2 A-B, Fig. 3 A-B, with reference to Fig. 5, in the present embodiment, advanced QFN encapsulating structure 200B comprises pin 201, chip carrier 202, insulation filling material 23, metal material layer 24, metal material layer 25, adhesive material 26, IC chip 27, plain conductor 28 and capsulation material 29.
In the present embodiment, chip carrier 202 is disposed at the central part of package structure 200B, pin 201 and chip carrier 202 as conduction, heat radiation, be connected the passage of external circuit, has staircase structural model 22b along thickness direction, has upper surface 20a and with respect to the lower surface 20b of upper surface 20a, and the ledge surface 22a of staircase structural model 22b, chip carrier 202 also has groove structure 22 and is used for the pin 201 of ground connection.The shape of cross section of pin 201 is rounded or rectangular-shaped, and wherein a plurality of pins 201 comprise the interior pin that is disposed at this upper surface 20a and are disposed at the outer pin of this lower surface 20b.
The staircase structural model 22b that insulation filling material 23 is disposed at a plurality of pins 201 is down and in the groove structure 22 of chip carrier 202; pin 201 and chip carrier 202 are played the effect of supporting and protecting; insulation filling material 23 has insulation filling material surface 23a, and the lower surface 20b of insulation filling material surface 23a and a plurality of pin 201 and chip carrier 202 is on the same horizontal plane.
To describe a kind of manufacturing process of advanced four limit flat non-pin package structures with Fig. 6 A to Fig. 6 N in detail below.
Fig. 6 A to Fig. 6 N is that all generalized sections all are along the generalized section shown in Fig. 4 section according to the manufacturing process generalized section of the advanced QFN package structure of embodiments of the invention drafting.
Please refer to Fig. 6 A, provide to have upper surface 20a and with respect to the thin plate base material 20 of the lower surface 20b of upper surface 20a, the material of thin plate base material 20 can be that copper, copper alloy, iron, ferroalloy, nickel, nickel alloy and other are applicable to the metal material of making lead frame.The thickness range of thin plate base material 20 is 0.1mm-0.25mm, for example is 0.127mm, 0.152mm, 0.203mm.Upper surface 20a and lower surface 20b to thin plate base material 20 clean and preliminary treatment, for example use plasma water degreasing, dust etc., with the upper surface 20a of realization thin plate base material 20 and the purpose of lower surface 20b cleaning.
Please refer to Fig. 6 B, dispose mask material layer 21a and mask material layer 21b respectively on the upper surface 20a of thin plate base material 20 and lower surface 20b, mask material layer 21a and mask material layer 21b require to combine firmly with thin plate base material 20, have thermal stability, as the erosion resistant layer, has etch-resistance.Mask material layer 21a and mask material layer 21b can make by be coated with chemical photosensitive materials such as wet film respectively on the upper surface 20a of thin plate base material 20 and lower surface 20b, coating process can be curtain coating, roller coating and spraying etc., perhaps pastes chemical photosensitive material such as photic dry film respectively and make on the upper surface 20a of thin plate base material 20 and lower surface 20b.
Please refer to Fig. 6 C; mask material layer 21b on the thin plate base material lower surface 20b carried out exposure imaging technology; form the etching window; etching window described here is meant after exposure imaging technology not by the subregion of the thin plate base material 20 of mask material layer 21b covering; will be in the processing step of back to not carried out etching by the subregion of the thin plate base material 20 of mask material layer 21b covering, mask material layer 21b protection is not etched by the zone of the thin plate base material 20 of its covering.Mask material layer 21b on the thin plate base material lower surface 20b is exposed under certain light source, as ultraviolet light, electron beam or X-ray, utilize the light sensitive characteristic of chemical photosensitive materials such as photic wet film and photic dry film, photic wet film or photic dry film are optionally exposed, mask plate patterns is duplicated on photic wet film or the photic dry film the final mask material layer 21b that on thin plate base material lower surface 20b, form after using developer solution to carry out developing process with etching window.
Please refer to Fig. 6 D, to have the mask material layer 21b of etching window on the thin plate base material lower surface 20b as etched resist layer, select the only etching solution of etched sheet base material 20 for use, it is partially-etched to adopt the spray mode that thin plate base material 20 lower surface 20b are carried out selectivity, form groove 22 structures and staircase structural model surface 22a, the etch depth scope can be the 40%-90% that accounts for the thickness of thin plate base material 20.In the present embodiment, the preferential spray mode that goes up that adopts of spray mode, and can in etching solution, add organic matters, reducing the lateral erosion effect of etching solution to thin plate base material 20, because mask material layer 21b has polymeric materials such as the wet film of light sensitive characteristic or dry film, acid resistance is alkali resistance not, as etched resist layer, etching solution is preferentially selected acidic etching liquid, as acid chlorization copper etchant solution, iron chloride etching solution, to reduce the destruction of etching solution to mask material layer 21b.
Please refer to Fig. 6 E, mask material layer 21b on the thin plate base material lower surface 20b removed, the method that removes in the present embodiment can be chemical reaction method and mechanical means, chemical reaction method is an alkaline solution of selecting solubility for use, for example potassium hydroxide (KOH), NaOH (NaOH), adopt the mask material layer 21b on mode such as spray and the thin plate base material lower surface 20b to carry out chemical reaction, thereby its dissolving is reached the effect that removes, also can select organic striping liquid that mask material layer 21b removed.
Please refer to Fig. 6 F, fill insulation filling material 23 at thin plate base material lower surface 20b in the groove structure 22 of the partially-etched formation of selectivity, insulation filling material 23 has surperficial 23a, and this surface and thin plate base material lower surface 20b are on the same horizontal plane.In the present embodiment, insulation filling material 23 can be the thermosetting capsulation material, plug socket resin, insulating material such as printing ink and welding resistance green oil, insulation filling material 23 has enough acidproof, alkali resistance, to guarantee that follow-up technology can not damage forming insulation filling material 23, the fill method of insulation filling material 23 can be to be filled in the groove structure 22 by methods such as injection moulding or silk screen printings, solidify to form the insulation filling material 23 of suitable hardness after the filling, need carry out ultraviolet exposure for photocuring insulation filling material 23, insulation filling material 23 after the sclerosis has certain intensity, has the effect of mutual locking with thin plate base material 20, remove too much insulation filling material 23 with mechanical grinding method or chemical treatment method, to eliminate the flash of insulation filling material 23, the surperficial 23a and the thin plate base material lower surface 20b of insulation filling material 23 are on the same horizontal plane, for insulation filling materials 23 such as photosensitive type welding resistance green oils, remove flash by developing method.
Please refer to Fig. 6 G; mask material layer 21a on the thin plate base material upper surface 20a carried out exposure imaging technology; form the etching window; etching window described here is meant after exposure imaging technology not by the subregion of the thin plate base material 20 of mask material layer 21a covering; will be in the processing step of back to not carried out etching by the subregion of the thin plate base material 20 of mask material layer 21a covering, mask material layer 21a protection is not etched by the zone of the thin plate base material 20 of its covering.Mask material layer 21a on the thin plate base material lower surface 20a is exposed under certain light source, as ultraviolet light, electron beam or X-ray, utilize the light sensitive characteristic of chemical photosensitive materials such as photic wet film and photic dry film, photic wet film or photic dry film are optionally exposed, mask plate patterns is duplicated on photic wet film or the photic dry film the final mask material layer 21a that on thin plate base material lower surface 20a, form after using developer solution to carry out developing process with etching window.
Please refer to Fig. 6 H, to have the mask material layer 21a of etching window on the thin plate base material upper surface 20a as etched resist layer, select the only etching solution of etched sheet base material 20 for use, it is partially-etched to adopt the spray mode that thin plate base material 20 upper surface 20a are carried out selectivity, be etched to staircase structural model surface 22a, expose insulation filling material 23.The pin 201 that formation face battle array distributes disposes insulation filling material 23 between the pin 201, the pin 201 that promptly is face battle array arranged distribution is fixed together by insulation filling material 23.In the pin 201 of the separation that forms after selectivity is partially-etched has pin with outside pin, interior pin is connected to the bonding welding pad of IC chip 27 by plain conductor 28 in follow-up lead key closing process, outer pin is as the passage of connection external circuit.Form staircase structural model 22b, staircase structural model 22b has staircase structural model surface 22a.In the present embodiment, the preferential spray mode that goes up that adopts of the spray mode of etching solution, and can in etching solution, add organic matters, to reduce the lateral erosion effect of etching solution to thin plate base material 20, because mask material layer 21a has polymeric materials such as the wet film of light sensitive characteristic or dry film, acid resistance is alkali resistance not, as etched resist layer, etching solution is preferentially selected acidic etching liquid, as acid chlorization copper etchant solution, iron chloride etching solution, to reduce the destruction of etching solution to mask material layer 21a.
Please refer to Fig. 6 I, mask material layer 21a on the thin plate base material upper surface 20a removed, the method that removes in the present embodiment can be chemical reaction method and mechanical means, chemical reaction method is an alkaline solution of selecting solubility for use, for example potassium hydroxide (KOH), NaOH (NaOH), adopt the mask material layer 21a on mode such as spray and the thin plate base material lower surface 20a to carry out chemical reaction, thereby its dissolving is reached the effect that removes, also can select organic striping liquid that mask material layer 21a removed.
Please refer to Fig. 6 J, configuration metal material layer 24 on the upper surface 20a of pin 201, metal material layer 24 has surperficial 24a, configuration metal material layer 25 on the lower surface 20b of pin 201, metal material layer 25 has surperficial 25a, metal material layer 24 has the same size size with the interior pin of pin 201, and metal material layer 25 has the same size size with the outer pin of pin 201.The collocation method of metal material layer 24 and metal material layer 25 can be methods such as chemical plating, evaporation, sputter, and can form by different metal materials, in the present embodiment, preferentially select the collocation method of chemical plating as metal material layer 24 and metal material layer 25.The material of metal material layer 24 and metal material layer 25 can be nickel (Ni), palladium (Pd), gold (Au), silver (Ag), tin metal material and alloys thereof such as (Sn), in the present embodiment, metal material layer 24 and metal material layer 25 for example are nickel-palladium-gold plates, for metal material layer 24, the gold plate of outside and middle palladium coating are to guarantee bonding and the bonding quality of plain conductor 28 on pin 201, the nickel coating of the inside is as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents to be caused by Elements Diffusion-chemical reaction, blocked up cocrystalization compound influences the reliability in bonding zone, for metal material layer 25, but the gold plate of outside and middle palladium coating are to guarantee the wettability of scolder at pin 201, improve the quality that packaging body mounts at circuit board upper surfaces such as PCB, the nickel coating of the inside is that blocked up cocrystalization compound influences the reliability of surface mount welding region as the generation of diffusion impervious layer with the blocked up cocrystalization compound that prevents to be caused by Elements Diffusion-chemical reaction.
Please refer to Fig. 6 K, by adhesive material 26 IC chip 27 is disposed at metal material layer 24 positions of pin upper surface 20a, in the present embodiment, adhesive material 26 can be the materials such as epoxy resin of bonding die adhesive tape, argentiferous particle.If the adhesive material 26 that is disposed is the epoxide resin material of argentiferous particle, behind configuration IC chip 27, needs that adhesive material 26 is carried out high-temperature baking and solidify, with the bond strength of enhancing with IC chip 27, metal material layer 24.
Please refer to Fig. 6 L, a plurality of bonding welding pads on the IC chip 27 are connected on a plurality of interior pins that dispose metal material layer 24 by plain conductor 28, to realize electrical interconnection, in the present embodiment, plain conductor 28 is gold thread, aluminum steel, copper cash and plating palladium copper cash etc.
Please refer to Fig. 6 M, adopt injection moulding process, pass through heat, use low water absorption, the environment-friendly type plastic closure material 29 of low stress coats sealing IC chip 27, adhesive material 26, plain conductor 28, the subregion of a plurality of pins 201 and metal material layer 24, in the present embodiment, capsulation material 29 can be materials such as thermosetting polymer, the insulation filling material 23 of being filled has the physical property similar to capsulation material 29, thermal coefficient of expansion for example, to reduce the product failure that causes by thermal mismatching, improve reliability of products, insulation filling material 23 can be a commaterial with capsulation material 29.Toasting the back behind the plastic packaging solidifies, capsulation material 29 and insulation filling material 23 have mutual lock function with the pin 201 with staircase structural model 22b, can effectively prevent pin 201 and capsulation material 29 and the layering of insulation filling material 23 and coming off of pin 201, and effectively stop moisture to be diffused into package interior along the combination interface of pin 201 and capsulation material 29 and insulation filling material 23, improved the reliability of packaging body.After treating that the back is solidified, product array is carried out laser printing.
Please refer to Fig. 6 N, cut advanced QFN products of separated array, thoroughly cutting and separating capsulation material 29 and insulation filling material 23 form the advanced QFN packaging part 200 of single battle array pin arrangements, in the present embodiment, single product separation method is methods such as blade cuts, laser cutting or the cutting of water cutter, and only cut capsulation material 29 and insulation filling material 23, cutting metal material is not only drawn out the advanced QFN packaging part 200 of 2 face battle array pin arrangements after the cutting and separating among Fig. 6 N.
Description to embodiments of the invention is for effectively illustrating and describe purpose of the present invention, be not in order to limit the present invention, those skilled in the art is to be understood that under any: under the condition that does not break away from inventive concept of the present invention and scope, can change the foregoing description.So the present invention is not limited to disclosed specific embodiment, but cover the modification in the defined the spirit and scope of the invention of claim.
Claims (10)
1. the manufacture method of a limit flat non-pin encapsulation, described four limit flat non-pins encapsulation comprise:
Chip carrier is disposed at the central part of encapsulation, has groove structure and is used for the pin of ground connection, and edge, four limits has staircase structural model along thickness direction, has upper surface, lower surface and ledge surface;
A plurality of pins are disposed at around the chip carrier, have upper surface, lower surface and ledge surface, have staircase structural model along thickness direction, and wherein each pin comprises interior pin that is disposed at this upper surface and the outer pin that is disposed at this lower surface;
Metal material layer is disposed at the upper surface and the lower surface position of chip carrier and a plurality of pins;
The IC chip is disposed on the metal material layer of chip carrier upper surface position;
Adhesive material is disposed between the metal material layer of IC chip and chip carrier upper surface;
Insulation filling material, the staircase structural model that is disposed at a plurality of pins are down and in the groove of chip carrier;
Plain conductor, a plurality of bonding welding pads on the IC chip are connected to a plurality of upper surfaces that dispose the interior pin of metal material layer and dispose the chip carrier of metal material layer respectively by plain conductor;
Capsulation material coats the subregion and the part metals material layer that seal above-mentioned IC chip, adhesive material, plain conductor, chip carrier, a plurality of pins, exposes the metal material layer that is disposed at chip carrier and a plurality of pin lower surfaces;
It is characterized in that comprising:
Configuration mask material layer is at the upper surface and the lower surface configuration mask material layer of thin plate base material;
Form the etching window, the mask material layer of thin plate base material lower surface is carried out exposure imaging technology, form the etching window;
The lower surface selectivity is partially-etched, and as resist layer, it is partially-etched that thin plate base material lower surface is carried out selectivity, forms groove structure with mask material layer with etching window;
Remove the mask material layer that is disposed at thin plate base material lower surface;
The configuration insulation filling material is at thin plate base material lower surface fill insulant in the groove structure of the partially-etched formation of selectivity;
Form the etching window, the mask material layer of thin plate base material upper surface is carried out exposure imaging, form the etching window;
The upper surface selectivity is partially-etched, with mask material layer with etching window as resist layer, it is partially-etched that thin plate base material upper surface is carried out selectivity, forms a plurality of pins with staircase structural model, forms the chip carrier that has staircase structural model, groove structure and be used for the pin of ground connection;
Remove the mask material layer, remove the mask material layer that is disposed at thin plate base material upper surface;
The configuration metal material layer is at upper surface, the lower surface configuration metal material layer of the chip carrier that forms and a plurality of pins;
Configuration IC chip, by adhesive material with the IC chip configuration on the metal material layer of chip carrier upper surface position;
The plain conductor bonding connects, and a plurality of bonding welding pads on the IC chip are connected to respectively by plain conductor and a plurality ofly dispose the interior pin of metal material layer and dispose on the chip carrier of metal material layer;
Form plastic-sealed body, coat the subregion and the part metals material layer of sealing IC chip, adhesive material, plain conductor, chip carrier, a plurality of pins with capsulation material, expose the metal material layer that is disposed at chip carrier and a plurality of pin lower surfaces, toast the back behind the plastic packaging and solidify;
Cutting and separating forms single encapsulation, and cutting and separating forms independently single encapsulation.
2. method according to claim 1 is characterized in that, above-mentioned configuration mask material layer has etch resistant properties, forms by being coated with photic wet film or pasting photic dry film.
3. method according to claim 1 is characterized in that, a plurality of pins and chip carrier are to be resist layer with the mask material layer, and thin plate base material upper surface and the partially-etched making of lower surface selectivity are formed.
4. method according to claim 1 is characterized in that, chip carrier and a plurality of pin of the separation that forms through this etching are connected and fixed by insulation filling material.
5. method according to claim 1 is characterized in that cutting and separating forms single encapsulation, is with blade cuts, laser cutting or the cutting of water cutter cutting method, and only cuts capsulation material and insulation filling material.
6. the manufacture method of a limit flat non-pin encapsulation, described four limit flat non-pins encapsulation comprise:
A plurality of pins are face battle array arranged distribution in encapsulation, have upper surface, lower surface and ledge surface, have staircase structural model along thickness direction, and wherein each pin comprises interior pin that is disposed at this upper surface and the outer pin that is disposed at this lower surface;
Metal material layer is disposed at the upper surface and the lower surface position of a plurality of pins;
The IC chip is disposed on the metal material layer of a plurality of pin upper surfaces position;
Adhesive material is disposed between the metal material layer of IC chip and a plurality of pin upper surfaces;
Insulation filling material is disposed under the staircase structural model of a plurality of pins;
Plain conductor, a plurality of bonding welding pads on the IC chip are connected on a plurality of interior pins that dispose metal material layer by plain conductor;
Capsulation material coats the subregion and the part metals material layer that seal above-mentioned IC chip, adhesive material, plain conductor, a plurality of pins, exposes the metal material layer that is disposed at a plurality of pin lower surfaces;
It is characterized in that comprising:
Configuration mask material layer is at the upper surface and the lower surface configuration mask material layer of thin plate base material;
Form the etching window, the mask material layer of thin plate base material lower surface is carried out exposure imaging technology, form the etching window;
The lower surface selectivity is partially-etched, and as resist layer, it is partially-etched that thin plate base material lower surface is carried out selectivity, forms groove structure with mask material layer with etching window;
Remove the mask material layer that is disposed at thin plate base material lower surface;
The configuration insulation filling material is at thin plate base material lower surface fill insulant in the groove structure of the partially-etched formation of selectivity;
Form the etching window, the mask material layer of thin plate base material upper surface is carried out exposure imaging, form the etching window;
The upper surface selectivity is partially-etched, and as resist layer, it is partially-etched that thin plate base material upper surface is carried out selectivity, forms a plurality of pins that are face battle array arranged distribution with staircase structural model with mask material layer with etching window;
Remove the mask material layer, remove the mask material layer that is disposed at thin plate base material upper surface;
The configuration metal material layer is at the upper surface that forms a plurality of pins, lower surface configuration metal material layer;
Configuration IC chip, by adhesive material with the IC chip configuration on the metal material layer of a plurality of pin upper surface of core position;
The plain conductor bonding connects, and a plurality of bonding welding pads on the IC chip are connected on a plurality of interior pins that dispose metal material layer by plain conductor;
Form plastic-sealed body, coat subregion and the part metals material layer that seals IC chip, adhesive material, plain conductor, a plurality of pins, expose the metal material layer that is disposed at a plurality of pin lower surfaces, toast the back behind the plastic packaging and solidify with capsulation material;
Cutting and separating forms single encapsulation, and cutting and separating forms independently single encapsulation.
7. method according to claim 6 is characterized in that, above-mentioned configuration mask material layer has etch resistant properties, forms by being coated with photic wet film or pasting photic dry film.
8. method according to claim 6 is characterized in that, a plurality of pins that are face battle array arranged distribution are to be resist layer with the mask material layer, and thin plate base material upper surface and the partially-etched making of lower surface selectivity are formed.
9. method according to claim 6 is characterized in that, a plurality of pins of the separation that forms through this etching are connected and fixed by insulation filling material.
10. method according to claim 6 is characterized in that cutting and separating forms single encapsulation, is with blade cuts, laser cutting or the cutting of water cutter cutting method, and only cuts capsulation material and insulation filling material.
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| CN2011103445253A CN102420205B (en) | 2011-11-04 | 2011-11-04 | Manufacturing method of advanced four-side flat pin-free package |
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| CN2011103445253A CN102420205B (en) | 2011-11-04 | 2011-11-04 | Manufacturing method of advanced four-side flat pin-free package |
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| CN102420205B true CN102420205B (en) | 2013-07-31 |
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| CN103474358A (en) * | 2013-09-29 | 2013-12-25 | 华进半导体封装先导技术研发中心有限公司 | Multi-circle QFN package lead frame manufacturing method |
| TWI570856B (en) * | 2014-11-10 | 2017-02-11 | 恆勁科技股份有限公司 | Package structure and method of manufacture |
| CN107492536B (en) * | 2017-08-09 | 2019-08-23 | 林英洪 | Lead frame and its manufacture craft |
| CN110676177A (en) * | 2019-09-29 | 2020-01-10 | 东莞市佳骏电子科技有限公司 | Anti-bending processing method of surface mount type semiconductor device |
| CN113056098B (en) * | 2021-02-10 | 2022-09-23 | 华为数字能源技术有限公司 | Electronic element packaging body, electronic element assembling structure and electronic equipment |
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| CN101131980A (en) * | 2006-08-23 | 2008-02-27 | 南茂科技股份有限公司 | Wafer packaging construction with array connecting pad and method of manufacturing the same |
| CN201752013U (en) * | 2010-04-30 | 2011-02-23 | 江苏长电科技股份有限公司 | Packaging structure capable of directly placing multi-ring pin by chip and passive device |
| CN102354689A (en) * | 2011-11-04 | 2012-02-15 | 北京工业大学 | Quad flat non-lead (QFN) package with leads arranged in plane array and manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030038358A1 (en) * | 2001-08-22 | 2003-02-27 | Walton Advanced Electronics Ltd | Semiconductor package without outer leads |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101131980A (en) * | 2006-08-23 | 2008-02-27 | 南茂科技股份有限公司 | Wafer packaging construction with array connecting pad and method of manufacturing the same |
| CN201752013U (en) * | 2010-04-30 | 2011-02-23 | 江苏长电科技股份有限公司 | Packaging structure capable of directly placing multi-ring pin by chip and passive device |
| CN102354689A (en) * | 2011-11-04 | 2012-02-15 | 北京工业大学 | Quad flat non-lead (QFN) package with leads arranged in plane array and manufacturing method |
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