CN110473853A - A kind of encapsulating structure of DFN device, the packaging method without lead frame carrier and DFN device - Google Patents
A kind of encapsulating structure of DFN device, the packaging method without lead frame carrier and DFN device Download PDFInfo
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- 238000004806 packaging method and process Methods 0.000 title claims description 42
- 238000000034 method Methods 0.000 title claims description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 262
- 239000002184 metal Substances 0.000 claims abstract description 259
- 229910000679 solder Inorganic materials 0.000 claims abstract description 44
- 239000004033 plastic Substances 0.000 claims abstract description 41
- 239000000463 material Substances 0.000 claims description 68
- 239000000758 substrate Substances 0.000 claims description 44
- 238000012545 processing Methods 0.000 claims description 34
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- 238000003466 welding Methods 0.000 claims description 20
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 238000011161 development Methods 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 238000005538 encapsulation Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 239000011368 organic material Substances 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 239000011147 inorganic material Substances 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 239000010935 stainless steel Substances 0.000 claims description 3
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- 239000010931 gold Substances 0.000 claims description 2
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- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 claims 1
- 230000032798 delamination Effects 0.000 claims 1
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- 230000008901 benefit Effects 0.000 description 3
- 239000003814 drug Substances 0.000 description 3
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- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本发明一种DFN器件的封装结构，包括一种无引线框架载体，载体表面设有多个第一金属焊盘，第一金属焊盘的表面设有第二金属焊盘，第二金属焊盘表面设有焊料层，焊料层连接芯片下焊盘或者键合线一端，键合线另一端连接芯片上焊盘。载体的表面及第一金属焊盘、第二金属焊盘、焊料层、芯片、键合线的四周，设有第一塑封层，或者载体的表面及第一金属焊盘的四周，设有第二塑封层、第二塑封层表面及第二金属焊盘、焊料层、芯片、键合线的四周，设有第一塑封层。第二金属焊盘的横截面积大于第一金属焊盘的横截面积，或者第二金属焊盘偏出第一金属焊盘一侧。本发明解决了引线框架封装体引脚电极和塑封料在同一平面易虚焊，封装体切割线导致毛刺，框架变形的问题。
A package structure of a DFN device according to the present invention comprises a lead frameless carrier, a plurality of first metal pads are provided on the surface of the carrier, a second metal pad is provided on the surface of the first metal pad, and the second metal pad A solder layer is provided on the surface, the solder layer is connected to the pad under the chip or one end of the bonding wire, and the other end of the bonding wire is connected to the pad on the chip. The surface of the carrier and the surroundings of the first metal pad, the second metal pad, the solder layer, the chip, and the bonding wire are provided with a first plastic sealing layer, or the surface of the carrier and the surroundings of the first metal pad are provided with a second The second plastic sealing layer, the surface of the second plastic sealing layer and the surroundings of the second metal pad, solder layer, chip and bonding wire are provided with the first plastic sealing layer. The cross-sectional area of the second metal pad is larger than the cross-sectional area of the first metal pad, or the second metal pad deviates from the side of the first metal pad. The invention solves the problems that the pin electrodes of the package body of the lead frame and the plastic sealing compound are easily welded on the same plane, burrs are caused by cutting lines of the package body, and the frame is deformed.
Description
技术领域technical field
本发明涉及微电子封装领域，尤其涉及一种DFN器件的封装结构、无引线框架载体及DFN器件的封装方法。The invention relates to the field of microelectronic packaging, in particular to a packaging structure of a DFN device, a lead frameless carrier and a packaging method of the DFN device.
背景技术Background technique
DFN封装(也叫双边扁平无引脚封装)，是在近几年随着通讯及便携式小型数码电子产品的产生而发展起来的，适用于高频、小体积、高速度等电性能要求的中小规模集成电路的封装。DFN封装能够有效的利用引线脚的封装空间，从而大幅提升了产品的组装效率并降低了实际的占用面积。DFN package (also known as bilateral flat no-lead package) has been developed in recent years with the emergence of communication and portable small digital electronic products. Packaging of large-scale integrated circuits. The DFN package can effectively utilize the packaging space of the lead pins, thereby greatly improving the assembly efficiency of the product and reducing the actual occupied area.
普通的DFN封装，通常包括引线框架、芯片、金属线和塑封料组成。其具体指根据芯片尺寸及电路连通设计框架图形，通过腐蚀工艺完成框架加工，通过设备完成芯片贴装及固化，通过打线完成芯片电极引出后塑封完成整个器件的加工。Ordinary DFN packages usually include lead frames, chips, metal wires and molding compounds. Specifically, it refers to designing the frame graphics according to the chip size and circuit connection, completing the frame processing through the corrosion process, completing the chip mounting and curing through the equipment, and completing the processing of the entire device after the lead-out of the chip electrodes is completed by wire bonding.
但是，针对超小型化的器件，如DFN1006(尺寸1.0mm*0.6mm*0.4mm)、DFN0603(尺寸0.6mm*0.3mm*0.3mm)等，采用现有引线框架的封装结构，存在如下缺陷：However, for ultra-miniature devices, such as DFN1006 (size 1.0mm*0.6mm*0.4mm), DFN0603 (size 0.6mm*0.3mm*0.3mm), etc., the packaging structure of the existing lead frame has the following defects:
(1)封装体的引脚电极和塑封料在同一个平面，不利于器件的整体焊接，容易产生虚焊等缺陷；(1) The pin electrodes of the package body and the plastic encapsulant are on the same plane, which is not conducive to the overall welding of the device, and is prone to defects such as virtual welding;
(2)封装体需要切割到键合线部分，导致器件的侧面存在部分金属毛刺，不利于器件的后续加工；(2) The package needs to be cut to the bonding wire part, resulting in some metal burrs on the side of the device, which is not conducive to the subsequent processing of the device;
(3)封装体受限于引线框架的生产制程，框架本身的厚度，最薄在125μm左右，框架过薄会存在变形严重，导致合格率低的问题。(3) The package body is limited by the production process of the lead frame. The thickness of the frame itself is at least about 125 μm. If the frame is too thin, there will be serious deformation, resulting in a low pass rate.
鉴于上述存在的问题，实现无引线框架的封装结构加工，成为亟待解决的课题。In view of the above-mentioned problems, realizing the processing of the package structure without the lead frame has become an urgent problem to be solved.
发明内容Contents of the invention
本发明的发明目的在于解决现有引线框架的封装结构，封装体的引脚电极和塑封料在同一个平面，不利于器件的整体焊接，容易产生虚焊，封装体需要切割到键合线部分，导致器件的侧面存在部分金属毛刺，不利于器件的后续加工，封装体受限于引线框架的生产制程，框架过薄会存在变形严重，导致合格率低，封装体无法实现超小型化的问题。其具体解决方案如下：The purpose of the present invention is to solve the packaging structure of the existing lead frame. The pin electrodes of the package body and the molding compound are on the same plane, which is not conducive to the overall welding of the device, and it is easy to produce virtual soldering. The package body needs to be cut to the bonding wire part. , resulting in some metal burrs on the side of the device, which is not conducive to the subsequent processing of the device. The package is limited by the production process of the lead frame. If the frame is too thin, there will be serious deformation, resulting in a low pass rate and the problem that the package cannot be miniaturized. . The specific solutions are as follows:
一种无引线框架载体，包括载体，所述载体由下部的基材层、中部的可剥层和上部的金属层构成，所述基材层为金属或者无机或者有机材料中的任一种，其厚度范围为0.6mm-2.0mm，所述可剥层为金属或者有机材料中的任一种，其厚度范围为0.1μm-20μm，可剥层位于基材层的表面，所述金属层为铜或者镍或者锡中的任一种，其厚度范围为10μm-30μm，金属层位于可剥层的表面或者位于可剥层表面以及可剥层和基材层的四周。A lead frameless carrier, including a carrier, the carrier is composed of a lower substrate layer, a middle peelable layer and an upper metal layer, and the substrate layer is any one of metal or inorganic or organic materials, Its thickness ranges from 0.6mm to 2.0mm, the peelable layer is any one of metal or organic material, its thickness ranges from 0.1μm to 20μm, the peelable layer is located on the surface of the substrate layer, and the metal layer is Any one of copper, nickel or tin, the thickness ranges from 10 μm to 30 μm, and the metal layer is located on the surface of the peelable layer or on the surface of the peelable layer and around the peelable layer and the substrate layer.
进一步地，所述基材层为不锈钢或者玻璃或者环氧树脂或者三嗪树脂中的任一种，基材层的材料剥离后，可重复再利用。Further, the base material layer is any one of stainless steel or glass or epoxy resin or triazine resin, and the material of the base material layer can be reused after peeling off.
一种DFN器件的封装结构，包括上述一种无引线框架载体，所述载体的表面设有多个第一金属焊盘，第一金属焊盘的表面设有第二金属焊盘，第二金属焊盘表面设有焊料层，焊料层连接芯片下焊盘或者键合线的一端，键合线的另一端连接芯片上焊盘。可选1：载体的表面及第一金属焊盘、第二金属焊盘、焊料层、芯片、键合线的四周，设有第一塑封层，或者可选2：载体的表面及第一金属焊盘的四周，设有第二塑封层、第二塑封层表面及第二金属焊盘、焊料层、芯片、键合线的四周，设有第一塑封层。A package structure of a DFN device, comprising the above-mentioned lead frameless carrier, the surface of the carrier is provided with a plurality of first metal pads, the surface of the first metal pads is provided with a second metal pad, and the second metal pad A solder layer is provided on the surface of the pad, and the solder layer is connected to the pad under the chip or one end of the bonding wire, and the other end of the bonding wire is connected to the pad on the chip. Option 1: The surface of the carrier and the first metal pad, the second metal pad, the solder layer, the chip, and the surrounding area of the bonding wire are provided with a first plastic sealing layer, or Option 2: the surface of the carrier and the first metal pad The pads are surrounded by a second plastic sealing layer, the surface of the second plastic sealing layer and the second metal pad, the solder layer, the chips, and the bonding wires are surrounded by a first plastic sealing layer.
进一步地，所述封装结构，通过物理方式或者化学方式，将可剥层、基材层与金属层进行剥离。Further, in the packaging structure, the peelable layer, the substrate layer and the metal layer are peeled off physically or chemically.
进一步地，所述第一金属焊盘为铜或者镍中的任一种，第一金属焊盘厚度范围为30μm-50μm。进一步地，所述焊料层为锡或者铟或者合金中的任一种。Further, the first metal pad is any one of copper or nickel, and the thickness of the first metal pad ranges from 30 μm to 50 μm. Further, the solder layer is any one of tin or indium or alloys.
进一步地，所述键合线为键合线，键合线为金线或者铜线中的任一种。Further, the bonding wires are bonding wires, and the bonding wires are either gold wires or copper wires.
进一步地，所述第二金属焊盘为铜或者镍中的任一种，第二金属焊盘厚度范围为5μm-10μm或者30μm-50μm，第二金属焊盘的横截面积大于第一金属焊盘的横截面积，或者第二金属焊盘偏出第一金属焊盘一侧。Further, the second metal pad is any one of copper or nickel, the thickness range of the second metal pad is 5 μm-10 μm or 30 μm-50 μm, and the cross-sectional area of the second metal pad is larger than that of the first metal pad. The cross-sectional area of the pad, or the second metal pad deviates to one side of the first metal pad.
一种DFN器件的封装方法，方案1按照以下步骤进行：A packaging method for a DFN device, scheme 1 is carried out according to the following steps:
步骤1，取一种基材材料，其厚度范围为0.6mm-2.0mm，作为基材层；Step 1, taking a base material with a thickness ranging from 0.6 mm to 2.0 mm as the base layer;
步骤2，在基材层的表面，附着一层具有剥离特性的材料，其厚度范围为0.1μm-20μm，形成可剥层；Step 2, attaching a layer of material with peeling properties on the surface of the substrate layer, the thickness of which is in the range of 0.1 μm-20 μm, to form a peelable layer;
步骤3，通过物理或者化学的方式，在可剥层的整个表面，或者在可剥层整个表面以及可剥层和基材层的四周，增加一层金属，其金属的厚度范围为10μm-30μm，形成金属层；Step 3, by physical or chemical means, add a layer of metal on the entire surface of the peelable layer, or on the entire surface of the peelable layer and around the peelable layer and the substrate layer, and the thickness of the metal is in the range of 10 μm-30 μm , forming a metal layer;
步骤4，根据芯片的导通电路设计，在金属层表面，通过覆盖光感材料、曝光显影方式，露出需加工的多个金属焊盘，光感材料的厚度范围为30μm-50μm；Step 4, according to the conduction circuit design of the chip, on the surface of the metal layer, expose multiple metal pads to be processed by covering the photosensitive material and exposing and developing. The thickness of the photosensitive material ranges from 30 μm to 50 μm;
步骤5，通过电镀方式，在金属焊盘上，加工形成多个第一金属焊盘，第一金属焊盘厚度范围为30μm-50μm；第一金属焊盘与光感材料的厚度相等；Step 5, processing and forming a plurality of first metal pads on the metal pads by electroplating, the thickness of the first metal pads ranges from 30 μm to 50 μm; the thickness of the first metal pads is equal to that of the photosensitive material;
步骤6，持续加电镀的电流，在第一金属焊盘上，形成第二金属焊盘，通过化学方法退掉光感材料，第二金属焊盘厚度范围为5μm-10μm，且第二金属焊盘尺寸比第一金属焊盘尺寸整体大5μm-10μm；Step 6, continue to apply the electroplating current, form a second metal pad on the first metal pad, remove the photosensitive material by chemical method, the thickness of the second metal pad is in the range of 5μm-10μm, and the second metal pad The size of the pad is generally 5 μm-10 μm larger than the size of the first metal pad;
步骤7，在第二金属焊盘上附着一层光感材料，通过曝光显影的方式，生成多个金属焊料的图形；Step 7, attaching a layer of photosensitive material on the second metal pad, and generating multiple metal solder patterns by means of exposure and development;
步骤8，通过电镀或者化镀方式，完成金属焊料层的加工，然后，通过化学方法去掉多余的光感材料；Step 8, complete the processing of the metal solder layer by electroplating or electroless plating, and then remove the excess photosensitive material by chemical methods;
步骤9，通过涂布助焊剂、将芯片下焊盘贴装到有焊料的第二金属焊盘上，加热后完成焊接；Step 9, by applying flux, attaching the pad under the chip to the second metal pad with solder, and completing the welding after heating;
步骤10，通过超声焊方式，将键合线的一端焊接于第二金属焊盘上，键合线的另一端，焊接于芯片上焊盘上；Step 10, welding one end of the bonding wire to the second metal pad by means of ultrasonic welding, and welding the other end of the bonding wire to the pad on the chip;
步骤11，将载体的表面及第一金属焊盘、第二金属焊盘、焊料层、芯片、键合线的四周，进行塑封，完成第一塑封层的封装；Step 11, plastic-encapsulate the surface of the carrier and the surroundings of the first metal pad, the second metal pad, the solder layer, the chip, and the bonding wire to complete the packaging of the first plastic-encapsulation layer;
步骤12，将已经完成封装的载体，通过物理或者化学的方式，将器件和载体从可剥层进行分离，剥离后的基材层可重复再利用；Step 12, separating the packaged carrier from the peelable layer by physical or chemical means, and the peeled substrate layer can be reused;
步骤13，在器件的底表面，通过物理或者化学的方式，根据器件的结构设计，去除掉多余的金属部分，完成器件焊盘的加工和器件的加工。Step 13, on the bottom surface of the device, by physical or chemical means, according to the structural design of the device, the redundant metal part is removed, and the processing of the device pad and the device are completed.
一种DFN器件的封装方法，方案2按照以下步骤进行：A packaging method for a DFN device, scheme 2 is carried out according to the following steps:
步骤1，取一种基材材料，其厚度范围为0.6mm-2.0mm，作为基材层；Step 1, taking a base material with a thickness ranging from 0.6 mm to 2.0 mm as the base layer;
步骤2，在基材层的表面，附着一层具有剥离特性的材料，其厚度范围为0.1μm-20μm，形成可剥层；Step 2, attaching a layer of material with peeling properties on the surface of the substrate layer, the thickness of which is in the range of 0.1 μm-20 μm, to form a peelable layer;
步骤3，通过物理或者化学的方式，在可剥层的整个表面，或者在可剥层整个表面以及可剥层和基材层的四周，增加一层金属，其金属的厚度范围为10μm-30μm，形成金属层；Step 3, by physical or chemical means, add a layer of metal on the entire surface of the peelable layer, or on the entire surface of the peelable layer and around the peelable layer and the substrate layer, and the thickness of the metal is in the range of 10 μm-30 μm , forming a metal layer;
步骤4，根据芯片的导通电路设计，在金属层表面，通过覆盖光感材料、曝光显影方式，露出需加工的多个金属焊盘，光感材料的厚度范围为30μm-50μm；Step 4, according to the conduction circuit design of the chip, on the surface of the metal layer, expose multiple metal pads to be processed by covering the photosensitive material and exposing and developing. The thickness of the photosensitive material ranges from 30 μm to 50 μm;
步骤5，通过电镀方式，在金属焊盘上，加工形成多个第一金属焊盘，第一金属焊盘厚度范围为30μm-50μm；第一金属焊盘与光感材料的厚度相等，通过化学方法退掉光感材料；Step 5, process and form a plurality of first metal pads on the metal pads by electroplating, the thickness of the first metal pads ranges from 30 μm to 50 μm; the thickness of the first metal pads is equal to that of the photosensitive material, and through chemical The method returns the photosensitive material;
步骤6，将载体的表面及第一金属焊盘的四周，进行塑封，完成第二塑封层的封装，并露出第一金属焊盘上表面；Step 6, plastic-encapsulating the surface of the carrier and the surroundings of the first metal pad to complete the packaging of the second plastic layer and expose the upper surface of the first metal pad;
步骤7，在第二塑封层及第一金属焊盘上表面，附着一层光感材料，通过曝光显影的方式，生成多个第二金属焊盘的图形；Step 7, attach a layer of photosensitive material to the upper surface of the second plastic sealing layer and the first metal pad, and generate a plurality of patterns of the second metal pad by exposure and development;
步骤8，通过电镀方式，在第二金属焊盘的图形上，加工形成第二金属焊盘，第二金属焊盘厚度范围为30μm-50μm，通过化学方法退掉光感材料；Step 8, processing and forming a second metal pad on the pattern of the second metal pad by electroplating, the second metal pad has a thickness ranging from 30 μm to 50 μm, and chemically removes the photosensitive material;
步骤9，在第二金属焊盘上表面，附着一层光感材料，通过曝光显影的方式，生成多个金属焊料的图形；Step 9, attaching a layer of photosensitive material on the upper surface of the second metal pad, and generating a plurality of metal solder patterns by means of exposure and development;
步骤10，通过电镀或者化镀方式，完成金属焊料层的加工，然后，通过化学方法去掉多余的光感材料；Step 10, complete the processing of the metal solder layer by means of electroplating or electroless plating, and then remove excess photosensitive material by chemical methods;
步骤11，通过涂布助焊剂、将芯片下焊盘贴装到有焊料的第二金属焊盘上，加热后完成焊接；Step 11, by applying flux, attaching the pad under the chip to the second metal pad with solder, and completing the welding after heating;
步骤12，通过超声焊方式，将键合线的一端焊接于第二金属焊盘上，键合线的另一端，焊接于芯片上焊盘上；Step 12, welding one end of the bonding wire to the second metal pad by means of ultrasonic welding, and welding the other end of the bonding wire to the pad on the chip;
步骤13，将第二塑封层表面及第二金属焊盘、焊料层、芯片、键合线的四周，进行塑封，完成第一塑封层的封装；Step 13, plastic sealing the surface of the second plastic sealing layer and the surroundings of the second metal pad, solder layer, chip, and bonding wire to complete the packaging of the first plastic sealing layer;
步骤14，将已经完成封装的载体，通过物理或者化学的方式，将器件和载体从可剥层进行分离，剥离后的基材层可重复再利用；Step 14, separating the packaged carrier from the peelable layer by physical or chemical means, and the peeled substrate layer can be reused;
步骤15，在器件的底表面，通过物理或者化学的方式，根据器件的结构设计，去除掉多余的金属部分，完成器件焊盘的加工和器件的加工。Step 15, on the bottom surface of the device, by physical or chemical means, according to the structural design of the device, the redundant metal part is removed, and the processing of the device pad and the device are completed.
综上所述，采用本发明的技术方案具有以下有益效果：In summary, adopting the technical solution of the present invention has the following beneficial effects:
本发明解决了现有引线框架的封装结构，封装体的引脚电极和塑封料在同一个平面，不利于器件的整体焊接，容易产生虚焊，封装体需要切割到键合线部分，导致器件的侧面存在部分金属毛刺，不利于器件的后续加工，封装体受限于引线框架的生产制程，框架过薄会存在变形严重，导致合格率低，封装体无法实现超小型化的问题。The present invention solves the packaging structure of the existing lead frame. The lead electrodes of the package body and the plastic encapsulant are on the same plane, which is not conducive to the overall welding of the device, and it is easy to produce virtual soldering. The package body needs to be cut to the bonding wire part, resulting in There are some metal burrs on the side of the device, which is not conducive to the subsequent processing of the device. The package is limited by the production process of the lead frame. If the frame is too thin, there will be serious deformation, resulting in a low pass rate and the problem that the package cannot be ultra-miniature.
采用本方案具有以下优点：Adopting this scheme has the following advantages:
(1)能够完成超薄型框架的加工，框架厚度(指金属层+第一金属焊盘+第二金属焊盘)最薄可控制在40μm-80μm；(1) The processing of ultra-thin frames can be completed, and the thickness of the frame (referring to the metal layer + the first metal pad + the second metal pad) can be controlled at the thinnest between 40 μm and 80 μm;
(2)能够实现无引线的框架加工，即封装体器件的侧面不存在露金属现象；(2) Leadless frame processing can be realized, that is, there is no metal exposure on the side of the package device;
(3)能够实现器件焊盘高于塑封本体表面，更加利于器件的焊接，露出的器件焊盘高度可控制在10μm-30μm；(3) It can realize that the device pad is higher than the surface of the plastic package body, which is more conducive to the welding of the device, and the height of the exposed device pad can be controlled at 10 μm-30 μm;
(4)采用第二金属焊盘与第一金属焊盘组成的T型结构设计，增强了焊盘的可靠性；(4) The T-shaped structure design composed of the second metal pad and the first metal pad is adopted to enhance the reliability of the pad;
(5)采用第二金属焊盘与第一金属焊盘组成的阶梯型结构设计，可缩减焊盘之间的间距；(5) The stepped structure design composed of the second metal pad and the first metal pad can reduce the distance between the pads;
(6)载体采用金属层包裹可剥层及可剥层和基材层的四周，这种方式保证了整个可剥离材料在后续的制程中，性能更加稳定，不容易存在进药水的现象。(6) The carrier uses a metal layer to wrap the peelable layer and the surroundings of the peelable layer and the substrate layer. This method ensures that the performance of the entire peelable material is more stable in the subsequent manufacturing process, and it is not easy to enter the phenomenon of liquid medicine.
附图说明Description of drawings
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例的描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本发明的一部分实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还能够根据这些附图获得其他的附图。In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the drawings required for the description of the embodiments of the present invention. Apparently, the drawings in the following description are only part of the embodiments of the present invention, and those skilled in the art can obtain other drawings according to these drawings without any creative effort.
图1为本发明实施例1一种无引线框架载体的结构图；FIG. 1 is a structural diagram of a lead frame-less carrier according to Embodiment 1 of the present invention;
图2为本发明实施例1一种DFN器件的封装结构的结构图；2 is a structural diagram of a packaging structure of a DFN device in Embodiment 1 of the present invention;
图3为本发明实施例1可剥层剥离的结构图；Fig. 3 is a structural diagram of peeling off the peelable layer of Embodiment 1 of the present invention;
图4为本发明实施例1器件及器件焊盘的结构图；4 is a structural diagram of a device and a device pad in Embodiment 1 of the present invention;
图5为本发明实施例2器件及器件焊盘的结构图；5 is a structural diagram of a device and a device pad in Embodiment 2 of the present invention;
图6为本发明实施例3一种无引线框架载体的结构图；6 is a structural diagram of a lead frame-less carrier according to Embodiment 3 of the present invention;
图7为本发明实施例3一种DFN器件的封装结构的结构图；7 is a structural diagram of a packaging structure of a DFN device according to Embodiment 3 of the present invention;
图8为本发明实施例4一种DFN器件的封装结构的结构图；8 is a structural diagram of a packaging structure of a DFN device according to Embodiment 4 of the present invention;
图9为本发明实施例4器件及器件焊盘的结构图；FIG. 9 is a structural diagram of a device and a device pad in Embodiment 4 of the present invention;
图10一种DFN器件的封装方法方案1光感材料、金属焊盘、第一金属焊盘、第二金属焊盘的结构图。FIG. 10 is a structural diagram of a photosensitive material, a metal pad, a first metal pad, and a second metal pad in Scheme 1 of a packaging method for a DFN device.
附图标记说明：Explanation of reference signs:
1-基材层，2-可剥层，3-金属层，4-第一金属焊盘，5-第二金属焊盘，6-焊料层，7-芯片，8-下焊盘，9-键合线，10-第一塑封层，11-器件焊盘，12-切割线，13-第二塑封层，14-光感材料，15-金属焊盘。1-substrate layer, 2-peelable layer, 3-metal layer, 4-first metal pad, 5-second metal pad, 6-solder layer, 7-chip, 8-lower pad, 9- Bonding wire, 10-first plastic sealing layer, 11-device pad, 12-cutting line, 13-second plastic sealing layer, 14-photosensitive material, 15-metal pad.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
需要说明的是，本方案中的全部附图，均为截面结构图，附图所示仅为帮助理解本方案的发明构思及结构原理，不等于实物产品。It should be noted that all the drawings in this scheme are cross-sectional structural diagrams, and the drawings shown in the drawings are only to help understand the inventive concepts and structural principles of this scheme, and are not equal to physical products.
实施例1:Example 1:
如图1所示，一种无引线框架载体，包括载体，载体由下部的基材层1、中部的可剥层2和上部的金属层3构成，基材层1为金属或者无机或者有机材料中的任一种，其厚度范围为0.6mm-2.0mm，可剥层2为金属或者有机材料中的任一种，其厚度范围为0.1μm-20μm，可剥层2位于基材层1的表面，金属层3为铜或者镍或者锡中的任一种，其厚度范围为10μm-30μm，金属层3位于可剥层的表面。As shown in Figure 1, a lead frame-free carrier includes a carrier, the carrier is composed of a lower substrate layer 1, a middle peelable layer 2 and an upper metal layer 3, and the substrate layer 1 is made of metal or inorganic or organic materials Any one of them, the thickness range is 0.6mm-2.0mm, the peelable layer 2 is any one of metal or organic material, the thickness range is 0.1μm-20μm, the peelable layer 2 is located on the base layer 1 On the surface, the metal layer 3 is any one of copper, nickel or tin, and its thickness ranges from 10 μm to 30 μm, and the metal layer 3 is located on the surface of the peelable layer.
进一步地，基材层1为不锈钢或者玻璃或者环氧树脂或者三嗪树脂中的任一种，基材层1的材料剥离后，可重复再利用。Further, the substrate layer 1 is any one of stainless steel or glass or epoxy resin or triazine resin, and the material of the substrate layer 1 can be reused after peeling off.
如图2所示，一种DFN(也叫双边扁平无引脚)器件的封装结构，包括上述一种无引线框架载体，载体的表面(即金属层3表面)设有多个第一金属焊盘4，第一金属焊盘4的表面设有第二金属焊盘5，第二金属焊盘5表面设有焊料层6，焊料层6连接芯片7下焊盘8或者键合线9的一端，键合线9的另一端连接芯片7上焊盘(图中未画出)。可选地，载体的表面及第一金属焊盘4、第二金属焊盘5、焊料层6、芯片7、键合线9的四周，设有第一塑封层10。As shown in Figure 2, a packaging structure of a DFN (also known as double-sided flat no-lead) device includes the above-mentioned lead frame-free carrier, and the surface of the carrier (ie, the surface of the metal layer 3) is provided with a plurality of first metal solder joints. Plate 4, the surface of the first metal pad 4 is provided with a second metal pad 5, the surface of the second metal pad 5 is provided with a solder layer 6, and the solder layer 6 is connected to one end of the pad 8 or the bonding wire 9 under the chip 7 , the other end of the bonding wire 9 is connected to the pad on the chip 7 (not shown in the figure). Optionally, a first plastic encapsulation layer 10 is provided on the surface of the carrier and around the first metal pad 4 , the second metal pad 5 , the solder layer 6 , the chip 7 , and the bonding wire 9 .
进一步地，第一金属焊盘4为铜或者镍中的任一种，第一金属焊盘4厚度范围为30μm-50μm。Further, the first metal pad 4 is any one of copper or nickel, and the thickness of the first metal pad 4 ranges from 30 μm to 50 μm.
进一步地，第二金属焊盘5为铜或者镍中的任一种，第二金属焊盘5厚度范围为5μm-10μm，第二金属焊盘5的横截面积大于第一金属焊盘4的横截面积，第二金属焊盘5与第一金属焊盘4组成T型焊盘(从纵截面上看)，增强了焊盘可靠性。Further, the second metal pad 5 is any one of copper or nickel, the thickness range of the second metal pad 5 is 5 μm-10 μm, and the cross-sectional area of the second metal pad 5 is larger than that of the first metal pad 4 Cross-sectional area, the second metal pad 5 and the first metal pad 4 form a T-shaped pad (viewed from the longitudinal section), which enhances the reliability of the pad.
进一步地，焊料层6为锡或者铟或者合金中的任一种。Further, the solder layer 6 is any one of tin or indium or an alloy.
进一步地，键合线9为金线或者铜线中的任一种。Further, the bonding wire 9 is any one of gold wire or copper wire.
进一步地，如图3所示，上述封装结构，通过物理方式或者化学方式，将可剥层2、基材层1与金属层3进行剥离。然后在器件的底表面(指金属层3的底表面)，通过物理或者化学的方式，根据器件的结构设计，去除掉多余的金属部分，完成器件焊盘11的加工和器件的加工，如图4所示，从图中可以看出，本实施例1的特点是，一个第一金属焊盘4连接至一个器件焊盘11。Further, as shown in FIG. 3 , in the above-mentioned packaging structure, the peelable layer 2 , the base material layer 1 and the metal layer 3 are peeled off physically or chemically. Then, on the bottom surface of the device (referring to the bottom surface of the metal layer 3), by physical or chemical means, according to the structural design of the device, the redundant metal part is removed, and the processing of the device pad 11 and the processing of the device are completed, as shown in the figure 4 , it can be seen from the figure that the feature of Embodiment 1 is that one first metal pad 4 is connected to one device pad 11 .
实施例2：Example 2:
如图5所示，与实施例1所不同的是，多个来自芯片7下焊盘8的第一金属焊盘4连接至一个器件焊盘11，一个来自芯片7上焊盘及键合线9的第一金属焊盘4连接至另一个器件焊盘11，本实施例2的优点是，能够有效改善芯片7温升或者多脚(指多个下焊盘8或者金属焊盘4)并接的问题。其余部分的内容与实施例1完全相同，不再赘述。As shown in Figure 5, the difference from Embodiment 1 is that a plurality of first metal pads 4 from the lower pads 8 of the chip 7 are connected to one device pad 11, and one is from the upper pads and bonding wires of the chip 7. The first metal pad 4 of 9 is connected to another device pad 11. The advantage of Embodiment 2 is that it can effectively improve the temperature rise of the chip 7 or multiple pins (referring to multiple lower pads 8 or metal pads 4) and answering question. The content of the remaining parts is exactly the same as that of Embodiment 1, and will not be repeated here.
实施例3：Example 3:
如图6、7所示，与实施例1所不同的是，载体的金属层3位于可剥层2表面以及可剥层2和基材层1的四周，这种结构保证了整个可剥离材料(包括可剥层2和基材层1)，在后续的制程中，性能更加稳定，不容易存在进药水的现象。在完成封装结构后，沿着封装体四周的切割线12，进行切割，然后再通过物理方式，将可剥层2、基材层1与金属层3进行剥离。其余部分的内容与实施例1完全相同，不再赘述。As shown in Figures 6 and 7, the difference from Example 1 is that the metal layer 3 of the carrier is located on the surface of the peelable layer 2 and around the peelable layer 2 and the substrate layer 1. This structure ensures that the entire peelable material (including the peelable layer 2 and the substrate layer 1), in the subsequent manufacturing process, the performance is more stable, and it is not easy to enter the phenomenon of liquid medicine. After the packaging structure is completed, cutting is carried out along the cutting line 12 around the package body, and then the peelable layer 2, the base material layer 1 and the metal layer 3 are peeled off by physical means. The content of the remaining parts is exactly the same as that of Embodiment 1, and will not be repeated here.
实施例4：Example 4:
如图8、9所示，与实施例3所不同的是，载体的表面及第一金属焊盘4的四周，设有第二塑封层13，第二塑封层13表面及第二金属焊盘5、焊料层6、芯片7、键合线9的四周，设有第一塑封层10。第二金属焊盘5偏出第一金属焊盘4一侧，第二金属焊盘5的厚度范围为30μm-50μm，本实施例4的第二金属焊盘5与第一金属焊盘4组成阶梯型焊盘(从纵截面上看)结构，可以将芯片7内部的间隔较小的下焊盘8及第二金属焊盘5，经第一金属焊盘4变换成器件外的间隔较大的器件焊盘11。其余部分的内容与实施例3完全相同，不再赘述。As shown in Figures 8 and 9, the difference from Embodiment 3 is that the surface of the carrier and the surroundings of the first metal pad 4 are provided with a second plastic sealing layer 13, and the surface of the second plastic sealing layer 13 and the second metal pad 5. A first plastic sealing layer 10 is provided around the solder layer 6 , the chip 7 and the bonding wire 9 . The second metal pad 5 deviates from the side of the first metal pad 4, and the thickness of the second metal pad 5 ranges from 30 μm to 50 μm. The second metal pad 5 and the first metal pad 4 in this embodiment 4 are composed The stepped pad (viewed from the longitudinal section) structure can convert the lower pad 8 and the second metal pad 5 with a smaller interval inside the chip 7 into a larger interval outside the device through the first metal pad 4 The device pad 11. The content of the remaining parts is exactly the same as that of Embodiment 3, and will not be repeated here.
一种DFN器件的封装方法，方案1按照以下步骤实施：A packaging method for a DFN device, scheme 1 is implemented according to the following steps:
步骤1，取一种基材材料，其厚度范围为0.6mm-2.0mm，作为基材层1(如图1所示)；Step 1, take a base material with a thickness ranging from 0.6 mm to 2.0 mm as the base layer 1 (as shown in Figure 1);
步骤2，在基材层1的表面，附着一层具有剥离特性的材料，其厚度范围为0.1μm-20μm，形成可剥层2(如图1所示)；Step 2, on the surface of the substrate layer 1, attach a layer of material with peeling properties, the thickness of which ranges from 0.1 μm to 20 μm, to form a peelable layer 2 (as shown in Figure 1);
步骤3，通过物理或者化学的方式，在可剥层2的整个表面(如图1所示为可选方式一)，或者在可剥层2整个表面以及可剥层2和基材层1的四周(如图6所示为可选方式二)，增加一层金属，其金属的厚度范围为10μm-30μm，形成金属层3；Step 3, by physical or chemical means, on the entire surface of the peelable layer 2 (as shown in Figure 1 is optional way 1), or on the entire surface of the peelable layer 2 and between the peelable layer 2 and the substrate layer 1 Around (as shown in Figure 6 is optional mode 2), add a layer of metal, the thickness of the metal ranges from 10 μm to 30 μm, forming a metal layer 3;
步骤4，根据芯片7的导通电路设计，在金属层3表面，通过覆盖光感材料14、曝光显影方式，露出需加工的多个金属焊盘15(实际为金属层3的一部分)，光感材料14的厚度范围为30μm-50μm；(如图10所示)Step 4, according to the conduction circuit design of the chip 7, on the surface of the metal layer 3, by covering the photosensitive material 14, exposing and developing, a plurality of metal pads 15 (actually a part of the metal layer 3) to be processed are exposed, and the light The thickness range of the sensing material 14 is 30 μm-50 μm; (as shown in FIG. 10 )
步骤5，通过电镀方式，在金属焊盘15上，加工形成多个第一金属焊盘4，第一金属焊盘4厚度范围为30μm-50μm；第一金属焊盘4与光感材料14的厚度相等；(如图10所示)Step 5, process and form a plurality of first metal pads 4 on the metal pad 15 by means of electroplating, the thickness of the first metal pads 4 ranges from 30 μm to 50 μm; the first metal pad 4 and the photosensitive material 14 The thickness is equal; (as shown in Figure 10)
步骤6，持续加电镀的电流，在第一金属焊盘4上，形成第二金属焊盘5，通过化学方法退掉光感材料14，第二金属焊盘5厚度范围为5μm-10μm，且第二金属焊盘尺寸比第一金属焊盘尺寸整体大5μm-10μm；(如图10所示)Step 6, continue to apply the electroplating current, form the second metal pad 5 on the first metal pad 4, remove the photosensitive material 14 by chemical method, the thickness of the second metal pad 5 is in the range of 5 μm-10 μm, and The size of the second metal pad is 5 μm-10 μm larger than the size of the first metal pad as a whole; (as shown in Figure 10)
步骤7，在第二金属焊盘5上附着一层光感材料，通过曝光显影的方式，生成多个金属焊料的图形；Step 7, attach a layer of photosensitive material on the second metal pad 5, and generate a plurality of patterns of metal solder by exposure and development;
步骤8，通过电镀或者化镀方式，完成金属焊料层6的加工，然后，通过化学方法去掉多余的光感材料；(如图2、5所示)Step 8, complete the processing of the metal solder layer 6 by electroplating or electroless plating, and then remove the excess photosensitive material by chemical methods; (as shown in Figures 2 and 5)
步骤9，通过涂布助焊剂、将芯片7下焊盘8贴装到有焊料的第二金属焊盘5上，加热后完成焊接；(如图2、5所示)Step 9, by applying flux, attaching the lower pad 8 of the chip 7 to the second metal pad 5 with solder, and completing the welding after heating; (as shown in Figures 2 and 5)
步骤10，通过超声焊方式，将键合线9的一端焊接于第二金属焊盘5上，键合线9的另一端，焊接于芯片7上焊盘上；(如图2、5所示)Step 10, by means of ultrasonic welding, one end of the bonding wire 9 is welded on the second metal pad 5, and the other end of the bonding wire 9 is welded on the pad on the chip 7; (as shown in Figures 2 and 5 )
步骤11，将载体的表面及第一金属焊盘4、第二金属焊盘5、焊料层6、芯片7、键合线9的四周，进行塑封，完成第一塑封层10的封装；(如图2、5所示)Step 11, the surface of the carrier and the surroundings of the first metal pad 4, the second metal pad 5, the solder layer 6, the chip 7, and the bonding wire 9 are plastic-sealed to complete the packaging of the first plastic-seal layer 10; (such as As shown in Figure 2 and 5)
步骤12，将已经完成封装的载体，通过物理或者化学的方式，将器件和载体从可剥层2进行分离，剥离后的基材层1可重复再利用；(如图3所示)Step 12, separating the packaged carrier from the peelable layer 2 by physical or chemical means, and the peeled substrate layer 1 can be reused; (as shown in Figure 3)
这里的物理方式是指机械力剥离，化学方式是指加热、药水浸泡等实现剥离。剥离后的器件一面是黑色的塑封料；一面是底面的金属(即金属层3)；The physical method here refers to mechanical peeling, and the chemical method refers to heating, liquid medicine immersion, etc. to achieve peeling. One side of the stripped device is black plastic encapsulant; one side is the metal on the bottom surface (that is, metal layer 3);
步骤13，在器件的底表面(指金属层3的底表面)，通过物理或者化学的方式，根据器件的结构设计，去除掉多余的金属部分，完成器件焊盘11的加工和器件的加工。(如图4、5所示)Step 13, on the bottom surface of the device (referring to the bottom surface of the metal layer 3), by physical or chemical means, according to the structural design of the device, the redundant metal part is removed, and the processing of the device pad 11 and the processing of the device are completed. (As shown in Figure 4 and 5)
这里的物理方式是指，通过激光烧蚀等工艺完成金属去除，化学方式是指，通过光感材料，曝光显影及蚀刻等完成器件焊盘11的加工。器件焊盘11尺寸与器件内部第一金属焊盘4尺寸相比，可以等大、也可以更大或者更小。Here, the physical method refers to metal removal through laser ablation and other processes, and the chemical method refers to the completion of the processing of the device pad 11 through photosensitive materials, exposure and development, and etching. The size of the device pad 11 can be equal to, larger or smaller than that of the first metal pad 4 inside the device.
一种DFN器件的封装方法，方案2按照以下步骤实施：A packaging method for a DFN device, scheme 2 is implemented according to the following steps:
步骤1，取一种基材材料，其厚度范围为0.6mm-2.0mm，作为基材层1；Step 1, taking a substrate material with a thickness ranging from 0.6 mm to 2.0 mm, as the substrate layer 1;
步骤2，在基材层1的表面，附着一层具有剥离特性的材料，其厚度范围为0.1μm-20μm，形成可剥层2；Step 2, on the surface of the substrate layer 1, attach a layer of material with peeling properties, the thickness of which ranges from 0.1 μm to 20 μm, to form a peelable layer 2;
步骤3，通过物理或者化学的方式，在可剥层2的整个表面，或者在可剥层2整个表面以及可剥层2和基材层1的四周，增加一层金属，其金属的厚度范围为10μm-30μm，形成金属层3；Step 3, by physical or chemical means, add a layer of metal on the entire surface of the peelable layer 2, or on the entire surface of the peelable layer 2 and around the peelable layer 2 and the substrate layer 1, and the thickness range of the metal is 10 μm-30 μm, forming a metal layer 3;
步骤4，根据芯片7的导通电路设计，在金属层3表面，通过覆盖光感材料、曝光显影方式，露出需加工的多个金属焊盘15，光感材料的厚度范围为30μm-50μm；Step 4, according to the conduction circuit design of the chip 7, on the surface of the metal layer 3, by covering the photosensitive material, exposing and developing, a plurality of metal pads 15 to be processed are exposed, and the thickness of the photosensitive material ranges from 30 μm to 50 μm;
步骤5，通过电镀方式，在金属焊盘15上，加工形成多个第一金属焊盘4，第一金属焊盘4厚度范围为30μm-50μm；第一金属焊盘4与光感材料的厚度相等，通过化学方法退掉光感材料；Step 5, process and form a plurality of first metal pads 4 on the metal pad 15 by means of electroplating, the thickness of the first metal pads 4 ranges from 30 μm to 50 μm; the thickness of the first metal pads 4 and the photosensitive material Equal, the photosensitive material is removed by chemical methods;
步骤6，将载体的表面及第一金属焊盘4的四周，进行塑封，完成第二塑封层13的封装，并露出第一金属焊盘4上表面；(如图8、9所示)Step 6, plastic-encapsulate the surface of the carrier and the surroundings of the first metal pad 4, complete the packaging of the second plastic-encapsulation layer 13, and expose the upper surface of the first metal pad 4; (as shown in Figures 8 and 9)
步骤7，在第二塑封层13及第一金属焊盘4上表面，附着一层光感材料，通过曝光显影的方式，生成多个第二金属焊盘5的图形；Step 7, attach a layer of photosensitive material on the upper surface of the second plastic sealing layer 13 and the first metal pad 4, and generate a plurality of patterns of the second metal pad 5 by means of exposure and development;
步骤8，通过电镀方式，在第二金属焊盘5的图形上，加工形成第二金属焊盘5，第二金属焊盘5厚度范围为30μm-50μm，通过化学方法退掉光感材料；(如图8、9所示)Step 8, process and form the second metal pad 5 on the pattern of the second metal pad 5 by electroplating, the second metal pad 5 has a thickness ranging from 30 μm to 50 μm, and remove the photosensitive material by chemical method; ( As shown in Figure 8 and 9)
步骤9，在第二金属焊盘5上表面，附着一层光感材料，通过曝光显影的方式，生成多个金属焊料的图形；(如图8、9所示)Step 9, on the upper surface of the second metal pad 5, attach a layer of photosensitive material, and generate a plurality of patterns of metal solder by means of exposure and development; (as shown in Figures 8 and 9)
步骤10，通过电镀或者化镀方式，完成金属焊料层6的加工，然后，通过化学方法去掉多余的光感材料；(如图8、9所示)Step 10, complete the processing of the metal solder layer 6 by means of electroplating or electroless plating, and then remove excess photosensitive material by chemical methods; (as shown in Figures 8 and 9)
步骤11，通过涂布助焊剂、将芯片7下焊盘8贴装到有焊料的第二金属焊盘5上，加热后完成焊接；(如图8、9所示)Step 11, by applying flux, attaching the lower pad 8 of the chip 7 to the second metal pad 5 with solder, and completing the welding after heating; (as shown in Figures 8 and 9)
步骤12，通过超声焊方式，将键合线9的一端焊接于第二金属焊盘5上，键合线9的另一端，焊接于芯片7上焊盘上；(如图8、9所示)Step 12, by means of ultrasonic welding, one end of the bonding wire 9 is welded on the second metal pad 5, and the other end of the bonding wire 9 is welded on the pad on the chip 7; (as shown in Figures 8 and 9 )
步骤13，将第二塑封层13表面及第二金属焊盘5、焊料层6、芯片7、键合线9的四周，进行塑封，完成第一塑封层10的封装；(如图8、9所示)Step 13, the surface of the second plastic sealing layer 13 and the surroundings of the second metal pad 5, the solder layer 6, the chip 7, and the bonding wire 9 are plastic-sealed to complete the packaging of the first plastic sealing layer 10; (as shown in Figures 8 and 9 shown)
步骤14，将已经完成封装的载体，通过物理或者化学的方式，将器件和载体从可剥层2进行分离，剥离后的基材层1可重复再利用；(如图9所示)Step 14, separating the packaged carrier from the peelable layer 2 by physical or chemical means, and the peeled substrate layer 1 can be reused; (as shown in Figure 9)
步骤15，在器件的底表面，通过物理或者化学的方式，根据器件的结构设计，去除掉多余的金属部分，完成器件焊盘11的加工和器件的加工。(如图9所示)Step 15 , on the bottom surface of the device, remove redundant metal parts by physical or chemical means according to the structural design of the device, and complete the processing of the device pad 11 and the device. (as shown in Figure 9)
综上所述，采用本发明的技术方案具有以下有益效果：In summary, adopting the technical solution of the present invention has the following beneficial effects:
本发明解决了现有引线框架的封装结构，封装体的引脚电极和塑封料在同一个平面，不利于器件的整体焊接，容易产生虚焊，封装体需要切割到键合线部分，导致器件的侧面存在部分金属毛刺，不利于器件的后续加工，封装体受限于引线框架的生产制程，框架过薄会存在变形严重，导致合格率低，封装体无法实现超小型化的问题。The present invention solves the packaging structure of the existing lead frame. The lead electrodes of the package body and the plastic encapsulant are on the same plane, which is not conducive to the overall welding of the device, and it is easy to produce virtual soldering. The package body needs to be cut to the bonding wire part, resulting in There are some metal burrs on the side of the device, which is not conducive to the subsequent processing of the device. The package is limited by the production process of the lead frame. If the frame is too thin, there will be serious deformation, resulting in a low pass rate and the problem that the package cannot be ultra-miniature.
采用本方案具有以下优点：Adopting this scheme has the following advantages:
(1)能够完成超薄型框架的加工，框架厚度(指金属层3+第一金属焊盘4+第二金属焊盘5)最薄可控制在40μm-80μm；(1) The processing of ultra-thin frames can be completed, and the thickness of the frame (referring to the metal layer 3 + the first metal pad 4 + the second metal pad 5) can be controlled at the thinnest between 40 μm and 80 μm;
(2)能够实现无引线的框架加工，即封装体器件的侧面不存在露金属现象；(2) Leadless frame processing can be realized, that is, there is no metal exposure on the side of the package device;
(3)能够实现器件焊盘11高于塑封本体表面，更加利于器件的焊接，露出的器件焊盘11高度可控制在10μm-30μm；(3) It can realize that the device pad 11 is higher than the surface of the plastic package body, which is more conducive to the welding of the device, and the height of the exposed device pad 11 can be controlled at 10 μm-30 μm;
(4)采用第二金属焊盘5与第一金属焊盘4组成的T型结构设计，增强了焊盘的可靠性；(4) The T-shaped structure design composed of the second metal pad 5 and the first metal pad 4 is adopted, which enhances the reliability of the pad;
(5)采用第二金属焊盘5与第一金属焊盘4组成的阶梯型结构设计，可缩减焊盘之间的间距；(5) The stepped structure design composed of the second metal pad 5 and the first metal pad 4 can be used to reduce the distance between the pads;
(6)载体采用金属层3包裹可剥层2及可剥层2和基材层1的四周，这种方式保证了整个可剥离材料在后续的制程中，性能更加稳定，不容易存在进药水的现象。(6) The carrier uses the metal layer 3 to wrap the peelable layer 2 and the surroundings of the peelable layer 2 and the base material layer 1. This method ensures that the performance of the entire peelable material is more stable in the subsequent manufacturing process, and it is not easy to enter the potion The phenomenon.
以上所述的实施方式，并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。The implementation methods described above do not constitute a limitation to the scope of protection of the technical solution. Any modifications, equivalent replacements and improvements made within the spirit and principles of the above implementation methods shall be included in the protection scope of the technical solution.
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| CN113257689A (en) * | 2021-05-12 | 2021-08-13 | 华宇华源电子科技（深圳）有限公司 | Chip packaging method and structure |
| CN113257688A (en) * | 2021-05-12 | 2021-08-13 | 华宇华源电子科技（深圳）有限公司 | Chip packaging method and chip packaging structure |
| CN113643990A (en) * | 2021-06-29 | 2021-11-12 | 华宇华源电子科技（深圳）有限公司 | Board level packaging method and structure for improving device strength |
| CN113643990B (en) * | 2021-06-29 | 2024-01-16 | 华宇华源电子科技（深圳）有限公司 | Board-level packaging method and structure for improving device strength |
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