TWI484611B - Foil based semiconductor package - Google Patents

Foil based semiconductor package Download PDF

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Publication number
TWI484611B
TWI484611B TW098117947A TW98117947A TWI484611B TW I484611 B TWI484611 B TW I484611B TW 098117947 A TW098117947 A TW 098117947A TW 98117947 A TW98117947 A TW 98117947A TW I484611 B TWI484611 B TW I484611B
Authority
TW
Taiwan
Prior art keywords
foil
carrier
metal foil
metal
construction
Prior art date
Application number
TW098117947A
Other languages
Chinese (zh)
Other versions
TW201001658A (en
Inventor
Will Wong
Nghia Thuc Tu
Jaime Bayan
David Chin
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Nat Semiconductor Corp
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Publication of TW201001658A publication Critical patent/TW201001658A/en
Application granted granted Critical
Publication of TWI484611B publication Critical patent/TWI484611B/en

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/49582—Metallic layers on lead frames
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12431—Foil or filament smaller than 6 mils
    • Y10T428/12438—Composite

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

箔片基底半導體封裝Foil base semiconductor package

本發明係一般關於積體電路(IC)的封裝。更具體的說，本發明關於涵蓋薄箔片的封裝方法與配置。The present invention is generally related to the packaging of integrated circuits (ICs). More specifically, the present invention relates to a packaging method and configuration that encompasses a thin foil.

有許多用於封裝積體電路(IC)晶粒的傳統處理。舉例來說，很多IC封裝利用由金屬薄片蝕刻或壓印的金屬引線架以提供連結至外部裝置的電氣互連。該晶粒可以藉由連結線、焊接凸塊或其他合適的電氣連接物以電氣連結至引線架。一般而言，該晶粒與引線架的一些部分以模製材料密封以保護在晶粒主動側上脆弱的電氣元件，而讓引線架的一些選定部分曝露以有助於電氣連接至外部裝置。There are many conventional processes for packaging integrated circuit (IC) dies. For example, many IC packages utilize metal lead frames that are etched or embossed with foil to provide electrical interconnections that are bonded to external devices. The die can be electrically bonded to the lead frame by bonding wires, solder bumps, or other suitable electrical connections. In general, the die and portions of the leadframe are sealed with a molding material to protect the fragile electrical components on the active side of the die, while some selected portions of the leadframe are exposed to facilitate electrical connection to an external device.

很多傳統引線架具有大約4到8密耳(mil，千分之一英寸)的厚度。進一步減少引線架厚度提供了幾個好處，包括可能減少總封裝尺寸與節省引線架金屬。但是一般而言，在封裝期間，較薄的引線架具有較容易彎曲的傾向。可以使用像是支持膠帶的支撐構造在引線架上以減少彎曲的風險。但是這一類的構造會負擔比較高的成本。Many conventional lead frames have a thickness of about 4 to 8 mils (mil, one thousandth of an inch). Further reductions in leadframe thickness offer several benefits, including the potential to reduce overall package size and save leadframe metal. In general, however, thinner lead frames have a tendency to bend more easily during packaging. A support such as a support tape can be used on the lead frame to reduce the risk of bending. But this type of construction will cost a relatively high cost.

封裝設計採用金屬箔片作為電性互連來取代引線架的概念已經被提出很多次。雖然一些箔片基底設計已經發展起來，但是沒有一個在工業界達到被廣泛接受的程度，一部分是因為箔片基底封裝處理傾向於比傳統引線架封裝來得更昂貴，而一部分是因為很多現有的封裝設備並不適用 於用在這一類的箔片基底封裝設計。The concept of package design using metal foil as an electrical interconnect to replace the lead frame has been proposed many times. Although some foil substrate designs have been developed, none have reached a level of acceptance in the industry, in part because foil substrate packaging processes tend to be more expensive than traditional lead frame packages, and in part because of many existing packages. Equipment is not applicable Used in this type of foil substrate package design.

雖然用於製造引線架與使用引線架科技封裝積體電路的現有技術運作良好，仍然有人持續努力發展用於封裝積體電路更有效的設計與方法。While the prior art for fabricating leadframes and using leadframe technology to package integrated circuits works well, there continues to be an ongoing effort to develop more efficient designs and methods for packaging integrated circuits.

所主張的發明係關於用於使用薄箔片以在積體電路封裝中形成電氣互連的方法與配置。在一實施例中，藉由將導電箔片的一些部分超音波式連結至金屬載體以形成箔片載體構造。該連結部分定義了在箔片載體構造中的嵌板。在一些實施例中，該箔片載體構造被切割以形成沿著其周圍密封的多個隔離嵌板。每一隔離嵌板可以大約是傳統引線架條或嵌板的尺寸。結果現有的封裝設備可以用來增加晶粒、連結線與模製材料到嵌板上。該超音波焊接幫助防止了不欲物質在這一類處理步驟中穿透箔片載體構造。在移除該模製箔片載體構造的載體部分之後，該構造被單塊化成積體電路封裝。一些實施例與利用一些或全部之上述操作的方法有關。其他實施例與新的封裝配置有關。The claimed invention relates to methods and configurations for using thin foils to form electrical interconnections in integrated circuit packages. In one embodiment, the foil carrier construction is formed by ultrasonically bonding portions of the conductive foil to the metal carrier. The joint portion defines a panel in the foil carrier construction. In some embodiments, the foil carrier construction is cut to form a plurality of isolation panels sealed along its circumference. Each isolation panel can be approximately the size of a conventional lead frame strip or panel. As a result, existing packaging equipment can be used to add dies, bond lines and molding materials to the panels. This ultrasonic welding helps prevent unwanted material from penetrating the foil carrier construction during this type of processing step. After removing the carrier portion of the molded foil carrier construction, the configuration is monolithically formed into an integrated circuit package. Some embodiments relate to methods that utilize some or all of the above operations. Other embodiments are related to the new package configuration.

在本發明的一些方面，說明了用於形成上述箔片載體構造的方法。該方法涵蓋了將金屬箔片的一些部分超音波式連結至載體。該金屬箔片與該載體個別的厚度可以根據特別應用的需求而變動。舉例來說，範圍從大約0.5密耳到2密耳的箔片厚度與範圍從大約5密耳到10密耳的載體厚度運作良好。該超音波式連結部分可以形成平行的焊接 線，該焊接線定義了箔片載體構造中的嵌板。在一些實施例中，該超音波式連結部分形成環繞每一嵌板的連續周邊。In some aspects of the invention, a method for forming the above described foil carrier construction is illustrated. The method encompasses ultrasonically joining portions of a metal foil to a carrier. The individual thickness of the metal foil and the carrier can vary depending on the needs of the particular application. For example, a foil thickness ranging from about 0.5 mils to 2 mils works well with a carrier thickness ranging from about 5 mils to 10 mils. The ultrasonic connecting portion can form a parallel welding A wire that defines the panel in the foil carrier construction. In some embodiments, the ultrasonic coupling portion forms a continuous perimeter around each panel.

可以加入額外金屬至箔片以減少電致遷移(electromigration)並且促進之後的焊線。在一些實施例中，該方法包括以金屬(像是銀合金)點鍍金屬薄片的頂端表面以形成多個裝置區域。可以不使用點鍍，而是施加銀的連續層至箔片的表面。在其他實施例中，施加鎳、鈀、及/或金到箔片的一側或兩側。也可以使用其他箔片金屬化層。Additional metal to foil can be added to reduce electromigration and promote subsequent bond wires. In some embodiments, the method includes spot plating a top surface of a metal foil with a metal such as a silver alloy to form a plurality of device regions. Instead of using spot plating, a continuous layer of silver is applied to the surface of the foil. In other embodiments, nickel, palladium, and/or gold are applied to one or both sides of the foil. Other foil metallization layers can also be used.

在本發明的另一方面，說明了用於封裝積體電路裝置的方法。該方法涵蓋黏附多個晶粒到箔片載體構造。該箔片載體構造可以採用上述說明的箔片載體構造形式，不過這並不是必要的。舉例來說，一些箔片載體構造的實施例使用黏著劑而不是超音波連結以將箔片黏附至載體。該方法進一步涵蓋了以模製材料密封一部分的金屬箔片與晶粒，並且移除載體。在載體從模製箔片載體構造移除之後，該箔片被蝕刻並曝露出一部分的模製材料。該蝕刻定義了箔片中的裝置區域。每一裝置區域組構以電氣連接至積體電路晶粒。在蝕刻步驟之後，該構造被單塊化以形成積體電路封裝。In another aspect of the invention, a method for packaging an integrated circuit device is illustrated. The method encompasses adhering multiple grains to a foil carrier construction. The foil carrier construction may take the form of a foil carrier construction as described above, although this is not essential. For example, some embodiments of foil carrier construction use an adhesive rather than an ultrasonic bond to adhere the foil to the carrier. The method further encompasses sealing a portion of the metal foil and the die with a molding material and removing the carrier. After the carrier is removed from the molded foil carrier construction, the foil is etched and exposes a portion of the molding material. This etch defines the area of the device in the foil. Each device area is configured to be electrically connected to the integrated circuit die. After the etching step, the configuration is monolithic to form an integrated circuit package.

其他的特點也是可能存在的。該密封可以涵蓋施加條狀連續體的模製材料。在一些方面，該金屬箔片包括基底金屬(例如銅)層與銀塗層。在其他方面，該金屬箔片包括基底金屬層與鈀與鎳的一或多個層。這一類的層可以在 相同的操作中被蝕刻以隔離在每一裝置區域中上的鉛觸點與連結點。在一些實施例中，該蝕刻處理發生在模製箔片被放置在可重覆使用的蝕刻載體腔室之後。Other features are also possible. The seal may encompass a molding material that applies a strip of continuous body. In some aspects, the metal foil comprises a base metal (eg, copper) layer and a silver coating. In other aspects, the metal foil comprises a base metal layer and one or more layers of palladium and nickel. This type of layer can be The same operation is etched to isolate the lead contacts and junctions in each device area. In some embodiments, the etching process occurs after the molded foil is placed in the reusable etched carrier chamber.

本發明的另一個方面涵蓋適於用在封裝積體電路晶粒的配置。該配置包括金屬箔片，該金屬箔片的一些部分與金屬載體超音波式連結。該箔片載體構造可以具有上面說明的一或多個特點。Another aspect of the invention encompasses configurations suitable for use in packaging integrated circuit dies. The arrangement includes a metal foil with portions of the metal foil that are ultrasonically coupled to the metal carrier. The foil carrier construction can have one or more of the features described above.

本發明一般係關於積體電路的封裝。更特別的是，本發明關於用於使用薄箔片以在積體電路封裝中形成電氣互連的改良式低成本方法與配置。The invention generally relates to the packaging of integrated circuits. More particularly, the present invention relates to an improved low cost method and arrangement for using thin foils to form electrical interconnects in integrated circuit packages.

薄箔片給半導體製造者帶來很多挑戰。如同稍早之前提到的，薄箔片在封裝處理的應力之下，很容易傾向於彎曲。此外，現有的封裝設備(組構以用於操控引線架)典型地不適用於處理薄箔片，因為薄箔片與傳統引線架在尺寸上不同，而且比傳統引線架脆弱。以下會說明用來處理這些挑戰之本發明的各種實施例。Thin foils present many challenges for semiconductor manufacturers. As mentioned earlier, thin foils tend to bend under the stress of the package process. Furthermore, existing packaging equipment (composition for manipulating the lead frame) is typically not suitable for processing thin foils because thin foils are different in size from conventional lead frames and are more fragile than conventional lead frames. Various embodiments of the invention for addressing these challenges are described below.

第一個說明的實施例涵蓋了箔片載體構造100，該箔片載體構造100設計以更有效率地將薄箔片整合進入半導體封裝製程。箔片載體構造100由銅箔片114製成，將銅箔片114沿著焊接線112超音波式連結至鋁載體。該箔片與該載體也可以由其他合適材料製成。焊接線112與預定切踞路徑110將該構造分離成多嵌板104。The first illustrated embodiment encompasses a foil carrier construction 100 that is designed to more efficiently integrate a thin foil into a semiconductor packaging process. The foil carrier construction 100 is made of a copper foil 114 that is ultrasonically bonded to the aluminum carrier along a weld line 112. The foil and the carrier may also be made of other suitable materials. The weld line 112 and the predetermined cut path 110 separate the structure into a multi-panel 104.

箔片載體構造100設計以沿著預定切踞路徑110切割。這一類的切割將會產生多個隔離嵌板。因為焊接線112與每一個預定切踞路徑110平行，並且位在每一個預定切踞路徑110的兩側上，在切割操作之後，焊接線112將圍繞著每一隔離嵌板形成連續的密封周邊。在這個實施例中，每一嵌板的尺寸與特點調適以讓現有的封裝設備處理。因此這一類的設備可以用來蝕刻、單塊化、增加晶粒、接線與模製材料到每一嵌板上。(這些處理步驟的例子將在以下連結圖3A到圖3E、圖4A到圖4C與圖5A到圖5E做討論。)因為每一嵌板使用超音波式連結做密封，避免了在上述處理步驟期間來自該嵌板層與層之間的不欲物質。The foil carrier construction 100 is designed to cut along a predetermined cutting path 110. This type of cutting will result in multiple isolation panels. Because weld line 112 is parallel to each predetermined cut path 110 and is located on either side of each predetermined cut path 110, after the cutting operation, weld line 112 will form a continuous sealed perimeter around each of the isolation panels. . In this embodiment, the size and characteristics of each panel are adapted to be handled by existing packaging equipment. This type of device can therefore be used to etch, monolithize, add dies, wire and molding materials to each panel. (Examples of these processing steps will be discussed below in connection with Figs. 3A to 3E, Figs. 4A to 4C, and Figs. 5A to 5E.) Since each panel is sealed using an ultrasonic bridge, the above processing steps are avoided. Undesirable material from between the panel layer and the layer.

超音波式連結提供強壯到足以忍受由封裝處理後面的階段施加的應力的優點，並且在加入晶粒、接線與模製材料到該箔片之後，仍然允許載體輕易從該箔片分離。在本發明書使用的用語「超音波式連結」包括具有超音波式元件的任何合適連結技術，也包括熱音波連結。雖然超音波式連結運作良好，但應該了解的是其他合適的連結技術也可以用來將箔片固定至載體上。舉例來說，也可以使用各種合適的黏著劑。Ultrasonic bonding provides the advantage of being strong enough to withstand the stresses imposed by the subsequent stages of the encapsulation process, and still allows the carrier to be easily separated from the foil after the addition of the die, wiring and molding material to the foil. The term "ultrasonic connection" as used in this specification includes any suitable joining technique with ultrasonic components, as well as thermosonic coupling. Although the ultrasonic connection works well, it should be understood that other suitable joining techniques can also be used to secure the foil to the carrier. For example, a variety of suitable adhesives can also be used.

在圖解的實施例中，該焊接線被限制在每一嵌板周邊的連結區域上，而且沒有延伸到該嵌板的中心或內部。但是應該了解的是該焊接線112可以用各種其他方式配置。舉例來說，嵌板104可以由單一且更寬的焊接線來加以分離而不是以一對較薄的焊接線分離。假如切踞路徑是沿著 每一較寬焊接線的中間行進，所得的嵌板也將會沿著嵌板周邊被密封。或者，也可以提供額外的中間焊接線以有效地將嵌板分離成較小的密封區段。舉例來說，每一密封區段可以包括二維陣列的裝置區域或是很像各種傳統引線架條中出現的裝置區域的配置。In the illustrated embodiment, the weld line is confined to the joint region of the perimeter of each panel and does not extend into the center or interior of the panel. It should be understood, however, that the weld line 112 can be configured in a variety of other manners. For example, the panels 104 can be separated by a single and wider weld line rather than being separated by a pair of thinner weld lines. If the cut path is along The middle of each wider weld line travels and the resulting panel will also be sealed along the perimeter of the panel. Alternatively, an additional intermediate weld line can be provided to effectively separate the panel into smaller seal sections. For example, each sealing section can include a two-dimensional array of device regions or a configuration that closely resembles the device regions present in various conventional lead frame strips.

應該了解的是在箔片載體構造100中的箔片可以包括各種金屬層。熟悉封裝技術者會了解到有時會施加像是鎳、鈀、或銀在銅引線架上以處理下列各種問題：減少電致遷移及/或改良在連結線與引線架之間的電氣連結等等。在本發明中，該箔片取代引線架，並希望施加類似的塗層到該箔片上。為了減少成本，在箔片接附到載體構造之前，有時候可以施加這一類的金屬化層到該箔片上。舉例來說，假如箔片載體構造100中的箔片由銅製成，可能會希望以鎳層與鈀層對箔片的兩側做塗層。在其他實施例中，該箔片頂端(被曝露的)表面由一層銀或銀合金覆蓋。或者，該箔片也可以是銀點鍍而成的，如同圖1B中圖解所示。It should be understood that the foil in the foil carrier construction 100 can include various metal layers. Those familiar with packaging technology will understand that nickel, palladium, or silver may be applied to copper leadframes to address the following issues: reducing electromigration and/or improving electrical connections between the bond wires and the leadframe. Wait. In the present invention, the foil replaces the lead frame and it is desirable to apply a similar coating to the foil. To reduce cost, it is sometimes possible to apply a metallization layer of this type to the foil before it is attached to the carrier construction. For example, if the foil in the foil carrier construction 100 is made of copper, it may be desirable to coat both sides of the foil with a nickel layer and a palladium layer. In other embodiments, the top (exposed) surface of the foil is covered by a layer of silver or silver alloy. Alternatively, the foil may be silver plated as shown in Figure 1B.

圖1B展示了根據本發明實施例之嵌板104的放大頂端視圖。嵌板104包括多個裝置區域106，該等裝置區域106由銀合金的點鍍形成，也可以使用其他合適的金屬。圖1C圖解裝置區域106其中之一的放大頂端視圖。點鍍部分108形成適用於焊線至積體電路晶粒的連結點圖案。這一類的點鍍可以在沿著預定切踞路徑110切割箔片載體構造100之前或之後發生。當連結線稍後連結到箔片的點鍍部分108時， 銀合金可以強化該連結。FIG. 1B shows an enlarged top view of panel 104 in accordance with an embodiment of the present invention. The panel 104 includes a plurality of device regions 106 formed by spot plating of silver alloy, and other suitable metals may be used. FIG. 1C illustrates an enlarged top view of one of the device regions 106. The spot plating portion 108 forms a joint pattern suitable for the bonding wire to the integrated circuit die. This type of spot plating can occur before or after cutting the foil carrier construction 100 along the predetermined cutting path 110. When the joining line is later joined to the spot plating portion 108 of the foil, Silver alloys can strengthen the bond.

裝置區域106可以採用各種圖案與組構。在圖解的實施例中，點鍍部分108定義了位在裝置區域106周邊附近的環中的複數個連結點。當然也可以使用各種其他的連結點圖案。舉例來說，假如希望下連結(down bonding)至類似晶粒接附墊的放大接地(或其他)觸點，可以接著在裝置區域106的中心提供合適的點鍍。在其他實施例中，可以點鍍多列連結點或各種其他連結點圖案的任何一種在箔片上。Device region 106 can take a variety of patterns and configurations. In the illustrated embodiment, the spot plated portion 108 defines a plurality of joint points in a ring located near the periphery of the device region 106. Of course, various other joint pattern can also be used. For example, if it is desired to down-bond to an enlarged ground (or other) contact similar to the die attach pad, then suitable spot plating can then be provided at the center of the device region 106. In other embodiments, any of a plurality of columns of joints or various other joint pattern may be spotted on the foil.

圖2與圖3A到圖3E圖解根據本發明一實施例用於封裝積體電路裝置的製程200。一開始，在步驟202時，提供了在圖3A中包括箔片306與載體308的箔片載體構造300。箔片載體構造300可以採用從圖1A之箔片載體構造100切割下來的嵌板104之形式，不過這不是必要的。在圖解的實施例中，箔片306是銅箔片而該載體308由鋁製成。在替代性實施例中，可以用不同的金屬箔片取代銅箔片，及可以用不同的載體構造來取代鋁載體308。舉例來說，該載體或者可以由銅、鋼或其他金屬、像是聚亞醯胺的非導電材料或各種其他合適材料製成。在一些實施例中，箔片306經由超音波式連結黏著到載體308上，而在其他實施例中，使用黏著劑或其他合適的連結機制來將箔片306固定到載體308。2 and 3A through 3E illustrate a process 200 for packaging integrated circuit devices in accordance with an embodiment of the present invention. Initially, at step 202, a foil carrier construction 300 including a foil 306 and a carrier 308 in FIG. 3A is provided. The foil carrier construction 300 can take the form of a panel 104 that is cut from the foil carrier construction 100 of Figure 1A, although this is not required. In the illustrated embodiment, the foil 306 is a copper foil and the carrier 308 is made of aluminum. In an alternative embodiment, the copper foil may be replaced with a different metal foil, and the aluminum carrier 308 may be replaced with a different carrier construction. For example, the carrier may alternatively be made of copper, steel or other metal, a non-conductive material such as polyamidomine or various other suitable materials. In some embodiments, the foil 306 is adhered to the carrier 308 via an ultrasonic bond, while in other embodiments, an adhesive or other suitable joining mechanism is used to secure the foil 306 to the carrier 308.

可以廣泛地變動箔片載體構造300的尺寸以符合特定應用的需要。在一些實施例中，箔片載體構造300大約是典型引線架條的尺寸。也可以廣泛地變動箔片306與載體 308的厚度。在一些實施例中，箔片厚度的範圍大約在0.5密耳到2密耳。載體厚度的範圍可以大約在5密耳到12密耳。當使用鋁載體時，厚度範圍在7密耳到10密耳的鋁載體運作良好。一般而言，箔片載體構造的厚度與標準引線架的厚度匹配是有利的，如此一來可以使用調適以操控引線架的標準封裝設備來處理該構造。The size of the foil carrier construction 300 can be varied widely to meet the needs of a particular application. In some embodiments, the foil carrier construction 300 is approximately the size of a typical lead frame strip. The foil 306 and the carrier can also be widely varied The thickness of 308. In some embodiments, the foil thickness ranges from about 0.5 mils to about 2 mils. The thickness of the carrier can range from about 5 mils to about 12 mils. Aluminum supports having a thickness ranging from 7 mils to 10 mils work well when aluminum supports are used. In general, it is advantageous to match the thickness of the foil carrier construction to the thickness of a standard lead frame, such that the configuration can be handled using standard packaging equipment adapted to manipulate the lead frame.

一開始，在步驟204時，使用傳統晶粒接附技術將晶粒318架置在箔片載體構造300上。在接附完晶粒之後，將晶粒用像是焊線的合適手段電氣連接到箔片上。該焊線的構造在圖3B中圖解。應該了解的是所說明方法的顯著優點之一是可以在晶粒接附與焊線的步驟中使用通常可得的晶粒接附與焊線設備。所得的構造具有藉由連結線316電氣連接到箔片的複數個晶粒。在圖解的實施例中，提供額外的鎳層與鈀層在箔片306的兩個表面上。上面的鈀層有助於將連結線316更牢固地固定在箔片上。Initially, at step 204, the die 318 is mounted on the foil carrier construction 300 using conventional die attach techniques. After the die is attached, the die is electrically connected to the foil with a suitable means such as a wire bond. The construction of this wire is illustrated in Figure 3B. It will be appreciated that one of the significant advantages of the illustrated method is that commonly available die attach and wire bonding equipment can be used in the steps of die attach and wire bonding. The resulting construction has a plurality of grains that are electrically connected to the foil by bond wires 316. In the illustrated embodiment, an additional layer of nickel and palladium is provided on both surfaces of the foil 306. The upper palladium layer helps to secure the bond line 316 to the foil more securely.

在步驟206與圖3C中，將載體308、連結線316與至少一部分箔片載體嵌板301與銅層306用模製材料322密封以形成模製箔片載體構造324。在圖3C的圖解實施例中，加入條狀連續體形式的模製材料322。也就是說，將該模製材料很平均地施加在整個箔片306的模製部分上。應該注意到的是這種型式的模製在引線架基底封裝中不是通用的。相對地來說，引線架條上承載的裝置典型地被個別模製或是以小嵌板模製。條狀連續體模製材料的好處將會連結圖3D、3E與步驟208加以討論。In step 206 and FIG. 3C, carrier 308, bond line 316, and at least a portion of foil carrier panel 301 and copper layer 306 are sealed with molding material 322 to form molded foil carrier construction 324. In the illustrated embodiment of Figure 3C, a molding material 322 in the form of a strip of continuous body is added. That is, the molding material is applied evenly over the molded portion of the entire foil 306. It should be noted that this type of molding is not versatile in lead frame base packages. In contrast, the devices carried on the lead frame strip are typically molded individually or in small panels. The benefits of the strip continuum molding material will be discussed in connection with Figures 3D, 3E and Step 208.

在步驟208中，移除圖3C中模製箔片載體構造324的載體部分，形成了圖3D中的模製箔片構造325。此時模製材料取代了載體308，提供了箔片的構造支撐。應該了解的是條狀連續體模製方法的優點是它提供了全部嵌板的良好支撐，因此該條狀物仍然可以用嵌板形式操控。反面來說，假如在模製操作期間在小嵌板之間提供模製溝槽，在移除載體之後，接著將需要獨立操控小嵌板。In step 208, the carrier portion of the molded foil carrier construction 324 of Figure 3C is removed, forming the molded foil construction 325 of Figure 3D. At this point the molding material replaces the carrier 308, providing structural support for the foil. It should be understood that the strip continuum molding method has the advantage that it provides good support for all panels, so that the strip can still be manipulated in the form of panels. Conversely, if a molded groove is provided between the small panels during the molding operation, the small panel will then need to be independently manipulated after the carrier is removed.

圖3E展示了模製箔片構造325的外部視圖，應該了解的是，雖然模製箔片構造325的頂端表面328大致上是平面的，但這不是一個必要需求。在模製箔片構造325中的模製材料322可以採用各種圖案與形狀，而且模製材料的深度334可以沿著模製箔片構造325的長度變動。3E shows an external view of the molded foil construction 325, it being understood that although the top surface 328 of the molded foil construction 325 is generally planar, this is not a necessary requirement. The molding material 322 in the molded foil construction 325 can take a variety of patterns and shapes, and the depth 334 of the molding material can vary along the length of the molded foil construction 325.

在步驟209中，如圖4A與圖4B中所示，將模製箔片構造325放置在蝕刻載體404中。圖4A圖解含有模製箔片構造325之蝕刻載體404的頂端視圖。在該圖解的實施例中，蝕刻載體404包括組構以接收模製箔片構造325的對準孔402與腔室406。蝕刻載體404設計以接收圖3F的模製箔片構造325，如此一來該模製箔片構造的頂端表面328被隱藏在腔室406內，而箔片306被曝露。該蝕刻載體可以被重覆使用，而且較佳地以鋁製成，不過也可以使用其他材料。In step 209, a molded foil construction 325 is placed in the etched carrier 404 as shown in Figures 4A and 4B. FIG. 4A illustrates a top view of an etched carrier 404 containing a molded foil construction 325. In the illustrated embodiment, the etched carrier 404 includes an alignment aperture 402 and a chamber 406 that are configured to receive the molded foil construction 325. The etched carrier 404 is designed to receive the molded foil construction 325 of FIG. 3F such that the top end surface 328 of the molded foil construction is hidden within the chamber 406 and the foil 306 is exposed. The etched carrier can be used repeatedly, and is preferably made of aluminum, although other materials can be used.

在步驟210中蝕刻箔片306。該蝕刻移除箔片306的一些部分並且定義了多個裝置區域410，如圖4B所示。也可以使用包括電漿蝕刻的各種合適蝕刻製程。也可以使用其 他合適技術形成裝置區域410，該等技術像是切鋸或雷射切割。The foil 306 is etched in step 210. This etch removes portions of the foil 306 and defines a plurality of device regions 410, as shown in Figure 4B. Various suitable etching processes including plasma etching can also be used. Can also use it His suitable technique forms device area 410, such as a saw or a laser cut.

一些實施例涵蓋了以匯流排形成裝置區域410以促進之後金屬(像是錫或焊錫)在由箔片形成之觸點上的電鍍。圖4C概略性地圖解這樣一個裝置區域。在圖解的實施例中，裝置區域410具有晶粒接附墊412、鉛觸點414與匯流排416。匯流排416電氣連接該墊與鉛。匯流排416也可以形成在多個裝置區域之間的導電連結。應該了解的是，裝置區域410只代表很多可能配置的其中之一。Some embodiments encompass forming the device region 410 in a bus bar to facilitate subsequent plating of metal (such as tin or solder) on the contacts formed by the foil. Figure 4C schematically illustrates such a device area. In the illustrated embodiment, device region 410 has die attach pads 412, lead contacts 414, and bus bars 416. Bus 416 electrically connects the pad to lead. Bus bar 416 can also form a conductive connection between a plurality of device regions. It should be appreciated that device area 410 represents only one of many possible configurations.

圖5A到圖5B提供模製箔片構造325上之蝕刻製程效果的側視圖。圖5A是在蝕刻之前模製箔片構造325的概略側視圖。圖5B圖解了蝕刻製程是如何移除箔片306的一些部分，露出模製材料322的一些區段並且形成鉛觸點414與晶粒接附墊412。5A-5B provide side views of the etching process effects on the molded foil construction 325. FIG. 5A is a schematic side view of a molded foil construction 325 prior to etching. FIG. 5B illustrates how the etch process removes portions of the foil 306, exposing portions of the molding material 322 and forming lead contacts 414 and die attach pads 412.

如同上面討論的，一些實施例考慮到圖2的步驟211，該步驟涵蓋了圖5C的焊錫508在晶粒接附墊412與鉛觸點414上的電鍍。在步驟212，該模製箔片構造325沿著圖5C的預定切踞路徑302單塊化以形成半導體封裝。可以使用包括切鋸與雷射切割的各種技術來單塊化模製箔片構造325。在圖5D中圖解單塊化封裝520的放大側視圖。在圖5E中顯示該封裝的概略底端視圖。該底端視圖圖解由模製材料322圍繞的晶粒接附墊516與鉛觸點518。As discussed above, some embodiments contemplate step 211 of FIG. 2, which includes the plating of solder 508 of FIG. 5C on die attach pads 412 and lead contacts 414. At step 212, the molded foil construction 325 is monolithically formed along the predetermined tangential path 302 of FIG. 5C to form a semiconductor package. The monolithic molded foil construction 325 can be monolithically fabricated using a variety of techniques including sawing and laser cutting. An enlarged side view of the monolithic package 520 is illustrated in Figure 5D. A schematic bottom end view of the package is shown in Figure 5E. The bottom end view illustrates the die attach pad 516 and lead contact 518 surrounded by molding material 322.

雖然只有詳細說明本發明的一些實施例，應該了解的是本發明可以用很多其他形式施行而不偏離本發明的精神 或範疇。在先前的說明當中，很多說明的引線架包括鉛及/或觸點，在這裡通常指稱為鉛觸點。在本發明的內容當中，該用語「鉛觸點」意圖包含可能出現在引線架內的鉛、觸點與其他電氣互連構造。因此本發明的實施例應該被視為解釋性的，並不是限制性的，而且本發明並不限於這裡所給定的細節，並且可以在本發明的範疇內修改，而且可以是隨附申請專利範圍的等效物。Although only some embodiments of the invention have been described in detail, it should be understood that the invention may be Or category. In the foregoing description, many of the illustrated lead frames include lead and/or contacts, commonly referred to herein as lead contacts. In the context of the present invention, the term "lead contact" is intended to include lead, contacts and other electrical interconnection configurations that may be present in the leadframe. The present invention is therefore to be considered in all respects as illustrative and not limiting, and the invention is not limited to the details given herein, and may be modified within the scope of the invention The equivalent of the range.

100‧‧‧箔片載體構造100‧‧‧Foil carrier construction

104‧‧‧嵌板104‧‧‧ Panel

106‧‧‧多個裝置區域106‧‧‧Multiple device areas

108‧‧‧點鍍部分108‧‧‧ Point plating

110‧‧‧預定切踞路徑110‧‧‧ Scheduled cutting path

112‧‧‧焊接線112‧‧‧welding line

114‧‧‧銅箔片114‧‧‧copper foil

200‧‧‧用於封裝積體電路裝置的製程200‧‧‧Process for packaging integrated circuit devices

202-212‧‧‧用於封裝積體電路裝置的處理中之每一步驟202-212‧‧‧Each step in the process of packaging integrated circuit devices

300‧‧‧箔片載體構造300‧‧‧Foil carrier construction

301‧‧‧箔片載體嵌板301‧‧‧Foil carrier panel

302‧‧‧預定切鋸路徑302‧‧‧Scheduled sawing path

306‧‧‧箔片306‧‧‧Foil

308‧‧‧載體308‧‧‧ Carrier

316‧‧‧連結線316‧‧‧Connected line

318‧‧‧晶粒318‧‧‧ grain

322‧‧‧模製材料322‧‧‧Molded materials

324‧‧‧模製箔片載體構造324‧‧‧Molded foil carrier construction

325‧‧‧模製箔片構造325‧‧·Molded foil construction

328‧‧‧模製箔片構造的頂端表面328‧‧‧ Top surface of molded foil construction

334‧‧‧模製材料的深度334‧‧‧Depth of moulding material

402‧‧‧對準孔402‧‧‧ Alignment hole

404‧‧‧蝕刻載體404‧‧‧etching carrier

406‧‧‧腔室406‧‧‧ chamber

410‧‧‧多個裝置區域410‧‧‧Multiple device areas

412‧‧‧晶粒接附墊412‧‧‧ die attach pad

414‧‧‧鉛觸點414‧‧‧ lead contacts

416‧‧‧匯流排416‧‧‧ Busbar

508‧‧‧焊錫508‧‧‧ solder

516‧‧‧晶粒接附墊516‧‧‧ die attach pad

518‧‧‧鉛觸點518‧‧‧ lead contacts

520‧‧‧單塊化封裝520‧‧‧Single package

本發明與其中的優點藉由參照與隨附圖式連結的上述說明可以最容易被理解，其中：圖1A為根據本發明一實施例之包括兩個超音波式連結層與多個嵌板之箔片載體構造的概略頂端視圖。The invention and its advantages are best understood by reference to the above description in conjunction with the accompanying drawings, in which: FIG. 1A is a two-sonic connection layer and a plurality of panels in accordance with an embodiment of the invention. A schematic top view of the foil carrier construction.

圖1B為根據本發明一實施例在圖1A中說明之嵌板其中之一的放大概略頂端視圖。Figure 1B is an enlarged schematic top plan view of one of the panels illustrated in Figure 1A, in accordance with an embodiment of the present invention.

圖1C為在圖1B中說明之嵌板上裝置區域其中之一的放大概略頂端視圖。Figure 1C is an enlarged schematic top plan view of one of the panel regions of the panel illustrated in Figure 1B.

圖2為根據本發明一實施例說明封裝積體電路裝置之處理的流程圖。2 is a flow chart showing the processing of a packaged integrated circuit device in accordance with an embodiment of the present invention.

圖3A到圖3E為根據本發明之實施例封裝處理之各種階段的概略側視圖。3A through 3E are schematic side views of various stages of a packaging process in accordance with an embodiment of the present invention.

圖4A為在圖3E說明之模製箔片構造放置在載體後之例示性蝕刻載體的概略頂端視圖。4A is a schematic top plan view of an exemplary etched carrier after the molded foil construction illustrated in FIG. 3E is placed on a carrier.

圖4B為在蝕刻之後在圖4A中說明之蝕刻載體與模製 箔片構造的概略頂端視圖。Figure 4B is an etched carrier and molding illustrated in Figure 4A after etching. A schematic top view of the foil construction.

圖4C為根據本發明一實施例由圖4B之蝕刻處理所得之裝置區域的放大概略頂端視圖。4C is an enlarged schematic top plan view of the device region resulting from the etching process of FIG. 4B, in accordance with an embodiment of the present invention.

圖5A到圖5C為在蝕刻、電鍍與單塊化之後在圖3D中說明之模製箔片構造的概略側視圖。5A through 5C are schematic side views of the molded foil configuration illustrated in Fig. 3D after etching, plating, and monolith.

圖5D為根據本發明之實施例單塊化封裝的概略側視圖。Figure 5D is a schematic side view of a monolithic package in accordance with an embodiment of the present invention.

圖5E為在圖5D中說明之單塊化封裝的概略底端視圖。Figure 5E is a schematic bottom end view of the monolithic package illustrated in Figure 5D.

在圖式當中，類似的元件符號有時候會用來代表類似的構造元件。讀者也應該了解圖式中的描繪是概略性的，並且沒有按比例縮放。In the drawings, similar component symbols are sometimes used to represent similar structural components. The reader should also understand that the depictions in the drawings are schematic and not scaled.

200‧‧‧用於封裝積體電路裝置的製程200‧‧‧Process for packaging integrated circuit devices

202-212‧‧‧用於封裝積體電路裝置的處理中之每一步驟202-212‧‧‧Each step in the process of packaging integrated circuit devices

Claims (18)

一種用於形成箔片載體構造的方法，包含：提供金屬載體；提供金屬箔片；將金屬箔片的一些部分超音波式連結至金屬載體，該連結部分定義在金屬箔片中的多個嵌板，該等嵌板適用於用來作為在積體電路封裝中的箔片載體嵌板；及以銀或銀合金點鍍金屬箔片的表面以形成在每一嵌板內的多個裝置區域，每一裝置區域適用於焊線至積體電路晶粒。 A method for forming a foil carrier construction, comprising: providing a metal carrier; providing a metal foil; ultrasonically bonding portions of the metal foil to the metal carrier, the bonding portion defining a plurality of inlays in the metal foil Plates suitable for use as a foil carrier panel in an integrated circuit package; and a surface of a metal foil plated with silver or silver alloy to form a plurality of device regions within each panel Each device area is suitable for wire bonding to integrated circuit die. 如申請專利範圍第1項所述之方法，其中該金屬箔片是銅箔片，該銅箔片具有形成在金屬箔片之頂端表面與底端表面的鎳層與鈀層。 The method of claim 1, wherein the metal foil is a copper foil having a nickel layer and a palladium layer formed on a top end surface and a bottom end surface of the metal foil. 如申請專利範圍第1項所述之方法，其中該金屬箔片的厚度介於大約0.6密耳與2密耳之間，及該載體的厚度介於大約5密耳與10密耳之間。 The method of claim 1, wherein the metal foil has a thickness of between about 0.6 mils and 2 mils, and the carrier has a thickness of between about 5 mils and 10 mils. 如申請專利範圍第1項所述之方法，其中該超音波式連結部分形成圍繞著該多個嵌板中之每一者的連續周邊。 The method of claim 1, wherein the ultrasonic connecting portion forms a continuous perimeter surrounding each of the plurality of panels. 如申請專利範圍第1項所述之方法，進一步包含切割已連結金屬箔片與金屬載體以形成多個隔離嵌板。 The method of claim 1, further comprising cutting the joined metal foil and the metal carrier to form a plurality of isolation panels. 如申請專利範圍第5項所述之方法，其中該超音波式連結形成平行焊接線，及其中該切割步驟進一步包括沿著平行焊接線切割和在平行焊接線之間切割。 The method of claim 5, wherein the ultrasonic coupling forms a parallel weld line, and wherein the cutting step further comprises cutting along the parallel weld line and cutting between the parallel weld lines. 一種用於封裝積體電路裝置的方法，該方法包含： 提供箔片載體構造，該箔片載體構造包括黏著至載體的金屬箔片；將多個晶粒接附到金屬箔片上；以模製材料密封多個晶粒及至少金屬箔片的一部分以形成模製箔片載體構造；從模製箔片載體構造移除載體以形成模製箔片構造；在移除載體後蝕刻金屬箔片以在金屬箔片中定義多個裝置區域，每一個裝置區域支持至少多個晶粒的其中之一及具有多個電氣觸點，其中該蝕刻曝露了模製材料的一些部分；及在蝕刻步驟之後，單塊化該模製箔片構造以提供多個封裝積體電路裝置。 A method for packaging an integrated circuit device, the method comprising: Providing a foil carrier construction comprising a metal foil adhered to the carrier; attaching a plurality of dies to the metal foil; sealing the plurality of dies and at least a portion of the metal foil with the molding material to form Molded foil carrier construction; removing the carrier from the molded foil carrier construction to form a molded foil construction; etching the metal foil after removing the carrier to define a plurality of device regions in the metal foil, each device region Supporting at least one of the plurality of dies and having a plurality of electrical contacts, wherein the etch exposes portions of the molding material; and after the etching step, monolithizing the molded foil construction to provide a plurality of packages Integrated circuit device. 如申請專利範圍第7項所述之方法，其中該載體是金屬載體及該金屬箔片的一些部分超音波式連結到金屬載體。 The method of claim 7, wherein the carrier is a metal carrier and portions of the metal foil are ultrasonically bonded to the metal carrier. 如申請專利範圍第7項所述之方法，其中以黏著劑將該金屬箔片接附至該載體。 The method of claim 7, wherein the metal foil is attached to the carrier with an adhesive. 如申請專利範圍第7項所述之方法，其中該密封步驟包括以在金屬箔片上形成單一連續模製條的方式施加模製材料至多個晶粒及該金屬箔片的一部分上。 The method of claim 7, wherein the sealing step comprises applying a molding material to the plurality of dies and a portion of the metal foil in a manner to form a single continuous molding strip on the metal foil. 如申請專利範圍第7項所述之方法，其中：該金屬箔片包括銅層及由銀或銀合金形成的第二層；該模製材料接觸該銀層；該蝕刻步驟包括蝕刻銅層與第二層以在每一裝置區域 上形成接觸墊，而在接觸墊之間的模製材料曝露出來；及該第二層在每一接觸墊上提供焊線點。 The method of claim 7, wherein the metal foil comprises a copper layer and a second layer formed of silver or a silver alloy; the molding material contacts the silver layer; and the etching step comprises etching the copper layer and The second layer is in each device area A contact pad is formed thereon, and a molding material between the contact pads is exposed; and the second layer provides a wire bond point on each contact pad. 如申請專利範圍第7項所述之方法，進一步包含將模製箔片構造放置在可重覆使用之蝕刻載體的腔室中，該蝕刻載體組構以將金屬箔片曝露於蝕刻製程之中。 The method of claim 7, further comprising placing the molded foil construction in a chamber of the reusable etched carrier, the etched carrier assembly to expose the metal foil to the etching process . 如申請專利範圍第7項所述之方法，其中該金屬箔片包括金屬層，該金屬層具有以鎳與鈀覆蓋的複數個表面。 The method of claim 7, wherein the metal foil comprises a metal layer having a plurality of surfaces covered with nickel and palladium. 一種適於用在封裝積體電路晶粒中的配置，包含：金屬載體；及金屬箔片，該金屬箔片的一些部分超音波式連結至金屬載體，該連結部分定義在金屬箔片中的多個嵌板，且該金屬箔片的表面以銀或銀合金點鍍以形成在每一嵌板內的多個裝置區域，每一裝置區域適用於焊線至積體電路晶粒。 A configuration suitable for use in a package integrated circuit die, comprising: a metal carrier; and a metal foil, some portions of the metal foil being ultrasonically coupled to a metal carrier, the bonded portion being defined in the metal foil A plurality of panels, and the surface of the metal foil is spotted with silver or silver alloy dots to form a plurality of device regions within each panel, each device region being adapted for wire bonding to integrated circuit die. 如申請專利範圍第14項所述之配置，其中每一嵌板包括多個裝置區域，用金屬點鍍每一裝置區域以形成適用於焊線至積體電路晶粒的電氣觸點。 The arrangement of claim 14, wherein each panel comprises a plurality of device regions, each device region being plated with metal dots to form electrical contacts suitable for wire bonding to integrated circuit die. 如申請專利範圍第14項所述之配置，其中該載體由鋁製成及該箔片由銅製成。 The arrangement of claim 14, wherein the carrier is made of aluminum and the foil is made of copper. 如申請專利範圍第14項所述之配置，其中該超音波式連結部分形成圍繞該多個嵌板之每一者的連續周邊。 The arrangement of claim 14, wherein the ultrasonic coupling portion forms a continuous perimeter around each of the plurality of panels. 如申請專利範圍第14項所述之配置，其中該超音波式連結部分形成定義該多個嵌板之每一者之邊界的平行焊接線。 The arrangement of claim 14, wherein the ultrasonic coupling portion forms a parallel weld line defining a boundary of each of the plurality of panels.
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